1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #include <rte_alarm.h> 6 #include <rte_bus_pci.h> 7 #include <ethdev_pci.h> 8 #include <rte_pci.h> 9 #include <rte_kvargs.h> 10 11 #include "hns3_ethdev.h" 12 #include "hns3_logs.h" 13 #include "hns3_rxtx.h" 14 #include "hns3_intr.h" 15 #include "hns3_regs.h" 16 #include "hns3_dcb.h" 17 #include "hns3_mp.h" 18 19 #define HNS3_SERVICE_INTERVAL 1000000 /* us */ 20 #define HNS3_SERVICE_QUICK_INTERVAL 10 21 #define HNS3_INVALID_PVID 0xFFFF 22 23 #define HNS3_FILTER_TYPE_VF 0 24 #define HNS3_FILTER_TYPE_PORT 1 25 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0) 26 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0) 27 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1) 28 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2) 29 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3) 30 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \ 31 | HNS3_FILTER_FE_ROCE_EGRESS_B) 32 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \ 33 | HNS3_FILTER_FE_ROCE_INGRESS_B) 34 35 /* Reset related Registers */ 36 #define HNS3_GLOBAL_RESET_BIT 0 37 #define HNS3_CORE_RESET_BIT 1 38 #define HNS3_IMP_RESET_BIT 2 39 #define HNS3_FUN_RST_ING_B 0 40 41 #define HNS3_VECTOR0_IMP_RESET_INT_B 1 42 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U 43 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U 44 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U 45 46 #define HNS3_RESET_WAIT_MS 100 47 #define HNS3_RESET_WAIT_CNT 200 48 49 /* FEC mode order defined in HNS3 hardware */ 50 #define HNS3_HW_FEC_MODE_NOFEC 0 51 #define HNS3_HW_FEC_MODE_BASER 1 52 #define HNS3_HW_FEC_MODE_RS 2 53 54 enum hns3_evt_cause { 55 HNS3_VECTOR0_EVENT_RST, 56 HNS3_VECTOR0_EVENT_MBX, 57 HNS3_VECTOR0_EVENT_ERR, 58 HNS3_VECTOR0_EVENT_PTP, 59 HNS3_VECTOR0_EVENT_OTHER, 60 }; 61 62 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = { 63 { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 64 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 65 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 66 67 { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 68 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 69 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 70 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 71 72 { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 73 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 74 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) }, 75 76 { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 77 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 78 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 79 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 80 81 { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 82 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 83 RTE_ETH_FEC_MODE_CAPA_MASK(RS) }, 84 85 { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 86 RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) | 87 RTE_ETH_FEC_MODE_CAPA_MASK(RS) } 88 }; 89 90 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns, 91 uint64_t *levels); 92 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 93 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, 94 int on); 95 static int hns3_update_link_info(struct rte_eth_dev *eth_dev); 96 static bool hns3_update_link_status(struct hns3_hw *hw); 97 98 static int hns3_add_mc_addr(struct hns3_hw *hw, 99 struct rte_ether_addr *mac_addr); 100 static int hns3_remove_mc_addr(struct hns3_hw *hw, 101 struct rte_ether_addr *mac_addr); 102 static int hns3_restore_fec(struct hns3_hw *hw); 103 static int hns3_query_dev_fec_info(struct hns3_hw *hw); 104 static int hns3_do_stop(struct hns3_adapter *hns); 105 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds); 106 107 void hns3_ether_format_addr(char *buf, uint16_t size, 108 const struct rte_ether_addr *ether_addr) 109 { 110 snprintf(buf, size, "%02X:**:**:**:%02X:%02X", 111 ether_addr->addr_bytes[0], 112 ether_addr->addr_bytes[4], 113 ether_addr->addr_bytes[5]); 114 } 115 116 static void 117 hns3_pf_disable_irq0(struct hns3_hw *hw) 118 { 119 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 120 } 121 122 static void 123 hns3_pf_enable_irq0(struct hns3_hw *hw) 124 { 125 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 126 } 127 128 static enum hns3_evt_cause 129 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay, 130 uint32_t *vec_val) 131 { 132 struct hns3_hw *hw = &hns->hw; 133 134 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 135 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 136 *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); 137 if (!is_delay) { 138 hw->reset.stats.imp_cnt++; 139 hns3_warn(hw, "IMP reset detected, clear reset status"); 140 } else { 141 hns3_schedule_delayed_reset(hns); 142 hns3_warn(hw, "IMP reset detected, don't clear reset status"); 143 } 144 145 return HNS3_VECTOR0_EVENT_RST; 146 } 147 148 static enum hns3_evt_cause 149 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay, 150 uint32_t *vec_val) 151 { 152 struct hns3_hw *hw = &hns->hw; 153 154 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 155 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); 156 *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); 157 if (!is_delay) { 158 hw->reset.stats.global_cnt++; 159 hns3_warn(hw, "Global reset detected, clear reset status"); 160 } else { 161 hns3_schedule_delayed_reset(hns); 162 hns3_warn(hw, 163 "Global reset detected, don't clear reset status"); 164 } 165 166 return HNS3_VECTOR0_EVENT_RST; 167 } 168 169 static enum hns3_evt_cause 170 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 171 { 172 struct hns3_hw *hw = &hns->hw; 173 uint32_t vector0_int_stats; 174 uint32_t cmdq_src_val; 175 uint32_t hw_err_src_reg; 176 uint32_t val; 177 enum hns3_evt_cause ret; 178 bool is_delay; 179 180 /* fetch the events from their corresponding regs */ 181 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 182 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 183 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 184 185 is_delay = clearval == NULL ? true : false; 186 /* 187 * Assumption: If by any chance reset and mailbox events are reported 188 * together then we will only process reset event and defer the 189 * processing of the mailbox events. Since, we would have not cleared 190 * RX CMDQ event this time we would receive again another interrupt 191 * from H/W just for the mailbox. 192 */ 193 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ 194 ret = hns3_proc_imp_reset_event(hns, is_delay, &val); 195 goto out; 196 } 197 198 /* Global reset */ 199 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { 200 ret = hns3_proc_global_reset_event(hns, is_delay, &val); 201 goto out; 202 } 203 204 /* Check for vector0 1588 event source */ 205 if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) { 206 val = BIT(HNS3_VECTOR0_1588_INT_B); 207 ret = HNS3_VECTOR0_EVENT_PTP; 208 goto out; 209 } 210 211 /* check for vector0 msix event source */ 212 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK || 213 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) { 214 val = vector0_int_stats | hw_err_src_reg; 215 ret = HNS3_VECTOR0_EVENT_ERR; 216 goto out; 217 } 218 219 /* check for vector0 mailbox(=CMDQ RX) event source */ 220 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { 221 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 222 val = cmdq_src_val; 223 ret = HNS3_VECTOR0_EVENT_MBX; 224 goto out; 225 } 226 227 val = vector0_int_stats; 228 ret = HNS3_VECTOR0_EVENT_OTHER; 229 out: 230 231 if (clearval) 232 *clearval = val; 233 return ret; 234 } 235 236 static bool 237 hns3_is_1588_event_type(uint32_t event_type) 238 { 239 return (event_type == HNS3_VECTOR0_EVENT_PTP); 240 } 241 242 static void 243 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) 244 { 245 if (event_type == HNS3_VECTOR0_EVENT_RST || 246 hns3_is_1588_event_type(event_type)) 247 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); 248 else if (event_type == HNS3_VECTOR0_EVENT_MBX) 249 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 250 } 251 252 static void 253 hns3_clear_all_event_cause(struct hns3_hw *hw) 254 { 255 uint32_t vector0_int_stats; 256 257 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 258 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) 259 hns3_warn(hw, "Probe during IMP reset interrupt"); 260 261 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) 262 hns3_warn(hw, "Probe during Global reset interrupt"); 263 264 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST, 265 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | 266 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | 267 BIT(HNS3_VECTOR0_CORERESET_INT_B)); 268 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); 269 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP, 270 BIT(HNS3_VECTOR0_1588_INT_B)); 271 } 272 273 static void 274 hns3_handle_mac_tnl(struct hns3_hw *hw) 275 { 276 struct hns3_cmd_desc desc; 277 uint32_t status; 278 int ret; 279 280 /* query and clear mac tnl interrupt */ 281 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true); 282 ret = hns3_cmd_send(hw, &desc, 1); 283 if (ret) { 284 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret); 285 return; 286 } 287 288 status = rte_le_to_cpu_32(desc.data[0]); 289 if (status) { 290 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status); 291 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT, 292 false); 293 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR); 294 ret = hns3_cmd_send(hw, &desc, 1); 295 if (ret) 296 hns3_err(hw, "failed to clear mac tnl int, ret = %d.", 297 ret); 298 } 299 } 300 301 static void 302 hns3_interrupt_handler(void *param) 303 { 304 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 305 struct hns3_adapter *hns = dev->data->dev_private; 306 struct hns3_hw *hw = &hns->hw; 307 enum hns3_evt_cause event_cause; 308 uint32_t clearval = 0; 309 uint32_t vector0_int; 310 uint32_t ras_int; 311 uint32_t cmdq_int; 312 313 /* Disable interrupt */ 314 hns3_pf_disable_irq0(hw); 315 316 event_cause = hns3_check_event_cause(hns, &clearval); 317 vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 318 ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 319 cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 320 /* vector 0 interrupt is shared with reset and mailbox source events. */ 321 if (event_cause == HNS3_VECTOR0_EVENT_ERR) { 322 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x " 323 "ras_int_stat:0x%x cmdq_int_stat:0x%x", 324 vector0_int, ras_int, cmdq_int); 325 hns3_handle_mac_tnl(hw); 326 hns3_handle_error(hns); 327 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) { 328 hns3_warn(hw, "received reset interrupt"); 329 hns3_schedule_reset(hns); 330 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) { 331 hns3_dev_handle_mbx_msg(hw); 332 } else { 333 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x " 334 "ras_int_stat:0x%x cmdq_int_stat:0x%x", 335 vector0_int, ras_int, cmdq_int); 336 } 337 338 hns3_clear_event_cause(hw, event_cause, clearval); 339 /* Enable interrupt if it is not cause by reset */ 340 hns3_pf_enable_irq0(hw); 341 } 342 343 static int 344 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on) 345 { 346 #define HNS3_VLAN_ID_OFFSET_STEP 160 347 #define HNS3_VLAN_BYTE_SIZE 8 348 struct hns3_vlan_filter_pf_cfg_cmd *req; 349 struct hns3_hw *hw = &hns->hw; 350 uint8_t vlan_offset_byte_val; 351 struct hns3_cmd_desc desc; 352 uint8_t vlan_offset_byte; 353 uint8_t vlan_offset_base; 354 int ret; 355 356 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false); 357 358 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP; 359 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) / 360 HNS3_VLAN_BYTE_SIZE; 361 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE); 362 363 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data; 364 req->vlan_offset = vlan_offset_base; 365 req->vlan_cfg = on ? 0 : 1; 366 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 367 368 ret = hns3_cmd_send(hw, &desc, 1); 369 if (ret) 370 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d", 371 vlan_id, ret); 372 373 return ret; 374 } 375 376 static void 377 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id) 378 { 379 struct hns3_user_vlan_table *vlan_entry; 380 struct hns3_pf *pf = &hns->pf; 381 382 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 383 if (vlan_entry->vlan_id == vlan_id) { 384 if (vlan_entry->hd_tbl_status) 385 hns3_set_port_vlan_filter(hns, vlan_id, 0); 386 LIST_REMOVE(vlan_entry, next); 387 rte_free(vlan_entry); 388 break; 389 } 390 } 391 } 392 393 static void 394 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id, 395 bool writen_to_tbl) 396 { 397 struct hns3_user_vlan_table *vlan_entry; 398 struct hns3_hw *hw = &hns->hw; 399 struct hns3_pf *pf = &hns->pf; 400 401 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 402 if (vlan_entry->vlan_id == vlan_id) 403 return; 404 } 405 406 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0); 407 if (vlan_entry == NULL) { 408 hns3_err(hw, "Failed to malloc hns3 vlan table"); 409 return; 410 } 411 412 vlan_entry->hd_tbl_status = writen_to_tbl; 413 vlan_entry->vlan_id = vlan_id; 414 415 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next); 416 } 417 418 static int 419 hns3_restore_vlan_table(struct hns3_adapter *hns) 420 { 421 struct hns3_user_vlan_table *vlan_entry; 422 struct hns3_hw *hw = &hns->hw; 423 struct hns3_pf *pf = &hns->pf; 424 uint16_t vlan_id; 425 int ret = 0; 426 427 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) 428 return hns3_vlan_pvid_configure(hns, 429 hw->port_base_vlan_cfg.pvid, 1); 430 431 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 432 if (vlan_entry->hd_tbl_status) { 433 vlan_id = vlan_entry->vlan_id; 434 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1); 435 if (ret) 436 break; 437 } 438 } 439 440 return ret; 441 } 442 443 static int 444 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 445 { 446 struct hns3_hw *hw = &hns->hw; 447 bool writen_to_tbl = false; 448 int ret = 0; 449 450 /* 451 * When vlan filter is enabled, hardware regards packets without vlan 452 * as packets with vlan 0. So, to receive packets without vlan, vlan id 453 * 0 is not allowed to be removed by rte_eth_dev_vlan_filter. 454 */ 455 if (on == 0 && vlan_id == 0) 456 return 0; 457 458 /* 459 * When port base vlan enabled, we use port base vlan as the vlan 460 * filter condition. In this case, we don't update vlan filter table 461 * when user add new vlan or remove exist vlan, just update the 462 * vlan list. The vlan id in vlan list will be written in vlan filter 463 * table until port base vlan disabled 464 */ 465 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 466 ret = hns3_set_port_vlan_filter(hns, vlan_id, on); 467 writen_to_tbl = true; 468 } 469 470 if (ret == 0) { 471 if (on) 472 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl); 473 else 474 hns3_rm_dev_vlan_table(hns, vlan_id); 475 } 476 return ret; 477 } 478 479 static int 480 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 481 { 482 struct hns3_adapter *hns = dev->data->dev_private; 483 struct hns3_hw *hw = &hns->hw; 484 int ret; 485 486 rte_spinlock_lock(&hw->lock); 487 ret = hns3_vlan_filter_configure(hns, vlan_id, on); 488 rte_spinlock_unlock(&hw->lock); 489 return ret; 490 } 491 492 static int 493 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type, 494 uint16_t tpid) 495 { 496 struct hns3_rx_vlan_type_cfg_cmd *rx_req; 497 struct hns3_tx_vlan_type_cfg_cmd *tx_req; 498 struct hns3_hw *hw = &hns->hw; 499 struct hns3_cmd_desc desc; 500 int ret; 501 502 if ((vlan_type != ETH_VLAN_TYPE_INNER && 503 vlan_type != ETH_VLAN_TYPE_OUTER)) { 504 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type); 505 return -EINVAL; 506 } 507 508 if (tpid != RTE_ETHER_TYPE_VLAN) { 509 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type); 510 return -EINVAL; 511 } 512 513 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false); 514 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data; 515 516 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 517 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 518 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 519 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 520 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 521 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 522 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid); 523 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid); 524 } 525 526 ret = hns3_cmd_send(hw, &desc, 1); 527 if (ret) { 528 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d", 529 ret); 530 return ret; 531 } 532 533 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false); 534 535 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data; 536 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid); 537 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid); 538 539 ret = hns3_cmd_send(hw, &desc, 1); 540 if (ret) 541 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d", 542 ret); 543 return ret; 544 } 545 546 static int 547 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 548 uint16_t tpid) 549 { 550 struct hns3_adapter *hns = dev->data->dev_private; 551 struct hns3_hw *hw = &hns->hw; 552 int ret; 553 554 rte_spinlock_lock(&hw->lock); 555 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid); 556 rte_spinlock_unlock(&hw->lock); 557 return ret; 558 } 559 560 static int 561 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns, 562 struct hns3_rx_vtag_cfg *vcfg) 563 { 564 struct hns3_vport_vtag_rx_cfg_cmd *req; 565 struct hns3_hw *hw = &hns->hw; 566 struct hns3_cmd_desc desc; 567 uint16_t vport_id; 568 uint8_t bitmap; 569 int ret; 570 571 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false); 572 573 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data; 574 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B, 575 vcfg->strip_tag1_en ? 1 : 0); 576 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B, 577 vcfg->strip_tag2_en ? 1 : 0); 578 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B, 579 vcfg->vlan1_vlan_prionly ? 1 : 0); 580 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B, 581 vcfg->vlan2_vlan_prionly ? 1 : 0); 582 583 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */ 584 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B, 585 vcfg->strip_tag1_discard_en ? 1 : 0); 586 hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B, 587 vcfg->strip_tag2_discard_en ? 1 : 0); 588 /* 589 * In current version VF is not supported when PF is driven by DPDK 590 * driver, just need to configure parameters for PF vport. 591 */ 592 vport_id = HNS3_PF_FUNC_ID; 593 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 594 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 595 req->vf_bitmap[req->vf_offset] = bitmap; 596 597 ret = hns3_cmd_send(hw, &desc, 1); 598 if (ret) 599 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret); 600 return ret; 601 } 602 603 static void 604 hns3_update_rx_offload_cfg(struct hns3_adapter *hns, 605 struct hns3_rx_vtag_cfg *vcfg) 606 { 607 struct hns3_pf *pf = &hns->pf; 608 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg)); 609 } 610 611 static void 612 hns3_update_tx_offload_cfg(struct hns3_adapter *hns, 613 struct hns3_tx_vtag_cfg *vcfg) 614 { 615 struct hns3_pf *pf = &hns->pf; 616 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg)); 617 } 618 619 static int 620 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable) 621 { 622 struct hns3_rx_vtag_cfg rxvlan_cfg; 623 struct hns3_hw *hw = &hns->hw; 624 int ret; 625 626 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 627 rxvlan_cfg.strip_tag1_en = false; 628 rxvlan_cfg.strip_tag2_en = enable; 629 rxvlan_cfg.strip_tag2_discard_en = false; 630 } else { 631 rxvlan_cfg.strip_tag1_en = enable; 632 rxvlan_cfg.strip_tag2_en = true; 633 rxvlan_cfg.strip_tag2_discard_en = true; 634 } 635 636 rxvlan_cfg.strip_tag1_discard_en = false; 637 rxvlan_cfg.vlan1_vlan_prionly = false; 638 rxvlan_cfg.vlan2_vlan_prionly = false; 639 rxvlan_cfg.rx_vlan_offload_en = enable; 640 641 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg); 642 if (ret) { 643 hns3_err(hw, "%s strip rx vtag failed, ret = %d.", 644 enable ? "enable" : "disable", ret); 645 return ret; 646 } 647 648 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg); 649 650 return ret; 651 } 652 653 static int 654 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type, 655 uint8_t fe_type, bool filter_en, uint8_t vf_id) 656 { 657 struct hns3_vlan_filter_ctrl_cmd *req; 658 struct hns3_cmd_desc desc; 659 int ret; 660 661 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false); 662 663 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data; 664 req->vlan_type = vlan_type; 665 req->vlan_fe = filter_en ? fe_type : 0; 666 req->vf_id = vf_id; 667 668 ret = hns3_cmd_send(hw, &desc, 1); 669 if (ret) 670 hns3_err(hw, "set vlan filter fail, ret =%d", ret); 671 672 return ret; 673 } 674 675 static int 676 hns3_vlan_filter_init(struct hns3_adapter *hns) 677 { 678 struct hns3_hw *hw = &hns->hw; 679 int ret; 680 681 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF, 682 HNS3_FILTER_FE_EGRESS, false, 683 HNS3_PF_FUNC_ID); 684 if (ret) { 685 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret); 686 return ret; 687 } 688 689 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 690 HNS3_FILTER_FE_INGRESS, false, 691 HNS3_PF_FUNC_ID); 692 if (ret) 693 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret); 694 695 return ret; 696 } 697 698 static int 699 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable) 700 { 701 struct hns3_hw *hw = &hns->hw; 702 int ret; 703 704 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 705 HNS3_FILTER_FE_INGRESS, enable, 706 HNS3_PF_FUNC_ID); 707 if (ret) 708 hns3_err(hw, "failed to %s port vlan filter, ret = %d", 709 enable ? "enable" : "disable", ret); 710 711 return ret; 712 } 713 714 static int 715 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask) 716 { 717 struct hns3_adapter *hns = dev->data->dev_private; 718 struct hns3_hw *hw = &hns->hw; 719 struct rte_eth_rxmode *rxmode; 720 unsigned int tmp_mask; 721 bool enable; 722 int ret = 0; 723 724 rte_spinlock_lock(&hw->lock); 725 rxmode = &dev->data->dev_conf.rxmode; 726 tmp_mask = (unsigned int)mask; 727 if (tmp_mask & ETH_VLAN_FILTER_MASK) { 728 /* ignore vlan filter configuration during promiscuous mode */ 729 if (!dev->data->promiscuous) { 730 /* Enable or disable VLAN filter */ 731 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? 732 true : false; 733 734 ret = hns3_enable_vlan_filter(hns, enable); 735 if (ret) { 736 rte_spinlock_unlock(&hw->lock); 737 hns3_err(hw, "failed to %s rx filter, ret = %d", 738 enable ? "enable" : "disable", ret); 739 return ret; 740 } 741 } 742 } 743 744 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 745 /* Enable or disable VLAN stripping */ 746 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? 747 true : false; 748 749 ret = hns3_en_hw_strip_rxvtag(hns, enable); 750 if (ret) { 751 rte_spinlock_unlock(&hw->lock); 752 hns3_err(hw, "failed to %s rx strip, ret = %d", 753 enable ? "enable" : "disable", ret); 754 return ret; 755 } 756 } 757 758 rte_spinlock_unlock(&hw->lock); 759 760 return ret; 761 } 762 763 static int 764 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns, 765 struct hns3_tx_vtag_cfg *vcfg) 766 { 767 struct hns3_vport_vtag_tx_cfg_cmd *req; 768 struct hns3_cmd_desc desc; 769 struct hns3_hw *hw = &hns->hw; 770 uint16_t vport_id; 771 uint8_t bitmap; 772 int ret; 773 774 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false); 775 776 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data; 777 req->def_vlan_tag1 = vcfg->default_tag1; 778 req->def_vlan_tag2 = vcfg->default_tag2; 779 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B, 780 vcfg->accept_tag1 ? 1 : 0); 781 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B, 782 vcfg->accept_untag1 ? 1 : 0); 783 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B, 784 vcfg->accept_tag2 ? 1 : 0); 785 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B, 786 vcfg->accept_untag2 ? 1 : 0); 787 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B, 788 vcfg->insert_tag1_en ? 1 : 0); 789 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B, 790 vcfg->insert_tag2_en ? 1 : 0); 791 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0); 792 793 /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */ 794 hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B, 795 vcfg->tag_shift_mode_en ? 1 : 0); 796 797 /* 798 * In current version VF is not supported when PF is driven by DPDK 799 * driver, just need to configure parameters for PF vport. 800 */ 801 vport_id = HNS3_PF_FUNC_ID; 802 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 803 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 804 req->vf_bitmap[req->vf_offset] = bitmap; 805 806 ret = hns3_cmd_send(hw, &desc, 1); 807 if (ret) 808 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret); 809 810 return ret; 811 } 812 813 static int 814 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state, 815 uint16_t pvid) 816 { 817 struct hns3_hw *hw = &hns->hw; 818 struct hns3_tx_vtag_cfg txvlan_cfg; 819 int ret; 820 821 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) { 822 txvlan_cfg.accept_tag1 = true; 823 txvlan_cfg.insert_tag1_en = false; 824 txvlan_cfg.default_tag1 = 0; 825 } else { 826 txvlan_cfg.accept_tag1 = 827 hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE; 828 txvlan_cfg.insert_tag1_en = true; 829 txvlan_cfg.default_tag1 = pvid; 830 } 831 832 txvlan_cfg.accept_untag1 = true; 833 txvlan_cfg.accept_tag2 = true; 834 txvlan_cfg.accept_untag2 = true; 835 txvlan_cfg.insert_tag2_en = false; 836 txvlan_cfg.default_tag2 = 0; 837 txvlan_cfg.tag_shift_mode_en = true; 838 839 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg); 840 if (ret) { 841 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid, 842 ret); 843 return ret; 844 } 845 846 hns3_update_tx_offload_cfg(hns, &txvlan_cfg); 847 return ret; 848 } 849 850 851 static void 852 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list) 853 { 854 struct hns3_user_vlan_table *vlan_entry; 855 struct hns3_pf *pf = &hns->pf; 856 857 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 858 if (vlan_entry->hd_tbl_status) { 859 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0); 860 vlan_entry->hd_tbl_status = false; 861 } 862 } 863 864 if (is_del_list) { 865 vlan_entry = LIST_FIRST(&pf->vlan_list); 866 while (vlan_entry) { 867 LIST_REMOVE(vlan_entry, next); 868 rte_free(vlan_entry); 869 vlan_entry = LIST_FIRST(&pf->vlan_list); 870 } 871 } 872 } 873 874 static void 875 hns3_add_all_vlan_table(struct hns3_adapter *hns) 876 { 877 struct hns3_user_vlan_table *vlan_entry; 878 struct hns3_pf *pf = &hns->pf; 879 880 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 881 if (!vlan_entry->hd_tbl_status) { 882 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1); 883 vlan_entry->hd_tbl_status = true; 884 } 885 } 886 } 887 888 static void 889 hns3_remove_all_vlan_table(struct hns3_adapter *hns) 890 { 891 struct hns3_hw *hw = &hns->hw; 892 int ret; 893 894 hns3_rm_all_vlan_table(hns, true); 895 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) { 896 ret = hns3_set_port_vlan_filter(hns, 897 hw->port_base_vlan_cfg.pvid, 0); 898 if (ret) { 899 hns3_err(hw, "Failed to remove all vlan table, ret =%d", 900 ret); 901 return; 902 } 903 } 904 } 905 906 static int 907 hns3_update_vlan_filter_entries(struct hns3_adapter *hns, 908 uint16_t port_base_vlan_state, uint16_t new_pvid) 909 { 910 struct hns3_hw *hw = &hns->hw; 911 uint16_t old_pvid; 912 int ret; 913 914 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) { 915 old_pvid = hw->port_base_vlan_cfg.pvid; 916 if (old_pvid != HNS3_INVALID_PVID) { 917 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0); 918 if (ret) { 919 hns3_err(hw, "failed to remove old pvid %u, " 920 "ret = %d", old_pvid, ret); 921 return ret; 922 } 923 } 924 925 hns3_rm_all_vlan_table(hns, false); 926 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1); 927 if (ret) { 928 hns3_err(hw, "failed to add new pvid %u, ret = %d", 929 new_pvid, ret); 930 return ret; 931 } 932 } else { 933 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0); 934 if (ret) { 935 hns3_err(hw, "failed to remove pvid %u, ret = %d", 936 new_pvid, ret); 937 return ret; 938 } 939 940 hns3_add_all_vlan_table(hns); 941 } 942 return 0; 943 } 944 945 static int 946 hns3_en_pvid_strip(struct hns3_adapter *hns, int on) 947 { 948 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg; 949 struct hns3_rx_vtag_cfg rx_vlan_cfg; 950 bool rx_strip_en; 951 int ret; 952 953 rx_strip_en = old_cfg->rx_vlan_offload_en; 954 if (on) { 955 rx_vlan_cfg.strip_tag1_en = rx_strip_en; 956 rx_vlan_cfg.strip_tag2_en = true; 957 rx_vlan_cfg.strip_tag2_discard_en = true; 958 } else { 959 rx_vlan_cfg.strip_tag1_en = false; 960 rx_vlan_cfg.strip_tag2_en = rx_strip_en; 961 rx_vlan_cfg.strip_tag2_discard_en = false; 962 } 963 rx_vlan_cfg.strip_tag1_discard_en = false; 964 rx_vlan_cfg.vlan1_vlan_prionly = false; 965 rx_vlan_cfg.vlan2_vlan_prionly = false; 966 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en; 967 968 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg); 969 if (ret) 970 return ret; 971 972 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg); 973 return ret; 974 } 975 976 static int 977 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on) 978 { 979 struct hns3_hw *hw = &hns->hw; 980 uint16_t port_base_vlan_state; 981 int ret, err; 982 983 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) { 984 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) 985 hns3_warn(hw, "Invalid operation! As current pvid set " 986 "is %u, disable pvid %u is invalid", 987 hw->port_base_vlan_cfg.pvid, pvid); 988 return 0; 989 } 990 991 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE : 992 HNS3_PORT_BASE_VLAN_DISABLE; 993 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid); 994 if (ret) { 995 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d", 996 ret); 997 return ret; 998 } 999 1000 ret = hns3_en_pvid_strip(hns, on); 1001 if (ret) { 1002 hns3_err(hw, "failed to config rx vlan strip for pvid, " 1003 "ret = %d", ret); 1004 goto pvid_vlan_strip_fail; 1005 } 1006 1007 if (pvid == HNS3_INVALID_PVID) 1008 goto out; 1009 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid); 1010 if (ret) { 1011 hns3_err(hw, "failed to update vlan filter entries, ret = %d", 1012 ret); 1013 goto vlan_filter_set_fail; 1014 } 1015 1016 out: 1017 hw->port_base_vlan_cfg.state = port_base_vlan_state; 1018 hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID; 1019 return ret; 1020 1021 vlan_filter_set_fail: 1022 err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state == 1023 HNS3_PORT_BASE_VLAN_ENABLE); 1024 if (err) 1025 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err); 1026 1027 pvid_vlan_strip_fail: 1028 err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state, 1029 hw->port_base_vlan_cfg.pvid); 1030 if (err) 1031 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err); 1032 1033 return ret; 1034 } 1035 1036 static int 1037 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 1038 { 1039 struct hns3_adapter *hns = dev->data->dev_private; 1040 struct hns3_hw *hw = &hns->hw; 1041 bool pvid_en_state_change; 1042 uint16_t pvid_state; 1043 int ret; 1044 1045 if (pvid > RTE_ETHER_MAX_VLAN_ID) { 1046 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid, 1047 RTE_ETHER_MAX_VLAN_ID); 1048 return -EINVAL; 1049 } 1050 1051 /* 1052 * If PVID configuration state change, should refresh the PVID 1053 * configuration state in struct hns3_tx_queue/hns3_rx_queue. 1054 */ 1055 pvid_state = hw->port_base_vlan_cfg.state; 1056 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) || 1057 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE)) 1058 pvid_en_state_change = false; 1059 else 1060 pvid_en_state_change = true; 1061 1062 rte_spinlock_lock(&hw->lock); 1063 ret = hns3_vlan_pvid_configure(hns, pvid, on); 1064 rte_spinlock_unlock(&hw->lock); 1065 if (ret) 1066 return ret; 1067 /* 1068 * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx 1069 * need be processed by PMD driver. 1070 */ 1071 if (pvid_en_state_change && 1072 hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE) 1073 hns3_update_all_queues_pvid_proc_en(hw); 1074 1075 return 0; 1076 } 1077 1078 static int 1079 hns3_default_vlan_config(struct hns3_adapter *hns) 1080 { 1081 struct hns3_hw *hw = &hns->hw; 1082 int ret; 1083 1084 /* 1085 * When vlan filter is enabled, hardware regards packets without vlan 1086 * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan 1087 * table, packets without vlan won't be received. So, add vlan 0 as 1088 * the default vlan. 1089 */ 1090 ret = hns3_vlan_filter_configure(hns, 0, 1); 1091 if (ret) 1092 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret); 1093 return ret; 1094 } 1095 1096 static int 1097 hns3_init_vlan_config(struct hns3_adapter *hns) 1098 { 1099 struct hns3_hw *hw = &hns->hw; 1100 int ret; 1101 1102 /* 1103 * This function can be called in the initialization and reset process, 1104 * when in reset process, it means that hardware had been reseted 1105 * successfully and we need to restore the hardware configuration to 1106 * ensure that the hardware configuration remains unchanged before and 1107 * after reset. 1108 */ 1109 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 1110 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE; 1111 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID; 1112 } 1113 1114 ret = hns3_vlan_filter_init(hns); 1115 if (ret) { 1116 hns3_err(hw, "vlan init fail in pf, ret =%d", ret); 1117 return ret; 1118 } 1119 1120 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER, 1121 RTE_ETHER_TYPE_VLAN); 1122 if (ret) { 1123 hns3_err(hw, "tpid set fail in pf, ret =%d", ret); 1124 return ret; 1125 } 1126 1127 /* 1128 * When in the reinit dev stage of the reset process, the following 1129 * vlan-related configurations may differ from those at initialization, 1130 * we will restore configurations to hardware in hns3_restore_vlan_table 1131 * and hns3_restore_vlan_conf later. 1132 */ 1133 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 1134 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0); 1135 if (ret) { 1136 hns3_err(hw, "pvid set fail in pf, ret =%d", ret); 1137 return ret; 1138 } 1139 1140 ret = hns3_en_hw_strip_rxvtag(hns, false); 1141 if (ret) { 1142 hns3_err(hw, "rx strip configure fail in pf, ret =%d", 1143 ret); 1144 return ret; 1145 } 1146 } 1147 1148 return hns3_default_vlan_config(hns); 1149 } 1150 1151 static int 1152 hns3_restore_vlan_conf(struct hns3_adapter *hns) 1153 { 1154 struct hns3_pf *pf = &hns->pf; 1155 struct hns3_hw *hw = &hns->hw; 1156 uint64_t offloads; 1157 bool enable; 1158 int ret; 1159 1160 if (!hw->data->promiscuous) { 1161 /* restore vlan filter states */ 1162 offloads = hw->data->dev_conf.rxmode.offloads; 1163 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false; 1164 ret = hns3_enable_vlan_filter(hns, enable); 1165 if (ret) { 1166 hns3_err(hw, "failed to restore vlan rx filter conf, " 1167 "ret = %d", ret); 1168 return ret; 1169 } 1170 } 1171 1172 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg); 1173 if (ret) { 1174 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret); 1175 return ret; 1176 } 1177 1178 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg); 1179 if (ret) 1180 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret); 1181 1182 return ret; 1183 } 1184 1185 static int 1186 hns3_dev_configure_vlan(struct rte_eth_dev *dev) 1187 { 1188 struct hns3_adapter *hns = dev->data->dev_private; 1189 struct rte_eth_dev_data *data = dev->data; 1190 struct rte_eth_txmode *txmode; 1191 struct hns3_hw *hw = &hns->hw; 1192 int mask; 1193 int ret; 1194 1195 txmode = &data->dev_conf.txmode; 1196 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged) 1197 hns3_warn(hw, 1198 "hw_vlan_reject_tagged or hw_vlan_reject_untagged " 1199 "configuration is not supported! Ignore these two " 1200 "parameters: hw_vlan_reject_tagged(%u), " 1201 "hw_vlan_reject_untagged(%u)", 1202 txmode->hw_vlan_reject_tagged, 1203 txmode->hw_vlan_reject_untagged); 1204 1205 /* Apply vlan offload setting */ 1206 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK; 1207 ret = hns3_vlan_offload_set(dev, mask); 1208 if (ret) { 1209 hns3_err(hw, "dev config rx vlan offload failed, ret = %d", 1210 ret); 1211 return ret; 1212 } 1213 1214 /* 1215 * If pvid config is not set in rte_eth_conf, driver needn't to set 1216 * VLAN pvid related configuration to hardware. 1217 */ 1218 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0) 1219 return 0; 1220 1221 /* Apply pvid setting */ 1222 ret = hns3_vlan_pvid_set(dev, txmode->pvid, 1223 txmode->hw_vlan_insert_pvid); 1224 if (ret) 1225 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d", 1226 txmode->pvid, ret); 1227 1228 return ret; 1229 } 1230 1231 static int 1232 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, 1233 unsigned int tso_mss_max) 1234 { 1235 struct hns3_cfg_tso_status_cmd *req; 1236 struct hns3_cmd_desc desc; 1237 uint16_t tso_mss; 1238 1239 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false); 1240 1241 req = (struct hns3_cfg_tso_status_cmd *)desc.data; 1242 1243 tso_mss = 0; 1244 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1245 tso_mss_min); 1246 req->tso_mss_min = rte_cpu_to_le_16(tso_mss); 1247 1248 tso_mss = 0; 1249 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1250 tso_mss_max); 1251 req->tso_mss_max = rte_cpu_to_le_16(tso_mss); 1252 1253 return hns3_cmd_send(hw, &desc, 1); 1254 } 1255 1256 static int 1257 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size, 1258 uint16_t *allocated_size, bool is_alloc) 1259 { 1260 struct hns3_umv_spc_alc_cmd *req; 1261 struct hns3_cmd_desc desc; 1262 int ret; 1263 1264 req = (struct hns3_umv_spc_alc_cmd *)desc.data; 1265 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false); 1266 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1); 1267 req->space_size = rte_cpu_to_le_32(space_size); 1268 1269 ret = hns3_cmd_send(hw, &desc, 1); 1270 if (ret) { 1271 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d", 1272 is_alloc ? "allocate" : "free", ret); 1273 return ret; 1274 } 1275 1276 if (is_alloc && allocated_size) 1277 *allocated_size = rte_le_to_cpu_32(desc.data[1]); 1278 1279 return 0; 1280 } 1281 1282 static int 1283 hns3_init_umv_space(struct hns3_hw *hw) 1284 { 1285 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1286 struct hns3_pf *pf = &hns->pf; 1287 uint16_t allocated_size = 0; 1288 int ret; 1289 1290 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size, 1291 true); 1292 if (ret) 1293 return ret; 1294 1295 if (allocated_size < pf->wanted_umv_size) 1296 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u", 1297 pf->wanted_umv_size, allocated_size); 1298 1299 pf->max_umv_size = (!!allocated_size) ? allocated_size : 1300 pf->wanted_umv_size; 1301 pf->used_umv_size = 0; 1302 return 0; 1303 } 1304 1305 static int 1306 hns3_uninit_umv_space(struct hns3_hw *hw) 1307 { 1308 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1309 struct hns3_pf *pf = &hns->pf; 1310 int ret; 1311 1312 if (pf->max_umv_size == 0) 1313 return 0; 1314 1315 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false); 1316 if (ret) 1317 return ret; 1318 1319 pf->max_umv_size = 0; 1320 1321 return 0; 1322 } 1323 1324 static bool 1325 hns3_is_umv_space_full(struct hns3_hw *hw) 1326 { 1327 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1328 struct hns3_pf *pf = &hns->pf; 1329 bool is_full; 1330 1331 is_full = (pf->used_umv_size >= pf->max_umv_size); 1332 1333 return is_full; 1334 } 1335 1336 static void 1337 hns3_update_umv_space(struct hns3_hw *hw, bool is_free) 1338 { 1339 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1340 struct hns3_pf *pf = &hns->pf; 1341 1342 if (is_free) { 1343 if (pf->used_umv_size > 0) 1344 pf->used_umv_size--; 1345 } else 1346 pf->used_umv_size++; 1347 } 1348 1349 static void 1350 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req, 1351 const uint8_t *addr, bool is_mc) 1352 { 1353 const unsigned char *mac_addr = addr; 1354 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) | 1355 ((uint32_t)mac_addr[2] << 16) | 1356 ((uint32_t)mac_addr[1] << 8) | 1357 (uint32_t)mac_addr[0]; 1358 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4]; 1359 1360 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1361 if (is_mc) { 1362 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1363 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1); 1364 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1365 } 1366 1367 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val); 1368 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff); 1369 } 1370 1371 static int 1372 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp, 1373 uint8_t resp_code, 1374 enum hns3_mac_vlan_tbl_opcode op) 1375 { 1376 if (cmdq_resp) { 1377 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u", 1378 cmdq_resp); 1379 return -EIO; 1380 } 1381 1382 if (op == HNS3_MAC_VLAN_ADD) { 1383 if (resp_code == 0 || resp_code == 1) { 1384 return 0; 1385 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) { 1386 hns3_err(hw, "add mac addr failed for uc_overflow"); 1387 return -ENOSPC; 1388 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) { 1389 hns3_err(hw, "add mac addr failed for mc_overflow"); 1390 return -ENOSPC; 1391 } 1392 1393 hns3_err(hw, "add mac addr failed for undefined, code=%u", 1394 resp_code); 1395 return -EIO; 1396 } else if (op == HNS3_MAC_VLAN_REMOVE) { 1397 if (resp_code == 0) { 1398 return 0; 1399 } else if (resp_code == 1) { 1400 hns3_dbg(hw, "remove mac addr failed for miss"); 1401 return -ENOENT; 1402 } 1403 1404 hns3_err(hw, "remove mac addr failed for undefined, code=%u", 1405 resp_code); 1406 return -EIO; 1407 } else if (op == HNS3_MAC_VLAN_LKUP) { 1408 if (resp_code == 0) { 1409 return 0; 1410 } else if (resp_code == 1) { 1411 hns3_dbg(hw, "lookup mac addr failed for miss"); 1412 return -ENOENT; 1413 } 1414 1415 hns3_err(hw, "lookup mac addr failed for undefined, code=%u", 1416 resp_code); 1417 return -EIO; 1418 } 1419 1420 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u", 1421 op); 1422 1423 return -EINVAL; 1424 } 1425 1426 static int 1427 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw, 1428 struct hns3_mac_vlan_tbl_entry_cmd *req, 1429 struct hns3_cmd_desc *desc, bool is_mc) 1430 { 1431 uint8_t resp_code; 1432 uint16_t retval; 1433 int ret; 1434 1435 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true); 1436 if (is_mc) { 1437 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1438 memcpy(desc[0].data, req, 1439 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1440 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD, 1441 true); 1442 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1443 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD, 1444 true); 1445 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1446 } else { 1447 memcpy(desc[0].data, req, 1448 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1449 ret = hns3_cmd_send(hw, desc, 1); 1450 } 1451 if (ret) { 1452 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.", 1453 ret); 1454 return ret; 1455 } 1456 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1457 retval = rte_le_to_cpu_16(desc[0].retval); 1458 1459 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1460 HNS3_MAC_VLAN_LKUP); 1461 } 1462 1463 static int 1464 hns3_add_mac_vlan_tbl(struct hns3_hw *hw, 1465 struct hns3_mac_vlan_tbl_entry_cmd *req, 1466 struct hns3_cmd_desc *mc_desc) 1467 { 1468 uint8_t resp_code; 1469 uint16_t retval; 1470 int cfg_status; 1471 int ret; 1472 1473 if (mc_desc == NULL) { 1474 struct hns3_cmd_desc desc; 1475 1476 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false); 1477 memcpy(desc.data, req, 1478 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1479 ret = hns3_cmd_send(hw, &desc, 1); 1480 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1481 retval = rte_le_to_cpu_16(desc.retval); 1482 1483 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1484 HNS3_MAC_VLAN_ADD); 1485 } else { 1486 hns3_cmd_reuse_desc(&mc_desc[0], false); 1487 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1488 hns3_cmd_reuse_desc(&mc_desc[1], false); 1489 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1490 hns3_cmd_reuse_desc(&mc_desc[2], false); 1491 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT); 1492 memcpy(mc_desc[0].data, req, 1493 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1494 mc_desc[0].retval = 0; 1495 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1496 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff; 1497 retval = rte_le_to_cpu_16(mc_desc[0].retval); 1498 1499 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1500 HNS3_MAC_VLAN_ADD); 1501 } 1502 1503 if (ret) { 1504 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret); 1505 return ret; 1506 } 1507 1508 return cfg_status; 1509 } 1510 1511 static int 1512 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw, 1513 struct hns3_mac_vlan_tbl_entry_cmd *req) 1514 { 1515 struct hns3_cmd_desc desc; 1516 uint8_t resp_code; 1517 uint16_t retval; 1518 int ret; 1519 1520 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false); 1521 1522 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1523 1524 ret = hns3_cmd_send(hw, &desc, 1); 1525 if (ret) { 1526 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret); 1527 return ret; 1528 } 1529 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1530 retval = rte_le_to_cpu_16(desc.retval); 1531 1532 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1533 HNS3_MAC_VLAN_REMOVE); 1534 } 1535 1536 static int 1537 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1538 { 1539 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1540 struct hns3_mac_vlan_tbl_entry_cmd req; 1541 struct hns3_pf *pf = &hns->pf; 1542 struct hns3_cmd_desc desc[3]; 1543 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1544 uint16_t egress_port = 0; 1545 uint8_t vf_id; 1546 int ret; 1547 1548 /* check if mac addr is valid */ 1549 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1550 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1551 mac_addr); 1552 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid", 1553 mac_str); 1554 return -EINVAL; 1555 } 1556 1557 memset(&req, 0, sizeof(req)); 1558 1559 /* 1560 * In current version VF is not supported when PF is driven by DPDK 1561 * driver, just need to configure parameters for PF vport. 1562 */ 1563 vf_id = HNS3_PF_FUNC_ID; 1564 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M, 1565 HNS3_MAC_EPORT_VFID_S, vf_id); 1566 1567 req.egress_port = rte_cpu_to_le_16(egress_port); 1568 1569 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1570 1571 /* 1572 * Lookup the mac address in the mac_vlan table, and add 1573 * it if the entry is inexistent. Repeated unicast entry 1574 * is not allowed in the mac vlan table. 1575 */ 1576 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false); 1577 if (ret == -ENOENT) { 1578 if (!hns3_is_umv_space_full(hw)) { 1579 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL); 1580 if (!ret) 1581 hns3_update_umv_space(hw, false); 1582 return ret; 1583 } 1584 1585 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size); 1586 1587 return -ENOSPC; 1588 } 1589 1590 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr); 1591 1592 /* check if we just hit the duplicate */ 1593 if (ret == 0) { 1594 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str); 1595 return 0; 1596 } 1597 1598 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table", 1599 mac_str); 1600 1601 return ret; 1602 } 1603 1604 static int 1605 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1606 { 1607 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1608 struct rte_ether_addr *addr; 1609 int ret; 1610 int i; 1611 1612 for (i = 0; i < hw->mc_addrs_num; i++) { 1613 addr = &hw->mc_addrs[i]; 1614 /* Check if there are duplicate addresses */ 1615 if (rte_is_same_ether_addr(addr, mac_addr)) { 1616 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1617 addr); 1618 hns3_err(hw, "failed to add mc mac addr, same addrs" 1619 "(%s) is added by the set_mc_mac_addr_list " 1620 "API", mac_str); 1621 return -EINVAL; 1622 } 1623 } 1624 1625 ret = hns3_add_mc_addr(hw, mac_addr); 1626 if (ret) { 1627 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1628 mac_addr); 1629 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 1630 mac_str, ret); 1631 } 1632 return ret; 1633 } 1634 1635 static int 1636 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1637 { 1638 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1639 int ret; 1640 1641 ret = hns3_remove_mc_addr(hw, mac_addr); 1642 if (ret) { 1643 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1644 mac_addr); 1645 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d", 1646 mac_str, ret); 1647 } 1648 return ret; 1649 } 1650 1651 static int 1652 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1653 uint32_t idx, __rte_unused uint32_t pool) 1654 { 1655 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1656 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1657 int ret; 1658 1659 rte_spinlock_lock(&hw->lock); 1660 1661 /* 1662 * In hns3 network engine adding UC and MC mac address with different 1663 * commands with firmware. We need to determine whether the input 1664 * address is a UC or a MC address to call different commands. 1665 * By the way, it is recommended calling the API function named 1666 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 1667 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 1668 * may affect the specifications of UC mac addresses. 1669 */ 1670 if (rte_is_multicast_ether_addr(mac_addr)) 1671 ret = hns3_add_mc_addr_common(hw, mac_addr); 1672 else 1673 ret = hns3_add_uc_addr_common(hw, mac_addr); 1674 1675 if (ret) { 1676 rte_spinlock_unlock(&hw->lock); 1677 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1678 mac_addr); 1679 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 1680 ret); 1681 return ret; 1682 } 1683 1684 if (idx == 0) 1685 hw->mac.default_addr_setted = true; 1686 rte_spinlock_unlock(&hw->lock); 1687 1688 return ret; 1689 } 1690 1691 static int 1692 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1693 { 1694 struct hns3_mac_vlan_tbl_entry_cmd req; 1695 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1696 int ret; 1697 1698 /* check if mac addr is valid */ 1699 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1700 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1701 mac_addr); 1702 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid", 1703 mac_str); 1704 return -EINVAL; 1705 } 1706 1707 memset(&req, 0, sizeof(req)); 1708 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1709 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1710 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1711 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */ 1712 return 0; 1713 else if (ret == 0) 1714 hns3_update_umv_space(hw, true); 1715 1716 return ret; 1717 } 1718 1719 static void 1720 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 1721 { 1722 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1723 /* index will be checked by upper level rte interface */ 1724 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 1725 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1726 int ret; 1727 1728 rte_spinlock_lock(&hw->lock); 1729 1730 if (rte_is_multicast_ether_addr(mac_addr)) 1731 ret = hns3_remove_mc_addr_common(hw, mac_addr); 1732 else 1733 ret = hns3_remove_uc_addr_common(hw, mac_addr); 1734 rte_spinlock_unlock(&hw->lock); 1735 if (ret) { 1736 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1737 mac_addr); 1738 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str, 1739 ret); 1740 } 1741 } 1742 1743 static int 1744 hns3_set_default_mac_addr(struct rte_eth_dev *dev, 1745 struct rte_ether_addr *mac_addr) 1746 { 1747 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1748 struct rte_ether_addr *oaddr; 1749 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1750 bool default_addr_setted; 1751 bool rm_succes = false; 1752 int ret, ret_val; 1753 1754 /* 1755 * It has been guaranteed that input parameter named mac_addr is valid 1756 * address in the rte layer of DPDK framework. 1757 */ 1758 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr; 1759 default_addr_setted = hw->mac.default_addr_setted; 1760 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr)) 1761 return 0; 1762 1763 rte_spinlock_lock(&hw->lock); 1764 if (default_addr_setted) { 1765 ret = hns3_remove_uc_addr_common(hw, oaddr); 1766 if (ret) { 1767 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1768 oaddr); 1769 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d", 1770 mac_str, ret); 1771 rm_succes = false; 1772 } else 1773 rm_succes = true; 1774 } 1775 1776 ret = hns3_add_uc_addr_common(hw, mac_addr); 1777 if (ret) { 1778 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1779 mac_addr); 1780 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret); 1781 goto err_add_uc_addr; 1782 } 1783 1784 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes); 1785 if (ret) { 1786 hns3_err(hw, "Failed to configure mac pause address: %d", ret); 1787 goto err_pause_addr_cfg; 1788 } 1789 1790 rte_ether_addr_copy(mac_addr, 1791 (struct rte_ether_addr *)hw->mac.mac_addr); 1792 hw->mac.default_addr_setted = true; 1793 rte_spinlock_unlock(&hw->lock); 1794 1795 return 0; 1796 1797 err_pause_addr_cfg: 1798 ret_val = hns3_remove_uc_addr_common(hw, mac_addr); 1799 if (ret_val) { 1800 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1801 mac_addr); 1802 hns3_warn(hw, 1803 "Failed to roll back to del setted mac addr(%s): %d", 1804 mac_str, ret_val); 1805 } 1806 1807 err_add_uc_addr: 1808 if (rm_succes) { 1809 ret_val = hns3_add_uc_addr_common(hw, oaddr); 1810 if (ret_val) { 1811 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1812 oaddr); 1813 hns3_warn(hw, 1814 "Failed to restore old uc mac addr(%s): %d", 1815 mac_str, ret_val); 1816 hw->mac.default_addr_setted = false; 1817 } 1818 } 1819 rte_spinlock_unlock(&hw->lock); 1820 1821 return ret; 1822 } 1823 1824 static int 1825 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del) 1826 { 1827 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1828 struct hns3_hw *hw = &hns->hw; 1829 struct rte_ether_addr *addr; 1830 int err = 0; 1831 int ret; 1832 int i; 1833 1834 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) { 1835 addr = &hw->data->mac_addrs[i]; 1836 if (rte_is_zero_ether_addr(addr)) 1837 continue; 1838 if (rte_is_multicast_ether_addr(addr)) 1839 ret = del ? hns3_remove_mc_addr(hw, addr) : 1840 hns3_add_mc_addr(hw, addr); 1841 else 1842 ret = del ? hns3_remove_uc_addr_common(hw, addr) : 1843 hns3_add_uc_addr_common(hw, addr); 1844 1845 if (ret) { 1846 err = ret; 1847 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1848 addr); 1849 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 1850 "ret = %d.", del ? "remove" : "restore", 1851 mac_str, i, ret); 1852 } 1853 } 1854 return err; 1855 } 1856 1857 static void 1858 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr) 1859 { 1860 #define HNS3_VF_NUM_IN_FIRST_DESC 192 1861 uint8_t word_num; 1862 uint8_t bit_num; 1863 1864 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) { 1865 word_num = vfid / 32; 1866 bit_num = vfid % 32; 1867 if (clr) 1868 desc[1].data[word_num] &= 1869 rte_cpu_to_le_32(~(1UL << bit_num)); 1870 else 1871 desc[1].data[word_num] |= 1872 rte_cpu_to_le_32(1UL << bit_num); 1873 } else { 1874 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32; 1875 bit_num = vfid % 32; 1876 if (clr) 1877 desc[2].data[word_num] &= 1878 rte_cpu_to_le_32(~(1UL << bit_num)); 1879 else 1880 desc[2].data[word_num] |= 1881 rte_cpu_to_le_32(1UL << bit_num); 1882 } 1883 } 1884 1885 static int 1886 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1887 { 1888 struct hns3_mac_vlan_tbl_entry_cmd req; 1889 struct hns3_cmd_desc desc[3]; 1890 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1891 uint8_t vf_id; 1892 int ret; 1893 1894 /* Check if mac addr is valid */ 1895 if (!rte_is_multicast_ether_addr(mac_addr)) { 1896 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1897 mac_addr); 1898 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid", 1899 mac_str); 1900 return -EINVAL; 1901 } 1902 1903 memset(&req, 0, sizeof(req)); 1904 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1905 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1906 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1907 if (ret) { 1908 /* This mac addr do not exist, add new entry for it */ 1909 memset(desc[0].data, 0, sizeof(desc[0].data)); 1910 memset(desc[1].data, 0, sizeof(desc[0].data)); 1911 memset(desc[2].data, 0, sizeof(desc[0].data)); 1912 } 1913 1914 /* 1915 * In current version VF is not supported when PF is driven by DPDK 1916 * driver, just need to configure parameters for PF vport. 1917 */ 1918 vf_id = HNS3_PF_FUNC_ID; 1919 hns3_update_desc_vfid(desc, vf_id, false); 1920 ret = hns3_add_mac_vlan_tbl(hw, &req, desc); 1921 if (ret) { 1922 if (ret == -ENOSPC) 1923 hns3_err(hw, "mc mac vlan table is full"); 1924 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1925 mac_addr); 1926 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret); 1927 } 1928 1929 return ret; 1930 } 1931 1932 static int 1933 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1934 { 1935 struct hns3_mac_vlan_tbl_entry_cmd req; 1936 struct hns3_cmd_desc desc[3]; 1937 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1938 uint8_t vf_id; 1939 int ret; 1940 1941 /* Check if mac addr is valid */ 1942 if (!rte_is_multicast_ether_addr(mac_addr)) { 1943 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1944 mac_addr); 1945 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid", 1946 mac_str); 1947 return -EINVAL; 1948 } 1949 1950 memset(&req, 0, sizeof(req)); 1951 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1952 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1953 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1954 if (ret == 0) { 1955 /* 1956 * This mac addr exist, remove this handle's VFID for it. 1957 * In current version VF is not supported when PF is driven by 1958 * DPDK driver, just need to configure parameters for PF vport. 1959 */ 1960 vf_id = HNS3_PF_FUNC_ID; 1961 hns3_update_desc_vfid(desc, vf_id, true); 1962 1963 /* All the vfid is zero, so need to delete this entry */ 1964 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1965 } else if (ret == -ENOENT) { 1966 /* This mac addr doesn't exist. */ 1967 return 0; 1968 } 1969 1970 if (ret) { 1971 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1972 mac_addr); 1973 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret); 1974 } 1975 1976 return ret; 1977 } 1978 1979 static int 1980 hns3_set_mc_addr_chk_param(struct hns3_hw *hw, 1981 struct rte_ether_addr *mc_addr_set, 1982 uint32_t nb_mc_addr) 1983 { 1984 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1985 struct rte_ether_addr *addr; 1986 uint32_t i; 1987 uint32_t j; 1988 1989 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 1990 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) " 1991 "invalid. valid range: 0~%d", 1992 nb_mc_addr, HNS3_MC_MACADDR_NUM); 1993 return -EINVAL; 1994 } 1995 1996 /* Check if input mac addresses are valid */ 1997 for (i = 0; i < nb_mc_addr; i++) { 1998 addr = &mc_addr_set[i]; 1999 if (!rte_is_multicast_ether_addr(addr)) { 2000 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2001 addr); 2002 hns3_err(hw, 2003 "failed to set mc mac addr, addr(%s) invalid.", 2004 mac_str); 2005 return -EINVAL; 2006 } 2007 2008 /* Check if there are duplicate addresses */ 2009 for (j = i + 1; j < nb_mc_addr; j++) { 2010 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 2011 hns3_ether_format_addr(mac_str, 2012 RTE_ETHER_ADDR_FMT_SIZE, 2013 addr); 2014 hns3_err(hw, "failed to set mc mac addr, " 2015 "addrs invalid. two same addrs(%s).", 2016 mac_str); 2017 return -EINVAL; 2018 } 2019 } 2020 2021 /* 2022 * Check if there are duplicate addresses between mac_addrs 2023 * and mc_addr_set 2024 */ 2025 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) { 2026 if (rte_is_same_ether_addr(addr, 2027 &hw->data->mac_addrs[j])) { 2028 hns3_ether_format_addr(mac_str, 2029 RTE_ETHER_ADDR_FMT_SIZE, 2030 addr); 2031 hns3_err(hw, "failed to set mc mac addr, " 2032 "addrs invalid. addrs(%s) has already " 2033 "configured in mac_addr add API", 2034 mac_str); 2035 return -EINVAL; 2036 } 2037 } 2038 } 2039 2040 return 0; 2041 } 2042 2043 static void 2044 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw, 2045 struct rte_ether_addr *mc_addr_set, 2046 int mc_addr_num, 2047 struct rte_ether_addr *reserved_addr_list, 2048 int *reserved_addr_num, 2049 struct rte_ether_addr *add_addr_list, 2050 int *add_addr_num, 2051 struct rte_ether_addr *rm_addr_list, 2052 int *rm_addr_num) 2053 { 2054 struct rte_ether_addr *addr; 2055 int current_addr_num; 2056 int reserved_num = 0; 2057 int add_num = 0; 2058 int rm_num = 0; 2059 int num; 2060 int i; 2061 int j; 2062 bool same_addr; 2063 2064 /* Calculate the mc mac address list that should be removed */ 2065 current_addr_num = hw->mc_addrs_num; 2066 for (i = 0; i < current_addr_num; i++) { 2067 addr = &hw->mc_addrs[i]; 2068 same_addr = false; 2069 for (j = 0; j < mc_addr_num; j++) { 2070 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 2071 same_addr = true; 2072 break; 2073 } 2074 } 2075 2076 if (!same_addr) { 2077 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]); 2078 rm_num++; 2079 } else { 2080 rte_ether_addr_copy(addr, 2081 &reserved_addr_list[reserved_num]); 2082 reserved_num++; 2083 } 2084 } 2085 2086 /* Calculate the mc mac address list that should be added */ 2087 for (i = 0; i < mc_addr_num; i++) { 2088 addr = &mc_addr_set[i]; 2089 same_addr = false; 2090 for (j = 0; j < current_addr_num; j++) { 2091 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) { 2092 same_addr = true; 2093 break; 2094 } 2095 } 2096 2097 if (!same_addr) { 2098 rte_ether_addr_copy(addr, &add_addr_list[add_num]); 2099 add_num++; 2100 } 2101 } 2102 2103 /* Reorder the mc mac address list maintained by driver */ 2104 for (i = 0; i < reserved_num; i++) 2105 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]); 2106 2107 for (i = 0; i < rm_num; i++) { 2108 num = reserved_num + i; 2109 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]); 2110 } 2111 2112 *reserved_addr_num = reserved_num; 2113 *add_addr_num = add_num; 2114 *rm_addr_num = rm_num; 2115 } 2116 2117 static int 2118 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, 2119 struct rte_ether_addr *mc_addr_set, 2120 uint32_t nb_mc_addr) 2121 { 2122 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2123 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM]; 2124 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM]; 2125 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM]; 2126 struct rte_ether_addr *addr; 2127 int reserved_addr_num; 2128 int add_addr_num; 2129 int rm_addr_num; 2130 int mc_addr_num; 2131 int num; 2132 int ret; 2133 int i; 2134 2135 /* Check if input parameters are valid */ 2136 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 2137 if (ret) 2138 return ret; 2139 2140 rte_spinlock_lock(&hw->lock); 2141 2142 /* 2143 * Calculate the mc mac address lists those should be removed and be 2144 * added, Reorder the mc mac address list maintained by driver. 2145 */ 2146 mc_addr_num = (int)nb_mc_addr; 2147 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num, 2148 reserved_addr_list, &reserved_addr_num, 2149 add_addr_list, &add_addr_num, 2150 rm_addr_list, &rm_addr_num); 2151 2152 /* Remove mc mac addresses */ 2153 for (i = 0; i < rm_addr_num; i++) { 2154 num = rm_addr_num - i - 1; 2155 addr = &rm_addr_list[num]; 2156 ret = hns3_remove_mc_addr(hw, addr); 2157 if (ret) { 2158 rte_spinlock_unlock(&hw->lock); 2159 return ret; 2160 } 2161 hw->mc_addrs_num--; 2162 } 2163 2164 /* Add mc mac addresses */ 2165 for (i = 0; i < add_addr_num; i++) { 2166 addr = &add_addr_list[i]; 2167 ret = hns3_add_mc_addr(hw, addr); 2168 if (ret) { 2169 rte_spinlock_unlock(&hw->lock); 2170 return ret; 2171 } 2172 2173 num = reserved_addr_num + i; 2174 rte_ether_addr_copy(addr, &hw->mc_addrs[num]); 2175 hw->mc_addrs_num++; 2176 } 2177 rte_spinlock_unlock(&hw->lock); 2178 2179 return 0; 2180 } 2181 2182 static int 2183 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 2184 { 2185 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2186 struct hns3_hw *hw = &hns->hw; 2187 struct rte_ether_addr *addr; 2188 int err = 0; 2189 int ret; 2190 int i; 2191 2192 for (i = 0; i < hw->mc_addrs_num; i++) { 2193 addr = &hw->mc_addrs[i]; 2194 if (!rte_is_multicast_ether_addr(addr)) 2195 continue; 2196 if (del) 2197 ret = hns3_remove_mc_addr(hw, addr); 2198 else 2199 ret = hns3_add_mc_addr(hw, addr); 2200 if (ret) { 2201 err = ret; 2202 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2203 addr); 2204 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d", 2205 del ? "Remove" : "Restore", mac_str, ret); 2206 } 2207 } 2208 return err; 2209 } 2210 2211 static int 2212 hns3_check_mq_mode(struct rte_eth_dev *dev) 2213 { 2214 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 2215 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 2216 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2217 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2218 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 2219 struct rte_eth_dcb_tx_conf *dcb_tx_conf; 2220 uint8_t num_tc; 2221 int max_tc = 0; 2222 int i; 2223 2224 if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) || 2225 (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB || 2226 tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) { 2227 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.", 2228 rx_mq_mode, tx_mq_mode); 2229 return -EOPNOTSUPP; 2230 } 2231 2232 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 2233 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf; 2234 if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) { 2235 if (dcb_rx_conf->nb_tcs > pf->tc_max) { 2236 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.", 2237 dcb_rx_conf->nb_tcs, pf->tc_max); 2238 return -EINVAL; 2239 } 2240 2241 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS || 2242 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) { 2243 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, " 2244 "nb_tcs(%d) != %d or %d in rx direction.", 2245 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS); 2246 return -EINVAL; 2247 } 2248 2249 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) { 2250 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)", 2251 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs); 2252 return -EINVAL; 2253 } 2254 2255 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) { 2256 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) { 2257 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, " 2258 "is not equal to one in tx direction.", 2259 i, dcb_rx_conf->dcb_tc[i]); 2260 return -EINVAL; 2261 } 2262 if (dcb_rx_conf->dcb_tc[i] > max_tc) 2263 max_tc = dcb_rx_conf->dcb_tc[i]; 2264 } 2265 2266 num_tc = max_tc + 1; 2267 if (num_tc > dcb_rx_conf->nb_tcs) { 2268 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)", 2269 num_tc, dcb_rx_conf->nb_tcs); 2270 return -EINVAL; 2271 } 2272 } 2273 2274 return 0; 2275 } 2276 2277 static int 2278 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en, 2279 enum hns3_ring_type queue_type, uint16_t queue_id) 2280 { 2281 struct hns3_cmd_desc desc; 2282 struct hns3_ctrl_vector_chain_cmd *req = 2283 (struct hns3_ctrl_vector_chain_cmd *)desc.data; 2284 enum hns3_opcode_type op; 2285 uint16_t tqp_type_and_id = 0; 2286 uint16_t type; 2287 uint16_t gl; 2288 int ret; 2289 2290 op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR; 2291 hns3_cmd_setup_basic_desc(&desc, op, false); 2292 req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M, 2293 HNS3_TQP_INT_ID_L_S); 2294 req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M, 2295 HNS3_TQP_INT_ID_H_S); 2296 2297 if (queue_type == HNS3_RING_TYPE_RX) 2298 gl = HNS3_RING_GL_RX; 2299 else 2300 gl = HNS3_RING_GL_TX; 2301 2302 type = queue_type; 2303 2304 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S, 2305 type); 2306 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id); 2307 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S, 2308 gl); 2309 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id); 2310 req->int_cause_num = 1; 2311 ret = hns3_cmd_send(hw, &desc, 1); 2312 if (ret) { 2313 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.", 2314 en ? "Map" : "Unmap", queue_id, vector_id, ret); 2315 return ret; 2316 } 2317 2318 return 0; 2319 } 2320 2321 static int 2322 hns3_init_ring_with_vector(struct hns3_hw *hw) 2323 { 2324 uint16_t vec; 2325 int ret; 2326 int i; 2327 2328 /* 2329 * In hns3 network engine, vector 0 is always the misc interrupt of this 2330 * function, vector 1~N can be used respectively for the queues of the 2331 * function. Tx and Rx queues with the same number share the interrupt 2332 * vector. In the initialization clearing the all hardware mapping 2333 * relationship configurations between queues and interrupt vectors is 2334 * needed, so some error caused by the residual configurations, such as 2335 * the unexpected Tx interrupt, can be avoid. 2336 */ 2337 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 2338 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) 2339 vec = vec - 1; /* the last interrupt is reserved */ 2340 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); 2341 for (i = 0; i < hw->intr_tqps_num; i++) { 2342 /* 2343 * Set gap limiter/rate limiter/quanity limiter algorithm 2344 * configuration for interrupt coalesce of queue's interrupt. 2345 */ 2346 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 2347 HNS3_TQP_INTR_GL_DEFAULT); 2348 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 2349 HNS3_TQP_INTR_GL_DEFAULT); 2350 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 2351 /* 2352 * QL(quantity limiter) is not used currently, just set 0 to 2353 * close it. 2354 */ 2355 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); 2356 2357 ret = hns3_bind_ring_with_vector(hw, vec, false, 2358 HNS3_RING_TYPE_TX, i); 2359 if (ret) { 2360 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with " 2361 "vector: %u, ret=%d", i, vec, ret); 2362 return ret; 2363 } 2364 2365 ret = hns3_bind_ring_with_vector(hw, vec, false, 2366 HNS3_RING_TYPE_RX, i); 2367 if (ret) { 2368 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with " 2369 "vector: %u, ret=%d", i, vec, ret); 2370 return ret; 2371 } 2372 } 2373 2374 return 0; 2375 } 2376 2377 static int 2378 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf) 2379 { 2380 struct hns3_adapter *hns = dev->data->dev_private; 2381 struct hns3_hw *hw = &hns->hw; 2382 uint32_t max_rx_pkt_len; 2383 uint16_t mtu; 2384 int ret; 2385 2386 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)) 2387 return 0; 2388 2389 /* 2390 * If jumbo frames are enabled, MTU needs to be refreshed 2391 * according to the maximum RX packet length. 2392 */ 2393 max_rx_pkt_len = conf->rxmode.max_rx_pkt_len; 2394 if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN || 2395 max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) { 2396 hns3_err(hw, "maximum Rx packet length must be greater than %u " 2397 "and no more than %u when jumbo frame enabled.", 2398 (uint16_t)HNS3_DEFAULT_FRAME_LEN, 2399 (uint16_t)HNS3_MAX_FRAME_LEN); 2400 return -EINVAL; 2401 } 2402 2403 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len); 2404 ret = hns3_dev_mtu_set(dev, mtu); 2405 if (ret) 2406 return ret; 2407 dev->data->mtu = mtu; 2408 2409 return 0; 2410 } 2411 2412 static int 2413 hns3_setup_dcb(struct rte_eth_dev *dev) 2414 { 2415 struct hns3_adapter *hns = dev->data->dev_private; 2416 struct hns3_hw *hw = &hns->hw; 2417 int ret; 2418 2419 if (!hns3_dev_dcb_supported(hw)) { 2420 hns3_err(hw, "this port does not support dcb configurations."); 2421 return -EOPNOTSUPP; 2422 } 2423 2424 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { 2425 hns3_err(hw, "MAC pause enabled, cannot config dcb info."); 2426 return -EOPNOTSUPP; 2427 } 2428 2429 ret = hns3_dcb_configure(hns); 2430 if (ret) 2431 hns3_err(hw, "failed to config dcb: %d", ret); 2432 2433 return ret; 2434 } 2435 2436 static int 2437 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds) 2438 { 2439 int ret; 2440 2441 /* 2442 * Some hardware doesn't support auto-negotiation, but users may not 2443 * configure link_speeds (default 0), which means auto-negotiation. 2444 * In this case, a warning message need to be printed, instead of 2445 * an error. 2446 */ 2447 if (link_speeds == ETH_LINK_SPEED_AUTONEG && 2448 hw->mac.support_autoneg == 0) { 2449 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!"); 2450 return 0; 2451 } 2452 2453 if (link_speeds != ETH_LINK_SPEED_AUTONEG) { 2454 ret = hns3_check_port_speed(hw, link_speeds); 2455 if (ret) 2456 return ret; 2457 } 2458 2459 return 0; 2460 } 2461 2462 static int 2463 hns3_check_dev_conf(struct rte_eth_dev *dev) 2464 { 2465 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2466 struct rte_eth_conf *conf = &dev->data->dev_conf; 2467 int ret; 2468 2469 ret = hns3_check_mq_mode(dev); 2470 if (ret) 2471 return ret; 2472 2473 return hns3_check_link_speed(hw, conf->link_speeds); 2474 } 2475 2476 static int 2477 hns3_dev_configure(struct rte_eth_dev *dev) 2478 { 2479 struct hns3_adapter *hns = dev->data->dev_private; 2480 struct rte_eth_conf *conf = &dev->data->dev_conf; 2481 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 2482 struct hns3_hw *hw = &hns->hw; 2483 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2484 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2485 struct rte_eth_rss_conf rss_conf; 2486 bool gro_en; 2487 int ret; 2488 2489 hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q); 2490 2491 /* 2492 * Some versions of hardware network engine does not support 2493 * individually enable/disable/reset the Tx or Rx queue. These devices 2494 * must enable/disable/reset Tx and Rx queues at the same time. When the 2495 * numbers of Tx queues allocated by upper applications are not equal to 2496 * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues 2497 * to adjust numbers of Tx/Rx queues. otherwise, network engine can not 2498 * work as usual. But these fake queues are imperceptible, and can not 2499 * be used by upper applications. 2500 */ 2501 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 2502 if (ret) { 2503 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret); 2504 hw->cfg_max_queues = 0; 2505 return ret; 2506 } 2507 2508 hw->adapter_state = HNS3_NIC_CONFIGURING; 2509 ret = hns3_check_dev_conf(dev); 2510 if (ret) 2511 goto cfg_err; 2512 2513 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) { 2514 ret = hns3_setup_dcb(dev); 2515 if (ret) 2516 goto cfg_err; 2517 } 2518 2519 /* When RSS is not configured, redirect the packet queue 0 */ 2520 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 2521 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2522 rss_conf = conf->rx_adv_conf.rss_conf; 2523 hw->rss_dis_flag = false; 2524 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 2525 if (ret) 2526 goto cfg_err; 2527 } 2528 2529 ret = hns3_refresh_mtu(dev, conf); 2530 if (ret) 2531 goto cfg_err; 2532 2533 ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf); 2534 if (ret) 2535 goto cfg_err; 2536 2537 ret = hns3_dev_configure_vlan(dev); 2538 if (ret) 2539 goto cfg_err; 2540 2541 /* config hardware GRO */ 2542 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 2543 ret = hns3_config_gro(hw, gro_en); 2544 if (ret) 2545 goto cfg_err; 2546 2547 hns3_init_rx_ptype_tble(dev); 2548 hw->adapter_state = HNS3_NIC_CONFIGURED; 2549 2550 return 0; 2551 2552 cfg_err: 2553 hw->cfg_max_queues = 0; 2554 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 2555 hw->adapter_state = HNS3_NIC_INITIALIZED; 2556 2557 return ret; 2558 } 2559 2560 static int 2561 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps) 2562 { 2563 struct hns3_config_max_frm_size_cmd *req; 2564 struct hns3_cmd_desc desc; 2565 2566 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false); 2567 2568 req = (struct hns3_config_max_frm_size_cmd *)desc.data; 2569 req->max_frm_size = rte_cpu_to_le_16(new_mps); 2570 req->min_frm_size = RTE_ETHER_MIN_LEN; 2571 2572 return hns3_cmd_send(hw, &desc, 1); 2573 } 2574 2575 static int 2576 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps) 2577 { 2578 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2579 uint16_t original_mps = hns->pf.mps; 2580 int err; 2581 int ret; 2582 2583 ret = hns3_set_mac_mtu(hw, mps); 2584 if (ret) { 2585 hns3_err(hw, "failed to set mtu, ret = %d", ret); 2586 return ret; 2587 } 2588 2589 hns->pf.mps = mps; 2590 ret = hns3_buffer_alloc(hw); 2591 if (ret) { 2592 hns3_err(hw, "failed to allocate buffer, ret = %d", ret); 2593 goto rollback; 2594 } 2595 2596 return 0; 2597 2598 rollback: 2599 err = hns3_set_mac_mtu(hw, original_mps); 2600 if (err) { 2601 hns3_err(hw, "fail to rollback MTU, err = %d", err); 2602 return ret; 2603 } 2604 hns->pf.mps = original_mps; 2605 2606 return ret; 2607 } 2608 2609 static int 2610 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2611 { 2612 struct hns3_adapter *hns = dev->data->dev_private; 2613 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 2614 struct hns3_hw *hw = &hns->hw; 2615 bool is_jumbo_frame; 2616 int ret; 2617 2618 if (dev->data->dev_started) { 2619 hns3_err(hw, "Failed to set mtu, port %u must be stopped " 2620 "before configuration", dev->data->port_id); 2621 return -EBUSY; 2622 } 2623 2624 rte_spinlock_lock(&hw->lock); 2625 is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false; 2626 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN); 2627 2628 /* 2629 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely 2630 * assign to "uint16_t" type variable. 2631 */ 2632 ret = hns3_config_mtu(hw, (uint16_t)frame_size); 2633 if (ret) { 2634 rte_spinlock_unlock(&hw->lock); 2635 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d", 2636 dev->data->port_id, mtu, ret); 2637 return ret; 2638 } 2639 2640 if (is_jumbo_frame) 2641 dev->data->dev_conf.rxmode.offloads |= 2642 DEV_RX_OFFLOAD_JUMBO_FRAME; 2643 else 2644 dev->data->dev_conf.rxmode.offloads &= 2645 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2646 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2647 rte_spinlock_unlock(&hw->lock); 2648 2649 return 0; 2650 } 2651 2652 static uint32_t 2653 hns3_get_copper_port_speed_capa(uint32_t supported_speed) 2654 { 2655 uint32_t speed_capa = 0; 2656 2657 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT) 2658 speed_capa |= ETH_LINK_SPEED_10M_HD; 2659 if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT) 2660 speed_capa |= ETH_LINK_SPEED_10M; 2661 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT) 2662 speed_capa |= ETH_LINK_SPEED_100M_HD; 2663 if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT) 2664 speed_capa |= ETH_LINK_SPEED_100M; 2665 if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT) 2666 speed_capa |= ETH_LINK_SPEED_1G; 2667 2668 return speed_capa; 2669 } 2670 2671 static uint32_t 2672 hns3_get_firber_port_speed_capa(uint32_t supported_speed) 2673 { 2674 uint32_t speed_capa = 0; 2675 2676 if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT) 2677 speed_capa |= ETH_LINK_SPEED_1G; 2678 if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT) 2679 speed_capa |= ETH_LINK_SPEED_10G; 2680 if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT) 2681 speed_capa |= ETH_LINK_SPEED_25G; 2682 if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT) 2683 speed_capa |= ETH_LINK_SPEED_40G; 2684 if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT) 2685 speed_capa |= ETH_LINK_SPEED_50G; 2686 if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT) 2687 speed_capa |= ETH_LINK_SPEED_100G; 2688 if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT) 2689 speed_capa |= ETH_LINK_SPEED_200G; 2690 2691 return speed_capa; 2692 } 2693 2694 static uint32_t 2695 hns3_get_speed_capa(struct hns3_hw *hw) 2696 { 2697 struct hns3_mac *mac = &hw->mac; 2698 uint32_t speed_capa; 2699 2700 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) 2701 speed_capa = 2702 hns3_get_copper_port_speed_capa(mac->supported_speed); 2703 else 2704 speed_capa = 2705 hns3_get_firber_port_speed_capa(mac->supported_speed); 2706 2707 if (mac->support_autoneg == 0) 2708 speed_capa |= ETH_LINK_SPEED_FIXED; 2709 2710 return speed_capa; 2711 } 2712 2713 int 2714 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 2715 { 2716 struct hns3_adapter *hns = eth_dev->data->dev_private; 2717 struct hns3_hw *hw = &hns->hw; 2718 uint16_t queue_num = hw->tqps_num; 2719 2720 /* 2721 * In interrupt mode, 'max_rx_queues' is set based on the number of 2722 * MSI-X interrupt resources of the hardware. 2723 */ 2724 if (hw->data->dev_conf.intr_conf.rxq == 1) 2725 queue_num = hw->intr_tqps_num; 2726 2727 info->max_rx_queues = queue_num; 2728 info->max_tx_queues = hw->tqps_num; 2729 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 2730 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 2731 info->max_mac_addrs = HNS3_UC_MACADDR_NUM; 2732 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 2733 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 2734 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 2735 DEV_RX_OFFLOAD_TCP_CKSUM | 2736 DEV_RX_OFFLOAD_UDP_CKSUM | 2737 DEV_RX_OFFLOAD_SCTP_CKSUM | 2738 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2739 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 2740 DEV_RX_OFFLOAD_KEEP_CRC | 2741 DEV_RX_OFFLOAD_SCATTER | 2742 DEV_RX_OFFLOAD_VLAN_STRIP | 2743 DEV_RX_OFFLOAD_VLAN_FILTER | 2744 DEV_RX_OFFLOAD_JUMBO_FRAME | 2745 DEV_RX_OFFLOAD_RSS_HASH | 2746 DEV_RX_OFFLOAD_TCP_LRO); 2747 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2748 DEV_TX_OFFLOAD_IPV4_CKSUM | 2749 DEV_TX_OFFLOAD_TCP_CKSUM | 2750 DEV_TX_OFFLOAD_UDP_CKSUM | 2751 DEV_TX_OFFLOAD_SCTP_CKSUM | 2752 DEV_TX_OFFLOAD_MULTI_SEGS | 2753 DEV_TX_OFFLOAD_TCP_TSO | 2754 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 2755 DEV_TX_OFFLOAD_GRE_TNL_TSO | 2756 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 2757 DEV_TX_OFFLOAD_MBUF_FAST_FREE | 2758 hns3_txvlan_cap_get(hw)); 2759 2760 if (hns3_dev_outer_udp_cksum_supported(hw)) 2761 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM; 2762 2763 if (hns3_dev_indep_txrx_supported(hw)) 2764 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 2765 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 2766 2767 if (hns3_dev_ptp_supported(hw)) 2768 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 2769 2770 info->rx_desc_lim = (struct rte_eth_desc_lim) { 2771 .nb_max = HNS3_MAX_RING_DESC, 2772 .nb_min = HNS3_MIN_RING_DESC, 2773 .nb_align = HNS3_ALIGN_RING_DESC, 2774 }; 2775 2776 info->tx_desc_lim = (struct rte_eth_desc_lim) { 2777 .nb_max = HNS3_MAX_RING_DESC, 2778 .nb_min = HNS3_MIN_RING_DESC, 2779 .nb_align = HNS3_ALIGN_RING_DESC, 2780 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 2781 .nb_mtu_seg_max = hw->max_non_tso_bd_num, 2782 }; 2783 2784 info->speed_capa = hns3_get_speed_capa(hw); 2785 info->default_rxconf = (struct rte_eth_rxconf) { 2786 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, 2787 /* 2788 * If there are no available Rx buffer descriptors, incoming 2789 * packets are always dropped by hardware based on hns3 network 2790 * engine. 2791 */ 2792 .rx_drop_en = 1, 2793 .offloads = 0, 2794 }; 2795 info->default_txconf = (struct rte_eth_txconf) { 2796 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, 2797 .offloads = 0, 2798 }; 2799 2800 info->reta_size = hw->rss_ind_tbl_size; 2801 info->hash_key_size = HNS3_RSS_KEY_SIZE; 2802 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 2803 2804 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2805 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2806 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2807 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2808 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2809 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2810 2811 return 0; 2812 } 2813 2814 static int 2815 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2816 size_t fw_size) 2817 { 2818 struct hns3_adapter *hns = eth_dev->data->dev_private; 2819 struct hns3_hw *hw = &hns->hw; 2820 uint32_t version = hw->fw_version; 2821 int ret; 2822 2823 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2824 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2825 HNS3_FW_VERSION_BYTE3_S), 2826 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2827 HNS3_FW_VERSION_BYTE2_S), 2828 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2829 HNS3_FW_VERSION_BYTE1_S), 2830 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2831 HNS3_FW_VERSION_BYTE0_S)); 2832 if (ret < 0) 2833 return -EINVAL; 2834 2835 ret += 1; /* add the size of '\0' */ 2836 if (fw_size < (size_t)ret) 2837 return ret; 2838 else 2839 return 0; 2840 } 2841 2842 static int 2843 hns3_update_port_link_info(struct rte_eth_dev *eth_dev) 2844 { 2845 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2846 int ret; 2847 2848 (void)hns3_update_link_status(hw); 2849 2850 ret = hns3_update_link_info(eth_dev); 2851 if (ret) 2852 hw->mac.link_status = ETH_LINK_DOWN; 2853 2854 return ret; 2855 } 2856 2857 static void 2858 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev, 2859 struct rte_eth_link *new_link) 2860 { 2861 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2862 struct hns3_mac *mac = &hw->mac; 2863 2864 switch (mac->link_speed) { 2865 case ETH_SPEED_NUM_10M: 2866 case ETH_SPEED_NUM_100M: 2867 case ETH_SPEED_NUM_1G: 2868 case ETH_SPEED_NUM_10G: 2869 case ETH_SPEED_NUM_25G: 2870 case ETH_SPEED_NUM_40G: 2871 case ETH_SPEED_NUM_50G: 2872 case ETH_SPEED_NUM_100G: 2873 case ETH_SPEED_NUM_200G: 2874 if (mac->link_status) 2875 new_link->link_speed = mac->link_speed; 2876 break; 2877 default: 2878 if (mac->link_status) 2879 new_link->link_speed = ETH_SPEED_NUM_UNKNOWN; 2880 break; 2881 } 2882 2883 if (!mac->link_status) 2884 new_link->link_speed = ETH_SPEED_NUM_NONE; 2885 2886 new_link->link_duplex = mac->link_duplex; 2887 new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2888 new_link->link_autoneg = mac->link_autoneg; 2889 } 2890 2891 static int 2892 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete) 2893 { 2894 #define HNS3_LINK_CHECK_INTERVAL 100 /* 100ms */ 2895 #define HNS3_MAX_LINK_CHECK_TIMES 20 /* 2s (100 * 20ms) in total */ 2896 2897 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 2898 uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES; 2899 struct hns3_mac *mac = &hw->mac; 2900 struct rte_eth_link new_link; 2901 int ret; 2902 2903 /* When port is stopped, report link down. */ 2904 if (eth_dev->data->dev_started == 0) { 2905 new_link.link_autoneg = mac->link_autoneg; 2906 new_link.link_duplex = mac->link_duplex; 2907 new_link.link_speed = ETH_SPEED_NUM_NONE; 2908 new_link.link_status = ETH_LINK_DOWN; 2909 goto out; 2910 } 2911 2912 do { 2913 ret = hns3_update_port_link_info(eth_dev); 2914 if (ret) { 2915 hns3_err(hw, "failed to get port link info, ret = %d.", 2916 ret); 2917 break; 2918 } 2919 2920 if (!wait_to_complete || mac->link_status == ETH_LINK_UP) 2921 break; 2922 2923 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL); 2924 } while (retry_cnt--); 2925 2926 memset(&new_link, 0, sizeof(new_link)); 2927 hns3_setup_linkstatus(eth_dev, &new_link); 2928 2929 out: 2930 return rte_eth_linkstatus_set(eth_dev, &new_link); 2931 } 2932 2933 static int 2934 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status) 2935 { 2936 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2937 struct hns3_pf *pf = &hns->pf; 2938 2939 if (!(status->pf_state & HNS3_PF_STATE_DONE)) 2940 return -EINVAL; 2941 2942 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false; 2943 2944 return 0; 2945 } 2946 2947 static int 2948 hns3_query_function_status(struct hns3_hw *hw) 2949 { 2950 #define HNS3_QUERY_MAX_CNT 10 2951 #define HNS3_QUERY_SLEEP_MSCOEND 1 2952 struct hns3_func_status_cmd *req; 2953 struct hns3_cmd_desc desc; 2954 int timeout = 0; 2955 int ret; 2956 2957 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true); 2958 req = (struct hns3_func_status_cmd *)desc.data; 2959 2960 do { 2961 ret = hns3_cmd_send(hw, &desc, 1); 2962 if (ret) { 2963 PMD_INIT_LOG(ERR, "query function status failed %d", 2964 ret); 2965 return ret; 2966 } 2967 2968 /* Check pf reset is done */ 2969 if (req->pf_state) 2970 break; 2971 2972 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND); 2973 } while (timeout++ < HNS3_QUERY_MAX_CNT); 2974 2975 return hns3_parse_func_status(hw, req); 2976 } 2977 2978 static int 2979 hns3_get_pf_max_tqp_num(struct hns3_hw *hw) 2980 { 2981 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2982 struct hns3_pf *pf = &hns->pf; 2983 2984 if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) { 2985 /* 2986 * The total_tqps_num obtained from firmware is maximum tqp 2987 * numbers of this port, which should be used for PF and VFs. 2988 * There is no need for pf to have so many tqp numbers in 2989 * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 2990 * coming from config file, is assigned to maximum queue number 2991 * for the PF of this port by user. So users can modify the 2992 * maximum queue number of PF according to their own application 2993 * scenarios, which is more flexible to use. In addition, many 2994 * memories can be saved due to allocating queue statistics 2995 * room according to the actual number of queues required. The 2996 * maximum queue number of PF for network engine with 2997 * revision_id greater than 0x30 is assigned by config file. 2998 */ 2999 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) { 3000 hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) " 3001 "must be greater than 0.", 3002 RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF); 3003 return -EINVAL; 3004 } 3005 3006 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF, 3007 hw->total_tqps_num); 3008 } else { 3009 /* 3010 * Due to the limitation on the number of PF interrupts 3011 * available, the maximum queue number assigned to PF on 3012 * the network engine with revision_id 0x21 is 64. 3013 */ 3014 hw->tqps_num = RTE_MIN(hw->total_tqps_num, 3015 HNS3_MAX_TQP_NUM_HIP08_PF); 3016 } 3017 3018 return 0; 3019 } 3020 3021 static int 3022 hns3_query_pf_resource(struct hns3_hw *hw) 3023 { 3024 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3025 struct hns3_pf *pf = &hns->pf; 3026 struct hns3_pf_res_cmd *req; 3027 struct hns3_cmd_desc desc; 3028 int ret; 3029 3030 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true); 3031 ret = hns3_cmd_send(hw, &desc, 1); 3032 if (ret) { 3033 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret); 3034 return ret; 3035 } 3036 3037 req = (struct hns3_pf_res_cmd *)desc.data; 3038 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) + 3039 rte_le_to_cpu_16(req->ext_tqp_num); 3040 ret = hns3_get_pf_max_tqp_num(hw); 3041 if (ret) 3042 return ret; 3043 3044 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S; 3045 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number); 3046 3047 if (req->tx_buf_size) 3048 pf->tx_buf_size = 3049 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S; 3050 else 3051 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF; 3052 3053 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT); 3054 3055 if (req->dv_buf_size) 3056 pf->dv_buf_size = 3057 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S; 3058 else 3059 pf->dv_buf_size = HNS3_DEFAULT_DV; 3060 3061 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT); 3062 3063 hw->num_msi = 3064 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number), 3065 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S); 3066 3067 return 0; 3068 } 3069 3070 static void 3071 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) 3072 { 3073 struct hns3_cfg_param_cmd *req; 3074 uint64_t mac_addr_tmp_high; 3075 uint8_t ext_rss_size_max; 3076 uint64_t mac_addr_tmp; 3077 uint32_t i; 3078 3079 req = (struct hns3_cfg_param_cmd *)desc[0].data; 3080 3081 /* get the configuration */ 3082 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 3083 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S); 3084 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 3085 HNS3_CFG_TQP_DESC_N_M, 3086 HNS3_CFG_TQP_DESC_N_S); 3087 3088 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3089 HNS3_CFG_PHY_ADDR_M, 3090 HNS3_CFG_PHY_ADDR_S); 3091 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3092 HNS3_CFG_MEDIA_TP_M, 3093 HNS3_CFG_MEDIA_TP_S); 3094 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3095 HNS3_CFG_RX_BUF_LEN_M, 3096 HNS3_CFG_RX_BUF_LEN_S); 3097 /* get mac address */ 3098 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]); 3099 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 3100 HNS3_CFG_MAC_ADDR_H_M, 3101 HNS3_CFG_MAC_ADDR_H_S); 3102 3103 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 3104 3105 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 3106 HNS3_CFG_DEFAULT_SPEED_M, 3107 HNS3_CFG_DEFAULT_SPEED_S); 3108 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 3109 HNS3_CFG_RSS_SIZE_M, 3110 HNS3_CFG_RSS_SIZE_S); 3111 3112 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 3113 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 3114 3115 req = (struct hns3_cfg_param_cmd *)desc[1].data; 3116 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]); 3117 3118 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3119 HNS3_CFG_SPEED_ABILITY_M, 3120 HNS3_CFG_SPEED_ABILITY_S); 3121 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 3122 HNS3_CFG_UMV_TBL_SPACE_M, 3123 HNS3_CFG_UMV_TBL_SPACE_S); 3124 if (!cfg->umv_space) 3125 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF; 3126 3127 ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]), 3128 HNS3_CFG_EXT_RSS_SIZE_M, 3129 HNS3_CFG_EXT_RSS_SIZE_S); 3130 /* 3131 * Field ext_rss_size_max obtained from firmware will be more flexible 3132 * for future changes and expansions, which is an exponent of 2, instead 3133 * of reading out directly. If this field is not zero, hns3 PF PMD 3134 * driver uses it as rss_size_max under one TC. Device, whose revision 3135 * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the 3136 * maximum number of queues supported under a TC through this field. 3137 */ 3138 if (ext_rss_size_max) 3139 cfg->rss_size_max = 1U << ext_rss_size_max; 3140 } 3141 3142 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash 3143 * @hw: pointer to struct hns3_hw 3144 * @hcfg: the config structure to be getted 3145 */ 3146 static int 3147 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg) 3148 { 3149 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM]; 3150 struct hns3_cfg_param_cmd *req; 3151 uint32_t offset; 3152 uint32_t i; 3153 int ret; 3154 3155 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) { 3156 offset = 0; 3157 req = (struct hns3_cfg_param_cmd *)desc[i].data; 3158 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM, 3159 true); 3160 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S, 3161 i * HNS3_CFG_RD_LEN_BYTES); 3162 /* Len should be divided by 4 when send to hardware */ 3163 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S, 3164 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT); 3165 req->offset = rte_cpu_to_le_32(offset); 3166 } 3167 3168 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM); 3169 if (ret) { 3170 PMD_INIT_LOG(ERR, "get config failed %d.", ret); 3171 return ret; 3172 } 3173 3174 hns3_parse_cfg(hcfg, desc); 3175 3176 return 0; 3177 } 3178 3179 static int 3180 hns3_parse_speed(int speed_cmd, uint32_t *speed) 3181 { 3182 switch (speed_cmd) { 3183 case HNS3_CFG_SPEED_10M: 3184 *speed = ETH_SPEED_NUM_10M; 3185 break; 3186 case HNS3_CFG_SPEED_100M: 3187 *speed = ETH_SPEED_NUM_100M; 3188 break; 3189 case HNS3_CFG_SPEED_1G: 3190 *speed = ETH_SPEED_NUM_1G; 3191 break; 3192 case HNS3_CFG_SPEED_10G: 3193 *speed = ETH_SPEED_NUM_10G; 3194 break; 3195 case HNS3_CFG_SPEED_25G: 3196 *speed = ETH_SPEED_NUM_25G; 3197 break; 3198 case HNS3_CFG_SPEED_40G: 3199 *speed = ETH_SPEED_NUM_40G; 3200 break; 3201 case HNS3_CFG_SPEED_50G: 3202 *speed = ETH_SPEED_NUM_50G; 3203 break; 3204 case HNS3_CFG_SPEED_100G: 3205 *speed = ETH_SPEED_NUM_100G; 3206 break; 3207 case HNS3_CFG_SPEED_200G: 3208 *speed = ETH_SPEED_NUM_200G; 3209 break; 3210 default: 3211 return -EINVAL; 3212 } 3213 3214 return 0; 3215 } 3216 3217 static void 3218 hns3_set_default_dev_specifications(struct hns3_hw *hw) 3219 { 3220 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 3221 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 3222 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 3223 hw->max_tm_rate = HNS3_ETHER_MAX_RATE; 3224 hw->intr.int_ql_max = HNS3_INTR_QL_NONE; 3225 } 3226 3227 static void 3228 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 3229 { 3230 struct hns3_dev_specs_0_cmd *req0; 3231 3232 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 3233 3234 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 3235 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 3236 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 3237 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate); 3238 hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max); 3239 } 3240 3241 static int 3242 hns3_check_dev_specifications(struct hns3_hw *hw) 3243 { 3244 if (hw->rss_ind_tbl_size == 0 || 3245 hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) { 3246 hns3_err(hw, "the size of hash lookup table configured (%u)" 3247 " exceeds the maximum(%u)", hw->rss_ind_tbl_size, 3248 HNS3_RSS_IND_TBL_SIZE_MAX); 3249 return -EINVAL; 3250 } 3251 3252 return 0; 3253 } 3254 3255 static int 3256 hns3_query_dev_specifications(struct hns3_hw *hw) 3257 { 3258 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 3259 int ret; 3260 int i; 3261 3262 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 3263 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 3264 true); 3265 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3266 } 3267 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 3268 3269 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 3270 if (ret) 3271 return ret; 3272 3273 hns3_parse_dev_specifications(hw, desc); 3274 3275 return hns3_check_dev_specifications(hw); 3276 } 3277 3278 static int 3279 hns3_get_capability(struct hns3_hw *hw) 3280 { 3281 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3282 struct rte_pci_device *pci_dev; 3283 struct hns3_pf *pf = &hns->pf; 3284 struct rte_eth_dev *eth_dev; 3285 uint16_t device_id; 3286 uint8_t revision; 3287 int ret; 3288 3289 eth_dev = &rte_eth_devices[hw->data->port_id]; 3290 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3291 device_id = pci_dev->id.device_id; 3292 3293 if (device_id == HNS3_DEV_ID_25GE_RDMA || 3294 device_id == HNS3_DEV_ID_50GE_RDMA || 3295 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC || 3296 device_id == HNS3_DEV_ID_200G_RDMA) 3297 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); 3298 3299 /* Get PCI revision id */ 3300 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 3301 HNS3_PCI_REVISION_ID); 3302 if (ret != HNS3_PCI_REVISION_ID_LEN) { 3303 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d", 3304 ret); 3305 return -EIO; 3306 } 3307 hw->revision = revision; 3308 3309 if (revision < PCI_REVISION_ID_HIP09_A) { 3310 hns3_set_default_dev_specifications(hw); 3311 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 3312 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 3313 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM; 3314 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE; 3315 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1; 3316 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 3317 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE; 3318 hw->rss_info.ipv6_sctp_offload_supported = false; 3319 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE; 3320 return 0; 3321 } 3322 3323 ret = hns3_query_dev_specifications(hw); 3324 if (ret) { 3325 PMD_INIT_LOG(ERR, 3326 "failed to query dev specifications, ret = %d", 3327 ret); 3328 return ret; 3329 } 3330 3331 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 3332 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 3333 hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM; 3334 hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE; 3335 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; 3336 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 3337 pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE; 3338 hw->rss_info.ipv6_sctp_offload_supported = true; 3339 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE; 3340 3341 return 0; 3342 } 3343 3344 static int 3345 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type) 3346 { 3347 int ret; 3348 3349 switch (media_type) { 3350 case HNS3_MEDIA_TYPE_COPPER: 3351 if (!hns3_dev_copper_supported(hw)) { 3352 PMD_INIT_LOG(ERR, 3353 "Media type is copper, not supported."); 3354 ret = -EOPNOTSUPP; 3355 } else { 3356 ret = 0; 3357 } 3358 break; 3359 case HNS3_MEDIA_TYPE_FIBER: 3360 ret = 0; 3361 break; 3362 case HNS3_MEDIA_TYPE_BACKPLANE: 3363 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported."); 3364 ret = -EOPNOTSUPP; 3365 break; 3366 default: 3367 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type); 3368 ret = -EINVAL; 3369 break; 3370 } 3371 3372 return ret; 3373 } 3374 3375 static int 3376 hns3_get_board_configuration(struct hns3_hw *hw) 3377 { 3378 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3379 struct hns3_pf *pf = &hns->pf; 3380 struct hns3_cfg cfg; 3381 int ret; 3382 3383 ret = hns3_get_board_cfg(hw, &cfg); 3384 if (ret) { 3385 PMD_INIT_LOG(ERR, "get board config failed %d", ret); 3386 return ret; 3387 } 3388 3389 ret = hns3_check_media_type(hw, cfg.media_type); 3390 if (ret) 3391 return ret; 3392 3393 hw->mac.media_type = cfg.media_type; 3394 hw->rss_size_max = cfg.rss_size_max; 3395 hw->rss_dis_flag = false; 3396 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN); 3397 hw->mac.phy_addr = cfg.phy_addr; 3398 hw->mac.default_addr_setted = false; 3399 hw->num_tx_desc = cfg.tqp_desc_num; 3400 hw->num_rx_desc = cfg.tqp_desc_num; 3401 hw->dcb_info.num_pg = 1; 3402 hw->dcb_info.hw_pfc_map = 0; 3403 3404 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed); 3405 if (ret) { 3406 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d", 3407 cfg.default_speed, ret); 3408 return ret; 3409 } 3410 3411 pf->tc_max = cfg.tc_num; 3412 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) { 3413 PMD_INIT_LOG(WARNING, 3414 "Get TC num(%u) from flash, set TC num to 1", 3415 pf->tc_max); 3416 pf->tc_max = 1; 3417 } 3418 3419 /* Dev does not support DCB */ 3420 if (!hns3_dev_dcb_supported(hw)) { 3421 pf->tc_max = 1; 3422 pf->pfc_max = 0; 3423 } else 3424 pf->pfc_max = pf->tc_max; 3425 3426 hw->dcb_info.num_tc = 1; 3427 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, 3428 hw->tqps_num / hw->dcb_info.num_tc); 3429 hns3_set_bit(hw->hw_tc_map, 0, 1); 3430 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE; 3431 3432 pf->wanted_umv_size = cfg.umv_space; 3433 3434 return ret; 3435 } 3436 3437 static int 3438 hns3_get_configuration(struct hns3_hw *hw) 3439 { 3440 int ret; 3441 3442 ret = hns3_query_function_status(hw); 3443 if (ret) { 3444 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret); 3445 return ret; 3446 } 3447 3448 /* Get device capability */ 3449 ret = hns3_get_capability(hw); 3450 if (ret) { 3451 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 3452 return ret; 3453 } 3454 3455 /* Get pf resource */ 3456 ret = hns3_query_pf_resource(hw); 3457 if (ret) { 3458 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret); 3459 return ret; 3460 } 3461 3462 ret = hns3_get_board_configuration(hw); 3463 if (ret) { 3464 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret); 3465 return ret; 3466 } 3467 3468 ret = hns3_query_dev_fec_info(hw); 3469 if (ret) 3470 PMD_INIT_LOG(ERR, 3471 "failed to query FEC information, ret = %d", ret); 3472 3473 return ret; 3474 } 3475 3476 static int 3477 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid, 3478 uint16_t tqp_vid, bool is_pf) 3479 { 3480 struct hns3_tqp_map_cmd *req; 3481 struct hns3_cmd_desc desc; 3482 int ret; 3483 3484 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false); 3485 3486 req = (struct hns3_tqp_map_cmd *)desc.data; 3487 req->tqp_id = rte_cpu_to_le_16(tqp_pid); 3488 req->tqp_vf = func_id; 3489 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B; 3490 if (!is_pf) 3491 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B); 3492 req->tqp_vid = rte_cpu_to_le_16(tqp_vid); 3493 3494 ret = hns3_cmd_send(hw, &desc, 1); 3495 if (ret) 3496 PMD_INIT_LOG(ERR, "TQP map failed %d", ret); 3497 3498 return ret; 3499 } 3500 3501 static int 3502 hns3_map_tqp(struct hns3_hw *hw) 3503 { 3504 int ret; 3505 int i; 3506 3507 /* 3508 * In current version, VF is not supported when PF is driven by DPDK 3509 * driver, so we assign total tqps_num tqps allocated to this port 3510 * to PF. 3511 */ 3512 for (i = 0; i < hw->total_tqps_num; i++) { 3513 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true); 3514 if (ret) 3515 return ret; 3516 } 3517 3518 return 0; 3519 } 3520 3521 static int 3522 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 3523 { 3524 struct hns3_config_mac_speed_dup_cmd *req; 3525 struct hns3_cmd_desc desc; 3526 int ret; 3527 3528 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data; 3529 3530 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false); 3531 3532 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0); 3533 3534 switch (speed) { 3535 case ETH_SPEED_NUM_10M: 3536 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3537 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M); 3538 break; 3539 case ETH_SPEED_NUM_100M: 3540 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3541 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M); 3542 break; 3543 case ETH_SPEED_NUM_1G: 3544 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3545 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G); 3546 break; 3547 case ETH_SPEED_NUM_10G: 3548 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3549 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G); 3550 break; 3551 case ETH_SPEED_NUM_25G: 3552 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3553 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G); 3554 break; 3555 case ETH_SPEED_NUM_40G: 3556 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3557 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G); 3558 break; 3559 case ETH_SPEED_NUM_50G: 3560 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3561 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G); 3562 break; 3563 case ETH_SPEED_NUM_100G: 3564 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3565 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G); 3566 break; 3567 case ETH_SPEED_NUM_200G: 3568 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3569 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G); 3570 break; 3571 default: 3572 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed); 3573 return -EINVAL; 3574 } 3575 3576 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); 3577 3578 ret = hns3_cmd_send(hw, &desc, 1); 3579 if (ret) 3580 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret); 3581 3582 return ret; 3583 } 3584 3585 static int 3586 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3587 { 3588 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3589 struct hns3_pf *pf = &hns->pf; 3590 struct hns3_priv_buf *priv; 3591 uint32_t i, total_size; 3592 3593 total_size = pf->pkt_buf_size; 3594 3595 /* alloc tx buffer for all enabled tc */ 3596 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3597 priv = &buf_alloc->priv_buf[i]; 3598 3599 if (hw->hw_tc_map & BIT(i)) { 3600 if (total_size < pf->tx_buf_size) 3601 return -ENOMEM; 3602 3603 priv->tx_buf_size = pf->tx_buf_size; 3604 } else 3605 priv->tx_buf_size = 0; 3606 3607 total_size -= priv->tx_buf_size; 3608 } 3609 3610 return 0; 3611 } 3612 3613 static int 3614 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3615 { 3616 /* TX buffer size is unit by 128 byte */ 3617 #define HNS3_BUF_SIZE_UNIT_SHIFT 7 3618 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15) 3619 struct hns3_tx_buff_alloc_cmd *req; 3620 struct hns3_cmd_desc desc; 3621 uint32_t buf_size; 3622 uint32_t i; 3623 int ret; 3624 3625 req = (struct hns3_tx_buff_alloc_cmd *)desc.data; 3626 3627 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0); 3628 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3629 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 3630 3631 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT; 3632 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size | 3633 HNS3_BUF_SIZE_UPDATE_EN_MSK); 3634 } 3635 3636 ret = hns3_cmd_send(hw, &desc, 1); 3637 if (ret) 3638 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret); 3639 3640 return ret; 3641 } 3642 3643 static int 3644 hns3_get_tc_num(struct hns3_hw *hw) 3645 { 3646 int cnt = 0; 3647 uint8_t i; 3648 3649 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3650 if (hw->hw_tc_map & BIT(i)) 3651 cnt++; 3652 return cnt; 3653 } 3654 3655 static uint32_t 3656 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3657 { 3658 struct hns3_priv_buf *priv; 3659 uint32_t rx_priv = 0; 3660 int i; 3661 3662 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3663 priv = &buf_alloc->priv_buf[i]; 3664 if (priv->enable) 3665 rx_priv += priv->buf_size; 3666 } 3667 return rx_priv; 3668 } 3669 3670 static uint32_t 3671 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3672 { 3673 uint32_t total_tx_size = 0; 3674 uint32_t i; 3675 3676 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3677 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 3678 3679 return total_tx_size; 3680 } 3681 3682 /* Get the number of pfc enabled TCs, which have private buffer */ 3683 static int 3684 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3685 { 3686 struct hns3_priv_buf *priv; 3687 int cnt = 0; 3688 uint8_t i; 3689 3690 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3691 priv = &buf_alloc->priv_buf[i]; 3692 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3693 cnt++; 3694 } 3695 3696 return cnt; 3697 } 3698 3699 /* Get the number of pfc disabled TCs, which have private buffer */ 3700 static int 3701 hns3_get_no_pfc_priv_num(struct hns3_hw *hw, 3702 struct hns3_pkt_buf_alloc *buf_alloc) 3703 { 3704 struct hns3_priv_buf *priv; 3705 int cnt = 0; 3706 uint8_t i; 3707 3708 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3709 priv = &buf_alloc->priv_buf[i]; 3710 if (hw->hw_tc_map & BIT(i) && 3711 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3712 cnt++; 3713 } 3714 3715 return cnt; 3716 } 3717 3718 static bool 3719 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, 3720 uint32_t rx_all) 3721 { 3722 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 3723 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3724 struct hns3_pf *pf = &hns->pf; 3725 uint32_t shared_buf, aligned_mps; 3726 uint32_t rx_priv; 3727 uint8_t tc_num; 3728 uint8_t i; 3729 3730 tc_num = hns3_get_tc_num(hw); 3731 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3732 3733 if (hns3_dev_dcb_supported(hw)) 3734 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps + 3735 pf->dv_buf_size; 3736 else 3737 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF 3738 + pf->dv_buf_size; 3739 3740 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 3741 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc), 3742 HNS3_BUF_SIZE_UNIT); 3743 3744 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc); 3745 if (rx_all < rx_priv + shared_std) 3746 return false; 3747 3748 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT); 3749 buf_alloc->s_buf.buf_size = shared_buf; 3750 if (hns3_dev_dcb_supported(hw)) { 3751 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size; 3752 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 3753 - roundup(aligned_mps / HNS3_BUF_DIV_BY, 3754 HNS3_BUF_SIZE_UNIT); 3755 } else { 3756 buf_alloc->s_buf.self.high = 3757 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3758 buf_alloc->s_buf.self.low = aligned_mps; 3759 } 3760 3761 if (hns3_dev_dcb_supported(hw)) { 3762 hi_thrd = shared_buf - pf->dv_buf_size; 3763 3764 if (tc_num <= NEED_RESERVE_TC_NUM) 3765 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT / 3766 BUF_MAX_PERCENT; 3767 3768 if (tc_num) 3769 hi_thrd = hi_thrd / tc_num; 3770 3771 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps); 3772 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT); 3773 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY; 3774 } else { 3775 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3776 lo_thrd = aligned_mps; 3777 } 3778 3779 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3780 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 3781 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 3782 } 3783 3784 return true; 3785 } 3786 3787 static bool 3788 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max, 3789 struct hns3_pkt_buf_alloc *buf_alloc) 3790 { 3791 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3792 struct hns3_pf *pf = &hns->pf; 3793 struct hns3_priv_buf *priv; 3794 uint32_t aligned_mps; 3795 uint32_t rx_all; 3796 uint8_t i; 3797 3798 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3799 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3800 3801 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3802 priv = &buf_alloc->priv_buf[i]; 3803 3804 priv->enable = 0; 3805 priv->wl.low = 0; 3806 priv->wl.high = 0; 3807 priv->buf_size = 0; 3808 3809 if (!(hw->hw_tc_map & BIT(i))) 3810 continue; 3811 3812 priv->enable = 1; 3813 if (hw->dcb_info.hw_pfc_map & BIT(i)) { 3814 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT; 3815 priv->wl.high = roundup(priv->wl.low + aligned_mps, 3816 HNS3_BUF_SIZE_UNIT); 3817 } else { 3818 priv->wl.low = 0; 3819 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) : 3820 aligned_mps; 3821 } 3822 3823 priv->buf_size = priv->wl.high + pf->dv_buf_size; 3824 } 3825 3826 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3827 } 3828 3829 static bool 3830 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw, 3831 struct hns3_pkt_buf_alloc *buf_alloc) 3832 { 3833 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3834 struct hns3_pf *pf = &hns->pf; 3835 struct hns3_priv_buf *priv; 3836 int no_pfc_priv_num; 3837 uint32_t rx_all; 3838 uint8_t mask; 3839 int i; 3840 3841 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3842 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc); 3843 3844 /* let the last to be cleared first */ 3845 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3846 priv = &buf_alloc->priv_buf[i]; 3847 mask = BIT((uint8_t)i); 3848 if (hw->hw_tc_map & mask && 3849 !(hw->dcb_info.hw_pfc_map & mask)) { 3850 /* Clear the no pfc TC private buffer */ 3851 priv->wl.low = 0; 3852 priv->wl.high = 0; 3853 priv->buf_size = 0; 3854 priv->enable = 0; 3855 no_pfc_priv_num--; 3856 } 3857 3858 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3859 no_pfc_priv_num == 0) 3860 break; 3861 } 3862 3863 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3864 } 3865 3866 static bool 3867 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw, 3868 struct hns3_pkt_buf_alloc *buf_alloc) 3869 { 3870 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3871 struct hns3_pf *pf = &hns->pf; 3872 struct hns3_priv_buf *priv; 3873 uint32_t rx_all; 3874 int pfc_priv_num; 3875 uint8_t mask; 3876 int i; 3877 3878 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3879 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc); 3880 3881 /* let the last to be cleared first */ 3882 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3883 priv = &buf_alloc->priv_buf[i]; 3884 mask = BIT((uint8_t)i); 3885 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) { 3886 /* Reduce the number of pfc TC with private buffer */ 3887 priv->wl.low = 0; 3888 priv->enable = 0; 3889 priv->wl.high = 0; 3890 priv->buf_size = 0; 3891 pfc_priv_num--; 3892 } 3893 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3894 pfc_priv_num == 0) 3895 break; 3896 } 3897 3898 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3899 } 3900 3901 static bool 3902 hns3_only_alloc_priv_buff(struct hns3_hw *hw, 3903 struct hns3_pkt_buf_alloc *buf_alloc) 3904 { 3905 #define COMPENSATE_BUFFER 0x3C00 3906 #define COMPENSATE_HALF_MPS_NUM 5 3907 #define PRIV_WL_GAP 0x1800 3908 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3909 struct hns3_pf *pf = &hns->pf; 3910 uint32_t tc_num = hns3_get_tc_num(hw); 3911 uint32_t half_mps = pf->mps >> 1; 3912 struct hns3_priv_buf *priv; 3913 uint32_t min_rx_priv; 3914 uint32_t rx_priv; 3915 uint8_t i; 3916 3917 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3918 if (tc_num) 3919 rx_priv = rx_priv / tc_num; 3920 3921 if (tc_num <= NEED_RESERVE_TC_NUM) 3922 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 3923 3924 /* 3925 * Minimum value of private buffer in rx direction (min_rx_priv) is 3926 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private 3927 * buffer if rx_priv is greater than min_rx_priv. 3928 */ 3929 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER + 3930 COMPENSATE_HALF_MPS_NUM * half_mps; 3931 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT); 3932 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT); 3933 if (rx_priv < min_rx_priv) 3934 return false; 3935 3936 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3937 priv = &buf_alloc->priv_buf[i]; 3938 priv->enable = 0; 3939 priv->wl.low = 0; 3940 priv->wl.high = 0; 3941 priv->buf_size = 0; 3942 3943 if (!(hw->hw_tc_map & BIT(i))) 3944 continue; 3945 3946 priv->enable = 1; 3947 priv->buf_size = rx_priv; 3948 priv->wl.high = rx_priv - pf->dv_buf_size; 3949 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 3950 } 3951 3952 buf_alloc->s_buf.buf_size = 0; 3953 3954 return true; 3955 } 3956 3957 /* 3958 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs 3959 * @hw: pointer to struct hns3_hw 3960 * @buf_alloc: pointer to buffer calculation data 3961 * @return: 0: calculate sucessful, negative: fail 3962 */ 3963 static int 3964 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3965 { 3966 /* When DCB is not supported, rx private buffer is not allocated. */ 3967 if (!hns3_dev_dcb_supported(hw)) { 3968 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3969 struct hns3_pf *pf = &hns->pf; 3970 uint32_t rx_all = pf->pkt_buf_size; 3971 3972 rx_all -= hns3_get_tx_buff_alloced(buf_alloc); 3973 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all)) 3974 return -ENOMEM; 3975 3976 return 0; 3977 } 3978 3979 /* 3980 * Try to allocate privated packet buffer for all TCs without share 3981 * buffer. 3982 */ 3983 if (hns3_only_alloc_priv_buff(hw, buf_alloc)) 3984 return 0; 3985 3986 /* 3987 * Try to allocate privated packet buffer for all TCs with share 3988 * buffer. 3989 */ 3990 if (hns3_rx_buf_calc_all(hw, true, buf_alloc)) 3991 return 0; 3992 3993 /* 3994 * For different application scenes, the enabled port number, TC number 3995 * and no_drop TC number are different. In order to obtain the better 3996 * performance, software could allocate the buffer size and configure 3997 * the waterline by trying to decrease the private buffer size according 3998 * to the order, namely, waterline of valid tc, pfc disabled tc, pfc 3999 * enabled tc. 4000 */ 4001 if (hns3_rx_buf_calc_all(hw, false, buf_alloc)) 4002 return 0; 4003 4004 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc)) 4005 return 0; 4006 4007 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc)) 4008 return 0; 4009 4010 return -ENOMEM; 4011 } 4012 4013 static int 4014 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4015 { 4016 struct hns3_rx_priv_buff_cmd *req; 4017 struct hns3_cmd_desc desc; 4018 uint32_t buf_size; 4019 int ret; 4020 int i; 4021 4022 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false); 4023 req = (struct hns3_rx_priv_buff_cmd *)desc.data; 4024 4025 /* Alloc private buffer TCs */ 4026 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 4027 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i]; 4028 4029 req->buf_num[i] = 4030 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S); 4031 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B); 4032 } 4033 4034 buf_size = buf_alloc->s_buf.buf_size; 4035 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) | 4036 (1 << HNS3_TC0_PRI_BUF_EN_B)); 4037 4038 ret = hns3_cmd_send(hw, &desc, 1); 4039 if (ret) 4040 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret); 4041 4042 return ret; 4043 } 4044 4045 static int 4046 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4047 { 4048 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2 4049 struct hns3_rx_priv_wl_buf *req; 4050 struct hns3_priv_buf *priv; 4051 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM]; 4052 int i, j; 4053 int ret; 4054 4055 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) { 4056 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC, 4057 false); 4058 req = (struct hns3_rx_priv_wl_buf *)desc[i].data; 4059 4060 /* The first descriptor set the NEXT bit to 1 */ 4061 if (i == 0) 4062 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4063 else 4064 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4065 4066 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 4067 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j; 4068 4069 priv = &buf_alloc->priv_buf[idx]; 4070 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >> 4071 HNS3_BUF_UNIT_S); 4072 req->tc_wl[j].high |= 4073 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4074 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >> 4075 HNS3_BUF_UNIT_S); 4076 req->tc_wl[j].low |= 4077 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4078 } 4079 } 4080 4081 /* Send 2 descriptor at one time */ 4082 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM); 4083 if (ret) 4084 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d", 4085 ret); 4086 return ret; 4087 } 4088 4089 static int 4090 hns3_common_thrd_config(struct hns3_hw *hw, 4091 struct hns3_pkt_buf_alloc *buf_alloc) 4092 { 4093 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2 4094 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf; 4095 struct hns3_rx_com_thrd *req; 4096 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM]; 4097 struct hns3_tc_thrd *tc; 4098 int tc_idx; 4099 int i, j; 4100 int ret; 4101 4102 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) { 4103 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC, 4104 false); 4105 req = (struct hns3_rx_com_thrd *)&desc[i].data; 4106 4107 /* The first descriptor set the NEXT bit to 1 */ 4108 if (i == 0) 4109 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4110 else 4111 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4112 4113 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 4114 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j; 4115 tc = &s_buf->tc_thrd[tc_idx]; 4116 4117 req->com_thrd[j].high = 4118 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S); 4119 req->com_thrd[j].high |= 4120 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4121 req->com_thrd[j].low = 4122 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S); 4123 req->com_thrd[j].low |= 4124 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4125 } 4126 } 4127 4128 /* Send 2 descriptors at one time */ 4129 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM); 4130 if (ret) 4131 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret); 4132 4133 return ret; 4134 } 4135 4136 static int 4137 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 4138 { 4139 struct hns3_shared_buf *buf = &buf_alloc->s_buf; 4140 struct hns3_rx_com_wl *req; 4141 struct hns3_cmd_desc desc; 4142 int ret; 4143 4144 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false); 4145 4146 req = (struct hns3_rx_com_wl *)desc.data; 4147 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S); 4148 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4149 4150 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S); 4151 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 4152 4153 ret = hns3_cmd_send(hw, &desc, 1); 4154 if (ret) 4155 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret); 4156 4157 return ret; 4158 } 4159 4160 int 4161 hns3_buffer_alloc(struct hns3_hw *hw) 4162 { 4163 struct hns3_pkt_buf_alloc pkt_buf; 4164 int ret; 4165 4166 memset(&pkt_buf, 0, sizeof(pkt_buf)); 4167 ret = hns3_tx_buffer_calc(hw, &pkt_buf); 4168 if (ret) { 4169 PMD_INIT_LOG(ERR, 4170 "could not calc tx buffer size for all TCs %d", 4171 ret); 4172 return ret; 4173 } 4174 4175 ret = hns3_tx_buffer_alloc(hw, &pkt_buf); 4176 if (ret) { 4177 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret); 4178 return ret; 4179 } 4180 4181 ret = hns3_rx_buffer_calc(hw, &pkt_buf); 4182 if (ret) { 4183 PMD_INIT_LOG(ERR, 4184 "could not calc rx priv buffer size for all TCs %d", 4185 ret); 4186 return ret; 4187 } 4188 4189 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf); 4190 if (ret) { 4191 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret); 4192 return ret; 4193 } 4194 4195 if (hns3_dev_dcb_supported(hw)) { 4196 ret = hns3_rx_priv_wl_config(hw, &pkt_buf); 4197 if (ret) { 4198 PMD_INIT_LOG(ERR, 4199 "could not configure rx private waterline %d", 4200 ret); 4201 return ret; 4202 } 4203 4204 ret = hns3_common_thrd_config(hw, &pkt_buf); 4205 if (ret) { 4206 PMD_INIT_LOG(ERR, 4207 "could not configure common threshold %d", 4208 ret); 4209 return ret; 4210 } 4211 } 4212 4213 ret = hns3_common_wl_config(hw, &pkt_buf); 4214 if (ret) 4215 PMD_INIT_LOG(ERR, "could not configure common waterline %d", 4216 ret); 4217 4218 return ret; 4219 } 4220 4221 static int 4222 hns3_mac_init(struct hns3_hw *hw) 4223 { 4224 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 4225 struct hns3_mac *mac = &hw->mac; 4226 struct hns3_pf *pf = &hns->pf; 4227 int ret; 4228 4229 pf->support_sfp_query = true; 4230 mac->link_duplex = ETH_LINK_FULL_DUPLEX; 4231 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); 4232 if (ret) { 4233 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); 4234 return ret; 4235 } 4236 4237 mac->link_status = ETH_LINK_DOWN; 4238 4239 return hns3_config_mtu(hw, pf->mps); 4240 } 4241 4242 static int 4243 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code) 4244 { 4245 #define HNS3_ETHERTYPE_SUCCESS_ADD 0 4246 #define HNS3_ETHERTYPE_ALREADY_ADD 1 4247 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2 4248 #define HNS3_ETHERTYPE_KEY_CONFLICT 3 4249 int return_status; 4250 4251 if (cmdq_resp) { 4252 PMD_INIT_LOG(ERR, 4253 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n", 4254 cmdq_resp); 4255 return -EIO; 4256 } 4257 4258 switch (resp_code) { 4259 case HNS3_ETHERTYPE_SUCCESS_ADD: 4260 case HNS3_ETHERTYPE_ALREADY_ADD: 4261 return_status = 0; 4262 break; 4263 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW: 4264 PMD_INIT_LOG(ERR, 4265 "add mac ethertype failed for manager table overflow."); 4266 return_status = -EIO; 4267 break; 4268 case HNS3_ETHERTYPE_KEY_CONFLICT: 4269 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict."); 4270 return_status = -EIO; 4271 break; 4272 default: 4273 PMD_INIT_LOG(ERR, 4274 "add mac ethertype failed for undefined, code=%u.", 4275 resp_code); 4276 return_status = -EIO; 4277 break; 4278 } 4279 4280 return return_status; 4281 } 4282 4283 static int 4284 hns3_add_mgr_tbl(struct hns3_hw *hw, 4285 const struct hns3_mac_mgr_tbl_entry_cmd *req) 4286 { 4287 struct hns3_cmd_desc desc; 4288 uint8_t resp_code; 4289 uint16_t retval; 4290 int ret; 4291 4292 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false); 4293 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd)); 4294 4295 ret = hns3_cmd_send(hw, &desc, 1); 4296 if (ret) { 4297 PMD_INIT_LOG(ERR, 4298 "add mac ethertype failed for cmd_send, ret =%d.", 4299 ret); 4300 return ret; 4301 } 4302 4303 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 4304 retval = rte_le_to_cpu_16(desc.retval); 4305 4306 return hns3_get_mac_ethertype_cmd_status(retval, resp_code); 4307 } 4308 4309 static void 4310 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table, 4311 int *table_item_num) 4312 { 4313 struct hns3_mac_mgr_tbl_entry_cmd *tbl; 4314 4315 /* 4316 * In current version, we add one item in management table as below: 4317 * 0x0180C200000E -- LLDP MC address 4318 */ 4319 tbl = mgr_table; 4320 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B; 4321 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP); 4322 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200)); 4323 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E)); 4324 tbl->i_port_bitmap = 0x1; 4325 *table_item_num = 1; 4326 } 4327 4328 static int 4329 hns3_init_mgr_tbl(struct hns3_hw *hw) 4330 { 4331 #define HNS_MAC_MGR_TBL_MAX_SIZE 16 4332 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE]; 4333 int table_item_num; 4334 int ret; 4335 int i; 4336 4337 memset(mgr_table, 0, sizeof(mgr_table)); 4338 hns3_prepare_mgr_tbl(mgr_table, &table_item_num); 4339 for (i = 0; i < table_item_num; i++) { 4340 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]); 4341 if (ret) { 4342 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d", 4343 ret); 4344 return ret; 4345 } 4346 } 4347 4348 return 0; 4349 } 4350 4351 static void 4352 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc, 4353 bool en_mc, bool en_bc, int vport_id) 4354 { 4355 if (!param) 4356 return; 4357 4358 memset(param, 0, sizeof(struct hns3_promisc_param)); 4359 if (en_uc) 4360 param->enable = HNS3_PROMISC_EN_UC; 4361 if (en_mc) 4362 param->enable |= HNS3_PROMISC_EN_MC; 4363 if (en_bc) 4364 param->enable |= HNS3_PROMISC_EN_BC; 4365 param->vf_id = vport_id; 4366 } 4367 4368 static int 4369 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param) 4370 { 4371 struct hns3_promisc_cfg_cmd *req; 4372 struct hns3_cmd_desc desc; 4373 int ret; 4374 4375 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false); 4376 4377 req = (struct hns3_promisc_cfg_cmd *)desc.data; 4378 req->vf_id = param->vf_id; 4379 req->flag = (param->enable << HNS3_PROMISC_EN_B) | 4380 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B; 4381 4382 ret = hns3_cmd_send(hw, &desc, 1); 4383 if (ret) 4384 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret); 4385 4386 return ret; 4387 } 4388 4389 static int 4390 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc) 4391 { 4392 struct hns3_promisc_param param; 4393 bool en_bc_pmc = true; 4394 uint8_t vf_id; 4395 4396 /* 4397 * In current version VF is not supported when PF is driven by DPDK 4398 * driver, just need to configure parameters for PF vport. 4399 */ 4400 vf_id = HNS3_PF_FUNC_ID; 4401 4402 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id); 4403 return hns3_cmd_set_promisc_mode(hw, ¶m); 4404 } 4405 4406 static int 4407 hns3_promisc_init(struct hns3_hw *hw) 4408 { 4409 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 4410 struct hns3_pf *pf = &hns->pf; 4411 struct hns3_promisc_param param; 4412 uint16_t func_id; 4413 int ret; 4414 4415 ret = hns3_set_promisc_mode(hw, false, false); 4416 if (ret) { 4417 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret); 4418 return ret; 4419 } 4420 4421 /* 4422 * In current version VFs are not supported when PF is driven by DPDK 4423 * driver. After PF has been taken over by DPDK, the original VF will 4424 * be invalid. So, there is a possibility of entry residues. It should 4425 * clear VFs's promisc mode to avoid unnecessary bandwidth usage 4426 * during init. 4427 */ 4428 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) { 4429 hns3_promisc_param_init(¶m, false, false, false, func_id); 4430 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 4431 if (ret) { 4432 PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode," 4433 " ret = %d", func_id, ret); 4434 return ret; 4435 } 4436 } 4437 4438 return 0; 4439 } 4440 4441 static void 4442 hns3_promisc_uninit(struct hns3_hw *hw) 4443 { 4444 struct hns3_promisc_param param; 4445 uint16_t func_id; 4446 int ret; 4447 4448 func_id = HNS3_PF_FUNC_ID; 4449 4450 /* 4451 * In current version VFs are not supported when PF is driven by 4452 * DPDK driver, and VFs' promisc mode status has been cleared during 4453 * init and their status will not change. So just clear PF's promisc 4454 * mode status during uninit. 4455 */ 4456 hns3_promisc_param_init(¶m, false, false, false, func_id); 4457 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 4458 if (ret) 4459 PMD_INIT_LOG(ERR, "failed to clear promisc status during" 4460 " uninit, ret = %d", ret); 4461 } 4462 4463 static int 4464 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev) 4465 { 4466 bool allmulti = dev->data->all_multicast ? true : false; 4467 struct hns3_adapter *hns = dev->data->dev_private; 4468 struct hns3_hw *hw = &hns->hw; 4469 uint64_t offloads; 4470 int err; 4471 int ret; 4472 4473 rte_spinlock_lock(&hw->lock); 4474 ret = hns3_set_promisc_mode(hw, true, true); 4475 if (ret) { 4476 rte_spinlock_unlock(&hw->lock); 4477 hns3_err(hw, "failed to enable promiscuous mode, ret = %d", 4478 ret); 4479 return ret; 4480 } 4481 4482 /* 4483 * When promiscuous mode was enabled, disable the vlan filter to let 4484 * all packets coming in in the receiving direction. 4485 */ 4486 offloads = dev->data->dev_conf.rxmode.offloads; 4487 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4488 ret = hns3_enable_vlan_filter(hns, false); 4489 if (ret) { 4490 hns3_err(hw, "failed to enable promiscuous mode due to " 4491 "failure to disable vlan filter, ret = %d", 4492 ret); 4493 err = hns3_set_promisc_mode(hw, false, allmulti); 4494 if (err) 4495 hns3_err(hw, "failed to restore promiscuous " 4496 "status after disable vlan filter " 4497 "failed during enabling promiscuous " 4498 "mode, ret = %d", ret); 4499 } 4500 } 4501 4502 rte_spinlock_unlock(&hw->lock); 4503 4504 return ret; 4505 } 4506 4507 static int 4508 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev) 4509 { 4510 bool allmulti = dev->data->all_multicast ? true : false; 4511 struct hns3_adapter *hns = dev->data->dev_private; 4512 struct hns3_hw *hw = &hns->hw; 4513 uint64_t offloads; 4514 int err; 4515 int ret; 4516 4517 /* If now in all_multicast mode, must remain in all_multicast mode. */ 4518 rte_spinlock_lock(&hw->lock); 4519 ret = hns3_set_promisc_mode(hw, false, allmulti); 4520 if (ret) { 4521 rte_spinlock_unlock(&hw->lock); 4522 hns3_err(hw, "failed to disable promiscuous mode, ret = %d", 4523 ret); 4524 return ret; 4525 } 4526 /* when promiscuous mode was disabled, restore the vlan filter status */ 4527 offloads = dev->data->dev_conf.rxmode.offloads; 4528 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4529 ret = hns3_enable_vlan_filter(hns, true); 4530 if (ret) { 4531 hns3_err(hw, "failed to disable promiscuous mode due to" 4532 " failure to restore vlan filter, ret = %d", 4533 ret); 4534 err = hns3_set_promisc_mode(hw, true, true); 4535 if (err) 4536 hns3_err(hw, "failed to restore promiscuous " 4537 "status after enabling vlan filter " 4538 "failed during disabling promiscuous " 4539 "mode, ret = %d", ret); 4540 } 4541 } 4542 rte_spinlock_unlock(&hw->lock); 4543 4544 return ret; 4545 } 4546 4547 static int 4548 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev) 4549 { 4550 struct hns3_adapter *hns = dev->data->dev_private; 4551 struct hns3_hw *hw = &hns->hw; 4552 int ret; 4553 4554 if (dev->data->promiscuous) 4555 return 0; 4556 4557 rte_spinlock_lock(&hw->lock); 4558 ret = hns3_set_promisc_mode(hw, false, true); 4559 rte_spinlock_unlock(&hw->lock); 4560 if (ret) 4561 hns3_err(hw, "failed to enable allmulticast mode, ret = %d", 4562 ret); 4563 4564 return ret; 4565 } 4566 4567 static int 4568 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev) 4569 { 4570 struct hns3_adapter *hns = dev->data->dev_private; 4571 struct hns3_hw *hw = &hns->hw; 4572 int ret; 4573 4574 /* If now in promiscuous mode, must remain in all_multicast mode. */ 4575 if (dev->data->promiscuous) 4576 return 0; 4577 4578 rte_spinlock_lock(&hw->lock); 4579 ret = hns3_set_promisc_mode(hw, false, false); 4580 rte_spinlock_unlock(&hw->lock); 4581 if (ret) 4582 hns3_err(hw, "failed to disable allmulticast mode, ret = %d", 4583 ret); 4584 4585 return ret; 4586 } 4587 4588 static int 4589 hns3_dev_promisc_restore(struct hns3_adapter *hns) 4590 { 4591 struct hns3_hw *hw = &hns->hw; 4592 bool allmulti = hw->data->all_multicast ? true : false; 4593 int ret; 4594 4595 if (hw->data->promiscuous) { 4596 ret = hns3_set_promisc_mode(hw, true, true); 4597 if (ret) 4598 hns3_err(hw, "failed to restore promiscuous mode, " 4599 "ret = %d", ret); 4600 return ret; 4601 } 4602 4603 ret = hns3_set_promisc_mode(hw, false, allmulti); 4604 if (ret) 4605 hns3_err(hw, "failed to restore allmulticast mode, ret = %d", 4606 ret); 4607 return ret; 4608 } 4609 4610 static int 4611 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info) 4612 { 4613 struct hns3_sfp_info_cmd *resp; 4614 struct hns3_cmd_desc desc; 4615 int ret; 4616 4617 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true); 4618 resp = (struct hns3_sfp_info_cmd *)desc.data; 4619 resp->query_type = HNS3_ACTIVE_QUERY; 4620 4621 ret = hns3_cmd_send(hw, &desc, 1); 4622 if (ret == -EOPNOTSUPP) { 4623 hns3_warn(hw, "firmware does not support get SFP info," 4624 " ret = %d.", ret); 4625 return ret; 4626 } else if (ret) { 4627 hns3_err(hw, "get sfp info failed, ret = %d.", ret); 4628 return ret; 4629 } 4630 4631 /* 4632 * In some case, the speed of MAC obtained from firmware may be 0, it 4633 * shouldn't be set to mac->speed. 4634 */ 4635 if (!rte_le_to_cpu_32(resp->sfp_speed)) 4636 return 0; 4637 4638 mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed); 4639 /* 4640 * if resp->supported_speed is 0, it means it's an old version 4641 * firmware, do not update these params. 4642 */ 4643 if (resp->supported_speed) { 4644 mac_info->query_type = HNS3_ACTIVE_QUERY; 4645 mac_info->supported_speed = 4646 rte_le_to_cpu_32(resp->supported_speed); 4647 mac_info->support_autoneg = resp->autoneg_ability; 4648 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED 4649 : ETH_LINK_AUTONEG; 4650 } else { 4651 mac_info->query_type = HNS3_DEFAULT_QUERY; 4652 } 4653 4654 return 0; 4655 } 4656 4657 static uint8_t 4658 hns3_check_speed_dup(uint8_t duplex, uint32_t speed) 4659 { 4660 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M)) 4661 duplex = ETH_LINK_FULL_DUPLEX; 4662 4663 return duplex; 4664 } 4665 4666 static int 4667 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 4668 { 4669 struct hns3_mac *mac = &hw->mac; 4670 int ret; 4671 4672 duplex = hns3_check_speed_dup(duplex, speed); 4673 if (mac->link_speed == speed && mac->link_duplex == duplex) 4674 return 0; 4675 4676 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); 4677 if (ret) 4678 return ret; 4679 4680 ret = hns3_port_shaper_update(hw, speed); 4681 if (ret) 4682 return ret; 4683 4684 mac->link_speed = speed; 4685 mac->link_duplex = duplex; 4686 4687 return 0; 4688 } 4689 4690 static int 4691 hns3_update_fiber_link_info(struct hns3_hw *hw) 4692 { 4693 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 4694 struct hns3_mac *mac = &hw->mac; 4695 struct hns3_mac mac_info; 4696 int ret; 4697 4698 /* If firmware do not support get SFP/qSFP speed, return directly */ 4699 if (!pf->support_sfp_query) 4700 return 0; 4701 4702 memset(&mac_info, 0, sizeof(struct hns3_mac)); 4703 ret = hns3_get_sfp_info(hw, &mac_info); 4704 if (ret == -EOPNOTSUPP) { 4705 pf->support_sfp_query = false; 4706 return ret; 4707 } else if (ret) 4708 return ret; 4709 4710 /* Do nothing if no SFP */ 4711 if (mac_info.link_speed == ETH_SPEED_NUM_NONE) 4712 return 0; 4713 4714 /* 4715 * If query_type is HNS3_ACTIVE_QUERY, it is no need 4716 * to reconfigure the speed of MAC. Otherwise, it indicates 4717 * that the current firmware only supports to obtain the 4718 * speed of the SFP, and the speed of MAC needs to reconfigure. 4719 */ 4720 mac->query_type = mac_info.query_type; 4721 if (mac->query_type == HNS3_ACTIVE_QUERY) { 4722 if (mac_info.link_speed != mac->link_speed) { 4723 ret = hns3_port_shaper_update(hw, mac_info.link_speed); 4724 if (ret) 4725 return ret; 4726 } 4727 4728 mac->link_speed = mac_info.link_speed; 4729 mac->supported_speed = mac_info.supported_speed; 4730 mac->support_autoneg = mac_info.support_autoneg; 4731 mac->link_autoneg = mac_info.link_autoneg; 4732 4733 return 0; 4734 } 4735 4736 /* Config full duplex for SFP */ 4737 return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed, 4738 ETH_LINK_FULL_DUPLEX); 4739 } 4740 4741 static void 4742 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac) 4743 { 4744 #define HNS3_PHY_SUPPORTED_SPEED_MASK 0x2f 4745 4746 struct hns3_phy_params_bd0_cmd *req; 4747 uint32_t supported; 4748 4749 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data; 4750 mac->link_speed = rte_le_to_cpu_32(req->speed); 4751 mac->link_duplex = hns3_get_bit(req->duplex, 4752 HNS3_PHY_DUPLEX_CFG_B); 4753 mac->link_autoneg = hns3_get_bit(req->autoneg, 4754 HNS3_PHY_AUTONEG_CFG_B); 4755 mac->advertising = rte_le_to_cpu_32(req->advertising); 4756 mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising); 4757 supported = rte_le_to_cpu_32(req->supported); 4758 mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK; 4759 mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT); 4760 } 4761 4762 static int 4763 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac) 4764 { 4765 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM]; 4766 uint16_t i; 4767 int ret; 4768 4769 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) { 4770 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, 4771 true); 4772 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 4773 } 4774 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true); 4775 4776 ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM); 4777 if (ret) { 4778 hns3_err(hw, "get phy parameters failed, ret = %d.", ret); 4779 return ret; 4780 } 4781 4782 hns3_parse_copper_phy_params(desc, mac); 4783 4784 return 0; 4785 } 4786 4787 static int 4788 hns3_update_copper_link_info(struct hns3_hw *hw) 4789 { 4790 struct hns3_mac *mac = &hw->mac; 4791 struct hns3_mac mac_info; 4792 int ret; 4793 4794 memset(&mac_info, 0, sizeof(struct hns3_mac)); 4795 ret = hns3_get_copper_phy_params(hw, &mac_info); 4796 if (ret) 4797 return ret; 4798 4799 if (mac_info.link_speed != mac->link_speed) { 4800 ret = hns3_port_shaper_update(hw, mac_info.link_speed); 4801 if (ret) 4802 return ret; 4803 } 4804 4805 mac->link_speed = mac_info.link_speed; 4806 mac->link_duplex = mac_info.link_duplex; 4807 mac->link_autoneg = mac_info.link_autoneg; 4808 mac->supported_speed = mac_info.supported_speed; 4809 mac->advertising = mac_info.advertising; 4810 mac->lp_advertising = mac_info.lp_advertising; 4811 mac->support_autoneg = mac_info.support_autoneg; 4812 4813 return 0; 4814 } 4815 4816 static int 4817 hns3_update_link_info(struct rte_eth_dev *eth_dev) 4818 { 4819 struct hns3_adapter *hns = eth_dev->data->dev_private; 4820 struct hns3_hw *hw = &hns->hw; 4821 int ret = 0; 4822 4823 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) 4824 ret = hns3_update_copper_link_info(hw); 4825 else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) 4826 ret = hns3_update_fiber_link_info(hw); 4827 4828 return ret; 4829 } 4830 4831 static int 4832 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable) 4833 { 4834 struct hns3_config_mac_mode_cmd *req; 4835 struct hns3_cmd_desc desc; 4836 uint32_t loop_en = 0; 4837 uint8_t val = 0; 4838 int ret; 4839 4840 req = (struct hns3_config_mac_mode_cmd *)desc.data; 4841 4842 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false); 4843 if (enable) 4844 val = 1; 4845 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val); 4846 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val); 4847 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val); 4848 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val); 4849 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0); 4850 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0); 4851 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0); 4852 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0); 4853 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val); 4854 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val); 4855 4856 /* 4857 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC 4858 * when receiving frames. Otherwise, CRC will be stripped. 4859 */ 4860 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) 4861 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0); 4862 else 4863 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val); 4864 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val); 4865 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val); 4866 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val); 4867 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en); 4868 4869 ret = hns3_cmd_send(hw, &desc, 1); 4870 if (ret) 4871 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret); 4872 4873 return ret; 4874 } 4875 4876 static int 4877 hns3_get_mac_link_status(struct hns3_hw *hw) 4878 { 4879 struct hns3_link_status_cmd *req; 4880 struct hns3_cmd_desc desc; 4881 int link_status; 4882 int ret; 4883 4884 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true); 4885 ret = hns3_cmd_send(hw, &desc, 1); 4886 if (ret) { 4887 hns3_err(hw, "get link status cmd failed %d", ret); 4888 return ETH_LINK_DOWN; 4889 } 4890 4891 req = (struct hns3_link_status_cmd *)desc.data; 4892 link_status = req->status & HNS3_LINK_STATUS_UP_M; 4893 4894 return !!link_status; 4895 } 4896 4897 static bool 4898 hns3_update_link_status(struct hns3_hw *hw) 4899 { 4900 int state; 4901 4902 state = hns3_get_mac_link_status(hw); 4903 if (state != hw->mac.link_status) { 4904 hw->mac.link_status = state; 4905 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down"); 4906 return true; 4907 } 4908 4909 return false; 4910 } 4911 4912 void 4913 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query) 4914 { 4915 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 4916 struct rte_eth_link new_link; 4917 int ret; 4918 4919 if (query) 4920 hns3_update_port_link_info(dev); 4921 4922 memset(&new_link, 0, sizeof(new_link)); 4923 hns3_setup_linkstatus(dev, &new_link); 4924 4925 ret = rte_eth_linkstatus_set(dev, &new_link); 4926 if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0) 4927 hns3_start_report_lse(dev); 4928 } 4929 4930 static void 4931 hns3_service_handler(void *param) 4932 { 4933 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 4934 struct hns3_adapter *hns = eth_dev->data->dev_private; 4935 struct hns3_hw *hw = &hns->hw; 4936 4937 if (!hns3_is_reset_pending(hns)) 4938 hns3_update_linkstatus_and_event(hw, true); 4939 else 4940 hns3_warn(hw, "Cancel the query when reset is pending"); 4941 4942 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev); 4943 } 4944 4945 static int 4946 hns3_init_hardware(struct hns3_adapter *hns) 4947 { 4948 struct hns3_hw *hw = &hns->hw; 4949 int ret; 4950 4951 ret = hns3_map_tqp(hw); 4952 if (ret) { 4953 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret); 4954 return ret; 4955 } 4956 4957 ret = hns3_init_umv_space(hw); 4958 if (ret) { 4959 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret); 4960 return ret; 4961 } 4962 4963 ret = hns3_mac_init(hw); 4964 if (ret) { 4965 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret); 4966 goto err_mac_init; 4967 } 4968 4969 ret = hns3_init_mgr_tbl(hw); 4970 if (ret) { 4971 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret); 4972 goto err_mac_init; 4973 } 4974 4975 ret = hns3_promisc_init(hw); 4976 if (ret) { 4977 PMD_INIT_LOG(ERR, "Failed to init promisc: %d", 4978 ret); 4979 goto err_mac_init; 4980 } 4981 4982 ret = hns3_init_vlan_config(hns); 4983 if (ret) { 4984 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret); 4985 goto err_mac_init; 4986 } 4987 4988 ret = hns3_dcb_init(hw); 4989 if (ret) { 4990 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret); 4991 goto err_mac_init; 4992 } 4993 4994 ret = hns3_init_fd_config(hns); 4995 if (ret) { 4996 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret); 4997 goto err_mac_init; 4998 } 4999 5000 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX); 5001 if (ret) { 5002 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret); 5003 goto err_mac_init; 5004 } 5005 5006 ret = hns3_config_gro(hw, false); 5007 if (ret) { 5008 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 5009 goto err_mac_init; 5010 } 5011 5012 /* 5013 * In the initialization clearing the all hardware mapping relationship 5014 * configurations between queues and interrupt vectors is needed, so 5015 * some error caused by the residual configurations, such as the 5016 * unexpected interrupt, can be avoid. 5017 */ 5018 ret = hns3_init_ring_with_vector(hw); 5019 if (ret) { 5020 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 5021 goto err_mac_init; 5022 } 5023 5024 return 0; 5025 5026 err_mac_init: 5027 hns3_uninit_umv_space(hw); 5028 return ret; 5029 } 5030 5031 static int 5032 hns3_clear_hw(struct hns3_hw *hw) 5033 { 5034 struct hns3_cmd_desc desc; 5035 int ret; 5036 5037 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false); 5038 5039 ret = hns3_cmd_send(hw, &desc, 1); 5040 if (ret && ret != -EOPNOTSUPP) 5041 return ret; 5042 5043 return 0; 5044 } 5045 5046 static void 5047 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable) 5048 { 5049 uint32_t val; 5050 5051 /* 5052 * The new firmware support report more hardware error types by 5053 * msix mode. These errors are defined as RAS errors in hardware 5054 * and belong to a different type from the MSI-x errors processed 5055 * by the network driver. 5056 * 5057 * Network driver should open the new error report on initialization. 5058 */ 5059 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5060 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0); 5061 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val); 5062 } 5063 5064 static uint32_t 5065 hns3_set_firber_default_support_speed(struct hns3_hw *hw) 5066 { 5067 struct hns3_mac *mac = &hw->mac; 5068 5069 switch (mac->link_speed) { 5070 case ETH_SPEED_NUM_1G: 5071 return HNS3_FIBER_LINK_SPEED_1G_BIT; 5072 case ETH_SPEED_NUM_10G: 5073 return HNS3_FIBER_LINK_SPEED_10G_BIT; 5074 case ETH_SPEED_NUM_25G: 5075 return HNS3_FIBER_LINK_SPEED_25G_BIT; 5076 case ETH_SPEED_NUM_40G: 5077 return HNS3_FIBER_LINK_SPEED_40G_BIT; 5078 case ETH_SPEED_NUM_50G: 5079 return HNS3_FIBER_LINK_SPEED_50G_BIT; 5080 case ETH_SPEED_NUM_100G: 5081 return HNS3_FIBER_LINK_SPEED_100G_BIT; 5082 case ETH_SPEED_NUM_200G: 5083 return HNS3_FIBER_LINK_SPEED_200G_BIT; 5084 default: 5085 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed); 5086 return 0; 5087 } 5088 } 5089 5090 /* 5091 * Validity of supported_speed for firber and copper media type can be 5092 * guaranteed by the following policy: 5093 * Copper: 5094 * Although the initialization of the phy in the firmware may not be 5095 * completed, the firmware can guarantees that the supported_speed is 5096 * an valid value. 5097 * Firber: 5098 * If the version of firmware supports the acitive query way of the 5099 * HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained 5100 * through it. If unsupported, use the SFP's speed as the value of the 5101 * supported_speed. 5102 */ 5103 static int 5104 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev) 5105 { 5106 struct hns3_adapter *hns = eth_dev->data->dev_private; 5107 struct hns3_hw *hw = &hns->hw; 5108 struct hns3_mac *mac = &hw->mac; 5109 int ret; 5110 5111 ret = hns3_update_link_info(eth_dev); 5112 if (ret) 5113 return ret; 5114 5115 if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) { 5116 /* 5117 * Some firmware does not support the report of supported_speed, 5118 * and only report the effective speed of SFP. In this case, it 5119 * is necessary to use the SFP's speed as the supported_speed. 5120 */ 5121 if (mac->supported_speed == 0) 5122 mac->supported_speed = 5123 hns3_set_firber_default_support_speed(hw); 5124 } 5125 5126 return 0; 5127 } 5128 5129 static void 5130 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns) 5131 { 5132 struct hns3_mac *mac = &hns->hw.mac; 5133 5134 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) { 5135 hns->pf.support_fc_autoneg = true; 5136 return; 5137 } 5138 5139 /* 5140 * Flow control auto-negotiation requires the cooperation of the driver 5141 * and firmware. Currently, the optical port does not support flow 5142 * control auto-negotiation. 5143 */ 5144 hns->pf.support_fc_autoneg = false; 5145 } 5146 5147 static int 5148 hns3_init_pf(struct rte_eth_dev *eth_dev) 5149 { 5150 struct rte_device *dev = eth_dev->device; 5151 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 5152 struct hns3_adapter *hns = eth_dev->data->dev_private; 5153 struct hns3_hw *hw = &hns->hw; 5154 int ret; 5155 5156 PMD_INIT_FUNC_TRACE(); 5157 5158 /* Get hardware io base address from pcie BAR2 IO space */ 5159 hw->io_base = pci_dev->mem_resource[2].addr; 5160 5161 /* Firmware command queue initialize */ 5162 ret = hns3_cmd_init_queue(hw); 5163 if (ret) { 5164 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 5165 goto err_cmd_init_queue; 5166 } 5167 5168 hns3_clear_all_event_cause(hw); 5169 5170 /* Firmware command initialize */ 5171 ret = hns3_cmd_init(hw); 5172 if (ret) { 5173 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 5174 goto err_cmd_init; 5175 } 5176 5177 hns3_tx_push_init(eth_dev); 5178 5179 /* 5180 * To ensure that the hardware environment is clean during 5181 * initialization, the driver actively clear the hardware environment 5182 * during initialization, including PF and corresponding VFs' vlan, mac, 5183 * flow table configurations, etc. 5184 */ 5185 ret = hns3_clear_hw(hw); 5186 if (ret) { 5187 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret); 5188 goto err_cmd_init; 5189 } 5190 5191 /* Hardware statistics of imissed registers cleared. */ 5192 ret = hns3_update_imissed_stats(hw, true); 5193 if (ret) { 5194 hns3_err(hw, "clear imissed stats failed, ret = %d", ret); 5195 goto err_cmd_init; 5196 } 5197 5198 hns3_config_all_msix_error(hw, true); 5199 5200 ret = rte_intr_callback_register(&pci_dev->intr_handle, 5201 hns3_interrupt_handler, 5202 eth_dev); 5203 if (ret) { 5204 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 5205 goto err_intr_callback_register; 5206 } 5207 5208 ret = hns3_ptp_init(hw); 5209 if (ret) 5210 goto err_get_config; 5211 5212 /* Enable interrupt */ 5213 rte_intr_enable(&pci_dev->intr_handle); 5214 hns3_pf_enable_irq0(hw); 5215 5216 /* Get configuration */ 5217 ret = hns3_get_configuration(hw); 5218 if (ret) { 5219 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 5220 goto err_get_config; 5221 } 5222 5223 ret = hns3_tqp_stats_init(hw); 5224 if (ret) 5225 goto err_get_config; 5226 5227 ret = hns3_init_hardware(hns); 5228 if (ret) { 5229 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret); 5230 goto err_init_hw; 5231 } 5232 5233 /* Initialize flow director filter list & hash */ 5234 ret = hns3_fdir_filter_init(hns); 5235 if (ret) { 5236 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret); 5237 goto err_fdir; 5238 } 5239 5240 hns3_rss_set_default_args(hw); 5241 5242 ret = hns3_enable_hw_error_intr(hns, true); 5243 if (ret) { 5244 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d", 5245 ret); 5246 goto err_enable_intr; 5247 } 5248 5249 ret = hns3_get_port_supported_speed(eth_dev); 5250 if (ret) { 5251 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported " 5252 "by device, ret = %d.", ret); 5253 goto err_supported_speed; 5254 } 5255 5256 hns3_get_fc_autoneg_capability(hns); 5257 5258 hns3_tm_conf_init(eth_dev); 5259 5260 return 0; 5261 5262 err_supported_speed: 5263 (void)hns3_enable_hw_error_intr(hns, false); 5264 err_enable_intr: 5265 hns3_fdir_filter_uninit(hns); 5266 err_fdir: 5267 hns3_uninit_umv_space(hw); 5268 err_init_hw: 5269 hns3_tqp_stats_uninit(hw); 5270 err_get_config: 5271 hns3_pf_disable_irq0(hw); 5272 rte_intr_disable(&pci_dev->intr_handle); 5273 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 5274 eth_dev); 5275 err_intr_callback_register: 5276 err_cmd_init: 5277 hns3_cmd_uninit(hw); 5278 hns3_cmd_destroy_queue(hw); 5279 err_cmd_init_queue: 5280 hw->io_base = NULL; 5281 5282 return ret; 5283 } 5284 5285 static void 5286 hns3_uninit_pf(struct rte_eth_dev *eth_dev) 5287 { 5288 struct hns3_adapter *hns = eth_dev->data->dev_private; 5289 struct rte_device *dev = eth_dev->device; 5290 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 5291 struct hns3_hw *hw = &hns->hw; 5292 5293 PMD_INIT_FUNC_TRACE(); 5294 5295 hns3_tm_conf_uninit(eth_dev); 5296 hns3_enable_hw_error_intr(hns, false); 5297 hns3_rss_uninit(hns); 5298 (void)hns3_config_gro(hw, false); 5299 hns3_promisc_uninit(hw); 5300 hns3_fdir_filter_uninit(hns); 5301 hns3_uninit_umv_space(hw); 5302 hns3_tqp_stats_uninit(hw); 5303 hns3_config_mac_tnl_int(hw, false); 5304 hns3_pf_disable_irq0(hw); 5305 rte_intr_disable(&pci_dev->intr_handle); 5306 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 5307 eth_dev); 5308 hns3_config_all_msix_error(hw, false); 5309 hns3_cmd_uninit(hw); 5310 hns3_cmd_destroy_queue(hw); 5311 hw->io_base = NULL; 5312 } 5313 5314 static uint32_t 5315 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds) 5316 { 5317 uint32_t speed_bit; 5318 5319 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) { 5320 case ETH_LINK_SPEED_10M: 5321 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT; 5322 break; 5323 case ETH_LINK_SPEED_10M_HD: 5324 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT; 5325 break; 5326 case ETH_LINK_SPEED_100M: 5327 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT; 5328 break; 5329 case ETH_LINK_SPEED_100M_HD: 5330 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT; 5331 break; 5332 case ETH_LINK_SPEED_1G: 5333 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT; 5334 break; 5335 default: 5336 speed_bit = 0; 5337 break; 5338 } 5339 5340 return speed_bit; 5341 } 5342 5343 static uint32_t 5344 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds) 5345 { 5346 uint32_t speed_bit; 5347 5348 switch (link_speeds & ~ETH_LINK_SPEED_FIXED) { 5349 case ETH_LINK_SPEED_1G: 5350 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT; 5351 break; 5352 case ETH_LINK_SPEED_10G: 5353 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT; 5354 break; 5355 case ETH_LINK_SPEED_25G: 5356 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT; 5357 break; 5358 case ETH_LINK_SPEED_40G: 5359 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT; 5360 break; 5361 case ETH_LINK_SPEED_50G: 5362 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT; 5363 break; 5364 case ETH_LINK_SPEED_100G: 5365 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT; 5366 break; 5367 case ETH_LINK_SPEED_200G: 5368 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT; 5369 break; 5370 default: 5371 speed_bit = 0; 5372 break; 5373 } 5374 5375 return speed_bit; 5376 } 5377 5378 static int 5379 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds) 5380 { 5381 struct hns3_mac *mac = &hw->mac; 5382 uint32_t supported_speed = mac->supported_speed; 5383 uint32_t speed_bit = 0; 5384 5385 if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) 5386 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds); 5387 else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) 5388 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds); 5389 5390 if (!(speed_bit & supported_speed)) { 5391 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.", 5392 link_speeds); 5393 return -EINVAL; 5394 } 5395 5396 return 0; 5397 } 5398 5399 static inline uint32_t 5400 hns3_get_link_speed(uint32_t link_speeds) 5401 { 5402 uint32_t speed = ETH_SPEED_NUM_NONE; 5403 5404 if (link_speeds & ETH_LINK_SPEED_10M || 5405 link_speeds & ETH_LINK_SPEED_10M_HD) 5406 speed = ETH_SPEED_NUM_10M; 5407 if (link_speeds & ETH_LINK_SPEED_100M || 5408 link_speeds & ETH_LINK_SPEED_100M_HD) 5409 speed = ETH_SPEED_NUM_100M; 5410 if (link_speeds & ETH_LINK_SPEED_1G) 5411 speed = ETH_SPEED_NUM_1G; 5412 if (link_speeds & ETH_LINK_SPEED_10G) 5413 speed = ETH_SPEED_NUM_10G; 5414 if (link_speeds & ETH_LINK_SPEED_25G) 5415 speed = ETH_SPEED_NUM_25G; 5416 if (link_speeds & ETH_LINK_SPEED_40G) 5417 speed = ETH_SPEED_NUM_40G; 5418 if (link_speeds & ETH_LINK_SPEED_50G) 5419 speed = ETH_SPEED_NUM_50G; 5420 if (link_speeds & ETH_LINK_SPEED_100G) 5421 speed = ETH_SPEED_NUM_100G; 5422 if (link_speeds & ETH_LINK_SPEED_200G) 5423 speed = ETH_SPEED_NUM_200G; 5424 5425 return speed; 5426 } 5427 5428 static uint8_t 5429 hns3_get_link_duplex(uint32_t link_speeds) 5430 { 5431 if ((link_speeds & ETH_LINK_SPEED_10M_HD) || 5432 (link_speeds & ETH_LINK_SPEED_100M_HD)) 5433 return ETH_LINK_HALF_DUPLEX; 5434 else 5435 return ETH_LINK_FULL_DUPLEX; 5436 } 5437 5438 static int 5439 hns3_set_copper_port_link_speed(struct hns3_hw *hw, 5440 struct hns3_set_link_speed_cfg *cfg) 5441 { 5442 struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM]; 5443 struct hns3_phy_params_bd0_cmd *req; 5444 uint16_t i; 5445 5446 for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) { 5447 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, 5448 false); 5449 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 5450 } 5451 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false); 5452 req = (struct hns3_phy_params_bd0_cmd *)desc[0].data; 5453 req->autoneg = cfg->autoneg; 5454 5455 /* 5456 * The full speed capability is used to negotiate when 5457 * auto-negotiation is enabled. 5458 */ 5459 if (cfg->autoneg) { 5460 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT | 5461 HNS3_PHY_LINK_SPEED_10M_HD_BIT | 5462 HNS3_PHY_LINK_SPEED_100M_BIT | 5463 HNS3_PHY_LINK_SPEED_100M_HD_BIT | 5464 HNS3_PHY_LINK_SPEED_1000M_BIT; 5465 } else { 5466 req->speed = cfg->speed; 5467 req->duplex = cfg->duplex; 5468 } 5469 5470 return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM); 5471 } 5472 5473 static int 5474 hns3_set_autoneg(struct hns3_hw *hw, bool enable) 5475 { 5476 struct hns3_config_auto_neg_cmd *req; 5477 struct hns3_cmd_desc desc; 5478 uint32_t flag = 0; 5479 int ret; 5480 5481 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false); 5482 5483 req = (struct hns3_config_auto_neg_cmd *)desc.data; 5484 if (enable) 5485 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1); 5486 req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag); 5487 5488 ret = hns3_cmd_send(hw, &desc, 1); 5489 if (ret) 5490 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret); 5491 5492 return ret; 5493 } 5494 5495 static int 5496 hns3_set_fiber_port_link_speed(struct hns3_hw *hw, 5497 struct hns3_set_link_speed_cfg *cfg) 5498 { 5499 int ret; 5500 5501 if (hw->mac.support_autoneg) { 5502 ret = hns3_set_autoneg(hw, cfg->autoneg); 5503 if (ret) { 5504 hns3_err(hw, "failed to configure auto-negotiation."); 5505 return ret; 5506 } 5507 5508 /* 5509 * To enable auto-negotiation, we only need to open the switch 5510 * of auto-negotiation, then firmware sets all speed 5511 * capabilities. 5512 */ 5513 if (cfg->autoneg) 5514 return 0; 5515 } 5516 5517 /* 5518 * Some hardware doesn't support auto-negotiation, but users may not 5519 * configure link_speeds (default 0), which means auto-negotiation. 5520 * In this case, it should return success. 5521 */ 5522 if (cfg->autoneg) 5523 return 0; 5524 5525 return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex); 5526 } 5527 5528 static int 5529 hns3_set_port_link_speed(struct hns3_hw *hw, 5530 struct hns3_set_link_speed_cfg *cfg) 5531 { 5532 int ret; 5533 5534 if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) { 5535 #if defined(RTE_HNS3_ONLY_1630_FPGA) 5536 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 5537 if (pf->is_tmp_phy) 5538 return 0; 5539 #endif 5540 5541 ret = hns3_set_copper_port_link_speed(hw, cfg); 5542 if (ret) { 5543 hns3_err(hw, "failed to set copper port link speed," 5544 "ret = %d.", ret); 5545 return ret; 5546 } 5547 } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) { 5548 ret = hns3_set_fiber_port_link_speed(hw, cfg); 5549 if (ret) { 5550 hns3_err(hw, "failed to set fiber port link speed," 5551 "ret = %d.", ret); 5552 return ret; 5553 } 5554 } 5555 5556 return 0; 5557 } 5558 5559 static int 5560 hns3_apply_link_speed(struct hns3_hw *hw) 5561 { 5562 struct rte_eth_conf *conf = &hw->data->dev_conf; 5563 struct hns3_set_link_speed_cfg cfg; 5564 5565 memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg)); 5566 cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ? 5567 ETH_LINK_AUTONEG : ETH_LINK_FIXED; 5568 if (cfg.autoneg != ETH_LINK_AUTONEG) { 5569 cfg.speed = hns3_get_link_speed(conf->link_speeds); 5570 cfg.duplex = hns3_get_link_duplex(conf->link_speeds); 5571 } 5572 5573 return hns3_set_port_link_speed(hw, &cfg); 5574 } 5575 5576 static int 5577 hns3_do_start(struct hns3_adapter *hns, bool reset_queue) 5578 { 5579 struct hns3_hw *hw = &hns->hw; 5580 int ret; 5581 5582 ret = hns3_update_queue_map_configure(hns); 5583 if (ret) { 5584 hns3_err(hw, "failed to update queue mapping configuration, ret = %d", 5585 ret); 5586 return ret; 5587 } 5588 5589 /* Note: hns3_tm_conf_update must be called after configuring DCB. */ 5590 ret = hns3_tm_conf_update(hw); 5591 if (ret) { 5592 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret); 5593 return ret; 5594 } 5595 5596 hns3_enable_rxd_adv_layout(hw); 5597 5598 ret = hns3_init_queues(hns, reset_queue); 5599 if (ret) { 5600 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret); 5601 return ret; 5602 } 5603 5604 ret = hns3_cfg_mac_mode(hw, true); 5605 if (ret) { 5606 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret); 5607 goto err_config_mac_mode; 5608 } 5609 5610 ret = hns3_apply_link_speed(hw); 5611 if (ret) 5612 goto err_set_link_speed; 5613 5614 return 0; 5615 5616 err_set_link_speed: 5617 (void)hns3_cfg_mac_mode(hw, false); 5618 5619 err_config_mac_mode: 5620 hns3_dev_release_mbufs(hns); 5621 /* 5622 * Here is exception handling, hns3_reset_all_tqps will have the 5623 * corresponding error message if it is handled incorrectly, so it is 5624 * not necessary to check hns3_reset_all_tqps return value, here keep 5625 * ret as the error code causing the exception. 5626 */ 5627 (void)hns3_reset_all_tqps(hns); 5628 return ret; 5629 } 5630 5631 static int 5632 hns3_map_rx_interrupt(struct rte_eth_dev *dev) 5633 { 5634 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5635 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5636 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5637 uint16_t base = RTE_INTR_VEC_ZERO_OFFSET; 5638 uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET; 5639 uint32_t intr_vector; 5640 uint16_t q_id; 5641 int ret; 5642 5643 /* 5644 * hns3 needs a separate interrupt to be used as event interrupt which 5645 * could not be shared with task queue pair, so KERNEL drivers need 5646 * support multiple interrupt vectors. 5647 */ 5648 if (dev->data->dev_conf.intr_conf.rxq == 0 || 5649 !rte_intr_cap_multiple(intr_handle)) 5650 return 0; 5651 5652 rte_intr_disable(intr_handle); 5653 intr_vector = hw->used_rx_queues; 5654 /* creates event fd for each intr vector when MSIX is used */ 5655 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5656 return -EINVAL; 5657 5658 if (intr_handle->intr_vec == NULL) { 5659 intr_handle->intr_vec = 5660 rte_zmalloc("intr_vec", 5661 hw->used_rx_queues * sizeof(int), 0); 5662 if (intr_handle->intr_vec == NULL) { 5663 hns3_err(hw, "failed to allocate %u rx_queues intr_vec", 5664 hw->used_rx_queues); 5665 ret = -ENOMEM; 5666 goto alloc_intr_vec_error; 5667 } 5668 } 5669 5670 if (rte_intr_allow_others(intr_handle)) { 5671 vec = RTE_INTR_VEC_RXTX_OFFSET; 5672 base = RTE_INTR_VEC_RXTX_OFFSET; 5673 } 5674 5675 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 5676 ret = hns3_bind_ring_with_vector(hw, vec, true, 5677 HNS3_RING_TYPE_RX, q_id); 5678 if (ret) 5679 goto bind_vector_error; 5680 intr_handle->intr_vec[q_id] = vec; 5681 /* 5682 * If there are not enough efds (e.g. not enough interrupt), 5683 * remaining queues will be bond to the last interrupt. 5684 */ 5685 if (vec < base + intr_handle->nb_efd - 1) 5686 vec++; 5687 } 5688 rte_intr_enable(intr_handle); 5689 return 0; 5690 5691 bind_vector_error: 5692 rte_free(intr_handle->intr_vec); 5693 intr_handle->intr_vec = NULL; 5694 alloc_intr_vec_error: 5695 rte_intr_efd_disable(intr_handle); 5696 return ret; 5697 } 5698 5699 static int 5700 hns3_restore_rx_interrupt(struct hns3_hw *hw) 5701 { 5702 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 5703 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5704 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5705 uint16_t q_id; 5706 int ret; 5707 5708 if (dev->data->dev_conf.intr_conf.rxq == 0) 5709 return 0; 5710 5711 if (rte_intr_dp_is_en(intr_handle)) { 5712 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 5713 ret = hns3_bind_ring_with_vector(hw, 5714 intr_handle->intr_vec[q_id], true, 5715 HNS3_RING_TYPE_RX, q_id); 5716 if (ret) 5717 return ret; 5718 } 5719 } 5720 5721 return 0; 5722 } 5723 5724 static void 5725 hns3_restore_filter(struct rte_eth_dev *dev) 5726 { 5727 hns3_restore_rss_filter(dev); 5728 } 5729 5730 static int 5731 hns3_dev_start(struct rte_eth_dev *dev) 5732 { 5733 struct hns3_adapter *hns = dev->data->dev_private; 5734 struct hns3_hw *hw = &hns->hw; 5735 int ret; 5736 5737 PMD_INIT_FUNC_TRACE(); 5738 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) 5739 return -EBUSY; 5740 5741 rte_spinlock_lock(&hw->lock); 5742 hw->adapter_state = HNS3_NIC_STARTING; 5743 5744 ret = hns3_do_start(hns, true); 5745 if (ret) { 5746 hw->adapter_state = HNS3_NIC_CONFIGURED; 5747 rte_spinlock_unlock(&hw->lock); 5748 return ret; 5749 } 5750 ret = hns3_map_rx_interrupt(dev); 5751 if (ret) 5752 goto map_rx_inter_err; 5753 5754 /* 5755 * There are three register used to control the status of a TQP 5756 * (contains a pair of Tx queue and Rx queue) in the new version network 5757 * engine. One is used to control the enabling of Tx queue, the other is 5758 * used to control the enabling of Rx queue, and the last is the master 5759 * switch used to control the enabling of the tqp. The Tx register and 5760 * TQP register must be enabled at the same time to enable a Tx queue. 5761 * The same applies to the Rx queue. For the older network engine, this 5762 * function only refresh the enabled flag, and it is used to update the 5763 * status of queue in the dpdk framework. 5764 */ 5765 ret = hns3_start_all_txqs(dev); 5766 if (ret) 5767 goto map_rx_inter_err; 5768 5769 ret = hns3_start_all_rxqs(dev); 5770 if (ret) 5771 goto start_all_rxqs_fail; 5772 5773 hw->adapter_state = HNS3_NIC_STARTED; 5774 rte_spinlock_unlock(&hw->lock); 5775 5776 hns3_rx_scattered_calc(dev); 5777 hns3_set_rxtx_function(dev); 5778 hns3_mp_req_start_rxtx(dev); 5779 5780 hns3_restore_filter(dev); 5781 5782 /* Enable interrupt of all rx queues before enabling queues */ 5783 hns3_dev_all_rx_queue_intr_enable(hw, true); 5784 5785 /* 5786 * After finished the initialization, enable tqps to receive/transmit 5787 * packets and refresh all queue status. 5788 */ 5789 hns3_start_tqps(hw); 5790 5791 hns3_tm_dev_start_proc(hw); 5792 5793 if (dev->data->dev_conf.intr_conf.lsc != 0) 5794 hns3_dev_link_update(dev, 0); 5795 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev); 5796 5797 hns3_info(hw, "hns3 dev start successful!"); 5798 5799 return 0; 5800 5801 start_all_rxqs_fail: 5802 hns3_stop_all_txqs(dev); 5803 map_rx_inter_err: 5804 (void)hns3_do_stop(hns); 5805 hw->adapter_state = HNS3_NIC_CONFIGURED; 5806 rte_spinlock_unlock(&hw->lock); 5807 5808 return ret; 5809 } 5810 5811 static int 5812 hns3_do_stop(struct hns3_adapter *hns) 5813 { 5814 struct hns3_hw *hw = &hns->hw; 5815 int ret; 5816 5817 /* 5818 * The "hns3_do_stop" function will also be called by .stop_service to 5819 * prepare reset. At the time of global or IMP reset, the command cannot 5820 * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be 5821 * accessed during the reset process. So the mbuf can not be released 5822 * during reset and is required to be released after the reset is 5823 * completed. 5824 */ 5825 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) 5826 hns3_dev_release_mbufs(hns); 5827 5828 ret = hns3_cfg_mac_mode(hw, false); 5829 if (ret) 5830 return ret; 5831 hw->mac.link_status = ETH_LINK_DOWN; 5832 5833 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) { 5834 hns3_configure_all_mac_addr(hns, true); 5835 ret = hns3_reset_all_tqps(hns); 5836 if (ret) { 5837 hns3_err(hw, "failed to reset all queues ret = %d.", 5838 ret); 5839 return ret; 5840 } 5841 } 5842 hw->mac.default_addr_setted = false; 5843 return 0; 5844 } 5845 5846 static void 5847 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev) 5848 { 5849 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5850 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5851 struct hns3_adapter *hns = dev->data->dev_private; 5852 struct hns3_hw *hw = &hns->hw; 5853 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 5854 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 5855 uint16_t q_id; 5856 5857 if (dev->data->dev_conf.intr_conf.rxq == 0) 5858 return; 5859 5860 /* unmap the ring with vector */ 5861 if (rte_intr_allow_others(intr_handle)) { 5862 vec = RTE_INTR_VEC_RXTX_OFFSET; 5863 base = RTE_INTR_VEC_RXTX_OFFSET; 5864 } 5865 if (rte_intr_dp_is_en(intr_handle)) { 5866 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 5867 (void)hns3_bind_ring_with_vector(hw, vec, false, 5868 HNS3_RING_TYPE_RX, 5869 q_id); 5870 if (vec < base + intr_handle->nb_efd - 1) 5871 vec++; 5872 } 5873 } 5874 /* Clean datapath event and queue/vec mapping */ 5875 rte_intr_efd_disable(intr_handle); 5876 if (intr_handle->intr_vec) { 5877 rte_free(intr_handle->intr_vec); 5878 intr_handle->intr_vec = NULL; 5879 } 5880 } 5881 5882 static int 5883 hns3_dev_stop(struct rte_eth_dev *dev) 5884 { 5885 struct hns3_adapter *hns = dev->data->dev_private; 5886 struct hns3_hw *hw = &hns->hw; 5887 5888 PMD_INIT_FUNC_TRACE(); 5889 dev->data->dev_started = 0; 5890 5891 hw->adapter_state = HNS3_NIC_STOPPING; 5892 hns3_set_rxtx_function(dev); 5893 rte_wmb(); 5894 /* Disable datapath on secondary process. */ 5895 hns3_mp_req_stop_rxtx(dev); 5896 /* Prevent crashes when queues are still in use. */ 5897 rte_delay_ms(hw->cfg_max_queues); 5898 5899 rte_spinlock_lock(&hw->lock); 5900 if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) { 5901 hns3_tm_dev_stop_proc(hw); 5902 hns3_config_mac_tnl_int(hw, false); 5903 hns3_stop_tqps(hw); 5904 hns3_do_stop(hns); 5905 hns3_unmap_rx_interrupt(dev); 5906 hw->adapter_state = HNS3_NIC_CONFIGURED; 5907 } 5908 hns3_rx_scattered_reset(dev); 5909 rte_eal_alarm_cancel(hns3_service_handler, dev); 5910 hns3_stop_report_lse(dev); 5911 rte_spinlock_unlock(&hw->lock); 5912 5913 return 0; 5914 } 5915 5916 static int 5917 hns3_dev_close(struct rte_eth_dev *eth_dev) 5918 { 5919 struct hns3_adapter *hns = eth_dev->data->dev_private; 5920 struct hns3_hw *hw = &hns->hw; 5921 int ret = 0; 5922 5923 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 5924 rte_free(eth_dev->process_private); 5925 eth_dev->process_private = NULL; 5926 return 0; 5927 } 5928 5929 if (hw->adapter_state == HNS3_NIC_STARTED) 5930 ret = hns3_dev_stop(eth_dev); 5931 5932 hw->adapter_state = HNS3_NIC_CLOSING; 5933 hns3_reset_abort(hns); 5934 hw->adapter_state = HNS3_NIC_CLOSED; 5935 5936 hns3_configure_all_mc_mac_addr(hns, true); 5937 hns3_remove_all_vlan_table(hns); 5938 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0); 5939 hns3_uninit_pf(eth_dev); 5940 hns3_free_all_queues(eth_dev); 5941 rte_free(hw->reset.wait_data); 5942 rte_free(eth_dev->process_private); 5943 eth_dev->process_private = NULL; 5944 hns3_mp_uninit_primary(); 5945 hns3_warn(hw, "Close port %u finished", hw->data->port_id); 5946 5947 return ret; 5948 } 5949 5950 static void 5951 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause, 5952 bool *tx_pause) 5953 { 5954 struct hns3_mac *mac = &hw->mac; 5955 uint32_t advertising = mac->advertising; 5956 uint32_t lp_advertising = mac->lp_advertising; 5957 *rx_pause = false; 5958 *tx_pause = false; 5959 5960 if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) { 5961 *rx_pause = true; 5962 *tx_pause = true; 5963 } else if (advertising & lp_advertising & 5964 HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) { 5965 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) 5966 *rx_pause = true; 5967 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) 5968 *tx_pause = true; 5969 } 5970 } 5971 5972 static enum hns3_fc_mode 5973 hns3_get_autoneg_fc_mode(struct hns3_hw *hw) 5974 { 5975 enum hns3_fc_mode current_mode; 5976 bool rx_pause = false; 5977 bool tx_pause = false; 5978 5979 switch (hw->mac.media_type) { 5980 case HNS3_MEDIA_TYPE_COPPER: 5981 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause); 5982 break; 5983 5984 /* 5985 * Flow control auto-negotiation is not supported for fiber and 5986 * backpalne media type. 5987 */ 5988 case HNS3_MEDIA_TYPE_FIBER: 5989 case HNS3_MEDIA_TYPE_BACKPLANE: 5990 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled."); 5991 current_mode = hw->requested_fc_mode; 5992 goto out; 5993 default: 5994 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).", 5995 hw->mac.media_type); 5996 current_mode = HNS3_FC_NONE; 5997 goto out; 5998 } 5999 6000 if (rx_pause && tx_pause) 6001 current_mode = HNS3_FC_FULL; 6002 else if (rx_pause) 6003 current_mode = HNS3_FC_RX_PAUSE; 6004 else if (tx_pause) 6005 current_mode = HNS3_FC_TX_PAUSE; 6006 else 6007 current_mode = HNS3_FC_NONE; 6008 6009 out: 6010 return current_mode; 6011 } 6012 6013 static enum hns3_fc_mode 6014 hns3_get_current_fc_mode(struct rte_eth_dev *dev) 6015 { 6016 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6017 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6018 struct hns3_mac *mac = &hw->mac; 6019 6020 /* 6021 * When the flow control mode is obtained, the device may not complete 6022 * auto-negotiation. It is necessary to wait for link establishment. 6023 */ 6024 (void)hns3_dev_link_update(dev, 1); 6025 6026 /* 6027 * If the link auto-negotiation of the nic is disabled, or the flow 6028 * control auto-negotiation is not supported, the forced flow control 6029 * mode is used. 6030 */ 6031 if (mac->link_autoneg == 0 || !pf->support_fc_autoneg) 6032 return hw->requested_fc_mode; 6033 6034 return hns3_get_autoneg_fc_mode(hw); 6035 } 6036 6037 static int 6038 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 6039 { 6040 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6041 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6042 enum hns3_fc_mode current_mode; 6043 6044 current_mode = hns3_get_current_fc_mode(dev); 6045 switch (current_mode) { 6046 case HNS3_FC_FULL: 6047 fc_conf->mode = RTE_FC_FULL; 6048 break; 6049 case HNS3_FC_TX_PAUSE: 6050 fc_conf->mode = RTE_FC_TX_PAUSE; 6051 break; 6052 case HNS3_FC_RX_PAUSE: 6053 fc_conf->mode = RTE_FC_RX_PAUSE; 6054 break; 6055 case HNS3_FC_NONE: 6056 default: 6057 fc_conf->mode = RTE_FC_NONE; 6058 break; 6059 } 6060 6061 fc_conf->pause_time = pf->pause_time; 6062 fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0; 6063 6064 return 0; 6065 } 6066 6067 static int 6068 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg) 6069 { 6070 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw); 6071 6072 if (!pf->support_fc_autoneg) { 6073 if (autoneg != 0) { 6074 hns3_err(hw, "unsupported fc auto-negotiation setting."); 6075 return -EOPNOTSUPP; 6076 } 6077 6078 /* 6079 * Flow control auto-negotiation of the NIC is not supported, 6080 * but other auto-negotiation features may be supported. 6081 */ 6082 if (autoneg != hw->mac.link_autoneg) { 6083 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!"); 6084 return -EOPNOTSUPP; 6085 } 6086 6087 return 0; 6088 } 6089 6090 /* 6091 * If flow control auto-negotiation of the NIC is supported, all 6092 * auto-negotiation features are supported. 6093 */ 6094 if (autoneg != hw->mac.link_autoneg) { 6095 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!"); 6096 return -EOPNOTSUPP; 6097 } 6098 6099 return 0; 6100 } 6101 6102 static int 6103 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 6104 { 6105 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6106 int ret; 6107 6108 if (fc_conf->high_water || fc_conf->low_water || 6109 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) { 6110 hns3_err(hw, "Unsupported flow control settings specified, " 6111 "high_water(%u), low_water(%u), send_xon(%u) and " 6112 "mac_ctrl_frame_fwd(%u) must be set to '0'", 6113 fc_conf->high_water, fc_conf->low_water, 6114 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd); 6115 return -EINVAL; 6116 } 6117 6118 ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg); 6119 if (ret) 6120 return ret; 6121 6122 if (!fc_conf->pause_time) { 6123 hns3_err(hw, "Invalid pause time %u setting.", 6124 fc_conf->pause_time); 6125 return -EINVAL; 6126 } 6127 6128 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 6129 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) { 6130 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. " 6131 "current_fc_status = %d", hw->current_fc_status); 6132 return -EOPNOTSUPP; 6133 } 6134 6135 if (hw->num_tc > 1) { 6136 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported."); 6137 return -EOPNOTSUPP; 6138 } 6139 6140 rte_spinlock_lock(&hw->lock); 6141 ret = hns3_fc_enable(dev, fc_conf); 6142 rte_spinlock_unlock(&hw->lock); 6143 6144 return ret; 6145 } 6146 6147 static int 6148 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev, 6149 struct rte_eth_pfc_conf *pfc_conf) 6150 { 6151 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6152 int ret; 6153 6154 if (!hns3_dev_dcb_supported(hw)) { 6155 hns3_err(hw, "This port does not support dcb configurations."); 6156 return -EOPNOTSUPP; 6157 } 6158 6159 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water || 6160 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) { 6161 hns3_err(hw, "Unsupported flow control settings specified, " 6162 "high_water(%u), low_water(%u), send_xon(%u) and " 6163 "mac_ctrl_frame_fwd(%u) must be set to '0'", 6164 pfc_conf->fc.high_water, pfc_conf->fc.low_water, 6165 pfc_conf->fc.send_xon, 6166 pfc_conf->fc.mac_ctrl_frame_fwd); 6167 return -EINVAL; 6168 } 6169 if (pfc_conf->fc.autoneg) { 6170 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 6171 return -EINVAL; 6172 } 6173 if (pfc_conf->fc.pause_time == 0) { 6174 hns3_err(hw, "Invalid pause time %u setting.", 6175 pfc_conf->fc.pause_time); 6176 return -EINVAL; 6177 } 6178 6179 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 6180 hw->current_fc_status == HNS3_FC_STATUS_PFC)) { 6181 hns3_err(hw, "MAC pause is enabled. Cannot set PFC." 6182 "current_fc_status = %d", hw->current_fc_status); 6183 return -EOPNOTSUPP; 6184 } 6185 6186 rte_spinlock_lock(&hw->lock); 6187 ret = hns3_dcb_pfc_enable(dev, pfc_conf); 6188 rte_spinlock_unlock(&hw->lock); 6189 6190 return ret; 6191 } 6192 6193 static int 6194 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info) 6195 { 6196 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6197 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 6198 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 6199 int i; 6200 6201 rte_spinlock_lock(&hw->lock); 6202 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) 6203 dcb_info->nb_tcs = pf->local_max_tc; 6204 else 6205 dcb_info->nb_tcs = 1; 6206 6207 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) 6208 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i]; 6209 for (i = 0; i < dcb_info->nb_tcs; i++) 6210 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i]; 6211 6212 for (i = 0; i < hw->num_tc; i++) { 6213 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i; 6214 dcb_info->tc_queue.tc_txq[0][i].base = 6215 hw->tc_queue[i].tqp_offset; 6216 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size; 6217 dcb_info->tc_queue.tc_txq[0][i].nb_queue = 6218 hw->tc_queue[i].tqp_count; 6219 } 6220 rte_spinlock_unlock(&hw->lock); 6221 6222 return 0; 6223 } 6224 6225 static int 6226 hns3_reinit_dev(struct hns3_adapter *hns) 6227 { 6228 struct hns3_hw *hw = &hns->hw; 6229 int ret; 6230 6231 ret = hns3_cmd_init(hw); 6232 if (ret) { 6233 hns3_err(hw, "Failed to init cmd: %d", ret); 6234 return ret; 6235 } 6236 6237 ret = hns3_reset_all_tqps(hns); 6238 if (ret) { 6239 hns3_err(hw, "Failed to reset all queues: %d", ret); 6240 return ret; 6241 } 6242 6243 ret = hns3_init_hardware(hns); 6244 if (ret) { 6245 hns3_err(hw, "Failed to init hardware: %d", ret); 6246 return ret; 6247 } 6248 6249 ret = hns3_enable_hw_error_intr(hns, true); 6250 if (ret) { 6251 hns3_err(hw, "fail to enable hw error interrupts: %d", 6252 ret); 6253 return ret; 6254 } 6255 hns3_info(hw, "Reset done, driver initialization finished."); 6256 6257 return 0; 6258 } 6259 6260 static bool 6261 is_pf_reset_done(struct hns3_hw *hw) 6262 { 6263 uint32_t val, reg, reg_bit; 6264 6265 switch (hw->reset.level) { 6266 case HNS3_IMP_RESET: 6267 reg = HNS3_GLOBAL_RESET_REG; 6268 reg_bit = HNS3_IMP_RESET_BIT; 6269 break; 6270 case HNS3_GLOBAL_RESET: 6271 reg = HNS3_GLOBAL_RESET_REG; 6272 reg_bit = HNS3_GLOBAL_RESET_BIT; 6273 break; 6274 case HNS3_FUNC_RESET: 6275 reg = HNS3_FUN_RST_ING; 6276 reg_bit = HNS3_FUN_RST_ING_B; 6277 break; 6278 case HNS3_FLR_RESET: 6279 default: 6280 hns3_err(hw, "Wait for unsupported reset level: %d", 6281 hw->reset.level); 6282 return true; 6283 } 6284 val = hns3_read_dev(hw, reg); 6285 if (hns3_get_bit(val, reg_bit)) 6286 return false; 6287 else 6288 return true; 6289 } 6290 6291 bool 6292 hns3_is_reset_pending(struct hns3_adapter *hns) 6293 { 6294 struct hns3_hw *hw = &hns->hw; 6295 enum hns3_reset_level reset; 6296 6297 hns3_check_event_cause(hns, NULL); 6298 reset = hns3_get_reset_level(hns, &hw->reset.pending); 6299 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && 6300 hw->reset.level < reset) { 6301 hns3_warn(hw, "High level reset %d is pending", reset); 6302 return true; 6303 } 6304 reset = hns3_get_reset_level(hns, &hw->reset.request); 6305 if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && 6306 hw->reset.level < reset) { 6307 hns3_warn(hw, "High level reset %d is request", reset); 6308 return true; 6309 } 6310 return false; 6311 } 6312 6313 static int 6314 hns3_wait_hardware_ready(struct hns3_adapter *hns) 6315 { 6316 struct hns3_hw *hw = &hns->hw; 6317 struct hns3_wait_data *wait_data = hw->reset.wait_data; 6318 struct timeval tv; 6319 6320 if (wait_data->result == HNS3_WAIT_SUCCESS) 6321 return 0; 6322 else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 6323 hns3_clock_gettime(&tv); 6324 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 6325 tv.tv_sec, tv.tv_usec); 6326 return -ETIME; 6327 } else if (wait_data->result == HNS3_WAIT_REQUEST) 6328 return -EAGAIN; 6329 6330 wait_data->hns = hns; 6331 wait_data->check_completion = is_pf_reset_done; 6332 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * 6333 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms(); 6334 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; 6335 wait_data->count = HNS3_RESET_WAIT_CNT; 6336 wait_data->result = HNS3_WAIT_REQUEST; 6337 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 6338 return -EAGAIN; 6339 } 6340 6341 static int 6342 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id) 6343 { 6344 struct hns3_cmd_desc desc; 6345 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data; 6346 6347 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 6348 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1); 6349 req->fun_reset_vfid = func_id; 6350 6351 return hns3_cmd_send(hw, &desc, 1); 6352 } 6353 6354 static int 6355 hns3_imp_reset_cmd(struct hns3_hw *hw) 6356 { 6357 struct hns3_cmd_desc desc; 6358 6359 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false); 6360 desc.data[0] = 0xeedd; 6361 6362 return hns3_cmd_send(hw, &desc, 1); 6363 } 6364 6365 static void 6366 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) 6367 { 6368 struct hns3_hw *hw = &hns->hw; 6369 struct timeval tv; 6370 uint32_t val; 6371 6372 hns3_clock_gettime(&tv); 6373 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || 6374 hns3_read_dev(hw, HNS3_FUN_RST_ING)) { 6375 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", 6376 tv.tv_sec, tv.tv_usec); 6377 return; 6378 } 6379 6380 switch (reset_level) { 6381 case HNS3_IMP_RESET: 6382 hns3_imp_reset_cmd(hw); 6383 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld", 6384 tv.tv_sec, tv.tv_usec); 6385 break; 6386 case HNS3_GLOBAL_RESET: 6387 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG); 6388 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1); 6389 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val); 6390 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld", 6391 tv.tv_sec, tv.tv_usec); 6392 break; 6393 case HNS3_FUNC_RESET: 6394 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld", 6395 tv.tv_sec, tv.tv_usec); 6396 /* schedule again to check later */ 6397 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending); 6398 hns3_schedule_reset(hns); 6399 break; 6400 default: 6401 hns3_warn(hw, "Unsupported reset level: %d", reset_level); 6402 return; 6403 } 6404 hns3_atomic_clear_bit(reset_level, &hw->reset.request); 6405 } 6406 6407 static enum hns3_reset_level 6408 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) 6409 { 6410 struct hns3_hw *hw = &hns->hw; 6411 enum hns3_reset_level reset_level = HNS3_NONE_RESET; 6412 6413 /* Return the highest priority reset level amongst all */ 6414 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels)) 6415 reset_level = HNS3_IMP_RESET; 6416 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels)) 6417 reset_level = HNS3_GLOBAL_RESET; 6418 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels)) 6419 reset_level = HNS3_FUNC_RESET; 6420 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 6421 reset_level = HNS3_FLR_RESET; 6422 6423 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 6424 return HNS3_NONE_RESET; 6425 6426 return reset_level; 6427 } 6428 6429 static void 6430 hns3_record_imp_error(struct hns3_adapter *hns) 6431 { 6432 struct hns3_hw *hw = &hns->hw; 6433 uint32_t reg_val; 6434 6435 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 6436 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { 6437 hns3_warn(hw, "Detected IMP RD poison!"); 6438 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); 6439 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 6440 } 6441 6442 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { 6443 hns3_warn(hw, "Detected IMP CMDQ error!"); 6444 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); 6445 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 6446 } 6447 } 6448 6449 static int 6450 hns3_prepare_reset(struct hns3_adapter *hns) 6451 { 6452 struct hns3_hw *hw = &hns->hw; 6453 uint32_t reg_val; 6454 int ret; 6455 6456 switch (hw->reset.level) { 6457 case HNS3_FUNC_RESET: 6458 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID); 6459 if (ret) 6460 return ret; 6461 6462 /* 6463 * After performaning pf reset, it is not necessary to do the 6464 * mailbox handling or send any command to firmware, because 6465 * any mailbox handling or command to firmware is only valid 6466 * after hns3_cmd_init is called. 6467 */ 6468 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 6469 hw->reset.stats.request_cnt++; 6470 break; 6471 case HNS3_IMP_RESET: 6472 hns3_record_imp_error(hns); 6473 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 6474 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val | 6475 BIT(HNS3_VECTOR0_IMP_RESET_INT_B)); 6476 break; 6477 default: 6478 break; 6479 } 6480 return 0; 6481 } 6482 6483 static int 6484 hns3_set_rst_done(struct hns3_hw *hw) 6485 { 6486 struct hns3_pf_rst_done_cmd *req; 6487 struct hns3_cmd_desc desc; 6488 6489 req = (struct hns3_pf_rst_done_cmd *)desc.data; 6490 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false); 6491 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT; 6492 return hns3_cmd_send(hw, &desc, 1); 6493 } 6494 6495 static int 6496 hns3_stop_service(struct hns3_adapter *hns) 6497 { 6498 struct hns3_hw *hw = &hns->hw; 6499 struct rte_eth_dev *eth_dev; 6500 6501 eth_dev = &rte_eth_devices[hw->data->port_id]; 6502 hw->mac.link_status = ETH_LINK_DOWN; 6503 if (hw->adapter_state == HNS3_NIC_STARTED) { 6504 rte_eal_alarm_cancel(hns3_service_handler, eth_dev); 6505 hns3_update_linkstatus_and_event(hw, false); 6506 } 6507 6508 hns3_set_rxtx_function(eth_dev); 6509 rte_wmb(); 6510 /* Disable datapath on secondary process. */ 6511 hns3_mp_req_stop_rxtx(eth_dev); 6512 rte_delay_ms(hw->cfg_max_queues); 6513 6514 rte_spinlock_lock(&hw->lock); 6515 if (hns->hw.adapter_state == HNS3_NIC_STARTED || 6516 hw->adapter_state == HNS3_NIC_STOPPING) { 6517 hns3_enable_all_queues(hw, false); 6518 hns3_do_stop(hns); 6519 hw->reset.mbuf_deferred_free = true; 6520 } else 6521 hw->reset.mbuf_deferred_free = false; 6522 6523 /* 6524 * It is cumbersome for hardware to pick-and-choose entries for deletion 6525 * from table space. Hence, for function reset software intervention is 6526 * required to delete the entries 6527 */ 6528 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) 6529 hns3_configure_all_mc_mac_addr(hns, true); 6530 rte_spinlock_unlock(&hw->lock); 6531 6532 return 0; 6533 } 6534 6535 static int 6536 hns3_start_service(struct hns3_adapter *hns) 6537 { 6538 struct hns3_hw *hw = &hns->hw; 6539 struct rte_eth_dev *eth_dev; 6540 6541 if (hw->reset.level == HNS3_IMP_RESET || 6542 hw->reset.level == HNS3_GLOBAL_RESET) 6543 hns3_set_rst_done(hw); 6544 eth_dev = &rte_eth_devices[hw->data->port_id]; 6545 hns3_set_rxtx_function(eth_dev); 6546 hns3_mp_req_start_rxtx(eth_dev); 6547 if (hw->adapter_state == HNS3_NIC_STARTED) { 6548 /* 6549 * This API parent function already hold the hns3_hw.lock, the 6550 * hns3_service_handler may report lse, in bonding application 6551 * it will call driver's ops which may acquire the hns3_hw.lock 6552 * again, thus lead to deadlock. 6553 * We defer calls hns3_service_handler to avoid the deadlock. 6554 */ 6555 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL, 6556 hns3_service_handler, eth_dev); 6557 6558 /* Enable interrupt of all rx queues before enabling queues */ 6559 hns3_dev_all_rx_queue_intr_enable(hw, true); 6560 /* 6561 * Enable state of each rxq and txq will be recovered after 6562 * reset, so we need to restore them before enable all tqps; 6563 */ 6564 hns3_restore_tqp_enable_state(hw); 6565 /* 6566 * When finished the initialization, enable queues to receive 6567 * and transmit packets. 6568 */ 6569 hns3_enable_all_queues(hw, true); 6570 } 6571 6572 return 0; 6573 } 6574 6575 static int 6576 hns3_restore_conf(struct hns3_adapter *hns) 6577 { 6578 struct hns3_hw *hw = &hns->hw; 6579 int ret; 6580 6581 ret = hns3_configure_all_mac_addr(hns, false); 6582 if (ret) 6583 return ret; 6584 6585 ret = hns3_configure_all_mc_mac_addr(hns, false); 6586 if (ret) 6587 goto err_mc_mac; 6588 6589 ret = hns3_dev_promisc_restore(hns); 6590 if (ret) 6591 goto err_promisc; 6592 6593 ret = hns3_restore_vlan_table(hns); 6594 if (ret) 6595 goto err_promisc; 6596 6597 ret = hns3_restore_vlan_conf(hns); 6598 if (ret) 6599 goto err_promisc; 6600 6601 ret = hns3_restore_all_fdir_filter(hns); 6602 if (ret) 6603 goto err_promisc; 6604 6605 ret = hns3_restore_ptp(hns); 6606 if (ret) 6607 goto err_promisc; 6608 6609 ret = hns3_restore_rx_interrupt(hw); 6610 if (ret) 6611 goto err_promisc; 6612 6613 ret = hns3_restore_gro_conf(hw); 6614 if (ret) 6615 goto err_promisc; 6616 6617 ret = hns3_restore_fec(hw); 6618 if (ret) 6619 goto err_promisc; 6620 6621 if (hns->hw.adapter_state == HNS3_NIC_STARTED) { 6622 ret = hns3_do_start(hns, false); 6623 if (ret) 6624 goto err_promisc; 6625 hns3_info(hw, "hns3 dev restart successful!"); 6626 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 6627 hw->adapter_state = HNS3_NIC_CONFIGURED; 6628 return 0; 6629 6630 err_promisc: 6631 hns3_configure_all_mc_mac_addr(hns, true); 6632 err_mc_mac: 6633 hns3_configure_all_mac_addr(hns, true); 6634 return ret; 6635 } 6636 6637 static void 6638 hns3_reset_service(void *param) 6639 { 6640 struct hns3_adapter *hns = (struct hns3_adapter *)param; 6641 struct hns3_hw *hw = &hns->hw; 6642 enum hns3_reset_level reset_level; 6643 struct timeval tv_delta; 6644 struct timeval tv_start; 6645 struct timeval tv; 6646 uint64_t msec; 6647 int ret; 6648 6649 /* 6650 * The interrupt is not triggered within the delay time. 6651 * The interrupt may have been lost. It is necessary to handle 6652 * the interrupt to recover from the error. 6653 */ 6654 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 6655 SCHEDULE_DEFERRED) { 6656 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, 6657 __ATOMIC_RELAXED); 6658 hns3_err(hw, "Handling interrupts in delayed tasks"); 6659 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 6660 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 6661 if (reset_level == HNS3_NONE_RESET) { 6662 hns3_err(hw, "No reset level is set, try IMP reset"); 6663 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 6664 } 6665 } 6666 __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED); 6667 6668 /* 6669 * Check if there is any ongoing reset in the hardware. This status can 6670 * be checked from reset_pending. If there is then, we need to wait for 6671 * hardware to complete reset. 6672 * a. If we are able to figure out in reasonable time that hardware 6673 * has fully resetted then, we can proceed with driver, client 6674 * reset. 6675 * b. else, we can come back later to check this status so re-sched 6676 * now. 6677 */ 6678 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 6679 if (reset_level != HNS3_NONE_RESET) { 6680 hns3_clock_gettime(&tv_start); 6681 ret = hns3_reset_process(hns, reset_level); 6682 hns3_clock_gettime(&tv); 6683 timersub(&tv, &tv_start, &tv_delta); 6684 msec = hns3_clock_calctime_ms(&tv_delta); 6685 if (msec > HNS3_RESET_PROCESS_MS) 6686 hns3_err(hw, "%d handle long time delta %" PRIu64 6687 " ms time=%ld.%.6ld", 6688 hw->reset.level, msec, 6689 tv.tv_sec, tv.tv_usec); 6690 if (ret == -EAGAIN) 6691 return; 6692 } 6693 6694 /* Check if we got any *new* reset requests to be honored */ 6695 reset_level = hns3_get_reset_level(hns, &hw->reset.request); 6696 if (reset_level != HNS3_NONE_RESET) 6697 hns3_msix_process(hns, reset_level); 6698 } 6699 6700 static unsigned int 6701 hns3_get_speed_capa_num(uint16_t device_id) 6702 { 6703 unsigned int num; 6704 6705 switch (device_id) { 6706 case HNS3_DEV_ID_25GE: 6707 case HNS3_DEV_ID_25GE_RDMA: 6708 num = 2; 6709 break; 6710 case HNS3_DEV_ID_100G_RDMA_MACSEC: 6711 case HNS3_DEV_ID_200G_RDMA: 6712 num = 1; 6713 break; 6714 default: 6715 num = 0; 6716 break; 6717 } 6718 6719 return num; 6720 } 6721 6722 static int 6723 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa, 6724 uint16_t device_id) 6725 { 6726 switch (device_id) { 6727 case HNS3_DEV_ID_25GE: 6728 /* fallthrough */ 6729 case HNS3_DEV_ID_25GE_RDMA: 6730 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed; 6731 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa; 6732 6733 /* In HNS3 device, the 25G NIC is compatible with 10G rate */ 6734 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed; 6735 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa; 6736 break; 6737 case HNS3_DEV_ID_100G_RDMA_MACSEC: 6738 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed; 6739 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa; 6740 break; 6741 case HNS3_DEV_ID_200G_RDMA: 6742 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed; 6743 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa; 6744 break; 6745 default: 6746 return -ENOTSUP; 6747 } 6748 6749 return 0; 6750 } 6751 6752 static int 6753 hns3_fec_get_capability(struct rte_eth_dev *dev, 6754 struct rte_eth_fec_capa *speed_fec_capa, 6755 unsigned int num) 6756 { 6757 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6758 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 6759 uint16_t device_id = pci_dev->id.device_id; 6760 unsigned int capa_num; 6761 int ret; 6762 6763 capa_num = hns3_get_speed_capa_num(device_id); 6764 if (capa_num == 0) { 6765 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD", 6766 device_id); 6767 return -ENOTSUP; 6768 } 6769 6770 if (speed_fec_capa == NULL || num < capa_num) 6771 return capa_num; 6772 6773 ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id); 6774 if (ret) 6775 return -ENOTSUP; 6776 6777 return capa_num; 6778 } 6779 6780 static int 6781 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state) 6782 { 6783 struct hns3_config_fec_cmd *req; 6784 struct hns3_cmd_desc desc; 6785 int ret; 6786 6787 /* 6788 * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported 6789 * in device of link speed 6790 * below 10 Gbps. 6791 */ 6792 if (hw->mac.link_speed < ETH_SPEED_NUM_10G) { 6793 *state = 0; 6794 return 0; 6795 } 6796 6797 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true); 6798 req = (struct hns3_config_fec_cmd *)desc.data; 6799 ret = hns3_cmd_send(hw, &desc, 1); 6800 if (ret) { 6801 hns3_err(hw, "get current fec auto state failed, ret = %d", 6802 ret); 6803 return ret; 6804 } 6805 6806 *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B); 6807 return 0; 6808 } 6809 6810 static int 6811 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa) 6812 { 6813 struct hns3_sfp_info_cmd *resp; 6814 uint32_t tmp_fec_capa; 6815 uint8_t auto_state; 6816 struct hns3_cmd_desc desc; 6817 int ret; 6818 6819 /* 6820 * If link is down and AUTO is enabled, AUTO is returned, otherwise, 6821 * configured FEC mode is returned. 6822 * If link is up, current FEC mode is returned. 6823 */ 6824 if (hw->mac.link_status == ETH_LINK_DOWN) { 6825 ret = get_current_fec_auto_state(hw, &auto_state); 6826 if (ret) 6827 return ret; 6828 6829 if (auto_state == 0x1) { 6830 *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO); 6831 return 0; 6832 } 6833 } 6834 6835 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true); 6836 resp = (struct hns3_sfp_info_cmd *)desc.data; 6837 resp->query_type = HNS3_ACTIVE_QUERY; 6838 6839 ret = hns3_cmd_send(hw, &desc, 1); 6840 if (ret == -EOPNOTSUPP) { 6841 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret); 6842 return ret; 6843 } else if (ret) { 6844 hns3_err(hw, "get FEC failed, ret = %d", ret); 6845 return ret; 6846 } 6847 6848 /* 6849 * FEC mode order defined in hns3 hardware is inconsistend with 6850 * that defined in the ethdev library. So the sequence needs 6851 * to be converted. 6852 */ 6853 switch (resp->active_fec) { 6854 case HNS3_HW_FEC_MODE_NOFEC: 6855 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6856 break; 6857 case HNS3_HW_FEC_MODE_BASER: 6858 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 6859 break; 6860 case HNS3_HW_FEC_MODE_RS: 6861 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 6862 break; 6863 default: 6864 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 6865 break; 6866 } 6867 6868 *fec_capa = tmp_fec_capa; 6869 return 0; 6870 } 6871 6872 static int 6873 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 6874 { 6875 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6876 6877 return hns3_fec_get_internal(hw, fec_capa); 6878 } 6879 6880 static int 6881 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode) 6882 { 6883 struct hns3_config_fec_cmd *req; 6884 struct hns3_cmd_desc desc; 6885 int ret; 6886 6887 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false); 6888 6889 req = (struct hns3_config_fec_cmd *)desc.data; 6890 switch (mode) { 6891 case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC): 6892 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6893 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF); 6894 break; 6895 case RTE_ETH_FEC_MODE_CAPA_MASK(BASER): 6896 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6897 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER); 6898 break; 6899 case RTE_ETH_FEC_MODE_CAPA_MASK(RS): 6900 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M, 6901 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS); 6902 break; 6903 case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO): 6904 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1); 6905 break; 6906 default: 6907 return 0; 6908 } 6909 ret = hns3_cmd_send(hw, &desc, 1); 6910 if (ret) 6911 hns3_err(hw, "set fec mode failed, ret = %d", ret); 6912 6913 return ret; 6914 } 6915 6916 static uint32_t 6917 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa) 6918 { 6919 struct hns3_mac *mac = &hw->mac; 6920 uint32_t cur_capa; 6921 6922 switch (mac->link_speed) { 6923 case ETH_SPEED_NUM_10G: 6924 cur_capa = fec_capa[1].capa; 6925 break; 6926 case ETH_SPEED_NUM_25G: 6927 case ETH_SPEED_NUM_100G: 6928 case ETH_SPEED_NUM_200G: 6929 cur_capa = fec_capa[0].capa; 6930 break; 6931 default: 6932 cur_capa = 0; 6933 break; 6934 } 6935 6936 return cur_capa; 6937 } 6938 6939 static bool 6940 is_fec_mode_one_bit_set(uint32_t mode) 6941 { 6942 int cnt = 0; 6943 uint8_t i; 6944 6945 for (i = 0; i < sizeof(mode); i++) 6946 if (mode >> i & 0x1) 6947 cnt++; 6948 6949 return cnt == 1 ? true : false; 6950 } 6951 6952 static int 6953 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode) 6954 { 6955 #define FEC_CAPA_NUM 2 6956 struct hns3_adapter *hns = dev->data->dev_private; 6957 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 6958 struct hns3_pf *pf = &hns->pf; 6959 6960 struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM]; 6961 uint32_t cur_capa; 6962 uint32_t num = FEC_CAPA_NUM; 6963 int ret; 6964 6965 ret = hns3_fec_get_capability(dev, fec_capa, num); 6966 if (ret < 0) 6967 return ret; 6968 6969 /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */ 6970 if (!is_fec_mode_one_bit_set(mode)) { 6971 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, " 6972 "FEC mode should be only one bit set", mode); 6973 return -EINVAL; 6974 } 6975 6976 /* 6977 * Check whether the configured mode is within the FEC capability. 6978 * If not, the configured mode will not be supported. 6979 */ 6980 cur_capa = get_current_speed_fec_cap(hw, fec_capa); 6981 if (!(cur_capa & mode)) { 6982 hns3_err(hw, "unsupported FEC mode = 0x%x", mode); 6983 return -EINVAL; 6984 } 6985 6986 rte_spinlock_lock(&hw->lock); 6987 ret = hns3_set_fec_hw(hw, mode); 6988 if (ret) { 6989 rte_spinlock_unlock(&hw->lock); 6990 return ret; 6991 } 6992 6993 pf->fec_mode = mode; 6994 rte_spinlock_unlock(&hw->lock); 6995 6996 return 0; 6997 } 6998 6999 static int 7000 hns3_restore_fec(struct hns3_hw *hw) 7001 { 7002 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 7003 struct hns3_pf *pf = &hns->pf; 7004 uint32_t mode = pf->fec_mode; 7005 int ret; 7006 7007 ret = hns3_set_fec_hw(hw, mode); 7008 if (ret) 7009 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d", 7010 mode, ret); 7011 7012 return ret; 7013 } 7014 7015 static int 7016 hns3_query_dev_fec_info(struct hns3_hw *hw) 7017 { 7018 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 7019 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns); 7020 int ret; 7021 7022 ret = hns3_fec_get_internal(hw, &pf->fec_mode); 7023 if (ret) 7024 hns3_err(hw, "query device FEC info failed, ret = %d", ret); 7025 7026 return ret; 7027 } 7028 7029 static bool 7030 hns3_optical_module_existed(struct hns3_hw *hw) 7031 { 7032 struct hns3_cmd_desc desc; 7033 bool existed; 7034 int ret; 7035 7036 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true); 7037 ret = hns3_cmd_send(hw, &desc, 1); 7038 if (ret) { 7039 hns3_err(hw, 7040 "fail to get optical module exist state, ret = %d.\n", 7041 ret); 7042 return false; 7043 } 7044 existed = !!desc.data[0]; 7045 7046 return existed; 7047 } 7048 7049 static int 7050 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset, 7051 uint32_t len, uint8_t *data) 7052 { 7053 #define HNS3_SFP_INFO_CMD_NUM 6 7054 #define HNS3_SFP_INFO_MAX_LEN \ 7055 (HNS3_SFP_INFO_BD0_LEN + \ 7056 (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN) 7057 struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM]; 7058 struct hns3_sfp_info_bd0_cmd *sfp_info_bd0; 7059 uint16_t read_len; 7060 uint16_t copy_len; 7061 int ret; 7062 int i; 7063 7064 for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) { 7065 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM, 7066 true); 7067 if (i < HNS3_SFP_INFO_CMD_NUM - 1) 7068 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 7069 } 7070 7071 sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data; 7072 sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset); 7073 read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN); 7074 sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len); 7075 7076 ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM); 7077 if (ret) { 7078 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n", 7079 ret); 7080 return ret; 7081 } 7082 7083 /* The data format in BD0 is different with the others. */ 7084 copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN); 7085 memcpy(data, sfp_info_bd0->data, copy_len); 7086 read_len = copy_len; 7087 7088 for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) { 7089 if (read_len >= len) 7090 break; 7091 7092 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN); 7093 memcpy(data + read_len, desc[i].data, copy_len); 7094 read_len += copy_len; 7095 } 7096 7097 return (int)read_len; 7098 } 7099 7100 static int 7101 hns3_get_module_eeprom(struct rte_eth_dev *dev, 7102 struct rte_dev_eeprom_info *info) 7103 { 7104 struct hns3_adapter *hns = dev->data->dev_private; 7105 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 7106 uint32_t offset = info->offset; 7107 uint32_t len = info->length; 7108 uint8_t *data = info->data; 7109 uint32_t read_len = 0; 7110 7111 if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER) 7112 return -ENOTSUP; 7113 7114 if (!hns3_optical_module_existed(hw)) { 7115 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n"); 7116 return -EIO; 7117 } 7118 7119 while (read_len < len) { 7120 int ret; 7121 ret = hns3_get_module_eeprom_data(hw, offset + read_len, 7122 len - read_len, 7123 data + read_len); 7124 if (ret < 0) 7125 return -EIO; 7126 read_len += ret; 7127 } 7128 7129 return 0; 7130 } 7131 7132 static int 7133 hns3_get_module_info(struct rte_eth_dev *dev, 7134 struct rte_eth_dev_module_info *modinfo) 7135 { 7136 #define HNS3_SFF8024_ID_SFP 0x03 7137 #define HNS3_SFF8024_ID_QSFP_8438 0x0c 7138 #define HNS3_SFF8024_ID_QSFP_8436_8636 0x0d 7139 #define HNS3_SFF8024_ID_QSFP28_8636 0x11 7140 #define HNS3_SFF_8636_V1_3 0x03 7141 struct hns3_adapter *hns = dev->data->dev_private; 7142 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns); 7143 struct rte_dev_eeprom_info info; 7144 struct hns3_sfp_type sfp_type; 7145 int ret; 7146 7147 memset(&sfp_type, 0, sizeof(sfp_type)); 7148 memset(&info, 0, sizeof(info)); 7149 info.data = (uint8_t *)&sfp_type; 7150 info.length = sizeof(sfp_type); 7151 ret = hns3_get_module_eeprom(dev, &info); 7152 if (ret) 7153 return ret; 7154 7155 switch (sfp_type.type) { 7156 case HNS3_SFF8024_ID_SFP: 7157 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7158 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7159 break; 7160 case HNS3_SFF8024_ID_QSFP_8438: 7161 modinfo->type = RTE_ETH_MODULE_SFF_8436; 7162 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN; 7163 break; 7164 case HNS3_SFF8024_ID_QSFP_8436_8636: 7165 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) { 7166 modinfo->type = RTE_ETH_MODULE_SFF_8436; 7167 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN; 7168 } else { 7169 modinfo->type = RTE_ETH_MODULE_SFF_8636; 7170 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 7171 } 7172 break; 7173 case HNS3_SFF8024_ID_QSFP28_8636: 7174 modinfo->type = RTE_ETH_MODULE_SFF_8636; 7175 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 7176 break; 7177 default: 7178 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n", 7179 sfp_type.type, sfp_type.ext_type); 7180 return -EINVAL; 7181 } 7182 7183 return 0; 7184 } 7185 7186 void 7187 hns3_clock_gettime(struct timeval *tv) 7188 { 7189 #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */ 7190 #define CLOCK_TYPE CLOCK_MONOTONIC_RAW 7191 #else 7192 #define CLOCK_TYPE CLOCK_MONOTONIC 7193 #endif 7194 #define NSEC_TO_USEC_DIV 1000 7195 7196 struct timespec spec; 7197 (void)clock_gettime(CLOCK_TYPE, &spec); 7198 7199 tv->tv_sec = spec.tv_sec; 7200 tv->tv_usec = spec.tv_nsec / NSEC_TO_USEC_DIV; 7201 } 7202 7203 uint64_t 7204 hns3_clock_calctime_ms(struct timeval *tv) 7205 { 7206 return (uint64_t)tv->tv_sec * MSEC_PER_SEC + 7207 tv->tv_usec / USEC_PER_MSEC; 7208 } 7209 7210 uint64_t 7211 hns3_clock_gettime_ms(void) 7212 { 7213 struct timeval tv; 7214 7215 hns3_clock_gettime(&tv); 7216 return hns3_clock_calctime_ms(&tv); 7217 } 7218 7219 static int 7220 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args) 7221 { 7222 uint32_t hint = HNS3_IO_FUNC_HINT_NONE; 7223 7224 RTE_SET_USED(key); 7225 7226 if (strcmp(value, "vec") == 0) 7227 hint = HNS3_IO_FUNC_HINT_VEC; 7228 else if (strcmp(value, "sve") == 0) 7229 hint = HNS3_IO_FUNC_HINT_SVE; 7230 else if (strcmp(value, "simple") == 0) 7231 hint = HNS3_IO_FUNC_HINT_SIMPLE; 7232 else if (strcmp(value, "common") == 0) 7233 hint = HNS3_IO_FUNC_HINT_COMMON; 7234 7235 /* If the hint is valid then update output parameters */ 7236 if (hint != HNS3_IO_FUNC_HINT_NONE) 7237 *(uint32_t *)extra_args = hint; 7238 7239 return 0; 7240 } 7241 7242 static const char * 7243 hns3_get_io_hint_func_name(uint32_t hint) 7244 { 7245 switch (hint) { 7246 case HNS3_IO_FUNC_HINT_VEC: 7247 return "vec"; 7248 case HNS3_IO_FUNC_HINT_SVE: 7249 return "sve"; 7250 case HNS3_IO_FUNC_HINT_SIMPLE: 7251 return "simple"; 7252 case HNS3_IO_FUNC_HINT_COMMON: 7253 return "common"; 7254 default: 7255 return "none"; 7256 } 7257 } 7258 7259 static int 7260 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args) 7261 { 7262 uint64_t val; 7263 7264 RTE_SET_USED(key); 7265 7266 val = strtoull(value, NULL, 16); 7267 *(uint64_t *)extra_args = val; 7268 7269 return 0; 7270 } 7271 7272 void 7273 hns3_parse_devargs(struct rte_eth_dev *dev) 7274 { 7275 struct hns3_adapter *hns = dev->data->dev_private; 7276 uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE; 7277 uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE; 7278 struct hns3_hw *hw = &hns->hw; 7279 uint64_t dev_caps_mask = 0; 7280 struct rte_kvargs *kvlist; 7281 7282 if (dev->device->devargs == NULL) 7283 return; 7284 7285 kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL); 7286 if (!kvlist) 7287 return; 7288 7289 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT, 7290 &hns3_parse_io_hint_func, &rx_func_hint); 7291 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT, 7292 &hns3_parse_io_hint_func, &tx_func_hint); 7293 (void)rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK, 7294 &hns3_parse_dev_caps_mask, &dev_caps_mask); 7295 rte_kvargs_free(kvlist); 7296 7297 if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE) 7298 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT, 7299 hns3_get_io_hint_func_name(rx_func_hint)); 7300 hns->rx_func_hint = rx_func_hint; 7301 if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE) 7302 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT, 7303 hns3_get_io_hint_func_name(tx_func_hint)); 7304 hns->tx_func_hint = tx_func_hint; 7305 7306 if (dev_caps_mask != 0) 7307 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".", 7308 HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask); 7309 hns->dev_caps_mask = dev_caps_mask; 7310 } 7311 7312 static const struct eth_dev_ops hns3_eth_dev_ops = { 7313 .dev_configure = hns3_dev_configure, 7314 .dev_start = hns3_dev_start, 7315 .dev_stop = hns3_dev_stop, 7316 .dev_close = hns3_dev_close, 7317 .promiscuous_enable = hns3_dev_promiscuous_enable, 7318 .promiscuous_disable = hns3_dev_promiscuous_disable, 7319 .allmulticast_enable = hns3_dev_allmulticast_enable, 7320 .allmulticast_disable = hns3_dev_allmulticast_disable, 7321 .mtu_set = hns3_dev_mtu_set, 7322 .stats_get = hns3_stats_get, 7323 .stats_reset = hns3_stats_reset, 7324 .xstats_get = hns3_dev_xstats_get, 7325 .xstats_get_names = hns3_dev_xstats_get_names, 7326 .xstats_reset = hns3_dev_xstats_reset, 7327 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 7328 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 7329 .dev_infos_get = hns3_dev_infos_get, 7330 .fw_version_get = hns3_fw_version_get, 7331 .rx_queue_setup = hns3_rx_queue_setup, 7332 .tx_queue_setup = hns3_tx_queue_setup, 7333 .rx_queue_release = hns3_dev_rx_queue_release, 7334 .tx_queue_release = hns3_dev_tx_queue_release, 7335 .rx_queue_start = hns3_dev_rx_queue_start, 7336 .rx_queue_stop = hns3_dev_rx_queue_stop, 7337 .tx_queue_start = hns3_dev_tx_queue_start, 7338 .tx_queue_stop = hns3_dev_tx_queue_stop, 7339 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 7340 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 7341 .rxq_info_get = hns3_rxq_info_get, 7342 .txq_info_get = hns3_txq_info_get, 7343 .rx_burst_mode_get = hns3_rx_burst_mode_get, 7344 .tx_burst_mode_get = hns3_tx_burst_mode_get, 7345 .flow_ctrl_get = hns3_flow_ctrl_get, 7346 .flow_ctrl_set = hns3_flow_ctrl_set, 7347 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set, 7348 .mac_addr_add = hns3_add_mac_addr, 7349 .mac_addr_remove = hns3_remove_mac_addr, 7350 .mac_addr_set = hns3_set_default_mac_addr, 7351 .set_mc_addr_list = hns3_set_mc_mac_addr_list, 7352 .link_update = hns3_dev_link_update, 7353 .rss_hash_update = hns3_dev_rss_hash_update, 7354 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 7355 .reta_update = hns3_dev_rss_reta_update, 7356 .reta_query = hns3_dev_rss_reta_query, 7357 .flow_ops_get = hns3_dev_flow_ops_get, 7358 .vlan_filter_set = hns3_vlan_filter_set, 7359 .vlan_tpid_set = hns3_vlan_tpid_set, 7360 .vlan_offload_set = hns3_vlan_offload_set, 7361 .vlan_pvid_set = hns3_vlan_pvid_set, 7362 .get_reg = hns3_get_regs, 7363 .get_module_info = hns3_get_module_info, 7364 .get_module_eeprom = hns3_get_module_eeprom, 7365 .get_dcb_info = hns3_get_dcb_info, 7366 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 7367 .fec_get_capability = hns3_fec_get_capability, 7368 .fec_get = hns3_fec_get, 7369 .fec_set = hns3_fec_set, 7370 .tm_ops_get = hns3_tm_ops_get, 7371 .tx_done_cleanup = hns3_tx_done_cleanup, 7372 .timesync_enable = hns3_timesync_enable, 7373 .timesync_disable = hns3_timesync_disable, 7374 .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp, 7375 .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp, 7376 .timesync_adjust_time = hns3_timesync_adjust_time, 7377 .timesync_read_time = hns3_timesync_read_time, 7378 .timesync_write_time = hns3_timesync_write_time, 7379 }; 7380 7381 static const struct hns3_reset_ops hns3_reset_ops = { 7382 .reset_service = hns3_reset_service, 7383 .stop_service = hns3_stop_service, 7384 .prepare_reset = hns3_prepare_reset, 7385 .wait_hardware_ready = hns3_wait_hardware_ready, 7386 .reinit_dev = hns3_reinit_dev, 7387 .restore_conf = hns3_restore_conf, 7388 .start_service = hns3_start_service, 7389 }; 7390 7391 static int 7392 hns3_dev_init(struct rte_eth_dev *eth_dev) 7393 { 7394 struct hns3_adapter *hns = eth_dev->data->dev_private; 7395 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 7396 struct rte_ether_addr *eth_addr; 7397 struct hns3_hw *hw = &hns->hw; 7398 int ret; 7399 7400 PMD_INIT_FUNC_TRACE(); 7401 7402 eth_dev->process_private = (struct hns3_process_private *) 7403 rte_zmalloc_socket("hns3_filter_list", 7404 sizeof(struct hns3_process_private), 7405 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 7406 if (eth_dev->process_private == NULL) { 7407 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 7408 return -ENOMEM; 7409 } 7410 7411 hns3_flow_init(eth_dev); 7412 7413 hns3_set_rxtx_function(eth_dev); 7414 eth_dev->dev_ops = &hns3_eth_dev_ops; 7415 eth_dev->rx_queue_count = hns3_rx_queue_count; 7416 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 7417 ret = hns3_mp_init_secondary(); 7418 if (ret) { 7419 PMD_INIT_LOG(ERR, "Failed to init for secondary " 7420 "process, ret = %d", ret); 7421 goto err_mp_init_secondary; 7422 } 7423 hw->secondary_cnt++; 7424 hns3_tx_push_init(eth_dev); 7425 return 0; 7426 } 7427 7428 ret = hns3_mp_init_primary(); 7429 if (ret) { 7430 PMD_INIT_LOG(ERR, 7431 "Failed to init for primary process, ret = %d", 7432 ret); 7433 goto err_mp_init_primary; 7434 } 7435 7436 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 7437 hns->is_vf = false; 7438 hw->data = eth_dev->data; 7439 hns3_parse_devargs(eth_dev); 7440 7441 /* 7442 * Set default max packet size according to the mtu 7443 * default vale in DPDK frame. 7444 */ 7445 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD; 7446 7447 ret = hns3_reset_init(hw); 7448 if (ret) 7449 goto err_init_reset; 7450 hw->reset.ops = &hns3_reset_ops; 7451 7452 ret = hns3_init_pf(eth_dev); 7453 if (ret) { 7454 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret); 7455 goto err_init_pf; 7456 } 7457 7458 /* Allocate memory for storing MAC addresses */ 7459 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac", 7460 sizeof(struct rte_ether_addr) * 7461 HNS3_UC_MACADDR_NUM, 0); 7462 if (eth_dev->data->mac_addrs == NULL) { 7463 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 7464 "to store MAC addresses", 7465 sizeof(struct rte_ether_addr) * 7466 HNS3_UC_MACADDR_NUM); 7467 ret = -ENOMEM; 7468 goto err_rte_zmalloc; 7469 } 7470 7471 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 7472 if (!rte_is_valid_assigned_ether_addr(eth_addr)) { 7473 rte_eth_random_addr(hw->mac.mac_addr); 7474 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 7475 (struct rte_ether_addr *)hw->mac.mac_addr); 7476 hns3_warn(hw, "default mac_addr from firmware is an invalid " 7477 "unicast address, using random MAC address %s", 7478 mac_str); 7479 } 7480 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 7481 ð_dev->data->mac_addrs[0]); 7482 7483 hw->adapter_state = HNS3_NIC_INITIALIZED; 7484 7485 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 7486 SCHEDULE_PENDING) { 7487 hns3_err(hw, "Reschedule reset service after dev_init"); 7488 hns3_schedule_reset(hns); 7489 } else { 7490 /* IMP will wait ready flag before reset */ 7491 hns3_notify_reset_ready(hw, false); 7492 } 7493 7494 hns3_info(hw, "hns3 dev initialization successful!"); 7495 return 0; 7496 7497 err_rte_zmalloc: 7498 hns3_uninit_pf(eth_dev); 7499 7500 err_init_pf: 7501 rte_free(hw->reset.wait_data); 7502 7503 err_init_reset: 7504 hns3_mp_uninit_primary(); 7505 7506 err_mp_init_primary: 7507 err_mp_init_secondary: 7508 eth_dev->dev_ops = NULL; 7509 eth_dev->rx_pkt_burst = NULL; 7510 eth_dev->rx_descriptor_status = NULL; 7511 eth_dev->tx_pkt_burst = NULL; 7512 eth_dev->tx_pkt_prepare = NULL; 7513 eth_dev->tx_descriptor_status = NULL; 7514 rte_free(eth_dev->process_private); 7515 eth_dev->process_private = NULL; 7516 return ret; 7517 } 7518 7519 static int 7520 hns3_dev_uninit(struct rte_eth_dev *eth_dev) 7521 { 7522 struct hns3_adapter *hns = eth_dev->data->dev_private; 7523 struct hns3_hw *hw = &hns->hw; 7524 7525 PMD_INIT_FUNC_TRACE(); 7526 7527 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 7528 rte_free(eth_dev->process_private); 7529 eth_dev->process_private = NULL; 7530 return 0; 7531 } 7532 7533 if (hw->adapter_state < HNS3_NIC_CLOSING) 7534 hns3_dev_close(eth_dev); 7535 7536 hw->adapter_state = HNS3_NIC_REMOVED; 7537 return 0; 7538 } 7539 7540 static int 7541 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 7542 struct rte_pci_device *pci_dev) 7543 { 7544 return rte_eth_dev_pci_generic_probe(pci_dev, 7545 sizeof(struct hns3_adapter), 7546 hns3_dev_init); 7547 } 7548 7549 static int 7550 eth_hns3_pci_remove(struct rte_pci_device *pci_dev) 7551 { 7552 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit); 7553 } 7554 7555 static const struct rte_pci_id pci_id_hns3_map[] = { 7556 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) }, 7557 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) }, 7558 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) }, 7559 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) }, 7560 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) }, 7561 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) }, 7562 { .vendor_id = 0, }, /* sentinel */ 7563 }; 7564 7565 static struct rte_pci_driver rte_hns3_pmd = { 7566 .id_table = pci_id_hns3_map, 7567 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 7568 .probe = eth_hns3_pci_probe, 7569 .remove = eth_hns3_pci_remove, 7570 }; 7571 7572 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); 7573 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); 7574 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); 7575 RTE_PMD_REGISTER_PARAM_STRING(net_hns3, 7576 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common " 7577 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common " 7578 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "); 7579 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE); 7580 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE); 7581