1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #include <errno.h> 6 #include <stdarg.h> 7 #include <stdbool.h> 8 #include <stdio.h> 9 #include <stdint.h> 10 #include <inttypes.h> 11 #include <unistd.h> 12 #include <rte_atomic.h> 13 #include <rte_bus_pci.h> 14 #include <rte_common.h> 15 #include <rte_cycles.h> 16 #include <rte_dev.h> 17 #include <rte_eal.h> 18 #include <rte_ether.h> 19 #include <rte_ethdev_driver.h> 20 #include <rte_ethdev_pci.h> 21 #include <rte_interrupts.h> 22 #include <rte_io.h> 23 #include <rte_log.h> 24 #include <rte_pci.h> 25 26 #include "hns3_ethdev.h" 27 #include "hns3_logs.h" 28 #include "hns3_rxtx.h" 29 #include "hns3_intr.h" 30 #include "hns3_regs.h" 31 #include "hns3_dcb.h" 32 #include "hns3_mp.h" 33 34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32 35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1 36 37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */ 38 #define HNS3_INVLID_PVID 0xFFFF 39 40 #define HNS3_FILTER_TYPE_VF 0 41 #define HNS3_FILTER_TYPE_PORT 1 42 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0) 43 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0) 44 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1) 45 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2) 46 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3) 47 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \ 48 | HNS3_FILTER_FE_ROCE_EGRESS_B) 49 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \ 50 | HNS3_FILTER_FE_ROCE_INGRESS_B) 51 52 /* Reset related Registers */ 53 #define HNS3_GLOBAL_RESET_BIT 0 54 #define HNS3_CORE_RESET_BIT 1 55 #define HNS3_IMP_RESET_BIT 2 56 #define HNS3_FUN_RST_ING_B 0 57 58 #define HNS3_VECTOR0_IMP_RESET_INT_B 1 59 60 #define HNS3_RESET_WAIT_MS 100 61 #define HNS3_RESET_WAIT_CNT 200 62 63 int hns3_logtype_init; 64 int hns3_logtype_driver; 65 66 enum hns3_evt_cause { 67 HNS3_VECTOR0_EVENT_RST, 68 HNS3_VECTOR0_EVENT_MBX, 69 HNS3_VECTOR0_EVENT_ERR, 70 HNS3_VECTOR0_EVENT_OTHER, 71 }; 72 73 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns, 74 uint64_t *levels); 75 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 76 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, 77 int on); 78 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev); 79 80 static int hns3_add_mc_addr(struct hns3_hw *hw, 81 struct rte_ether_addr *mac_addr); 82 static int hns3_remove_mc_addr(struct hns3_hw *hw, 83 struct rte_ether_addr *mac_addr); 84 85 static void 86 hns3_pf_disable_irq0(struct hns3_hw *hw) 87 { 88 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 89 } 90 91 static void 92 hns3_pf_enable_irq0(struct hns3_hw *hw) 93 { 94 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 95 } 96 97 static enum hns3_evt_cause 98 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 99 { 100 struct hns3_hw *hw = &hns->hw; 101 uint32_t vector0_int_stats; 102 uint32_t cmdq_src_val; 103 uint32_t val; 104 enum hns3_evt_cause ret; 105 106 /* fetch the events from their corresponding regs */ 107 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 108 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 109 110 /* 111 * Assumption: If by any chance reset and mailbox events are reported 112 * together then we will only process reset event and defer the 113 * processing of the mailbox events. Since, we would have not cleared 114 * RX CMDQ event this time we would receive again another interrupt 115 * from H/W just for the mailbox. 116 */ 117 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ 118 rte_atomic16_set(&hw->reset.disable_cmd, 1); 119 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 120 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); 121 if (clearval) { 122 hw->reset.stats.imp_cnt++; 123 hns3_warn(hw, "IMP reset detected, clear reset status"); 124 } else { 125 hns3_schedule_delayed_reset(hns); 126 hns3_warn(hw, "IMP reset detected, don't clear reset status"); 127 } 128 129 ret = HNS3_VECTOR0_EVENT_RST; 130 goto out; 131 } 132 133 /* Global reset */ 134 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { 135 rte_atomic16_set(&hw->reset.disable_cmd, 1); 136 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); 137 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); 138 if (clearval) { 139 hw->reset.stats.global_cnt++; 140 hns3_warn(hw, "Global reset detected, clear reset status"); 141 } else { 142 hns3_schedule_delayed_reset(hns); 143 hns3_warn(hw, "Global reset detected, don't clear reset status"); 144 } 145 146 ret = HNS3_VECTOR0_EVENT_RST; 147 goto out; 148 } 149 150 /* check for vector0 msix event source */ 151 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) { 152 val = vector0_int_stats; 153 ret = HNS3_VECTOR0_EVENT_ERR; 154 goto out; 155 } 156 157 /* check for vector0 mailbox(=CMDQ RX) event source */ 158 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { 159 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 160 val = cmdq_src_val; 161 ret = HNS3_VECTOR0_EVENT_MBX; 162 goto out; 163 } 164 165 if (clearval && (vector0_int_stats || cmdq_src_val)) 166 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x", 167 vector0_int_stats, cmdq_src_val); 168 val = vector0_int_stats; 169 ret = HNS3_VECTOR0_EVENT_OTHER; 170 out: 171 172 if (clearval) 173 *clearval = val; 174 return ret; 175 } 176 177 static void 178 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) 179 { 180 if (event_type == HNS3_VECTOR0_EVENT_RST) 181 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); 182 else if (event_type == HNS3_VECTOR0_EVENT_MBX) 183 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 184 } 185 186 static void 187 hns3_clear_all_event_cause(struct hns3_hw *hw) 188 { 189 uint32_t vector0_int_stats; 190 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 191 192 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) 193 hns3_warn(hw, "Probe during IMP reset interrupt"); 194 195 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) 196 hns3_warn(hw, "Probe during Global reset interrupt"); 197 198 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST, 199 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | 200 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | 201 BIT(HNS3_VECTOR0_CORERESET_INT_B)); 202 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); 203 } 204 205 static void 206 hns3_interrupt_handler(void *param) 207 { 208 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 209 struct hns3_adapter *hns = dev->data->dev_private; 210 struct hns3_hw *hw = &hns->hw; 211 enum hns3_evt_cause event_cause; 212 uint32_t clearval = 0; 213 214 /* Disable interrupt */ 215 hns3_pf_disable_irq0(hw); 216 217 event_cause = hns3_check_event_cause(hns, &clearval); 218 219 /* vector 0 interrupt is shared with reset and mailbox source events. */ 220 if (event_cause == HNS3_VECTOR0_EVENT_ERR) { 221 hns3_handle_msix_error(hns, &hw->reset.request); 222 hns3_schedule_reset(hns); 223 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) 224 hns3_schedule_reset(hns); 225 else if (event_cause == HNS3_VECTOR0_EVENT_MBX) 226 hns3_dev_handle_mbx_msg(hw); 227 else 228 hns3_err(hw, "Received unknown event"); 229 230 hns3_clear_event_cause(hw, event_cause, clearval); 231 /* Enable interrupt if it is not cause by reset */ 232 hns3_pf_enable_irq0(hw); 233 } 234 235 static int 236 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on) 237 { 238 #define HNS3_VLAN_ID_OFFSET_STEP 160 239 #define HNS3_VLAN_BYTE_SIZE 8 240 struct hns3_vlan_filter_pf_cfg_cmd *req; 241 struct hns3_hw *hw = &hns->hw; 242 uint8_t vlan_offset_byte_val; 243 struct hns3_cmd_desc desc; 244 uint8_t vlan_offset_byte; 245 uint8_t vlan_offset_base; 246 int ret; 247 248 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false); 249 250 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP; 251 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) / 252 HNS3_VLAN_BYTE_SIZE; 253 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE); 254 255 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data; 256 req->vlan_offset = vlan_offset_base; 257 req->vlan_cfg = on ? 0 : 1; 258 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 259 260 ret = hns3_cmd_send(hw, &desc, 1); 261 if (ret) 262 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d", 263 vlan_id, ret); 264 265 return ret; 266 } 267 268 static void 269 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id) 270 { 271 struct hns3_user_vlan_table *vlan_entry; 272 struct hns3_pf *pf = &hns->pf; 273 274 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 275 if (vlan_entry->vlan_id == vlan_id) { 276 if (vlan_entry->hd_tbl_status) 277 hns3_set_port_vlan_filter(hns, vlan_id, 0); 278 LIST_REMOVE(vlan_entry, next); 279 rte_free(vlan_entry); 280 break; 281 } 282 } 283 } 284 285 static void 286 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id, 287 bool writen_to_tbl) 288 { 289 struct hns3_user_vlan_table *vlan_entry; 290 struct hns3_hw *hw = &hns->hw; 291 struct hns3_pf *pf = &hns->pf; 292 293 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 294 if (vlan_entry->vlan_id == vlan_id) 295 return; 296 } 297 298 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0); 299 if (vlan_entry == NULL) { 300 hns3_err(hw, "Failed to malloc hns3 vlan table"); 301 return; 302 } 303 304 vlan_entry->hd_tbl_status = writen_to_tbl; 305 vlan_entry->vlan_id = vlan_id; 306 307 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next); 308 } 309 310 static int 311 hns3_restore_vlan_table(struct hns3_adapter *hns) 312 { 313 struct hns3_user_vlan_table *vlan_entry; 314 struct hns3_hw *hw = &hns->hw; 315 struct hns3_pf *pf = &hns->pf; 316 uint16_t vlan_id; 317 int ret = 0; 318 319 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) 320 return hns3_vlan_pvid_configure(hns, 321 hw->port_base_vlan_cfg.pvid, 1); 322 323 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 324 if (vlan_entry->hd_tbl_status) { 325 vlan_id = vlan_entry->vlan_id; 326 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1); 327 if (ret) 328 break; 329 } 330 } 331 332 return ret; 333 } 334 335 static int 336 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 337 { 338 struct hns3_hw *hw = &hns->hw; 339 bool writen_to_tbl = false; 340 int ret = 0; 341 342 /* 343 * When vlan filter is enabled, hardware regards vlan id 0 as the entry 344 * for normal packet, deleting vlan id 0 is not allowed. 345 */ 346 if (on == 0 && vlan_id == 0) 347 return 0; 348 349 /* 350 * When port base vlan enabled, we use port base vlan as the vlan 351 * filter condition. In this case, we don't update vlan filter table 352 * when user add new vlan or remove exist vlan, just update the 353 * vlan list. The vlan id in vlan list will be writen in vlan filter 354 * table until port base vlan disabled 355 */ 356 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 357 ret = hns3_set_port_vlan_filter(hns, vlan_id, on); 358 writen_to_tbl = true; 359 } 360 361 if (ret == 0 && vlan_id) { 362 if (on) 363 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl); 364 else 365 hns3_rm_dev_vlan_table(hns, vlan_id); 366 } 367 return ret; 368 } 369 370 static int 371 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 372 { 373 struct hns3_adapter *hns = dev->data->dev_private; 374 struct hns3_hw *hw = &hns->hw; 375 int ret; 376 377 rte_spinlock_lock(&hw->lock); 378 ret = hns3_vlan_filter_configure(hns, vlan_id, on); 379 rte_spinlock_unlock(&hw->lock); 380 return ret; 381 } 382 383 static int 384 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type, 385 uint16_t tpid) 386 { 387 struct hns3_rx_vlan_type_cfg_cmd *rx_req; 388 struct hns3_tx_vlan_type_cfg_cmd *tx_req; 389 struct hns3_hw *hw = &hns->hw; 390 struct hns3_cmd_desc desc; 391 int ret; 392 393 if ((vlan_type != ETH_VLAN_TYPE_INNER && 394 vlan_type != ETH_VLAN_TYPE_OUTER)) { 395 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type); 396 return -EINVAL; 397 } 398 399 if (tpid != RTE_ETHER_TYPE_VLAN) { 400 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type); 401 return -EINVAL; 402 } 403 404 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false); 405 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data; 406 407 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 408 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 409 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 410 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 411 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 412 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 413 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid); 414 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid); 415 } 416 417 ret = hns3_cmd_send(hw, &desc, 1); 418 if (ret) { 419 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d", 420 ret); 421 return ret; 422 } 423 424 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false); 425 426 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data; 427 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid); 428 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid); 429 430 ret = hns3_cmd_send(hw, &desc, 1); 431 if (ret) 432 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d", 433 ret); 434 return ret; 435 } 436 437 static int 438 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 439 uint16_t tpid) 440 { 441 struct hns3_adapter *hns = dev->data->dev_private; 442 struct hns3_hw *hw = &hns->hw; 443 int ret; 444 445 rte_spinlock_lock(&hw->lock); 446 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid); 447 rte_spinlock_unlock(&hw->lock); 448 return ret; 449 } 450 451 static int 452 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns, 453 struct hns3_rx_vtag_cfg *vcfg) 454 { 455 struct hns3_vport_vtag_rx_cfg_cmd *req; 456 struct hns3_hw *hw = &hns->hw; 457 struct hns3_cmd_desc desc; 458 uint16_t vport_id; 459 uint8_t bitmap; 460 int ret; 461 462 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false); 463 464 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data; 465 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B, 466 vcfg->strip_tag1_en ? 1 : 0); 467 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B, 468 vcfg->strip_tag2_en ? 1 : 0); 469 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B, 470 vcfg->vlan1_vlan_prionly ? 1 : 0); 471 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B, 472 vcfg->vlan2_vlan_prionly ? 1 : 0); 473 474 /* 475 * In current version VF is not supported when PF is driven by DPDK 476 * driver, just need to configure parameters for PF vport. 477 */ 478 vport_id = HNS3_PF_FUNC_ID; 479 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 480 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 481 req->vf_bitmap[req->vf_offset] = bitmap; 482 483 ret = hns3_cmd_send(hw, &desc, 1); 484 if (ret) 485 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret); 486 return ret; 487 } 488 489 static void 490 hns3_update_rx_offload_cfg(struct hns3_adapter *hns, 491 struct hns3_rx_vtag_cfg *vcfg) 492 { 493 struct hns3_pf *pf = &hns->pf; 494 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg)); 495 } 496 497 static void 498 hns3_update_tx_offload_cfg(struct hns3_adapter *hns, 499 struct hns3_tx_vtag_cfg *vcfg) 500 { 501 struct hns3_pf *pf = &hns->pf; 502 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg)); 503 } 504 505 static int 506 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable) 507 { 508 struct hns3_rx_vtag_cfg rxvlan_cfg; 509 struct hns3_hw *hw = &hns->hw; 510 int ret; 511 512 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 513 rxvlan_cfg.strip_tag1_en = false; 514 rxvlan_cfg.strip_tag2_en = enable; 515 } else { 516 rxvlan_cfg.strip_tag1_en = enable; 517 rxvlan_cfg.strip_tag2_en = true; 518 } 519 520 rxvlan_cfg.vlan1_vlan_prionly = false; 521 rxvlan_cfg.vlan2_vlan_prionly = false; 522 rxvlan_cfg.rx_vlan_offload_en = enable; 523 524 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg); 525 if (ret) { 526 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret); 527 return ret; 528 } 529 530 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg); 531 532 return ret; 533 } 534 535 static int 536 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type, 537 uint8_t fe_type, bool filter_en, uint8_t vf_id) 538 { 539 struct hns3_vlan_filter_ctrl_cmd *req; 540 struct hns3_cmd_desc desc; 541 int ret; 542 543 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false); 544 545 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data; 546 req->vlan_type = vlan_type; 547 req->vlan_fe = filter_en ? fe_type : 0; 548 req->vf_id = vf_id; 549 550 ret = hns3_cmd_send(hw, &desc, 1); 551 if (ret) 552 hns3_err(hw, "set vlan filter fail, ret =%d", ret); 553 554 return ret; 555 } 556 557 static int 558 hns3_vlan_filter_init(struct hns3_adapter *hns) 559 { 560 struct hns3_hw *hw = &hns->hw; 561 int ret; 562 563 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF, 564 HNS3_FILTER_FE_EGRESS, false, 565 HNS3_PF_FUNC_ID); 566 if (ret) { 567 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret); 568 return ret; 569 } 570 571 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 572 HNS3_FILTER_FE_INGRESS, false, 573 HNS3_PF_FUNC_ID); 574 if (ret) 575 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret); 576 577 return ret; 578 } 579 580 static int 581 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable) 582 { 583 struct hns3_hw *hw = &hns->hw; 584 int ret; 585 586 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 587 HNS3_FILTER_FE_INGRESS, enable, 588 HNS3_PF_FUNC_ID); 589 if (ret) 590 hns3_err(hw, "failed to %s port vlan filter, ret = %d", 591 enable ? "enable" : "disable", ret); 592 593 return ret; 594 } 595 596 static int 597 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask) 598 { 599 struct hns3_adapter *hns = dev->data->dev_private; 600 struct hns3_hw *hw = &hns->hw; 601 struct rte_eth_rxmode *rxmode; 602 unsigned int tmp_mask; 603 bool enable; 604 int ret = 0; 605 606 rte_spinlock_lock(&hw->lock); 607 rxmode = &dev->data->dev_conf.rxmode; 608 tmp_mask = (unsigned int)mask; 609 if (tmp_mask & ETH_VLAN_FILTER_MASK) { 610 /* ignore vlan filter configuration during promiscuous mode */ 611 if (!dev->data->promiscuous) { 612 /* Enable or disable VLAN filter */ 613 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? 614 true : false; 615 616 ret = hns3_enable_vlan_filter(hns, enable); 617 if (ret) { 618 rte_spinlock_unlock(&hw->lock); 619 hns3_err(hw, "failed to %s rx filter, ret = %d", 620 enable ? "enable" : "disable", ret); 621 return ret; 622 } 623 } 624 } 625 626 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 627 /* Enable or disable VLAN stripping */ 628 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? 629 true : false; 630 631 ret = hns3_en_hw_strip_rxvtag(hns, enable); 632 if (ret) { 633 rte_spinlock_unlock(&hw->lock); 634 hns3_err(hw, "failed to %s rx strip, ret = %d", 635 enable ? "enable" : "disable", ret); 636 return ret; 637 } 638 } 639 640 rte_spinlock_unlock(&hw->lock); 641 642 return ret; 643 } 644 645 static int 646 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns, 647 struct hns3_tx_vtag_cfg *vcfg) 648 { 649 struct hns3_vport_vtag_tx_cfg_cmd *req; 650 struct hns3_cmd_desc desc; 651 struct hns3_hw *hw = &hns->hw; 652 uint16_t vport_id; 653 uint8_t bitmap; 654 int ret; 655 656 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false); 657 658 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data; 659 req->def_vlan_tag1 = vcfg->default_tag1; 660 req->def_vlan_tag2 = vcfg->default_tag2; 661 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B, 662 vcfg->accept_tag1 ? 1 : 0); 663 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B, 664 vcfg->accept_untag1 ? 1 : 0); 665 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B, 666 vcfg->accept_tag2 ? 1 : 0); 667 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B, 668 vcfg->accept_untag2 ? 1 : 0); 669 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B, 670 vcfg->insert_tag1_en ? 1 : 0); 671 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B, 672 vcfg->insert_tag2_en ? 1 : 0); 673 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0); 674 675 /* 676 * In current version VF is not supported when PF is driven by DPDK 677 * driver, just need to configure parameters for PF vport. 678 */ 679 vport_id = HNS3_PF_FUNC_ID; 680 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 681 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 682 req->vf_bitmap[req->vf_offset] = bitmap; 683 684 ret = hns3_cmd_send(hw, &desc, 1); 685 if (ret) 686 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret); 687 688 return ret; 689 } 690 691 static int 692 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state, 693 uint16_t pvid) 694 { 695 struct hns3_hw *hw = &hns->hw; 696 struct hns3_tx_vtag_cfg txvlan_cfg; 697 int ret; 698 699 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) { 700 txvlan_cfg.accept_tag1 = true; 701 txvlan_cfg.insert_tag1_en = false; 702 txvlan_cfg.default_tag1 = 0; 703 } else { 704 txvlan_cfg.accept_tag1 = false; 705 txvlan_cfg.insert_tag1_en = true; 706 txvlan_cfg.default_tag1 = pvid; 707 } 708 709 txvlan_cfg.accept_untag1 = true; 710 txvlan_cfg.accept_tag2 = true; 711 txvlan_cfg.accept_untag2 = true; 712 txvlan_cfg.insert_tag2_en = false; 713 txvlan_cfg.default_tag2 = 0; 714 715 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg); 716 if (ret) { 717 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid, 718 ret); 719 return ret; 720 } 721 722 hns3_update_tx_offload_cfg(hns, &txvlan_cfg); 723 return ret; 724 } 725 726 static void 727 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on) 728 { 729 struct hns3_hw *hw = &hns->hw; 730 731 hw->port_base_vlan_cfg.state = on ? 732 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE; 733 734 hw->port_base_vlan_cfg.pvid = pvid; 735 } 736 737 static void 738 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list) 739 { 740 struct hns3_user_vlan_table *vlan_entry; 741 struct hns3_pf *pf = &hns->pf; 742 743 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 744 if (vlan_entry->hd_tbl_status) 745 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0); 746 747 vlan_entry->hd_tbl_status = false; 748 } 749 750 if (is_del_list) { 751 vlan_entry = LIST_FIRST(&pf->vlan_list); 752 while (vlan_entry) { 753 LIST_REMOVE(vlan_entry, next); 754 rte_free(vlan_entry); 755 vlan_entry = LIST_FIRST(&pf->vlan_list); 756 } 757 } 758 } 759 760 static void 761 hns3_add_all_vlan_table(struct hns3_adapter *hns) 762 { 763 struct hns3_user_vlan_table *vlan_entry; 764 struct hns3_pf *pf = &hns->pf; 765 766 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 767 if (!vlan_entry->hd_tbl_status) 768 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1); 769 770 vlan_entry->hd_tbl_status = true; 771 } 772 } 773 774 static void 775 hns3_remove_all_vlan_table(struct hns3_adapter *hns) 776 { 777 struct hns3_hw *hw = &hns->hw; 778 int ret; 779 780 hns3_rm_all_vlan_table(hns, true); 781 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) { 782 ret = hns3_set_port_vlan_filter(hns, 783 hw->port_base_vlan_cfg.pvid, 0); 784 if (ret) { 785 hns3_err(hw, "Failed to remove all vlan table, ret =%d", 786 ret); 787 return; 788 } 789 } 790 } 791 792 static int 793 hns3_update_vlan_filter_entries(struct hns3_adapter *hns, 794 uint16_t port_base_vlan_state, 795 uint16_t new_pvid, uint16_t old_pvid) 796 { 797 struct hns3_hw *hw = &hns->hw; 798 int ret = 0; 799 800 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) { 801 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) { 802 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0); 803 if (ret) { 804 hns3_err(hw, 805 "Failed to clear clear old pvid filter, ret =%d", 806 ret); 807 return ret; 808 } 809 } 810 811 hns3_rm_all_vlan_table(hns, false); 812 return hns3_set_port_vlan_filter(hns, new_pvid, 1); 813 } 814 815 if (new_pvid != 0) { 816 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0); 817 if (ret) { 818 hns3_err(hw, "Failed to set port vlan filter, ret =%d", 819 ret); 820 return ret; 821 } 822 } 823 824 if (new_pvid == hw->port_base_vlan_cfg.pvid) 825 hns3_add_all_vlan_table(hns); 826 827 return ret; 828 } 829 830 static int 831 hns3_en_pvid_strip(struct hns3_adapter *hns, int on) 832 { 833 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg; 834 struct hns3_rx_vtag_cfg rx_vlan_cfg; 835 bool rx_strip_en; 836 int ret; 837 838 rx_strip_en = old_cfg->rx_vlan_offload_en ? true : false; 839 if (on) { 840 rx_vlan_cfg.strip_tag1_en = rx_strip_en; 841 rx_vlan_cfg.strip_tag2_en = true; 842 } else { 843 rx_vlan_cfg.strip_tag1_en = false; 844 rx_vlan_cfg.strip_tag2_en = rx_strip_en; 845 } 846 rx_vlan_cfg.vlan1_vlan_prionly = false; 847 rx_vlan_cfg.vlan2_vlan_prionly = false; 848 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en; 849 850 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg); 851 if (ret) 852 return ret; 853 854 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg); 855 return ret; 856 } 857 858 static int 859 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on) 860 { 861 struct hns3_hw *hw = &hns->hw; 862 uint16_t port_base_vlan_state; 863 uint16_t old_pvid; 864 int ret; 865 866 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) { 867 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) 868 hns3_warn(hw, "Invalid operation! As current pvid set " 869 "is %u, disable pvid %u is invalid", 870 hw->port_base_vlan_cfg.pvid, pvid); 871 return 0; 872 } 873 874 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE : 875 HNS3_PORT_BASE_VLAN_DISABLE; 876 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid); 877 if (ret) { 878 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d", 879 ret); 880 return ret; 881 } 882 883 ret = hns3_en_pvid_strip(hns, on); 884 if (ret) { 885 hns3_err(hw, "failed to config rx vlan strip for pvid, " 886 "ret = %d", ret); 887 return ret; 888 } 889 890 if (pvid == HNS3_INVLID_PVID) 891 goto out; 892 old_pvid = hw->port_base_vlan_cfg.pvid; 893 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid, 894 old_pvid); 895 if (ret) { 896 hns3_err(hw, "Failed to update vlan filter entries, ret =%d", 897 ret); 898 return ret; 899 } 900 901 out: 902 hns3_store_port_base_vlan_info(hns, pvid, on); 903 return ret; 904 } 905 906 static int 907 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 908 { 909 struct hns3_adapter *hns = dev->data->dev_private; 910 struct hns3_hw *hw = &hns->hw; 911 int ret; 912 913 if (pvid > RTE_ETHER_MAX_VLAN_ID) { 914 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid, 915 RTE_ETHER_MAX_VLAN_ID); 916 return -EINVAL; 917 } 918 919 rte_spinlock_lock(&hw->lock); 920 ret = hns3_vlan_pvid_configure(hns, pvid, on); 921 rte_spinlock_unlock(&hw->lock); 922 return ret; 923 } 924 925 static void 926 init_port_base_vlan_info(struct hns3_hw *hw) 927 { 928 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE; 929 hw->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID; 930 } 931 932 static int 933 hns3_default_vlan_config(struct hns3_adapter *hns) 934 { 935 struct hns3_hw *hw = &hns->hw; 936 int ret; 937 938 ret = hns3_set_port_vlan_filter(hns, 0, 1); 939 if (ret) 940 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret); 941 return ret; 942 } 943 944 static int 945 hns3_init_vlan_config(struct hns3_adapter *hns) 946 { 947 struct hns3_hw *hw = &hns->hw; 948 int ret; 949 950 /* 951 * This function can be called in the initialization and reset process, 952 * when in reset process, it means that hardware had been reseted 953 * successfully and we need to restore the hardware configuration to 954 * ensure that the hardware configuration remains unchanged before and 955 * after reset. 956 */ 957 if (rte_atomic16_read(&hw->reset.resetting) == 0) 958 init_port_base_vlan_info(hw); 959 960 ret = hns3_vlan_filter_init(hns); 961 if (ret) { 962 hns3_err(hw, "vlan init fail in pf, ret =%d", ret); 963 return ret; 964 } 965 966 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER, 967 RTE_ETHER_TYPE_VLAN); 968 if (ret) { 969 hns3_err(hw, "tpid set fail in pf, ret =%d", ret); 970 return ret; 971 } 972 973 /* 974 * When in the reinit dev stage of the reset process, the following 975 * vlan-related configurations may differ from those at initialization, 976 * we will restore configurations to hardware in hns3_restore_vlan_table 977 * and hns3_restore_vlan_conf later. 978 */ 979 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 980 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0); 981 if (ret) { 982 hns3_err(hw, "pvid set fail in pf, ret =%d", ret); 983 return ret; 984 } 985 986 ret = hns3_en_hw_strip_rxvtag(hns, false); 987 if (ret) { 988 hns3_err(hw, "rx strip configure fail in pf, ret =%d", 989 ret); 990 return ret; 991 } 992 } 993 994 return hns3_default_vlan_config(hns); 995 } 996 997 static int 998 hns3_restore_vlan_conf(struct hns3_adapter *hns) 999 { 1000 struct hns3_pf *pf = &hns->pf; 1001 struct hns3_hw *hw = &hns->hw; 1002 uint64_t offloads; 1003 bool enable; 1004 int ret; 1005 1006 if (!hw->data->promiscuous) { 1007 /* restore vlan filter states */ 1008 offloads = hw->data->dev_conf.rxmode.offloads; 1009 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false; 1010 ret = hns3_enable_vlan_filter(hns, enable); 1011 if (ret) { 1012 hns3_err(hw, "failed to restore vlan rx filter conf, " 1013 "ret = %d", ret); 1014 return ret; 1015 } 1016 } 1017 1018 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg); 1019 if (ret) { 1020 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret); 1021 return ret; 1022 } 1023 1024 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg); 1025 if (ret) 1026 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret); 1027 1028 return ret; 1029 } 1030 1031 static int 1032 hns3_dev_configure_vlan(struct rte_eth_dev *dev) 1033 { 1034 struct hns3_adapter *hns = dev->data->dev_private; 1035 struct rte_eth_dev_data *data = dev->data; 1036 struct rte_eth_txmode *txmode; 1037 struct hns3_hw *hw = &hns->hw; 1038 int mask; 1039 int ret; 1040 1041 txmode = &data->dev_conf.txmode; 1042 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged) 1043 hns3_warn(hw, 1044 "hw_vlan_reject_tagged or hw_vlan_reject_untagged " 1045 "configuration is not supported! Ignore these two " 1046 "parameters: hw_vlan_reject_tagged(%d), " 1047 "hw_vlan_reject_untagged(%d)", 1048 txmode->hw_vlan_reject_tagged, 1049 txmode->hw_vlan_reject_untagged); 1050 1051 /* Apply vlan offload setting */ 1052 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK; 1053 ret = hns3_vlan_offload_set(dev, mask); 1054 if (ret) { 1055 hns3_err(hw, "dev config rx vlan offload failed, ret = %d", 1056 ret); 1057 return ret; 1058 } 1059 1060 /* 1061 * If pvid config is not set in rte_eth_conf, driver needn't to set 1062 * VLAN pvid related configuration to hardware. 1063 */ 1064 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0) 1065 return 0; 1066 1067 /* Apply pvid setting */ 1068 ret = hns3_vlan_pvid_set(dev, txmode->pvid, 1069 txmode->hw_vlan_insert_pvid); 1070 if (ret) 1071 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d", 1072 txmode->pvid, ret); 1073 1074 return ret; 1075 } 1076 1077 static int 1078 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, 1079 unsigned int tso_mss_max) 1080 { 1081 struct hns3_cfg_tso_status_cmd *req; 1082 struct hns3_cmd_desc desc; 1083 uint16_t tso_mss; 1084 1085 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false); 1086 1087 req = (struct hns3_cfg_tso_status_cmd *)desc.data; 1088 1089 tso_mss = 0; 1090 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1091 tso_mss_min); 1092 req->tso_mss_min = rte_cpu_to_le_16(tso_mss); 1093 1094 tso_mss = 0; 1095 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1096 tso_mss_max); 1097 req->tso_mss_max = rte_cpu_to_le_16(tso_mss); 1098 1099 return hns3_cmd_send(hw, &desc, 1); 1100 } 1101 1102 int 1103 hns3_config_gro(struct hns3_hw *hw, bool en) 1104 { 1105 struct hns3_cfg_gro_status_cmd *req; 1106 struct hns3_cmd_desc desc; 1107 int ret; 1108 1109 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false); 1110 req = (struct hns3_cfg_gro_status_cmd *)desc.data; 1111 1112 req->gro_en = rte_cpu_to_le_16(en ? 1 : 0); 1113 1114 ret = hns3_cmd_send(hw, &desc, 1); 1115 if (ret) 1116 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret); 1117 1118 return ret; 1119 } 1120 1121 static int 1122 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size, 1123 uint16_t *allocated_size, bool is_alloc) 1124 { 1125 struct hns3_umv_spc_alc_cmd *req; 1126 struct hns3_cmd_desc desc; 1127 int ret; 1128 1129 req = (struct hns3_umv_spc_alc_cmd *)desc.data; 1130 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false); 1131 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1); 1132 req->space_size = rte_cpu_to_le_32(space_size); 1133 1134 ret = hns3_cmd_send(hw, &desc, 1); 1135 if (ret) { 1136 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d", 1137 is_alloc ? "allocate" : "free", ret); 1138 return ret; 1139 } 1140 1141 if (is_alloc && allocated_size) 1142 *allocated_size = rte_le_to_cpu_32(desc.data[1]); 1143 1144 return 0; 1145 } 1146 1147 static int 1148 hns3_init_umv_space(struct hns3_hw *hw) 1149 { 1150 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1151 struct hns3_pf *pf = &hns->pf; 1152 uint16_t allocated_size = 0; 1153 int ret; 1154 1155 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size, 1156 true); 1157 if (ret) 1158 return ret; 1159 1160 if (allocated_size < pf->wanted_umv_size) 1161 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u", 1162 pf->wanted_umv_size, allocated_size); 1163 1164 pf->max_umv_size = (!!allocated_size) ? allocated_size : 1165 pf->wanted_umv_size; 1166 pf->used_umv_size = 0; 1167 return 0; 1168 } 1169 1170 static int 1171 hns3_uninit_umv_space(struct hns3_hw *hw) 1172 { 1173 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1174 struct hns3_pf *pf = &hns->pf; 1175 int ret; 1176 1177 if (pf->max_umv_size == 0) 1178 return 0; 1179 1180 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false); 1181 if (ret) 1182 return ret; 1183 1184 pf->max_umv_size = 0; 1185 1186 return 0; 1187 } 1188 1189 static bool 1190 hns3_is_umv_space_full(struct hns3_hw *hw) 1191 { 1192 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1193 struct hns3_pf *pf = &hns->pf; 1194 bool is_full; 1195 1196 is_full = (pf->used_umv_size >= pf->max_umv_size); 1197 1198 return is_full; 1199 } 1200 1201 static void 1202 hns3_update_umv_space(struct hns3_hw *hw, bool is_free) 1203 { 1204 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1205 struct hns3_pf *pf = &hns->pf; 1206 1207 if (is_free) { 1208 if (pf->used_umv_size > 0) 1209 pf->used_umv_size--; 1210 } else 1211 pf->used_umv_size++; 1212 } 1213 1214 static void 1215 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req, 1216 const uint8_t *addr, bool is_mc) 1217 { 1218 const unsigned char *mac_addr = addr; 1219 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) | 1220 ((uint32_t)mac_addr[2] << 16) | 1221 ((uint32_t)mac_addr[1] << 8) | 1222 (uint32_t)mac_addr[0]; 1223 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4]; 1224 1225 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1226 if (is_mc) { 1227 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1228 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1); 1229 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1230 } 1231 1232 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val); 1233 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff); 1234 } 1235 1236 static int 1237 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp, 1238 uint8_t resp_code, 1239 enum hns3_mac_vlan_tbl_opcode op) 1240 { 1241 if (cmdq_resp) { 1242 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u", 1243 cmdq_resp); 1244 return -EIO; 1245 } 1246 1247 if (op == HNS3_MAC_VLAN_ADD) { 1248 if (resp_code == 0 || resp_code == 1) { 1249 return 0; 1250 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) { 1251 hns3_err(hw, "add mac addr failed for uc_overflow"); 1252 return -ENOSPC; 1253 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) { 1254 hns3_err(hw, "add mac addr failed for mc_overflow"); 1255 return -ENOSPC; 1256 } 1257 1258 hns3_err(hw, "add mac addr failed for undefined, code=%u", 1259 resp_code); 1260 return -EIO; 1261 } else if (op == HNS3_MAC_VLAN_REMOVE) { 1262 if (resp_code == 0) { 1263 return 0; 1264 } else if (resp_code == 1) { 1265 hns3_dbg(hw, "remove mac addr failed for miss"); 1266 return -ENOENT; 1267 } 1268 1269 hns3_err(hw, "remove mac addr failed for undefined, code=%u", 1270 resp_code); 1271 return -EIO; 1272 } else if (op == HNS3_MAC_VLAN_LKUP) { 1273 if (resp_code == 0) { 1274 return 0; 1275 } else if (resp_code == 1) { 1276 hns3_dbg(hw, "lookup mac addr failed for miss"); 1277 return -ENOENT; 1278 } 1279 1280 hns3_err(hw, "lookup mac addr failed for undefined, code=%u", 1281 resp_code); 1282 return -EIO; 1283 } 1284 1285 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u", 1286 op); 1287 1288 return -EINVAL; 1289 } 1290 1291 static int 1292 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw, 1293 struct hns3_mac_vlan_tbl_entry_cmd *req, 1294 struct hns3_cmd_desc *desc, bool is_mc) 1295 { 1296 uint8_t resp_code; 1297 uint16_t retval; 1298 int ret; 1299 1300 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true); 1301 if (is_mc) { 1302 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1303 memcpy(desc[0].data, req, 1304 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1305 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD, 1306 true); 1307 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1308 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD, 1309 true); 1310 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1311 } else { 1312 memcpy(desc[0].data, req, 1313 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1314 ret = hns3_cmd_send(hw, desc, 1); 1315 } 1316 if (ret) { 1317 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.", 1318 ret); 1319 return ret; 1320 } 1321 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1322 retval = rte_le_to_cpu_16(desc[0].retval); 1323 1324 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1325 HNS3_MAC_VLAN_LKUP); 1326 } 1327 1328 static int 1329 hns3_add_mac_vlan_tbl(struct hns3_hw *hw, 1330 struct hns3_mac_vlan_tbl_entry_cmd *req, 1331 struct hns3_cmd_desc *mc_desc) 1332 { 1333 uint8_t resp_code; 1334 uint16_t retval; 1335 int cfg_status; 1336 int ret; 1337 1338 if (mc_desc == NULL) { 1339 struct hns3_cmd_desc desc; 1340 1341 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false); 1342 memcpy(desc.data, req, 1343 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1344 ret = hns3_cmd_send(hw, &desc, 1); 1345 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1346 retval = rte_le_to_cpu_16(desc.retval); 1347 1348 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1349 HNS3_MAC_VLAN_ADD); 1350 } else { 1351 hns3_cmd_reuse_desc(&mc_desc[0], false); 1352 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1353 hns3_cmd_reuse_desc(&mc_desc[1], false); 1354 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1355 hns3_cmd_reuse_desc(&mc_desc[2], false); 1356 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT); 1357 memcpy(mc_desc[0].data, req, 1358 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1359 mc_desc[0].retval = 0; 1360 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1361 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff; 1362 retval = rte_le_to_cpu_16(mc_desc[0].retval); 1363 1364 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1365 HNS3_MAC_VLAN_ADD); 1366 } 1367 1368 if (ret) { 1369 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret); 1370 return ret; 1371 } 1372 1373 return cfg_status; 1374 } 1375 1376 static int 1377 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw, 1378 struct hns3_mac_vlan_tbl_entry_cmd *req) 1379 { 1380 struct hns3_cmd_desc desc; 1381 uint8_t resp_code; 1382 uint16_t retval; 1383 int ret; 1384 1385 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false); 1386 1387 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1388 1389 ret = hns3_cmd_send(hw, &desc, 1); 1390 if (ret) { 1391 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret); 1392 return ret; 1393 } 1394 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1395 retval = rte_le_to_cpu_16(desc.retval); 1396 1397 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1398 HNS3_MAC_VLAN_REMOVE); 1399 } 1400 1401 static int 1402 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1403 { 1404 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1405 struct hns3_mac_vlan_tbl_entry_cmd req; 1406 struct hns3_pf *pf = &hns->pf; 1407 struct hns3_cmd_desc desc; 1408 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1409 uint16_t egress_port = 0; 1410 uint8_t vf_id; 1411 int ret; 1412 1413 /* check if mac addr is valid */ 1414 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1415 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1416 mac_addr); 1417 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid", 1418 mac_str); 1419 return -EINVAL; 1420 } 1421 1422 memset(&req, 0, sizeof(req)); 1423 1424 /* 1425 * In current version VF is not supported when PF is driven by DPDK 1426 * driver, just need to configure parameters for PF vport. 1427 */ 1428 vf_id = HNS3_PF_FUNC_ID; 1429 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M, 1430 HNS3_MAC_EPORT_VFID_S, vf_id); 1431 1432 req.egress_port = rte_cpu_to_le_16(egress_port); 1433 1434 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1435 1436 /* 1437 * Lookup the mac address in the mac_vlan table, and add 1438 * it if the entry is inexistent. Repeated unicast entry 1439 * is not allowed in the mac vlan table. 1440 */ 1441 ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false); 1442 if (ret == -ENOENT) { 1443 if (!hns3_is_umv_space_full(hw)) { 1444 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL); 1445 if (!ret) 1446 hns3_update_umv_space(hw, false); 1447 return ret; 1448 } 1449 1450 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size); 1451 1452 return -ENOSPC; 1453 } 1454 1455 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr); 1456 1457 /* check if we just hit the duplicate */ 1458 if (ret == 0) { 1459 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str); 1460 return 0; 1461 } 1462 1463 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table", 1464 mac_str); 1465 1466 return ret; 1467 } 1468 1469 static int 1470 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1471 { 1472 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1473 struct rte_ether_addr *addr; 1474 int ret; 1475 int i; 1476 1477 for (i = 0; i < hw->mc_addrs_num; i++) { 1478 addr = &hw->mc_addrs[i]; 1479 /* Check if there are duplicate addresses */ 1480 if (rte_is_same_ether_addr(addr, mac_addr)) { 1481 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1482 addr); 1483 hns3_err(hw, "failed to add mc mac addr, same addrs" 1484 "(%s) is added by the set_mc_mac_addr_list " 1485 "API", mac_str); 1486 return -EINVAL; 1487 } 1488 } 1489 1490 ret = hns3_add_mc_addr(hw, mac_addr); 1491 if (ret) { 1492 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1493 mac_addr); 1494 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 1495 mac_str, ret); 1496 } 1497 return ret; 1498 } 1499 1500 static int 1501 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1502 { 1503 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1504 int ret; 1505 1506 ret = hns3_remove_mc_addr(hw, mac_addr); 1507 if (ret) { 1508 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1509 mac_addr); 1510 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d", 1511 mac_str, ret); 1512 } 1513 return ret; 1514 } 1515 1516 static int 1517 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1518 uint32_t idx, __rte_unused uint32_t pool) 1519 { 1520 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1521 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1522 int ret; 1523 1524 rte_spinlock_lock(&hw->lock); 1525 1526 /* 1527 * In hns3 network engine adding UC and MC mac address with different 1528 * commands with firmware. We need to determine whether the input 1529 * address is a UC or a MC address to call different commands. 1530 * By the way, it is recommended calling the API function named 1531 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 1532 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 1533 * may affect the specifications of UC mac addresses. 1534 */ 1535 if (rte_is_multicast_ether_addr(mac_addr)) 1536 ret = hns3_add_mc_addr_common(hw, mac_addr); 1537 else 1538 ret = hns3_add_uc_addr_common(hw, mac_addr); 1539 1540 if (ret) { 1541 rte_spinlock_unlock(&hw->lock); 1542 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1543 mac_addr); 1544 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 1545 ret); 1546 return ret; 1547 } 1548 1549 if (idx == 0) 1550 hw->mac.default_addr_setted = true; 1551 rte_spinlock_unlock(&hw->lock); 1552 1553 return ret; 1554 } 1555 1556 static int 1557 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1558 { 1559 struct hns3_mac_vlan_tbl_entry_cmd req; 1560 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1561 int ret; 1562 1563 /* check if mac addr is valid */ 1564 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1565 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1566 mac_addr); 1567 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid", 1568 mac_str); 1569 return -EINVAL; 1570 } 1571 1572 memset(&req, 0, sizeof(req)); 1573 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1574 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1575 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1576 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */ 1577 return 0; 1578 else if (ret == 0) 1579 hns3_update_umv_space(hw, true); 1580 1581 return ret; 1582 } 1583 1584 static void 1585 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 1586 { 1587 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1588 /* index will be checked by upper level rte interface */ 1589 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 1590 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1591 int ret; 1592 1593 rte_spinlock_lock(&hw->lock); 1594 1595 if (rte_is_multicast_ether_addr(mac_addr)) 1596 ret = hns3_remove_mc_addr_common(hw, mac_addr); 1597 else 1598 ret = hns3_remove_uc_addr_common(hw, mac_addr); 1599 rte_spinlock_unlock(&hw->lock); 1600 if (ret) { 1601 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1602 mac_addr); 1603 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str, 1604 ret); 1605 } 1606 } 1607 1608 static int 1609 hns3_set_default_mac_addr(struct rte_eth_dev *dev, 1610 struct rte_ether_addr *mac_addr) 1611 { 1612 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1613 struct rte_ether_addr *oaddr; 1614 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1615 bool default_addr_setted; 1616 bool rm_succes = false; 1617 int ret, ret_val; 1618 1619 /* 1620 * It has been guaranteed that input parameter named mac_addr is valid 1621 * address in the rte layer of DPDK framework. 1622 */ 1623 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr; 1624 default_addr_setted = hw->mac.default_addr_setted; 1625 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr)) 1626 return 0; 1627 1628 rte_spinlock_lock(&hw->lock); 1629 if (default_addr_setted) { 1630 ret = hns3_remove_uc_addr_common(hw, oaddr); 1631 if (ret) { 1632 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1633 oaddr); 1634 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d", 1635 mac_str, ret); 1636 rm_succes = false; 1637 } else 1638 rm_succes = true; 1639 } 1640 1641 ret = hns3_add_uc_addr_common(hw, mac_addr); 1642 if (ret) { 1643 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1644 mac_addr); 1645 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret); 1646 goto err_add_uc_addr; 1647 } 1648 1649 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes); 1650 if (ret) { 1651 hns3_err(hw, "Failed to configure mac pause address: %d", ret); 1652 goto err_pause_addr_cfg; 1653 } 1654 1655 rte_ether_addr_copy(mac_addr, 1656 (struct rte_ether_addr *)hw->mac.mac_addr); 1657 hw->mac.default_addr_setted = true; 1658 rte_spinlock_unlock(&hw->lock); 1659 1660 return 0; 1661 1662 err_pause_addr_cfg: 1663 ret_val = hns3_remove_uc_addr_common(hw, mac_addr); 1664 if (ret_val) { 1665 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1666 mac_addr); 1667 hns3_warn(hw, 1668 "Failed to roll back to del setted mac addr(%s): %d", 1669 mac_str, ret_val); 1670 } 1671 1672 err_add_uc_addr: 1673 if (rm_succes) { 1674 ret_val = hns3_add_uc_addr_common(hw, oaddr); 1675 if (ret_val) { 1676 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1677 oaddr); 1678 hns3_warn(hw, 1679 "Failed to restore old uc mac addr(%s): %d", 1680 mac_str, ret_val); 1681 hw->mac.default_addr_setted = false; 1682 } 1683 } 1684 rte_spinlock_unlock(&hw->lock); 1685 1686 return ret; 1687 } 1688 1689 static int 1690 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del) 1691 { 1692 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1693 struct hns3_hw *hw = &hns->hw; 1694 struct rte_ether_addr *addr; 1695 int err = 0; 1696 int ret; 1697 int i; 1698 1699 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) { 1700 addr = &hw->data->mac_addrs[i]; 1701 if (rte_is_zero_ether_addr(addr)) 1702 continue; 1703 if (rte_is_multicast_ether_addr(addr)) 1704 ret = del ? hns3_remove_mc_addr(hw, addr) : 1705 hns3_add_mc_addr(hw, addr); 1706 else 1707 ret = del ? hns3_remove_uc_addr_common(hw, addr) : 1708 hns3_add_uc_addr_common(hw, addr); 1709 1710 if (ret) { 1711 err = ret; 1712 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1713 addr); 1714 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 1715 "ret = %d.", del ? "remove" : "restore", 1716 mac_str, i, ret); 1717 } 1718 } 1719 return err; 1720 } 1721 1722 static void 1723 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr) 1724 { 1725 #define HNS3_VF_NUM_IN_FIRST_DESC 192 1726 uint8_t word_num; 1727 uint8_t bit_num; 1728 1729 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) { 1730 word_num = vfid / 32; 1731 bit_num = vfid % 32; 1732 if (clr) 1733 desc[1].data[word_num] &= 1734 rte_cpu_to_le_32(~(1UL << bit_num)); 1735 else 1736 desc[1].data[word_num] |= 1737 rte_cpu_to_le_32(1UL << bit_num); 1738 } else { 1739 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32; 1740 bit_num = vfid % 32; 1741 if (clr) 1742 desc[2].data[word_num] &= 1743 rte_cpu_to_le_32(~(1UL << bit_num)); 1744 else 1745 desc[2].data[word_num] |= 1746 rte_cpu_to_le_32(1UL << bit_num); 1747 } 1748 } 1749 1750 static int 1751 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1752 { 1753 struct hns3_mac_vlan_tbl_entry_cmd req; 1754 struct hns3_cmd_desc desc[3]; 1755 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1756 uint8_t vf_id; 1757 int ret; 1758 1759 /* Check if mac addr is valid */ 1760 if (!rte_is_multicast_ether_addr(mac_addr)) { 1761 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1762 mac_addr); 1763 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid", 1764 mac_str); 1765 return -EINVAL; 1766 } 1767 1768 memset(&req, 0, sizeof(req)); 1769 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1770 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1771 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1772 if (ret) { 1773 /* This mac addr do not exist, add new entry for it */ 1774 memset(desc[0].data, 0, sizeof(desc[0].data)); 1775 memset(desc[1].data, 0, sizeof(desc[0].data)); 1776 memset(desc[2].data, 0, sizeof(desc[0].data)); 1777 } 1778 1779 /* 1780 * In current version VF is not supported when PF is driven by DPDK 1781 * driver, just need to configure parameters for PF vport. 1782 */ 1783 vf_id = HNS3_PF_FUNC_ID; 1784 hns3_update_desc_vfid(desc, vf_id, false); 1785 ret = hns3_add_mac_vlan_tbl(hw, &req, desc); 1786 if (ret) { 1787 if (ret == -ENOSPC) 1788 hns3_err(hw, "mc mac vlan table is full"); 1789 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1790 mac_addr); 1791 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret); 1792 } 1793 1794 return ret; 1795 } 1796 1797 static int 1798 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1799 { 1800 struct hns3_mac_vlan_tbl_entry_cmd req; 1801 struct hns3_cmd_desc desc[3]; 1802 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1803 uint8_t vf_id; 1804 int ret; 1805 1806 /* Check if mac addr is valid */ 1807 if (!rte_is_multicast_ether_addr(mac_addr)) { 1808 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1809 mac_addr); 1810 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid", 1811 mac_str); 1812 return -EINVAL; 1813 } 1814 1815 memset(&req, 0, sizeof(req)); 1816 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1817 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1818 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1819 if (ret == 0) { 1820 /* 1821 * This mac addr exist, remove this handle's VFID for it. 1822 * In current version VF is not supported when PF is driven by 1823 * DPDK driver, just need to configure parameters for PF vport. 1824 */ 1825 vf_id = HNS3_PF_FUNC_ID; 1826 hns3_update_desc_vfid(desc, vf_id, true); 1827 1828 /* All the vfid is zero, so need to delete this entry */ 1829 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1830 } else if (ret == -ENOENT) { 1831 /* This mac addr doesn't exist. */ 1832 return 0; 1833 } 1834 1835 if (ret) { 1836 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1837 mac_addr); 1838 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret); 1839 } 1840 1841 return ret; 1842 } 1843 1844 static int 1845 hns3_set_mc_addr_chk_param(struct hns3_hw *hw, 1846 struct rte_ether_addr *mc_addr_set, 1847 uint32_t nb_mc_addr) 1848 { 1849 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1850 struct rte_ether_addr *addr; 1851 uint32_t i; 1852 uint32_t j; 1853 1854 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 1855 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) " 1856 "invalid. valid range: 0~%d", 1857 nb_mc_addr, HNS3_MC_MACADDR_NUM); 1858 return -EINVAL; 1859 } 1860 1861 /* Check if input mac addresses are valid */ 1862 for (i = 0; i < nb_mc_addr; i++) { 1863 addr = &mc_addr_set[i]; 1864 if (!rte_is_multicast_ether_addr(addr)) { 1865 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1866 addr); 1867 hns3_err(hw, 1868 "failed to set mc mac addr, addr(%s) invalid.", 1869 mac_str); 1870 return -EINVAL; 1871 } 1872 1873 /* Check if there are duplicate addresses */ 1874 for (j = i + 1; j < nb_mc_addr; j++) { 1875 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 1876 rte_ether_format_addr(mac_str, 1877 RTE_ETHER_ADDR_FMT_SIZE, 1878 addr); 1879 hns3_err(hw, "failed to set mc mac addr, " 1880 "addrs invalid. two same addrs(%s).", 1881 mac_str); 1882 return -EINVAL; 1883 } 1884 } 1885 1886 /* 1887 * Check if there are duplicate addresses between mac_addrs 1888 * and mc_addr_set 1889 */ 1890 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) { 1891 if (rte_is_same_ether_addr(addr, 1892 &hw->data->mac_addrs[j])) { 1893 rte_ether_format_addr(mac_str, 1894 RTE_ETHER_ADDR_FMT_SIZE, 1895 addr); 1896 hns3_err(hw, "failed to set mc mac addr, " 1897 "addrs invalid. addrs(%s) has already " 1898 "configured in mac_addr add API", 1899 mac_str); 1900 return -EINVAL; 1901 } 1902 } 1903 } 1904 1905 return 0; 1906 } 1907 1908 static void 1909 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw, 1910 struct rte_ether_addr *mc_addr_set, 1911 int mc_addr_num, 1912 struct rte_ether_addr *reserved_addr_list, 1913 int *reserved_addr_num, 1914 struct rte_ether_addr *add_addr_list, 1915 int *add_addr_num, 1916 struct rte_ether_addr *rm_addr_list, 1917 int *rm_addr_num) 1918 { 1919 struct rte_ether_addr *addr; 1920 int current_addr_num; 1921 int reserved_num = 0; 1922 int add_num = 0; 1923 int rm_num = 0; 1924 int num; 1925 int i; 1926 int j; 1927 bool same_addr; 1928 1929 /* Calculate the mc mac address list that should be removed */ 1930 current_addr_num = hw->mc_addrs_num; 1931 for (i = 0; i < current_addr_num; i++) { 1932 addr = &hw->mc_addrs[i]; 1933 same_addr = false; 1934 for (j = 0; j < mc_addr_num; j++) { 1935 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 1936 same_addr = true; 1937 break; 1938 } 1939 } 1940 1941 if (!same_addr) { 1942 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]); 1943 rm_num++; 1944 } else { 1945 rte_ether_addr_copy(addr, 1946 &reserved_addr_list[reserved_num]); 1947 reserved_num++; 1948 } 1949 } 1950 1951 /* Calculate the mc mac address list that should be added */ 1952 for (i = 0; i < mc_addr_num; i++) { 1953 addr = &mc_addr_set[i]; 1954 same_addr = false; 1955 for (j = 0; j < current_addr_num; j++) { 1956 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) { 1957 same_addr = true; 1958 break; 1959 } 1960 } 1961 1962 if (!same_addr) { 1963 rte_ether_addr_copy(addr, &add_addr_list[add_num]); 1964 add_num++; 1965 } 1966 } 1967 1968 /* Reorder the mc mac address list maintained by driver */ 1969 for (i = 0; i < reserved_num; i++) 1970 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]); 1971 1972 for (i = 0; i < rm_num; i++) { 1973 num = reserved_num + i; 1974 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]); 1975 } 1976 1977 *reserved_addr_num = reserved_num; 1978 *add_addr_num = add_num; 1979 *rm_addr_num = rm_num; 1980 } 1981 1982 static int 1983 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, 1984 struct rte_ether_addr *mc_addr_set, 1985 uint32_t nb_mc_addr) 1986 { 1987 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1988 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM]; 1989 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM]; 1990 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM]; 1991 struct rte_ether_addr *addr; 1992 int reserved_addr_num; 1993 int add_addr_num; 1994 int rm_addr_num; 1995 int mc_addr_num; 1996 int num; 1997 int ret; 1998 int i; 1999 2000 /* Check if input parameters are valid */ 2001 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 2002 if (ret) 2003 return ret; 2004 2005 rte_spinlock_lock(&hw->lock); 2006 2007 /* 2008 * Calculate the mc mac address lists those should be removed and be 2009 * added, Reorder the mc mac address list maintained by driver. 2010 */ 2011 mc_addr_num = (int)nb_mc_addr; 2012 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num, 2013 reserved_addr_list, &reserved_addr_num, 2014 add_addr_list, &add_addr_num, 2015 rm_addr_list, &rm_addr_num); 2016 2017 /* Remove mc mac addresses */ 2018 for (i = 0; i < rm_addr_num; i++) { 2019 num = rm_addr_num - i - 1; 2020 addr = &rm_addr_list[num]; 2021 ret = hns3_remove_mc_addr(hw, addr); 2022 if (ret) { 2023 rte_spinlock_unlock(&hw->lock); 2024 return ret; 2025 } 2026 hw->mc_addrs_num--; 2027 } 2028 2029 /* Add mc mac addresses */ 2030 for (i = 0; i < add_addr_num; i++) { 2031 addr = &add_addr_list[i]; 2032 ret = hns3_add_mc_addr(hw, addr); 2033 if (ret) { 2034 rte_spinlock_unlock(&hw->lock); 2035 return ret; 2036 } 2037 2038 num = reserved_addr_num + i; 2039 rte_ether_addr_copy(addr, &hw->mc_addrs[num]); 2040 hw->mc_addrs_num++; 2041 } 2042 rte_spinlock_unlock(&hw->lock); 2043 2044 return 0; 2045 } 2046 2047 static int 2048 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 2049 { 2050 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2051 struct hns3_hw *hw = &hns->hw; 2052 struct rte_ether_addr *addr; 2053 int err = 0; 2054 int ret; 2055 int i; 2056 2057 for (i = 0; i < hw->mc_addrs_num; i++) { 2058 addr = &hw->mc_addrs[i]; 2059 if (!rte_is_multicast_ether_addr(addr)) 2060 continue; 2061 if (del) 2062 ret = hns3_remove_mc_addr(hw, addr); 2063 else 2064 ret = hns3_add_mc_addr(hw, addr); 2065 if (ret) { 2066 err = ret; 2067 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2068 addr); 2069 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d", 2070 del ? "Remove" : "Restore", mac_str, ret); 2071 } 2072 } 2073 return err; 2074 } 2075 2076 static int 2077 hns3_check_mq_mode(struct rte_eth_dev *dev) 2078 { 2079 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 2080 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 2081 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2082 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2083 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 2084 struct rte_eth_dcb_tx_conf *dcb_tx_conf; 2085 uint8_t num_tc; 2086 int max_tc = 0; 2087 int i; 2088 2089 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 2090 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf; 2091 2092 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2093 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. " 2094 "rx_mq_mode = %d", rx_mq_mode); 2095 return -EINVAL; 2096 } 2097 2098 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB || 2099 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2100 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB " 2101 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d", 2102 rx_mq_mode, tx_mq_mode); 2103 return -EINVAL; 2104 } 2105 2106 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) { 2107 if (dcb_rx_conf->nb_tcs > pf->tc_max) { 2108 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.", 2109 dcb_rx_conf->nb_tcs, pf->tc_max); 2110 return -EINVAL; 2111 } 2112 2113 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS || 2114 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) { 2115 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, " 2116 "nb_tcs(%d) != %d or %d in rx direction.", 2117 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS); 2118 return -EINVAL; 2119 } 2120 2121 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) { 2122 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)", 2123 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs); 2124 return -EINVAL; 2125 } 2126 2127 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) { 2128 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) { 2129 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, " 2130 "is not equal to one in tx direction.", 2131 i, dcb_rx_conf->dcb_tc[i]); 2132 return -EINVAL; 2133 } 2134 if (dcb_rx_conf->dcb_tc[i] > max_tc) 2135 max_tc = dcb_rx_conf->dcb_tc[i]; 2136 } 2137 2138 num_tc = max_tc + 1; 2139 if (num_tc > dcb_rx_conf->nb_tcs) { 2140 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)", 2141 num_tc, dcb_rx_conf->nb_tcs); 2142 return -EINVAL; 2143 } 2144 } 2145 2146 return 0; 2147 } 2148 2149 static int 2150 hns3_check_dcb_cfg(struct rte_eth_dev *dev) 2151 { 2152 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2153 2154 if (!hns3_dev_dcb_supported(hw)) { 2155 hns3_err(hw, "this port does not support dcb configurations."); 2156 return -EOPNOTSUPP; 2157 } 2158 2159 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { 2160 hns3_err(hw, "MAC pause enabled, cannot config dcb info."); 2161 return -EOPNOTSUPP; 2162 } 2163 2164 /* Check multiple queue mode */ 2165 return hns3_check_mq_mode(dev); 2166 } 2167 2168 static int 2169 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap, 2170 enum hns3_ring_type queue_type, uint16_t queue_id) 2171 { 2172 struct hns3_cmd_desc desc; 2173 struct hns3_ctrl_vector_chain_cmd *req = 2174 (struct hns3_ctrl_vector_chain_cmd *)desc.data; 2175 enum hns3_cmd_status status; 2176 enum hns3_opcode_type op; 2177 uint16_t tqp_type_and_id = 0; 2178 const char *op_str; 2179 uint16_t type; 2180 uint16_t gl; 2181 2182 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR; 2183 hns3_cmd_setup_basic_desc(&desc, op, false); 2184 req->int_vector_id = vector_id; 2185 2186 if (queue_type == HNS3_RING_TYPE_RX) 2187 gl = HNS3_RING_GL_RX; 2188 else 2189 gl = HNS3_RING_GL_TX; 2190 2191 type = queue_type; 2192 2193 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S, 2194 type); 2195 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id); 2196 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S, 2197 gl); 2198 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id); 2199 req->int_cause_num = 1; 2200 op_str = mmap ? "Map" : "Unmap"; 2201 status = hns3_cmd_send(hw, &desc, 1); 2202 if (status) { 2203 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.", 2204 op_str, queue_id, req->int_vector_id, status); 2205 return status; 2206 } 2207 2208 return 0; 2209 } 2210 2211 static int 2212 hns3_init_ring_with_vector(struct hns3_hw *hw) 2213 { 2214 uint8_t vec; 2215 int ret; 2216 int i; 2217 2218 /* 2219 * In hns3 network engine, vector 0 is always the misc interrupt of this 2220 * function, vector 1~N can be used respectively for the queues of the 2221 * function. Tx and Rx queues with the same number share the interrupt 2222 * vector. In the initialization clearing the all hardware mapping 2223 * relationship configurations between queues and interrupt vectors is 2224 * needed, so some error caused by the residual configurations, such as 2225 * the unexpected Tx interrupt, can be avoid. Because of the hardware 2226 * constraints in hns3 hardware engine, we have to implement clearing 2227 * the mapping relationship configurations by binding all queues to the 2228 * last interrupt vector and reserving the last interrupt vector. This 2229 * method results in a decrease of the maximum queues when upper 2230 * applications call the rte_eth_dev_configure API function to enable 2231 * Rx interrupt. 2232 */ 2233 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 2234 /* vec - 1: the last interrupt is reserved */ 2235 hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1; 2236 for (i = 0; i < hw->intr_tqps_num; i++) { 2237 /* 2238 * Set gap limiter and rate limiter configuration of queue's 2239 * interrupt. 2240 */ 2241 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 2242 HNS3_TQP_INTR_GL_DEFAULT); 2243 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 2244 HNS3_TQP_INTR_GL_DEFAULT); 2245 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 2246 2247 ret = hns3_bind_ring_with_vector(hw, vec, false, 2248 HNS3_RING_TYPE_TX, i); 2249 if (ret) { 2250 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with " 2251 "vector: %d, ret=%d", i, vec, ret); 2252 return ret; 2253 } 2254 2255 ret = hns3_bind_ring_with_vector(hw, vec, false, 2256 HNS3_RING_TYPE_RX, i); 2257 if (ret) { 2258 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with " 2259 "vector: %d, ret=%d", i, vec, ret); 2260 return ret; 2261 } 2262 } 2263 2264 return 0; 2265 } 2266 2267 static int 2268 hns3_dev_configure(struct rte_eth_dev *dev) 2269 { 2270 struct hns3_adapter *hns = dev->data->dev_private; 2271 struct rte_eth_conf *conf = &dev->data->dev_conf; 2272 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 2273 struct hns3_hw *hw = &hns->hw; 2274 struct hns3_rss_conf *rss_cfg = &hw->rss_info; 2275 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2276 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2277 struct rte_eth_rss_conf rss_conf; 2278 uint16_t mtu; 2279 int ret; 2280 2281 /* 2282 * Hardware does not support individually enable/disable/reset the Tx or 2283 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx 2284 * and Rx queues at the same time. When the numbers of Tx queues 2285 * allocated by upper applications are not equal to the numbers of Rx 2286 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers 2287 * of Tx/Rx queues. otherwise, network engine can not work as usual. But 2288 * these fake queues are imperceptible, and can not be used by upper 2289 * applications. 2290 */ 2291 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 2292 if (ret) { 2293 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret); 2294 return ret; 2295 } 2296 2297 hw->adapter_state = HNS3_NIC_CONFIGURING; 2298 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 2299 hns3_err(hw, "setting link speed/duplex not supported"); 2300 ret = -EINVAL; 2301 goto cfg_err; 2302 } 2303 2304 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) { 2305 ret = hns3_check_dcb_cfg(dev); 2306 if (ret) 2307 goto cfg_err; 2308 } 2309 2310 /* When RSS is not configured, redirect the packet queue 0 */ 2311 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 2312 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2313 rss_conf = conf->rx_adv_conf.rss_conf; 2314 if (rss_conf.rss_key == NULL) { 2315 rss_conf.rss_key = rss_cfg->key; 2316 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE; 2317 } 2318 2319 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 2320 if (ret) 2321 goto cfg_err; 2322 } 2323 2324 /* 2325 * If jumbo frames are enabled, MTU needs to be refreshed 2326 * according to the maximum RX packet length. 2327 */ 2328 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 2329 /* 2330 * Security of max_rx_pkt_len is guaranteed in dpdk frame. 2331 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it 2332 * can safely assign to "uint16_t" type variable. 2333 */ 2334 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len); 2335 ret = hns3_dev_mtu_set(dev, mtu); 2336 if (ret) 2337 goto cfg_err; 2338 dev->data->mtu = mtu; 2339 } 2340 2341 ret = hns3_dev_configure_vlan(dev); 2342 if (ret) 2343 goto cfg_err; 2344 2345 hw->adapter_state = HNS3_NIC_CONFIGURED; 2346 2347 return 0; 2348 2349 cfg_err: 2350 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 2351 hw->adapter_state = HNS3_NIC_INITIALIZED; 2352 2353 return ret; 2354 } 2355 2356 static int 2357 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps) 2358 { 2359 struct hns3_config_max_frm_size_cmd *req; 2360 struct hns3_cmd_desc desc; 2361 2362 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false); 2363 2364 req = (struct hns3_config_max_frm_size_cmd *)desc.data; 2365 req->max_frm_size = rte_cpu_to_le_16(new_mps); 2366 req->min_frm_size = RTE_ETHER_MIN_LEN; 2367 2368 return hns3_cmd_send(hw, &desc, 1); 2369 } 2370 2371 static int 2372 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps) 2373 { 2374 int ret; 2375 2376 ret = hns3_set_mac_mtu(hw, mps); 2377 if (ret) { 2378 hns3_err(hw, "Failed to set mtu, ret = %d", ret); 2379 return ret; 2380 } 2381 2382 ret = hns3_buffer_alloc(hw); 2383 if (ret) 2384 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret); 2385 2386 return ret; 2387 } 2388 2389 static int 2390 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2391 { 2392 struct hns3_adapter *hns = dev->data->dev_private; 2393 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 2394 struct hns3_hw *hw = &hns->hw; 2395 bool is_jumbo_frame; 2396 int ret; 2397 2398 if (dev->data->dev_started) { 2399 hns3_err(hw, "Failed to set mtu, port %u must be stopped " 2400 "before configuration", dev->data->port_id); 2401 return -EBUSY; 2402 } 2403 2404 rte_spinlock_lock(&hw->lock); 2405 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false; 2406 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN); 2407 2408 /* 2409 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely 2410 * assign to "uint16_t" type variable. 2411 */ 2412 ret = hns3_config_mtu(hw, (uint16_t)frame_size); 2413 if (ret) { 2414 rte_spinlock_unlock(&hw->lock); 2415 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d", 2416 dev->data->port_id, mtu, ret); 2417 return ret; 2418 } 2419 hns->pf.mps = (uint16_t)frame_size; 2420 if (is_jumbo_frame) 2421 dev->data->dev_conf.rxmode.offloads |= 2422 DEV_RX_OFFLOAD_JUMBO_FRAME; 2423 else 2424 dev->data->dev_conf.rxmode.offloads &= 2425 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2426 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2427 rte_spinlock_unlock(&hw->lock); 2428 2429 return 0; 2430 } 2431 2432 static int 2433 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 2434 { 2435 struct hns3_adapter *hns = eth_dev->data->dev_private; 2436 struct hns3_hw *hw = &hns->hw; 2437 uint16_t queue_num = hw->tqps_num; 2438 2439 /* 2440 * In interrupt mode, 'max_rx_queues' is set based on the number of 2441 * MSI-X interrupt resources of the hardware. 2442 */ 2443 if (hw->data->dev_conf.intr_conf.rxq == 1) 2444 queue_num = hw->intr_tqps_num; 2445 2446 info->max_rx_queues = queue_num; 2447 info->max_tx_queues = hw->tqps_num; 2448 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 2449 info->min_rx_bufsize = hw->rx_buf_len; 2450 info->max_mac_addrs = HNS3_UC_MACADDR_NUM; 2451 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 2452 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 2453 DEV_RX_OFFLOAD_TCP_CKSUM | 2454 DEV_RX_OFFLOAD_UDP_CKSUM | 2455 DEV_RX_OFFLOAD_SCTP_CKSUM | 2456 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2457 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 2458 DEV_RX_OFFLOAD_KEEP_CRC | 2459 DEV_RX_OFFLOAD_SCATTER | 2460 DEV_RX_OFFLOAD_VLAN_STRIP | 2461 DEV_RX_OFFLOAD_VLAN_FILTER | 2462 DEV_RX_OFFLOAD_JUMBO_FRAME | 2463 DEV_RX_OFFLOAD_RSS_HASH); 2464 info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 2465 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2466 DEV_TX_OFFLOAD_IPV4_CKSUM | 2467 DEV_TX_OFFLOAD_TCP_CKSUM | 2468 DEV_TX_OFFLOAD_UDP_CKSUM | 2469 DEV_TX_OFFLOAD_SCTP_CKSUM | 2470 DEV_TX_OFFLOAD_VLAN_INSERT | 2471 DEV_TX_OFFLOAD_QINQ_INSERT | 2472 DEV_TX_OFFLOAD_MULTI_SEGS | 2473 DEV_TX_OFFLOAD_TCP_TSO | 2474 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 2475 DEV_TX_OFFLOAD_GRE_TNL_TSO | 2476 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 2477 info->tx_queue_offload_capa); 2478 2479 info->rx_desc_lim = (struct rte_eth_desc_lim) { 2480 .nb_max = HNS3_MAX_RING_DESC, 2481 .nb_min = HNS3_MIN_RING_DESC, 2482 .nb_align = HNS3_ALIGN_RING_DESC, 2483 }; 2484 2485 info->tx_desc_lim = (struct rte_eth_desc_lim) { 2486 .nb_max = HNS3_MAX_RING_DESC, 2487 .nb_min = HNS3_MIN_RING_DESC, 2488 .nb_align = HNS3_ALIGN_RING_DESC, 2489 }; 2490 2491 info->vmdq_queue_num = 0; 2492 2493 info->reta_size = HNS3_RSS_IND_TBL_SIZE; 2494 info->hash_key_size = HNS3_RSS_KEY_SIZE; 2495 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 2496 2497 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2498 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2499 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2500 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2501 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2502 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2503 2504 return 0; 2505 } 2506 2507 static int 2508 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2509 size_t fw_size) 2510 { 2511 struct hns3_adapter *hns = eth_dev->data->dev_private; 2512 struct hns3_hw *hw = &hns->hw; 2513 uint32_t version = hw->fw_version; 2514 int ret; 2515 2516 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2517 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2518 HNS3_FW_VERSION_BYTE3_S), 2519 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2520 HNS3_FW_VERSION_BYTE2_S), 2521 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2522 HNS3_FW_VERSION_BYTE1_S), 2523 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2524 HNS3_FW_VERSION_BYTE0_S)); 2525 ret += 1; /* add the size of '\0' */ 2526 if (fw_size < (uint32_t)ret) 2527 return ret; 2528 else 2529 return 0; 2530 } 2531 2532 static int 2533 hns3_dev_link_update(struct rte_eth_dev *eth_dev, 2534 __rte_unused int wait_to_complete) 2535 { 2536 struct hns3_adapter *hns = eth_dev->data->dev_private; 2537 struct hns3_hw *hw = &hns->hw; 2538 struct hns3_mac *mac = &hw->mac; 2539 struct rte_eth_link new_link; 2540 2541 if (!hns3_is_reset_pending(hns)) { 2542 hns3_update_speed_duplex(eth_dev); 2543 hns3_update_link_status(hw); 2544 } 2545 2546 memset(&new_link, 0, sizeof(new_link)); 2547 switch (mac->link_speed) { 2548 case ETH_SPEED_NUM_10M: 2549 case ETH_SPEED_NUM_100M: 2550 case ETH_SPEED_NUM_1G: 2551 case ETH_SPEED_NUM_10G: 2552 case ETH_SPEED_NUM_25G: 2553 case ETH_SPEED_NUM_40G: 2554 case ETH_SPEED_NUM_50G: 2555 case ETH_SPEED_NUM_100G: 2556 new_link.link_speed = mac->link_speed; 2557 break; 2558 default: 2559 new_link.link_speed = ETH_SPEED_NUM_100M; 2560 break; 2561 } 2562 2563 new_link.link_duplex = mac->link_duplex; 2564 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2565 new_link.link_autoneg = 2566 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); 2567 2568 return rte_eth_linkstatus_set(eth_dev, &new_link); 2569 } 2570 2571 static int 2572 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status) 2573 { 2574 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2575 struct hns3_pf *pf = &hns->pf; 2576 2577 if (!(status->pf_state & HNS3_PF_STATE_DONE)) 2578 return -EINVAL; 2579 2580 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false; 2581 2582 return 0; 2583 } 2584 2585 static int 2586 hns3_query_function_status(struct hns3_hw *hw) 2587 { 2588 #define HNS3_QUERY_MAX_CNT 10 2589 #define HNS3_QUERY_SLEEP_MSCOEND 1 2590 struct hns3_func_status_cmd *req; 2591 struct hns3_cmd_desc desc; 2592 int timeout = 0; 2593 int ret; 2594 2595 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true); 2596 req = (struct hns3_func_status_cmd *)desc.data; 2597 2598 do { 2599 ret = hns3_cmd_send(hw, &desc, 1); 2600 if (ret) { 2601 PMD_INIT_LOG(ERR, "query function status failed %d", 2602 ret); 2603 return ret; 2604 } 2605 2606 /* Check pf reset is done */ 2607 if (req->pf_state) 2608 break; 2609 2610 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND); 2611 } while (timeout++ < HNS3_QUERY_MAX_CNT); 2612 2613 return hns3_parse_func_status(hw, req); 2614 } 2615 2616 static int 2617 hns3_query_pf_resource(struct hns3_hw *hw) 2618 { 2619 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2620 struct hns3_pf *pf = &hns->pf; 2621 struct hns3_pf_res_cmd *req; 2622 struct hns3_cmd_desc desc; 2623 int ret; 2624 2625 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true); 2626 ret = hns3_cmd_send(hw, &desc, 1); 2627 if (ret) { 2628 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret); 2629 return ret; 2630 } 2631 2632 req = (struct hns3_pf_res_cmd *)desc.data; 2633 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num); 2634 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S; 2635 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC); 2636 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number); 2637 2638 if (req->tx_buf_size) 2639 pf->tx_buf_size = 2640 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S; 2641 else 2642 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF; 2643 2644 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT); 2645 2646 if (req->dv_buf_size) 2647 pf->dv_buf_size = 2648 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S; 2649 else 2650 pf->dv_buf_size = HNS3_DEFAULT_DV; 2651 2652 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT); 2653 2654 hw->num_msi = 2655 hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number), 2656 HNS3_VEC_NUM_M, HNS3_VEC_NUM_S); 2657 2658 return 0; 2659 } 2660 2661 static void 2662 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) 2663 { 2664 struct hns3_cfg_param_cmd *req; 2665 uint64_t mac_addr_tmp_high; 2666 uint64_t mac_addr_tmp; 2667 uint32_t i; 2668 2669 req = (struct hns3_cfg_param_cmd *)desc[0].data; 2670 2671 /* get the configuration */ 2672 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2673 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S); 2674 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2675 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S); 2676 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2677 HNS3_CFG_TQP_DESC_N_M, 2678 HNS3_CFG_TQP_DESC_N_S); 2679 2680 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2681 HNS3_CFG_PHY_ADDR_M, 2682 HNS3_CFG_PHY_ADDR_S); 2683 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2684 HNS3_CFG_MEDIA_TP_M, 2685 HNS3_CFG_MEDIA_TP_S); 2686 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2687 HNS3_CFG_RX_BUF_LEN_M, 2688 HNS3_CFG_RX_BUF_LEN_S); 2689 /* get mac address */ 2690 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]); 2691 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2692 HNS3_CFG_MAC_ADDR_H_M, 2693 HNS3_CFG_MAC_ADDR_H_S); 2694 2695 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 2696 2697 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2698 HNS3_CFG_DEFAULT_SPEED_M, 2699 HNS3_CFG_DEFAULT_SPEED_S); 2700 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2701 HNS3_CFG_RSS_SIZE_M, 2702 HNS3_CFG_RSS_SIZE_S); 2703 2704 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 2705 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 2706 2707 req = (struct hns3_cfg_param_cmd *)desc[1].data; 2708 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]); 2709 2710 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2711 HNS3_CFG_SPEED_ABILITY_M, 2712 HNS3_CFG_SPEED_ABILITY_S); 2713 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2714 HNS3_CFG_UMV_TBL_SPACE_M, 2715 HNS3_CFG_UMV_TBL_SPACE_S); 2716 if (!cfg->umv_space) 2717 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF; 2718 } 2719 2720 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash 2721 * @hw: pointer to struct hns3_hw 2722 * @hcfg: the config structure to be getted 2723 */ 2724 static int 2725 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg) 2726 { 2727 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM]; 2728 struct hns3_cfg_param_cmd *req; 2729 uint32_t offset; 2730 uint32_t i; 2731 int ret; 2732 2733 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) { 2734 offset = 0; 2735 req = (struct hns3_cfg_param_cmd *)desc[i].data; 2736 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM, 2737 true); 2738 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S, 2739 i * HNS3_CFG_RD_LEN_BYTES); 2740 /* Len should be divided by 4 when send to hardware */ 2741 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S, 2742 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT); 2743 req->offset = rte_cpu_to_le_32(offset); 2744 } 2745 2746 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM); 2747 if (ret) { 2748 PMD_INIT_LOG(ERR, "get config failed %d.", ret); 2749 return ret; 2750 } 2751 2752 hns3_parse_cfg(hcfg, desc); 2753 2754 return 0; 2755 } 2756 2757 static int 2758 hns3_parse_speed(int speed_cmd, uint32_t *speed) 2759 { 2760 switch (speed_cmd) { 2761 case HNS3_CFG_SPEED_10M: 2762 *speed = ETH_SPEED_NUM_10M; 2763 break; 2764 case HNS3_CFG_SPEED_100M: 2765 *speed = ETH_SPEED_NUM_100M; 2766 break; 2767 case HNS3_CFG_SPEED_1G: 2768 *speed = ETH_SPEED_NUM_1G; 2769 break; 2770 case HNS3_CFG_SPEED_10G: 2771 *speed = ETH_SPEED_NUM_10G; 2772 break; 2773 case HNS3_CFG_SPEED_25G: 2774 *speed = ETH_SPEED_NUM_25G; 2775 break; 2776 case HNS3_CFG_SPEED_40G: 2777 *speed = ETH_SPEED_NUM_40G; 2778 break; 2779 case HNS3_CFG_SPEED_50G: 2780 *speed = ETH_SPEED_NUM_50G; 2781 break; 2782 case HNS3_CFG_SPEED_100G: 2783 *speed = ETH_SPEED_NUM_100G; 2784 break; 2785 default: 2786 return -EINVAL; 2787 } 2788 2789 return 0; 2790 } 2791 2792 static int 2793 hns3_get_board_configuration(struct hns3_hw *hw) 2794 { 2795 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2796 struct hns3_pf *pf = &hns->pf; 2797 struct hns3_cfg cfg; 2798 int ret; 2799 2800 ret = hns3_get_board_cfg(hw, &cfg); 2801 if (ret) { 2802 PMD_INIT_LOG(ERR, "get board config failed %d", ret); 2803 return ret; 2804 } 2805 2806 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) { 2807 PMD_INIT_LOG(ERR, "media type is copper, not supported."); 2808 return -EOPNOTSUPP; 2809 } 2810 2811 hw->mac.media_type = cfg.media_type; 2812 hw->rss_size_max = cfg.rss_size_max; 2813 hw->rss_dis_flag = false; 2814 hw->rx_buf_len = cfg.rx_buf_len; 2815 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN); 2816 hw->mac.phy_addr = cfg.phy_addr; 2817 hw->mac.default_addr_setted = false; 2818 hw->num_tx_desc = cfg.tqp_desc_num; 2819 hw->num_rx_desc = cfg.tqp_desc_num; 2820 hw->dcb_info.num_pg = 1; 2821 hw->dcb_info.hw_pfc_map = 0; 2822 2823 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed); 2824 if (ret) { 2825 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d", 2826 cfg.default_speed, ret); 2827 return ret; 2828 } 2829 2830 pf->tc_max = cfg.tc_num; 2831 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) { 2832 PMD_INIT_LOG(WARNING, 2833 "Get TC num(%u) from flash, set TC num to 1", 2834 pf->tc_max); 2835 pf->tc_max = 1; 2836 } 2837 2838 /* Dev does not support DCB */ 2839 if (!hns3_dev_dcb_supported(hw)) { 2840 pf->tc_max = 1; 2841 pf->pfc_max = 0; 2842 } else 2843 pf->pfc_max = pf->tc_max; 2844 2845 hw->dcb_info.num_tc = 1; 2846 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, 2847 hw->tqps_num / hw->dcb_info.num_tc); 2848 hns3_set_bit(hw->hw_tc_map, 0, 1); 2849 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE; 2850 2851 pf->wanted_umv_size = cfg.umv_space; 2852 2853 return ret; 2854 } 2855 2856 static int 2857 hns3_get_configuration(struct hns3_hw *hw) 2858 { 2859 int ret; 2860 2861 ret = hns3_query_function_status(hw); 2862 if (ret) { 2863 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret); 2864 return ret; 2865 } 2866 2867 /* Get pf resource */ 2868 ret = hns3_query_pf_resource(hw); 2869 if (ret) { 2870 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret); 2871 return ret; 2872 } 2873 2874 ret = hns3_get_board_configuration(hw); 2875 if (ret) 2876 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret); 2877 2878 return ret; 2879 } 2880 2881 static int 2882 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid, 2883 uint16_t tqp_vid, bool is_pf) 2884 { 2885 struct hns3_tqp_map_cmd *req; 2886 struct hns3_cmd_desc desc; 2887 int ret; 2888 2889 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false); 2890 2891 req = (struct hns3_tqp_map_cmd *)desc.data; 2892 req->tqp_id = rte_cpu_to_le_16(tqp_pid); 2893 req->tqp_vf = func_id; 2894 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B; 2895 if (!is_pf) 2896 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B); 2897 req->tqp_vid = rte_cpu_to_le_16(tqp_vid); 2898 2899 ret = hns3_cmd_send(hw, &desc, 1); 2900 if (ret) 2901 PMD_INIT_LOG(ERR, "TQP map failed %d", ret); 2902 2903 return ret; 2904 } 2905 2906 static int 2907 hns3_map_tqp(struct hns3_hw *hw) 2908 { 2909 uint16_t tqps_num = hw->total_tqps_num; 2910 uint16_t func_id; 2911 uint16_t tqp_id; 2912 bool is_pf; 2913 int num; 2914 int ret; 2915 int i; 2916 2917 /* 2918 * In current version VF is not supported when PF is driven by DPDK 2919 * driver, so we allocate tqps to PF as much as possible. 2920 */ 2921 tqp_id = 0; 2922 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC); 2923 for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) { 2924 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false; 2925 for (i = 0; 2926 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) { 2927 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i, 2928 is_pf); 2929 if (ret) 2930 return ret; 2931 } 2932 } 2933 2934 return 0; 2935 } 2936 2937 static int 2938 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 2939 { 2940 struct hns3_config_mac_speed_dup_cmd *req; 2941 struct hns3_cmd_desc desc; 2942 int ret; 2943 2944 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data; 2945 2946 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false); 2947 2948 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0); 2949 2950 switch (speed) { 2951 case ETH_SPEED_NUM_10M: 2952 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2953 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M); 2954 break; 2955 case ETH_SPEED_NUM_100M: 2956 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2957 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M); 2958 break; 2959 case ETH_SPEED_NUM_1G: 2960 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2961 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G); 2962 break; 2963 case ETH_SPEED_NUM_10G: 2964 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2965 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G); 2966 break; 2967 case ETH_SPEED_NUM_25G: 2968 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2969 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G); 2970 break; 2971 case ETH_SPEED_NUM_40G: 2972 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2973 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G); 2974 break; 2975 case ETH_SPEED_NUM_50G: 2976 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2977 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G); 2978 break; 2979 case ETH_SPEED_NUM_100G: 2980 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 2981 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G); 2982 break; 2983 default: 2984 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed); 2985 return -EINVAL; 2986 } 2987 2988 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); 2989 2990 ret = hns3_cmd_send(hw, &desc, 1); 2991 if (ret) 2992 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret); 2993 2994 return ret; 2995 } 2996 2997 static int 2998 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 2999 { 3000 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3001 struct hns3_pf *pf = &hns->pf; 3002 struct hns3_priv_buf *priv; 3003 uint32_t i, total_size; 3004 3005 total_size = pf->pkt_buf_size; 3006 3007 /* alloc tx buffer for all enabled tc */ 3008 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3009 priv = &buf_alloc->priv_buf[i]; 3010 3011 if (hw->hw_tc_map & BIT(i)) { 3012 if (total_size < pf->tx_buf_size) 3013 return -ENOMEM; 3014 3015 priv->tx_buf_size = pf->tx_buf_size; 3016 } else 3017 priv->tx_buf_size = 0; 3018 3019 total_size -= priv->tx_buf_size; 3020 } 3021 3022 return 0; 3023 } 3024 3025 static int 3026 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3027 { 3028 /* TX buffer size is unit by 128 byte */ 3029 #define HNS3_BUF_SIZE_UNIT_SHIFT 7 3030 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15) 3031 struct hns3_tx_buff_alloc_cmd *req; 3032 struct hns3_cmd_desc desc; 3033 uint32_t buf_size; 3034 uint32_t i; 3035 int ret; 3036 3037 req = (struct hns3_tx_buff_alloc_cmd *)desc.data; 3038 3039 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0); 3040 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3041 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 3042 3043 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT; 3044 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size | 3045 HNS3_BUF_SIZE_UPDATE_EN_MSK); 3046 } 3047 3048 ret = hns3_cmd_send(hw, &desc, 1); 3049 if (ret) 3050 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret); 3051 3052 return ret; 3053 } 3054 3055 static int 3056 hns3_get_tc_num(struct hns3_hw *hw) 3057 { 3058 int cnt = 0; 3059 uint8_t i; 3060 3061 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3062 if (hw->hw_tc_map & BIT(i)) 3063 cnt++; 3064 return cnt; 3065 } 3066 3067 static uint32_t 3068 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3069 { 3070 struct hns3_priv_buf *priv; 3071 uint32_t rx_priv = 0; 3072 int i; 3073 3074 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3075 priv = &buf_alloc->priv_buf[i]; 3076 if (priv->enable) 3077 rx_priv += priv->buf_size; 3078 } 3079 return rx_priv; 3080 } 3081 3082 static uint32_t 3083 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3084 { 3085 uint32_t total_tx_size = 0; 3086 uint32_t i; 3087 3088 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3089 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 3090 3091 return total_tx_size; 3092 } 3093 3094 /* Get the number of pfc enabled TCs, which have private buffer */ 3095 static int 3096 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3097 { 3098 struct hns3_priv_buf *priv; 3099 int cnt = 0; 3100 uint8_t i; 3101 3102 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3103 priv = &buf_alloc->priv_buf[i]; 3104 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3105 cnt++; 3106 } 3107 3108 return cnt; 3109 } 3110 3111 /* Get the number of pfc disabled TCs, which have private buffer */ 3112 static int 3113 hns3_get_no_pfc_priv_num(struct hns3_hw *hw, 3114 struct hns3_pkt_buf_alloc *buf_alloc) 3115 { 3116 struct hns3_priv_buf *priv; 3117 int cnt = 0; 3118 uint8_t i; 3119 3120 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3121 priv = &buf_alloc->priv_buf[i]; 3122 if (hw->hw_tc_map & BIT(i) && 3123 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3124 cnt++; 3125 } 3126 3127 return cnt; 3128 } 3129 3130 static bool 3131 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, 3132 uint32_t rx_all) 3133 { 3134 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 3135 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3136 struct hns3_pf *pf = &hns->pf; 3137 uint32_t shared_buf, aligned_mps; 3138 uint32_t rx_priv; 3139 uint8_t tc_num; 3140 uint8_t i; 3141 3142 tc_num = hns3_get_tc_num(hw); 3143 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3144 3145 if (hns3_dev_dcb_supported(hw)) 3146 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps + 3147 pf->dv_buf_size; 3148 else 3149 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF 3150 + pf->dv_buf_size; 3151 3152 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 3153 shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc), 3154 HNS3_BUF_SIZE_UNIT); 3155 3156 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc); 3157 if (rx_all < rx_priv + shared_std) 3158 return false; 3159 3160 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT); 3161 buf_alloc->s_buf.buf_size = shared_buf; 3162 if (hns3_dev_dcb_supported(hw)) { 3163 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size; 3164 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 3165 - roundup(aligned_mps / HNS3_BUF_DIV_BY, 3166 HNS3_BUF_SIZE_UNIT); 3167 } else { 3168 buf_alloc->s_buf.self.high = 3169 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3170 buf_alloc->s_buf.self.low = aligned_mps; 3171 } 3172 3173 if (hns3_dev_dcb_supported(hw)) { 3174 hi_thrd = shared_buf - pf->dv_buf_size; 3175 3176 if (tc_num <= NEED_RESERVE_TC_NUM) 3177 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 3178 / BUF_MAX_PERCENT; 3179 3180 if (tc_num) 3181 hi_thrd = hi_thrd / tc_num; 3182 3183 hi_thrd = max_t(uint32_t, hi_thrd, 3184 HNS3_BUF_MUL_BY * aligned_mps); 3185 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT); 3186 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY; 3187 } else { 3188 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3189 lo_thrd = aligned_mps; 3190 } 3191 3192 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3193 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 3194 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 3195 } 3196 3197 return true; 3198 } 3199 3200 static bool 3201 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max, 3202 struct hns3_pkt_buf_alloc *buf_alloc) 3203 { 3204 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3205 struct hns3_pf *pf = &hns->pf; 3206 struct hns3_priv_buf *priv; 3207 uint32_t aligned_mps; 3208 uint32_t rx_all; 3209 uint8_t i; 3210 3211 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3212 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3213 3214 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3215 priv = &buf_alloc->priv_buf[i]; 3216 3217 priv->enable = 0; 3218 priv->wl.low = 0; 3219 priv->wl.high = 0; 3220 priv->buf_size = 0; 3221 3222 if (!(hw->hw_tc_map & BIT(i))) 3223 continue; 3224 3225 priv->enable = 1; 3226 if (hw->dcb_info.hw_pfc_map & BIT(i)) { 3227 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT; 3228 priv->wl.high = roundup(priv->wl.low + aligned_mps, 3229 HNS3_BUF_SIZE_UNIT); 3230 } else { 3231 priv->wl.low = 0; 3232 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) : 3233 aligned_mps; 3234 } 3235 3236 priv->buf_size = priv->wl.high + pf->dv_buf_size; 3237 } 3238 3239 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3240 } 3241 3242 static bool 3243 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw, 3244 struct hns3_pkt_buf_alloc *buf_alloc) 3245 { 3246 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3247 struct hns3_pf *pf = &hns->pf; 3248 struct hns3_priv_buf *priv; 3249 int no_pfc_priv_num; 3250 uint32_t rx_all; 3251 uint8_t mask; 3252 int i; 3253 3254 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3255 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc); 3256 3257 /* let the last to be cleared first */ 3258 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3259 priv = &buf_alloc->priv_buf[i]; 3260 mask = BIT((uint8_t)i); 3261 3262 if (hw->hw_tc_map & mask && 3263 !(hw->dcb_info.hw_pfc_map & mask)) { 3264 /* Clear the no pfc TC private buffer */ 3265 priv->wl.low = 0; 3266 priv->wl.high = 0; 3267 priv->buf_size = 0; 3268 priv->enable = 0; 3269 no_pfc_priv_num--; 3270 } 3271 3272 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3273 no_pfc_priv_num == 0) 3274 break; 3275 } 3276 3277 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3278 } 3279 3280 static bool 3281 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw, 3282 struct hns3_pkt_buf_alloc *buf_alloc) 3283 { 3284 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3285 struct hns3_pf *pf = &hns->pf; 3286 struct hns3_priv_buf *priv; 3287 uint32_t rx_all; 3288 int pfc_priv_num; 3289 uint8_t mask; 3290 int i; 3291 3292 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3293 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc); 3294 3295 /* let the last to be cleared first */ 3296 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3297 priv = &buf_alloc->priv_buf[i]; 3298 mask = BIT((uint8_t)i); 3299 3300 if (hw->hw_tc_map & mask && 3301 hw->dcb_info.hw_pfc_map & mask) { 3302 /* Reduce the number of pfc TC with private buffer */ 3303 priv->wl.low = 0; 3304 priv->enable = 0; 3305 priv->wl.high = 0; 3306 priv->buf_size = 0; 3307 pfc_priv_num--; 3308 } 3309 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3310 pfc_priv_num == 0) 3311 break; 3312 } 3313 3314 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3315 } 3316 3317 static bool 3318 hns3_only_alloc_priv_buff(struct hns3_hw *hw, 3319 struct hns3_pkt_buf_alloc *buf_alloc) 3320 { 3321 #define COMPENSATE_BUFFER 0x3C00 3322 #define COMPENSATE_HALF_MPS_NUM 5 3323 #define PRIV_WL_GAP 0x1800 3324 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3325 struct hns3_pf *pf = &hns->pf; 3326 uint32_t tc_num = hns3_get_tc_num(hw); 3327 uint32_t half_mps = pf->mps >> 1; 3328 struct hns3_priv_buf *priv; 3329 uint32_t min_rx_priv; 3330 uint32_t rx_priv; 3331 uint8_t i; 3332 3333 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3334 if (tc_num) 3335 rx_priv = rx_priv / tc_num; 3336 3337 if (tc_num <= NEED_RESERVE_TC_NUM) 3338 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 3339 3340 /* 3341 * Minimum value of private buffer in rx direction (min_rx_priv) is 3342 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private 3343 * buffer if rx_priv is greater than min_rx_priv. 3344 */ 3345 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER + 3346 COMPENSATE_HALF_MPS_NUM * half_mps; 3347 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT); 3348 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT); 3349 3350 if (rx_priv < min_rx_priv) 3351 return false; 3352 3353 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3354 priv = &buf_alloc->priv_buf[i]; 3355 3356 priv->enable = 0; 3357 priv->wl.low = 0; 3358 priv->wl.high = 0; 3359 priv->buf_size = 0; 3360 3361 if (!(hw->hw_tc_map & BIT(i))) 3362 continue; 3363 3364 priv->enable = 1; 3365 priv->buf_size = rx_priv; 3366 priv->wl.high = rx_priv - pf->dv_buf_size; 3367 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 3368 } 3369 3370 buf_alloc->s_buf.buf_size = 0; 3371 3372 return true; 3373 } 3374 3375 /* 3376 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs 3377 * @hw: pointer to struct hns3_hw 3378 * @buf_alloc: pointer to buffer calculation data 3379 * @return: 0: calculate sucessful, negative: fail 3380 */ 3381 static int 3382 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3383 { 3384 /* When DCB is not supported, rx private buffer is not allocated. */ 3385 if (!hns3_dev_dcb_supported(hw)) { 3386 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3387 struct hns3_pf *pf = &hns->pf; 3388 uint32_t rx_all = pf->pkt_buf_size; 3389 3390 rx_all -= hns3_get_tx_buff_alloced(buf_alloc); 3391 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all)) 3392 return -ENOMEM; 3393 3394 return 0; 3395 } 3396 3397 /* 3398 * Try to allocate privated packet buffer for all TCs without share 3399 * buffer. 3400 */ 3401 if (hns3_only_alloc_priv_buff(hw, buf_alloc)) 3402 return 0; 3403 3404 /* 3405 * Try to allocate privated packet buffer for all TCs with share 3406 * buffer. 3407 */ 3408 if (hns3_rx_buf_calc_all(hw, true, buf_alloc)) 3409 return 0; 3410 3411 /* 3412 * For different application scenes, the enabled port number, TC number 3413 * and no_drop TC number are different. In order to obtain the better 3414 * performance, software could allocate the buffer size and configure 3415 * the waterline by tring to decrease the private buffer size according 3416 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc 3417 * enabled tc. 3418 */ 3419 if (hns3_rx_buf_calc_all(hw, false, buf_alloc)) 3420 return 0; 3421 3422 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc)) 3423 return 0; 3424 3425 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc)) 3426 return 0; 3427 3428 return -ENOMEM; 3429 } 3430 3431 static int 3432 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3433 { 3434 struct hns3_rx_priv_buff_cmd *req; 3435 struct hns3_cmd_desc desc; 3436 uint32_t buf_size; 3437 int ret; 3438 int i; 3439 3440 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false); 3441 req = (struct hns3_rx_priv_buff_cmd *)desc.data; 3442 3443 /* Alloc private buffer TCs */ 3444 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3445 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i]; 3446 3447 req->buf_num[i] = 3448 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S); 3449 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B); 3450 } 3451 3452 buf_size = buf_alloc->s_buf.buf_size; 3453 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) | 3454 (1 << HNS3_TC0_PRI_BUF_EN_B)); 3455 3456 ret = hns3_cmd_send(hw, &desc, 1); 3457 if (ret) 3458 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret); 3459 3460 return ret; 3461 } 3462 3463 static int 3464 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3465 { 3466 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2 3467 struct hns3_rx_priv_wl_buf *req; 3468 struct hns3_priv_buf *priv; 3469 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM]; 3470 int i, j; 3471 int ret; 3472 3473 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) { 3474 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC, 3475 false); 3476 req = (struct hns3_rx_priv_wl_buf *)desc[i].data; 3477 3478 /* The first descriptor set the NEXT bit to 1 */ 3479 if (i == 0) 3480 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3481 else 3482 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3483 3484 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3485 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j; 3486 3487 priv = &buf_alloc->priv_buf[idx]; 3488 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >> 3489 HNS3_BUF_UNIT_S); 3490 req->tc_wl[j].high |= 3491 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3492 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >> 3493 HNS3_BUF_UNIT_S); 3494 req->tc_wl[j].low |= 3495 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3496 } 3497 } 3498 3499 /* Send 2 descriptor at one time */ 3500 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM); 3501 if (ret) 3502 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d", 3503 ret); 3504 return ret; 3505 } 3506 3507 static int 3508 hns3_common_thrd_config(struct hns3_hw *hw, 3509 struct hns3_pkt_buf_alloc *buf_alloc) 3510 { 3511 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2 3512 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf; 3513 struct hns3_rx_com_thrd *req; 3514 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM]; 3515 struct hns3_tc_thrd *tc; 3516 int tc_idx; 3517 int i, j; 3518 int ret; 3519 3520 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) { 3521 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC, 3522 false); 3523 req = (struct hns3_rx_com_thrd *)&desc[i].data; 3524 3525 /* The first descriptor set the NEXT bit to 1 */ 3526 if (i == 0) 3527 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3528 else 3529 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3530 3531 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3532 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j; 3533 tc = &s_buf->tc_thrd[tc_idx]; 3534 3535 req->com_thrd[j].high = 3536 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S); 3537 req->com_thrd[j].high |= 3538 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3539 req->com_thrd[j].low = 3540 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S); 3541 req->com_thrd[j].low |= 3542 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3543 } 3544 } 3545 3546 /* Send 2 descriptors at one time */ 3547 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM); 3548 if (ret) 3549 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret); 3550 3551 return ret; 3552 } 3553 3554 static int 3555 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3556 { 3557 struct hns3_shared_buf *buf = &buf_alloc->s_buf; 3558 struct hns3_rx_com_wl *req; 3559 struct hns3_cmd_desc desc; 3560 int ret; 3561 3562 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false); 3563 3564 req = (struct hns3_rx_com_wl *)desc.data; 3565 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S); 3566 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3567 3568 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S); 3569 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3570 3571 ret = hns3_cmd_send(hw, &desc, 1); 3572 if (ret) 3573 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret); 3574 3575 return ret; 3576 } 3577 3578 int 3579 hns3_buffer_alloc(struct hns3_hw *hw) 3580 { 3581 struct hns3_pkt_buf_alloc pkt_buf; 3582 int ret; 3583 3584 memset(&pkt_buf, 0, sizeof(pkt_buf)); 3585 ret = hns3_tx_buffer_calc(hw, &pkt_buf); 3586 if (ret) { 3587 PMD_INIT_LOG(ERR, 3588 "could not calc tx buffer size for all TCs %d", 3589 ret); 3590 return ret; 3591 } 3592 3593 ret = hns3_tx_buffer_alloc(hw, &pkt_buf); 3594 if (ret) { 3595 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret); 3596 return ret; 3597 } 3598 3599 ret = hns3_rx_buffer_calc(hw, &pkt_buf); 3600 if (ret) { 3601 PMD_INIT_LOG(ERR, 3602 "could not calc rx priv buffer size for all TCs %d", 3603 ret); 3604 return ret; 3605 } 3606 3607 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf); 3608 if (ret) { 3609 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret); 3610 return ret; 3611 } 3612 3613 if (hns3_dev_dcb_supported(hw)) { 3614 ret = hns3_rx_priv_wl_config(hw, &pkt_buf); 3615 if (ret) { 3616 PMD_INIT_LOG(ERR, 3617 "could not configure rx private waterline %d", 3618 ret); 3619 return ret; 3620 } 3621 3622 ret = hns3_common_thrd_config(hw, &pkt_buf); 3623 if (ret) { 3624 PMD_INIT_LOG(ERR, 3625 "could not configure common threshold %d", 3626 ret); 3627 return ret; 3628 } 3629 } 3630 3631 ret = hns3_common_wl_config(hw, &pkt_buf); 3632 if (ret) 3633 PMD_INIT_LOG(ERR, "could not configure common waterline %d", 3634 ret); 3635 3636 return ret; 3637 } 3638 3639 static int 3640 hns3_mac_init(struct hns3_hw *hw) 3641 { 3642 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3643 struct hns3_mac *mac = &hw->mac; 3644 struct hns3_pf *pf = &hns->pf; 3645 int ret; 3646 3647 pf->support_sfp_query = true; 3648 mac->link_duplex = ETH_LINK_FULL_DUPLEX; 3649 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); 3650 if (ret) { 3651 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); 3652 return ret; 3653 } 3654 3655 mac->link_status = ETH_LINK_DOWN; 3656 3657 return hns3_config_mtu(hw, pf->mps); 3658 } 3659 3660 static int 3661 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code) 3662 { 3663 #define HNS3_ETHERTYPE_SUCCESS_ADD 0 3664 #define HNS3_ETHERTYPE_ALREADY_ADD 1 3665 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2 3666 #define HNS3_ETHERTYPE_KEY_CONFLICT 3 3667 int return_status; 3668 3669 if (cmdq_resp) { 3670 PMD_INIT_LOG(ERR, 3671 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", 3672 cmdq_resp); 3673 return -EIO; 3674 } 3675 3676 switch (resp_code) { 3677 case HNS3_ETHERTYPE_SUCCESS_ADD: 3678 case HNS3_ETHERTYPE_ALREADY_ADD: 3679 return_status = 0; 3680 break; 3681 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW: 3682 PMD_INIT_LOG(ERR, 3683 "add mac ethertype failed for manager table overflow."); 3684 return_status = -EIO; 3685 break; 3686 case HNS3_ETHERTYPE_KEY_CONFLICT: 3687 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict."); 3688 return_status = -EIO; 3689 break; 3690 default: 3691 PMD_INIT_LOG(ERR, 3692 "add mac ethertype failed for undefined, code=%d.", 3693 resp_code); 3694 return_status = -EIO; 3695 break; 3696 } 3697 3698 return return_status; 3699 } 3700 3701 static int 3702 hns3_add_mgr_tbl(struct hns3_hw *hw, 3703 const struct hns3_mac_mgr_tbl_entry_cmd *req) 3704 { 3705 struct hns3_cmd_desc desc; 3706 uint8_t resp_code; 3707 uint16_t retval; 3708 int ret; 3709 3710 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false); 3711 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd)); 3712 3713 ret = hns3_cmd_send(hw, &desc, 1); 3714 if (ret) { 3715 PMD_INIT_LOG(ERR, 3716 "add mac ethertype failed for cmd_send, ret =%d.", 3717 ret); 3718 return ret; 3719 } 3720 3721 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 3722 retval = rte_le_to_cpu_16(desc.retval); 3723 3724 return hns3_get_mac_ethertype_cmd_status(retval, resp_code); 3725 } 3726 3727 static void 3728 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table, 3729 int *table_item_num) 3730 { 3731 struct hns3_mac_mgr_tbl_entry_cmd *tbl; 3732 3733 /* 3734 * In current version, we add one item in management table as below: 3735 * 0x0180C200000E -- LLDP MC address 3736 */ 3737 tbl = mgr_table; 3738 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B; 3739 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP); 3740 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200)); 3741 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E)); 3742 tbl->i_port_bitmap = 0x1; 3743 *table_item_num = 1; 3744 } 3745 3746 static int 3747 hns3_init_mgr_tbl(struct hns3_hw *hw) 3748 { 3749 #define HNS_MAC_MGR_TBL_MAX_SIZE 16 3750 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE]; 3751 int table_item_num; 3752 int ret; 3753 int i; 3754 3755 memset(mgr_table, 0, sizeof(mgr_table)); 3756 hns3_prepare_mgr_tbl(mgr_table, &table_item_num); 3757 for (i = 0; i < table_item_num; i++) { 3758 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]); 3759 if (ret) { 3760 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d", 3761 ret); 3762 return ret; 3763 } 3764 } 3765 3766 return 0; 3767 } 3768 3769 static void 3770 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc, 3771 bool en_mc, bool en_bc, int vport_id) 3772 { 3773 if (!param) 3774 return; 3775 3776 memset(param, 0, sizeof(struct hns3_promisc_param)); 3777 if (en_uc) 3778 param->enable = HNS3_PROMISC_EN_UC; 3779 if (en_mc) 3780 param->enable |= HNS3_PROMISC_EN_MC; 3781 if (en_bc) 3782 param->enable |= HNS3_PROMISC_EN_BC; 3783 param->vf_id = vport_id; 3784 } 3785 3786 static int 3787 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param) 3788 { 3789 struct hns3_promisc_cfg_cmd *req; 3790 struct hns3_cmd_desc desc; 3791 int ret; 3792 3793 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false); 3794 3795 req = (struct hns3_promisc_cfg_cmd *)desc.data; 3796 req->vf_id = param->vf_id; 3797 req->flag = (param->enable << HNS3_PROMISC_EN_B) | 3798 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B; 3799 3800 ret = hns3_cmd_send(hw, &desc, 1); 3801 if (ret) 3802 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret); 3803 3804 return ret; 3805 } 3806 3807 static int 3808 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc) 3809 { 3810 struct hns3_promisc_param param; 3811 bool en_bc_pmc = true; 3812 uint8_t vf_id; 3813 3814 /* 3815 * In current version VF is not supported when PF is driven by DPDK 3816 * driver, just need to configure parameters for PF vport. 3817 */ 3818 vf_id = HNS3_PF_FUNC_ID; 3819 3820 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id); 3821 return hns3_cmd_set_promisc_mode(hw, ¶m); 3822 } 3823 3824 static int 3825 hns3_promisc_init(struct hns3_hw *hw) 3826 { 3827 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3828 struct hns3_pf *pf = &hns->pf; 3829 struct hns3_promisc_param param; 3830 uint16_t func_id; 3831 int ret; 3832 3833 ret = hns3_set_promisc_mode(hw, false, false); 3834 if (ret) { 3835 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret); 3836 return ret; 3837 } 3838 3839 /* 3840 * In current version VFs are not supported when PF is driven by DPDK 3841 * driver. After PF has been taken over by DPDK, the original VF will 3842 * be invalid. So, there is a possibility of entry residues. It should 3843 * clear VFs's promisc mode to avoid unnecessary bandwidth usage 3844 * during init. 3845 */ 3846 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) { 3847 hns3_promisc_param_init(¶m, false, false, false, func_id); 3848 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 3849 if (ret) { 3850 PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode," 3851 " ret = %d", func_id, ret); 3852 return ret; 3853 } 3854 } 3855 3856 return 0; 3857 } 3858 3859 static void 3860 hns3_promisc_uninit(struct hns3_hw *hw) 3861 { 3862 struct hns3_promisc_param param; 3863 uint16_t func_id; 3864 int ret; 3865 3866 func_id = HNS3_PF_FUNC_ID; 3867 3868 /* 3869 * In current version VFs are not supported when PF is driven by 3870 * DPDK driver, and VFs' promisc mode status has been cleared during 3871 * init and their status will not change. So just clear PF's promisc 3872 * mode status during uninit. 3873 */ 3874 hns3_promisc_param_init(¶m, false, false, false, func_id); 3875 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 3876 if (ret) 3877 PMD_INIT_LOG(ERR, "failed to clear promisc status during" 3878 " uninit, ret = %d", ret); 3879 } 3880 3881 static int 3882 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev) 3883 { 3884 bool allmulti = dev->data->all_multicast ? true : false; 3885 struct hns3_adapter *hns = dev->data->dev_private; 3886 struct hns3_hw *hw = &hns->hw; 3887 uint64_t offloads; 3888 int err; 3889 int ret; 3890 3891 rte_spinlock_lock(&hw->lock); 3892 ret = hns3_set_promisc_mode(hw, true, true); 3893 if (ret) { 3894 rte_spinlock_unlock(&hw->lock); 3895 hns3_err(hw, "failed to enable promiscuous mode, ret = %d", 3896 ret); 3897 return ret; 3898 } 3899 3900 /* 3901 * When promiscuous mode was enabled, disable the vlan filter to let 3902 * all packets coming in in the receiving direction. 3903 */ 3904 offloads = dev->data->dev_conf.rxmode.offloads; 3905 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 3906 ret = hns3_enable_vlan_filter(hns, false); 3907 if (ret) { 3908 hns3_err(hw, "failed to enable promiscuous mode due to " 3909 "failure to disable vlan filter, ret = %d", 3910 ret); 3911 err = hns3_set_promisc_mode(hw, false, allmulti); 3912 if (err) 3913 hns3_err(hw, "failed to restore promiscuous " 3914 "status after disable vlan filter " 3915 "failed during enabling promiscuous " 3916 "mode, ret = %d", ret); 3917 } 3918 } 3919 3920 rte_spinlock_unlock(&hw->lock); 3921 3922 return ret; 3923 } 3924 3925 static int 3926 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev) 3927 { 3928 bool allmulti = dev->data->all_multicast ? true : false; 3929 struct hns3_adapter *hns = dev->data->dev_private; 3930 struct hns3_hw *hw = &hns->hw; 3931 uint64_t offloads; 3932 int err; 3933 int ret; 3934 3935 /* If now in all_multicast mode, must remain in all_multicast mode. */ 3936 rte_spinlock_lock(&hw->lock); 3937 ret = hns3_set_promisc_mode(hw, false, allmulti); 3938 if (ret) { 3939 rte_spinlock_unlock(&hw->lock); 3940 hns3_err(hw, "failed to disable promiscuous mode, ret = %d", 3941 ret); 3942 return ret; 3943 } 3944 /* when promiscuous mode was disabled, restore the vlan filter status */ 3945 offloads = dev->data->dev_conf.rxmode.offloads; 3946 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 3947 ret = hns3_enable_vlan_filter(hns, true); 3948 if (ret) { 3949 hns3_err(hw, "failed to disable promiscuous mode due to" 3950 " failure to restore vlan filter, ret = %d", 3951 ret); 3952 err = hns3_set_promisc_mode(hw, true, true); 3953 if (err) 3954 hns3_err(hw, "failed to restore promiscuous " 3955 "status after enabling vlan filter " 3956 "failed during disabling promiscuous " 3957 "mode, ret = %d", ret); 3958 } 3959 } 3960 rte_spinlock_unlock(&hw->lock); 3961 3962 return ret; 3963 } 3964 3965 static int 3966 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev) 3967 { 3968 struct hns3_adapter *hns = dev->data->dev_private; 3969 struct hns3_hw *hw = &hns->hw; 3970 int ret; 3971 3972 if (dev->data->promiscuous) 3973 return 0; 3974 3975 rte_spinlock_lock(&hw->lock); 3976 ret = hns3_set_promisc_mode(hw, false, true); 3977 rte_spinlock_unlock(&hw->lock); 3978 if (ret) 3979 hns3_err(hw, "failed to enable allmulticast mode, ret = %d", 3980 ret); 3981 3982 return ret; 3983 } 3984 3985 static int 3986 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev) 3987 { 3988 struct hns3_adapter *hns = dev->data->dev_private; 3989 struct hns3_hw *hw = &hns->hw; 3990 int ret; 3991 3992 /* If now in promiscuous mode, must remain in all_multicast mode. */ 3993 if (dev->data->promiscuous) 3994 return 0; 3995 3996 rte_spinlock_lock(&hw->lock); 3997 ret = hns3_set_promisc_mode(hw, false, false); 3998 rte_spinlock_unlock(&hw->lock); 3999 if (ret) 4000 hns3_err(hw, "failed to disable allmulticast mode, ret = %d", 4001 ret); 4002 4003 return ret; 4004 } 4005 4006 static int 4007 hns3_dev_promisc_restore(struct hns3_adapter *hns) 4008 { 4009 struct hns3_hw *hw = &hns->hw; 4010 bool allmulti = hw->data->all_multicast ? true : false; 4011 int ret; 4012 4013 if (hw->data->promiscuous) { 4014 ret = hns3_set_promisc_mode(hw, true, true); 4015 if (ret) 4016 hns3_err(hw, "failed to restore promiscuous mode, " 4017 "ret = %d", ret); 4018 return ret; 4019 } 4020 4021 ret = hns3_set_promisc_mode(hw, false, allmulti); 4022 if (ret) 4023 hns3_err(hw, "failed to restore allmulticast mode, ret = %d", 4024 ret); 4025 return ret; 4026 } 4027 4028 static int 4029 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed) 4030 { 4031 struct hns3_sfp_speed_cmd *resp; 4032 struct hns3_cmd_desc desc; 4033 int ret; 4034 4035 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true); 4036 resp = (struct hns3_sfp_speed_cmd *)desc.data; 4037 ret = hns3_cmd_send(hw, &desc, 1); 4038 if (ret == -EOPNOTSUPP) { 4039 hns3_err(hw, "IMP do not support get SFP speed %d", ret); 4040 return ret; 4041 } else if (ret) { 4042 hns3_err(hw, "get sfp speed failed %d", ret); 4043 return ret; 4044 } 4045 4046 *speed = resp->sfp_speed; 4047 4048 return 0; 4049 } 4050 4051 static uint8_t 4052 hns3_check_speed_dup(uint8_t duplex, uint32_t speed) 4053 { 4054 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M)) 4055 duplex = ETH_LINK_FULL_DUPLEX; 4056 4057 return duplex; 4058 } 4059 4060 static int 4061 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 4062 { 4063 struct hns3_mac *mac = &hw->mac; 4064 int ret; 4065 4066 duplex = hns3_check_speed_dup(duplex, speed); 4067 if (mac->link_speed == speed && mac->link_duplex == duplex) 4068 return 0; 4069 4070 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); 4071 if (ret) 4072 return ret; 4073 4074 mac->link_speed = speed; 4075 mac->link_duplex = duplex; 4076 4077 return 0; 4078 } 4079 4080 static int 4081 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev) 4082 { 4083 struct hns3_adapter *hns = eth_dev->data->dev_private; 4084 struct hns3_hw *hw = &hns->hw; 4085 struct hns3_pf *pf = &hns->pf; 4086 uint32_t speed; 4087 int ret; 4088 4089 /* If IMP do not support get SFP/qSFP speed, return directly */ 4090 if (!pf->support_sfp_query) 4091 return 0; 4092 4093 ret = hns3_get_sfp_speed(hw, &speed); 4094 if (ret == -EOPNOTSUPP) { 4095 pf->support_sfp_query = false; 4096 return ret; 4097 } else if (ret) 4098 return ret; 4099 4100 if (speed == ETH_SPEED_NUM_NONE) 4101 return 0; /* do nothing if no SFP */ 4102 4103 /* Config full duplex for SFP */ 4104 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX); 4105 } 4106 4107 static int 4108 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable) 4109 { 4110 struct hns3_config_mac_mode_cmd *req; 4111 struct hns3_cmd_desc desc; 4112 uint32_t loop_en = 0; 4113 uint8_t val = 0; 4114 int ret; 4115 4116 req = (struct hns3_config_mac_mode_cmd *)desc.data; 4117 4118 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false); 4119 if (enable) 4120 val = 1; 4121 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val); 4122 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val); 4123 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val); 4124 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val); 4125 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0); 4126 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0); 4127 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0); 4128 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0); 4129 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val); 4130 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val); 4131 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val); 4132 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val); 4133 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val); 4134 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val); 4135 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en); 4136 4137 ret = hns3_cmd_send(hw, &desc, 1); 4138 if (ret) 4139 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret); 4140 4141 return ret; 4142 } 4143 4144 static int 4145 hns3_get_mac_link_status(struct hns3_hw *hw) 4146 { 4147 struct hns3_link_status_cmd *req; 4148 struct hns3_cmd_desc desc; 4149 int link_status; 4150 int ret; 4151 4152 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true); 4153 ret = hns3_cmd_send(hw, &desc, 1); 4154 if (ret) { 4155 hns3_err(hw, "get link status cmd failed %d", ret); 4156 return ETH_LINK_DOWN; 4157 } 4158 4159 req = (struct hns3_link_status_cmd *)desc.data; 4160 link_status = req->status & HNS3_LINK_STATUS_UP_M; 4161 4162 return !!link_status; 4163 } 4164 4165 void 4166 hns3_update_link_status(struct hns3_hw *hw) 4167 { 4168 int state; 4169 4170 state = hns3_get_mac_link_status(hw); 4171 if (state != hw->mac.link_status) { 4172 hw->mac.link_status = state; 4173 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down"); 4174 } 4175 } 4176 4177 static void 4178 hns3_service_handler(void *param) 4179 { 4180 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 4181 struct hns3_adapter *hns = eth_dev->data->dev_private; 4182 struct hns3_hw *hw = &hns->hw; 4183 4184 if (!hns3_is_reset_pending(hns)) { 4185 hns3_update_speed_duplex(eth_dev); 4186 hns3_update_link_status(hw); 4187 } else 4188 hns3_warn(hw, "Cancel the query when reset is pending"); 4189 4190 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev); 4191 } 4192 4193 static int 4194 hns3_init_hardware(struct hns3_adapter *hns) 4195 { 4196 struct hns3_hw *hw = &hns->hw; 4197 int ret; 4198 4199 ret = hns3_map_tqp(hw); 4200 if (ret) { 4201 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret); 4202 return ret; 4203 } 4204 4205 ret = hns3_init_umv_space(hw); 4206 if (ret) { 4207 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret); 4208 return ret; 4209 } 4210 4211 ret = hns3_mac_init(hw); 4212 if (ret) { 4213 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret); 4214 goto err_mac_init; 4215 } 4216 4217 ret = hns3_init_mgr_tbl(hw); 4218 if (ret) { 4219 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret); 4220 goto err_mac_init; 4221 } 4222 4223 ret = hns3_promisc_init(hw); 4224 if (ret) { 4225 PMD_INIT_LOG(ERR, "Failed to init promisc: %d", 4226 ret); 4227 goto err_mac_init; 4228 } 4229 4230 ret = hns3_init_vlan_config(hns); 4231 if (ret) { 4232 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret); 4233 goto err_mac_init; 4234 } 4235 4236 ret = hns3_dcb_init(hw); 4237 if (ret) { 4238 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret); 4239 goto err_mac_init; 4240 } 4241 4242 ret = hns3_init_fd_config(hns); 4243 if (ret) { 4244 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret); 4245 goto err_mac_init; 4246 } 4247 4248 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX); 4249 if (ret) { 4250 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret); 4251 goto err_mac_init; 4252 } 4253 4254 ret = hns3_config_gro(hw, false); 4255 if (ret) { 4256 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 4257 goto err_mac_init; 4258 } 4259 4260 /* 4261 * In the initialization clearing the all hardware mapping relationship 4262 * configurations between queues and interrupt vectors is needed, so 4263 * some error caused by the residual configurations, such as the 4264 * unexpected interrupt, can be avoid. 4265 */ 4266 ret = hns3_init_ring_with_vector(hw); 4267 if (ret) { 4268 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 4269 goto err_mac_init; 4270 } 4271 4272 return 0; 4273 4274 err_mac_init: 4275 hns3_uninit_umv_space(hw); 4276 return ret; 4277 } 4278 4279 static int 4280 hns3_init_pf(struct rte_eth_dev *eth_dev) 4281 { 4282 struct rte_device *dev = eth_dev->device; 4283 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4284 struct hns3_adapter *hns = eth_dev->data->dev_private; 4285 struct hns3_hw *hw = &hns->hw; 4286 int ret; 4287 4288 PMD_INIT_FUNC_TRACE(); 4289 4290 /* Get hardware io base address from pcie BAR2 IO space */ 4291 hw->io_base = pci_dev->mem_resource[2].addr; 4292 4293 /* Firmware command queue initialize */ 4294 ret = hns3_cmd_init_queue(hw); 4295 if (ret) { 4296 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 4297 goto err_cmd_init_queue; 4298 } 4299 4300 hns3_clear_all_event_cause(hw); 4301 4302 /* Firmware command initialize */ 4303 ret = hns3_cmd_init(hw); 4304 if (ret) { 4305 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 4306 goto err_cmd_init; 4307 } 4308 4309 ret = rte_intr_callback_register(&pci_dev->intr_handle, 4310 hns3_interrupt_handler, 4311 eth_dev); 4312 if (ret) { 4313 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 4314 goto err_intr_callback_register; 4315 } 4316 4317 /* Enable interrupt */ 4318 rte_intr_enable(&pci_dev->intr_handle); 4319 hns3_pf_enable_irq0(hw); 4320 4321 /* Get configuration */ 4322 ret = hns3_get_configuration(hw); 4323 if (ret) { 4324 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 4325 goto err_get_config; 4326 } 4327 4328 ret = hns3_init_hardware(hns); 4329 if (ret) { 4330 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret); 4331 goto err_get_config; 4332 } 4333 4334 /* Initialize flow director filter list & hash */ 4335 ret = hns3_fdir_filter_init(hns); 4336 if (ret) { 4337 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret); 4338 goto err_hw_init; 4339 } 4340 4341 hns3_set_default_rss_args(hw); 4342 4343 ret = hns3_enable_hw_error_intr(hns, true); 4344 if (ret) { 4345 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d", 4346 ret); 4347 goto err_fdir; 4348 } 4349 4350 return 0; 4351 4352 err_fdir: 4353 hns3_fdir_filter_uninit(hns); 4354 err_hw_init: 4355 hns3_uninit_umv_space(hw); 4356 4357 err_get_config: 4358 hns3_pf_disable_irq0(hw); 4359 rte_intr_disable(&pci_dev->intr_handle); 4360 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 4361 eth_dev); 4362 err_intr_callback_register: 4363 err_cmd_init: 4364 hns3_cmd_uninit(hw); 4365 hns3_cmd_destroy_queue(hw); 4366 err_cmd_init_queue: 4367 hw->io_base = NULL; 4368 4369 return ret; 4370 } 4371 4372 static void 4373 hns3_uninit_pf(struct rte_eth_dev *eth_dev) 4374 { 4375 struct hns3_adapter *hns = eth_dev->data->dev_private; 4376 struct rte_device *dev = eth_dev->device; 4377 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4378 struct hns3_hw *hw = &hns->hw; 4379 4380 PMD_INIT_FUNC_TRACE(); 4381 4382 hns3_enable_hw_error_intr(hns, false); 4383 hns3_rss_uninit(hns); 4384 hns3_promisc_uninit(hw); 4385 hns3_fdir_filter_uninit(hns); 4386 hns3_uninit_umv_space(hw); 4387 hns3_pf_disable_irq0(hw); 4388 rte_intr_disable(&pci_dev->intr_handle); 4389 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 4390 eth_dev); 4391 hns3_cmd_uninit(hw); 4392 hns3_cmd_destroy_queue(hw); 4393 hw->io_base = NULL; 4394 } 4395 4396 static int 4397 hns3_do_start(struct hns3_adapter *hns, bool reset_queue) 4398 { 4399 struct hns3_hw *hw = &hns->hw; 4400 int ret; 4401 4402 ret = hns3_dcb_cfg_update(hns); 4403 if (ret) 4404 return ret; 4405 4406 /* Enable queues */ 4407 ret = hns3_start_queues(hns, reset_queue); 4408 if (ret) { 4409 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret); 4410 return ret; 4411 } 4412 4413 /* Enable MAC */ 4414 ret = hns3_cfg_mac_mode(hw, true); 4415 if (ret) { 4416 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret); 4417 goto err_config_mac_mode; 4418 } 4419 return 0; 4420 4421 err_config_mac_mode: 4422 hns3_stop_queues(hns, true); 4423 return ret; 4424 } 4425 4426 static int 4427 hns3_map_rx_interrupt(struct rte_eth_dev *dev) 4428 { 4429 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4430 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4431 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4432 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 4433 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 4434 uint32_t intr_vector; 4435 uint16_t q_id; 4436 int ret; 4437 4438 if (dev->data->dev_conf.intr_conf.rxq == 0) 4439 return 0; 4440 4441 /* disable uio/vfio intr/eventfd mapping */ 4442 rte_intr_disable(intr_handle); 4443 4444 /* check and configure queue intr-vector mapping */ 4445 if (rte_intr_cap_multiple(intr_handle) || 4446 !RTE_ETH_DEV_SRIOV(dev).active) { 4447 intr_vector = hw->used_rx_queues; 4448 /* creates event fd for each intr vector when MSIX is used */ 4449 if (rte_intr_efd_enable(intr_handle, intr_vector)) 4450 return -EINVAL; 4451 } 4452 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 4453 intr_handle->intr_vec = 4454 rte_zmalloc("intr_vec", 4455 hw->used_rx_queues * sizeof(int), 0); 4456 if (intr_handle->intr_vec == NULL) { 4457 hns3_err(hw, "Failed to allocate %d rx_queues" 4458 " intr_vec", hw->used_rx_queues); 4459 ret = -ENOMEM; 4460 goto alloc_intr_vec_error; 4461 } 4462 } 4463 4464 if (rte_intr_allow_others(intr_handle)) { 4465 vec = RTE_INTR_VEC_RXTX_OFFSET; 4466 base = RTE_INTR_VEC_RXTX_OFFSET; 4467 } 4468 if (rte_intr_dp_is_en(intr_handle)) { 4469 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 4470 ret = hns3_bind_ring_with_vector(hw, vec, true, 4471 HNS3_RING_TYPE_RX, 4472 q_id); 4473 if (ret) 4474 goto bind_vector_error; 4475 intr_handle->intr_vec[q_id] = vec; 4476 if (vec < base + intr_handle->nb_efd - 1) 4477 vec++; 4478 } 4479 } 4480 rte_intr_enable(intr_handle); 4481 return 0; 4482 4483 bind_vector_error: 4484 rte_intr_efd_disable(intr_handle); 4485 if (intr_handle->intr_vec) { 4486 free(intr_handle->intr_vec); 4487 intr_handle->intr_vec = NULL; 4488 } 4489 return ret; 4490 alloc_intr_vec_error: 4491 rte_intr_efd_disable(intr_handle); 4492 return ret; 4493 } 4494 4495 static int 4496 hns3_restore_rx_interrupt(struct hns3_hw *hw) 4497 { 4498 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 4499 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4500 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4501 uint16_t q_id; 4502 int ret; 4503 4504 if (dev->data->dev_conf.intr_conf.rxq == 0) 4505 return 0; 4506 4507 if (rte_intr_dp_is_en(intr_handle)) { 4508 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 4509 ret = hns3_bind_ring_with_vector(hw, 4510 intr_handle->intr_vec[q_id], true, 4511 HNS3_RING_TYPE_RX, q_id); 4512 if (ret) 4513 return ret; 4514 } 4515 } 4516 4517 return 0; 4518 } 4519 4520 static void 4521 hns3_restore_filter(struct rte_eth_dev *dev) 4522 { 4523 hns3_restore_rss_filter(dev); 4524 } 4525 4526 static int 4527 hns3_dev_start(struct rte_eth_dev *dev) 4528 { 4529 struct hns3_adapter *hns = dev->data->dev_private; 4530 struct hns3_hw *hw = &hns->hw; 4531 int ret; 4532 4533 PMD_INIT_FUNC_TRACE(); 4534 if (rte_atomic16_read(&hw->reset.resetting)) 4535 return -EBUSY; 4536 4537 rte_spinlock_lock(&hw->lock); 4538 hw->adapter_state = HNS3_NIC_STARTING; 4539 4540 ret = hns3_do_start(hns, true); 4541 if (ret) { 4542 hw->adapter_state = HNS3_NIC_CONFIGURED; 4543 rte_spinlock_unlock(&hw->lock); 4544 return ret; 4545 } 4546 ret = hns3_map_rx_interrupt(dev); 4547 if (ret) { 4548 hw->adapter_state = HNS3_NIC_CONFIGURED; 4549 rte_spinlock_unlock(&hw->lock); 4550 return ret; 4551 } 4552 4553 hw->adapter_state = HNS3_NIC_STARTED; 4554 rte_spinlock_unlock(&hw->lock); 4555 4556 hns3_set_rxtx_function(dev); 4557 hns3_mp_req_start_rxtx(dev); 4558 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev); 4559 4560 hns3_restore_filter(dev); 4561 4562 /* Enable interrupt of all rx queues before enabling queues */ 4563 hns3_dev_all_rx_queue_intr_enable(hw, true); 4564 /* 4565 * When finished the initialization, enable queues to receive/transmit 4566 * packets. 4567 */ 4568 hns3_enable_all_queues(hw, true); 4569 4570 hns3_info(hw, "hns3 dev start successful!"); 4571 return 0; 4572 } 4573 4574 static int 4575 hns3_do_stop(struct hns3_adapter *hns) 4576 { 4577 struct hns3_hw *hw = &hns->hw; 4578 bool reset_queue; 4579 int ret; 4580 4581 ret = hns3_cfg_mac_mode(hw, false); 4582 if (ret) 4583 return ret; 4584 hw->mac.link_status = ETH_LINK_DOWN; 4585 4586 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) { 4587 hns3_configure_all_mac_addr(hns, true); 4588 reset_queue = true; 4589 } else 4590 reset_queue = false; 4591 hw->mac.default_addr_setted = false; 4592 return hns3_stop_queues(hns, reset_queue); 4593 } 4594 4595 static void 4596 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev) 4597 { 4598 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4599 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4600 struct hns3_adapter *hns = dev->data->dev_private; 4601 struct hns3_hw *hw = &hns->hw; 4602 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 4603 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 4604 uint16_t q_id; 4605 4606 if (dev->data->dev_conf.intr_conf.rxq == 0) 4607 return; 4608 4609 /* unmap the ring with vector */ 4610 if (rte_intr_allow_others(intr_handle)) { 4611 vec = RTE_INTR_VEC_RXTX_OFFSET; 4612 base = RTE_INTR_VEC_RXTX_OFFSET; 4613 } 4614 if (rte_intr_dp_is_en(intr_handle)) { 4615 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 4616 (void)hns3_bind_ring_with_vector(hw, vec, false, 4617 HNS3_RING_TYPE_RX, 4618 q_id); 4619 if (vec < base + intr_handle->nb_efd - 1) 4620 vec++; 4621 } 4622 } 4623 /* Clean datapath event and queue/vec mapping */ 4624 rte_intr_efd_disable(intr_handle); 4625 if (intr_handle->intr_vec) { 4626 rte_free(intr_handle->intr_vec); 4627 intr_handle->intr_vec = NULL; 4628 } 4629 } 4630 4631 static void 4632 hns3_dev_stop(struct rte_eth_dev *dev) 4633 { 4634 struct hns3_adapter *hns = dev->data->dev_private; 4635 struct hns3_hw *hw = &hns->hw; 4636 4637 PMD_INIT_FUNC_TRACE(); 4638 4639 hw->adapter_state = HNS3_NIC_STOPPING; 4640 hns3_set_rxtx_function(dev); 4641 rte_wmb(); 4642 /* Disable datapath on secondary process. */ 4643 hns3_mp_req_stop_rxtx(dev); 4644 /* Prevent crashes when queues are still in use. */ 4645 rte_delay_ms(hw->tqps_num); 4646 4647 rte_spinlock_lock(&hw->lock); 4648 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 4649 hns3_do_stop(hns); 4650 hns3_unmap_rx_interrupt(dev); 4651 hns3_dev_release_mbufs(hns); 4652 hw->adapter_state = HNS3_NIC_CONFIGURED; 4653 } 4654 rte_eal_alarm_cancel(hns3_service_handler, dev); 4655 rte_spinlock_unlock(&hw->lock); 4656 } 4657 4658 static void 4659 hns3_dev_close(struct rte_eth_dev *eth_dev) 4660 { 4661 struct hns3_adapter *hns = eth_dev->data->dev_private; 4662 struct hns3_hw *hw = &hns->hw; 4663 4664 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 4665 rte_free(eth_dev->process_private); 4666 eth_dev->process_private = NULL; 4667 return; 4668 } 4669 4670 if (hw->adapter_state == HNS3_NIC_STARTED) 4671 hns3_dev_stop(eth_dev); 4672 4673 hw->adapter_state = HNS3_NIC_CLOSING; 4674 hns3_reset_abort(hns); 4675 hw->adapter_state = HNS3_NIC_CLOSED; 4676 4677 hns3_configure_all_mc_mac_addr(hns, true); 4678 hns3_remove_all_vlan_table(hns); 4679 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0); 4680 hns3_uninit_pf(eth_dev); 4681 hns3_free_all_queues(eth_dev); 4682 rte_free(hw->reset.wait_data); 4683 rte_free(eth_dev->process_private); 4684 eth_dev->process_private = NULL; 4685 hns3_mp_uninit_primary(); 4686 hns3_warn(hw, "Close port %d finished", hw->data->port_id); 4687 } 4688 4689 static int 4690 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4691 { 4692 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4693 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4694 4695 fc_conf->pause_time = pf->pause_time; 4696 4697 /* return fc current mode */ 4698 switch (hw->current_mode) { 4699 case HNS3_FC_FULL: 4700 fc_conf->mode = RTE_FC_FULL; 4701 break; 4702 case HNS3_FC_TX_PAUSE: 4703 fc_conf->mode = RTE_FC_TX_PAUSE; 4704 break; 4705 case HNS3_FC_RX_PAUSE: 4706 fc_conf->mode = RTE_FC_RX_PAUSE; 4707 break; 4708 case HNS3_FC_NONE: 4709 default: 4710 fc_conf->mode = RTE_FC_NONE; 4711 break; 4712 } 4713 4714 return 0; 4715 } 4716 4717 static void 4718 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode) 4719 { 4720 switch (mode) { 4721 case RTE_FC_NONE: 4722 hw->requested_mode = HNS3_FC_NONE; 4723 break; 4724 case RTE_FC_RX_PAUSE: 4725 hw->requested_mode = HNS3_FC_RX_PAUSE; 4726 break; 4727 case RTE_FC_TX_PAUSE: 4728 hw->requested_mode = HNS3_FC_TX_PAUSE; 4729 break; 4730 case RTE_FC_FULL: 4731 hw->requested_mode = HNS3_FC_FULL; 4732 break; 4733 default: 4734 hw->requested_mode = HNS3_FC_NONE; 4735 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is " 4736 "configured to RTE_FC_NONE", mode); 4737 break; 4738 } 4739 } 4740 4741 static int 4742 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4743 { 4744 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4745 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4746 int ret; 4747 4748 if (fc_conf->high_water || fc_conf->low_water || 4749 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) { 4750 hns3_err(hw, "Unsupported flow control settings specified, " 4751 "high_water(%u), low_water(%u), send_xon(%u) and " 4752 "mac_ctrl_frame_fwd(%u) must be set to '0'", 4753 fc_conf->high_water, fc_conf->low_water, 4754 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd); 4755 return -EINVAL; 4756 } 4757 if (fc_conf->autoneg) { 4758 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 4759 return -EINVAL; 4760 } 4761 if (!fc_conf->pause_time) { 4762 hns3_err(hw, "Invalid pause time %d setting.", 4763 fc_conf->pause_time); 4764 return -EINVAL; 4765 } 4766 4767 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 4768 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) { 4769 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. " 4770 "current_fc_status = %d", hw->current_fc_status); 4771 return -EOPNOTSUPP; 4772 } 4773 4774 hns3_get_fc_mode(hw, fc_conf->mode); 4775 if (hw->requested_mode == hw->current_mode && 4776 pf->pause_time == fc_conf->pause_time) 4777 return 0; 4778 4779 rte_spinlock_lock(&hw->lock); 4780 ret = hns3_fc_enable(dev, fc_conf); 4781 rte_spinlock_unlock(&hw->lock); 4782 4783 return ret; 4784 } 4785 4786 static int 4787 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev, 4788 struct rte_eth_pfc_conf *pfc_conf) 4789 { 4790 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4791 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4792 uint8_t priority; 4793 int ret; 4794 4795 if (!hns3_dev_dcb_supported(hw)) { 4796 hns3_err(hw, "This port does not support dcb configurations."); 4797 return -EOPNOTSUPP; 4798 } 4799 4800 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water || 4801 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) { 4802 hns3_err(hw, "Unsupported flow control settings specified, " 4803 "high_water(%u), low_water(%u), send_xon(%u) and " 4804 "mac_ctrl_frame_fwd(%u) must be set to '0'", 4805 pfc_conf->fc.high_water, pfc_conf->fc.low_water, 4806 pfc_conf->fc.send_xon, 4807 pfc_conf->fc.mac_ctrl_frame_fwd); 4808 return -EINVAL; 4809 } 4810 if (pfc_conf->fc.autoneg) { 4811 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 4812 return -EINVAL; 4813 } 4814 if (pfc_conf->fc.pause_time == 0) { 4815 hns3_err(hw, "Invalid pause time %d setting.", 4816 pfc_conf->fc.pause_time); 4817 return -EINVAL; 4818 } 4819 4820 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 4821 hw->current_fc_status == HNS3_FC_STATUS_PFC)) { 4822 hns3_err(hw, "MAC pause is enabled. Cannot set PFC." 4823 "current_fc_status = %d", hw->current_fc_status); 4824 return -EOPNOTSUPP; 4825 } 4826 4827 priority = pfc_conf->priority; 4828 hns3_get_fc_mode(hw, pfc_conf->fc.mode); 4829 if (hw->dcb_info.pfc_en & BIT(priority) && 4830 hw->requested_mode == hw->current_mode && 4831 pfc_conf->fc.pause_time == pf->pause_time) 4832 return 0; 4833 4834 rte_spinlock_lock(&hw->lock); 4835 ret = hns3_dcb_pfc_enable(dev, pfc_conf); 4836 rte_spinlock_unlock(&hw->lock); 4837 4838 return ret; 4839 } 4840 4841 static int 4842 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info) 4843 { 4844 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4845 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4846 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 4847 int i; 4848 4849 rte_spinlock_lock(&hw->lock); 4850 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) 4851 dcb_info->nb_tcs = pf->local_max_tc; 4852 else 4853 dcb_info->nb_tcs = 1; 4854 4855 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) 4856 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i]; 4857 for (i = 0; i < dcb_info->nb_tcs; i++) 4858 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i]; 4859 4860 for (i = 0; i < hw->num_tc; i++) { 4861 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i; 4862 dcb_info->tc_queue.tc_txq[0][i].base = 4863 hw->tc_queue[i].tqp_offset; 4864 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size; 4865 dcb_info->tc_queue.tc_txq[0][i].nb_queue = 4866 hw->tc_queue[i].tqp_count; 4867 } 4868 rte_spinlock_unlock(&hw->lock); 4869 4870 return 0; 4871 } 4872 4873 static int 4874 hns3_reinit_dev(struct hns3_adapter *hns) 4875 { 4876 struct hns3_hw *hw = &hns->hw; 4877 int ret; 4878 4879 ret = hns3_cmd_init(hw); 4880 if (ret) { 4881 hns3_err(hw, "Failed to init cmd: %d", ret); 4882 return ret; 4883 } 4884 4885 ret = hns3_reset_all_queues(hns); 4886 if (ret) { 4887 hns3_err(hw, "Failed to reset all queues: %d", ret); 4888 return ret; 4889 } 4890 4891 ret = hns3_init_hardware(hns); 4892 if (ret) { 4893 hns3_err(hw, "Failed to init hardware: %d", ret); 4894 return ret; 4895 } 4896 4897 ret = hns3_enable_hw_error_intr(hns, true); 4898 if (ret) { 4899 hns3_err(hw, "fail to enable hw error interrupts: %d", 4900 ret); 4901 return ret; 4902 } 4903 hns3_info(hw, "Reset done, driver initialization finished."); 4904 4905 return 0; 4906 } 4907 4908 static bool 4909 is_pf_reset_done(struct hns3_hw *hw) 4910 { 4911 uint32_t val, reg, reg_bit; 4912 4913 switch (hw->reset.level) { 4914 case HNS3_IMP_RESET: 4915 reg = HNS3_GLOBAL_RESET_REG; 4916 reg_bit = HNS3_IMP_RESET_BIT; 4917 break; 4918 case HNS3_GLOBAL_RESET: 4919 reg = HNS3_GLOBAL_RESET_REG; 4920 reg_bit = HNS3_GLOBAL_RESET_BIT; 4921 break; 4922 case HNS3_FUNC_RESET: 4923 reg = HNS3_FUN_RST_ING; 4924 reg_bit = HNS3_FUN_RST_ING_B; 4925 break; 4926 case HNS3_FLR_RESET: 4927 default: 4928 hns3_err(hw, "Wait for unsupported reset level: %d", 4929 hw->reset.level); 4930 return true; 4931 } 4932 val = hns3_read_dev(hw, reg); 4933 if (hns3_get_bit(val, reg_bit)) 4934 return false; 4935 else 4936 return true; 4937 } 4938 4939 bool 4940 hns3_is_reset_pending(struct hns3_adapter *hns) 4941 { 4942 struct hns3_hw *hw = &hns->hw; 4943 enum hns3_reset_level reset; 4944 4945 hns3_check_event_cause(hns, NULL); 4946 reset = hns3_get_reset_level(hns, &hw->reset.pending); 4947 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 4948 hns3_warn(hw, "High level reset %d is pending", reset); 4949 return true; 4950 } 4951 reset = hns3_get_reset_level(hns, &hw->reset.request); 4952 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 4953 hns3_warn(hw, "High level reset %d is request", reset); 4954 return true; 4955 } 4956 return false; 4957 } 4958 4959 static int 4960 hns3_wait_hardware_ready(struct hns3_adapter *hns) 4961 { 4962 struct hns3_hw *hw = &hns->hw; 4963 struct hns3_wait_data *wait_data = hw->reset.wait_data; 4964 struct timeval tv; 4965 4966 if (wait_data->result == HNS3_WAIT_SUCCESS) 4967 return 0; 4968 else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 4969 gettimeofday(&tv, NULL); 4970 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 4971 tv.tv_sec, tv.tv_usec); 4972 return -ETIME; 4973 } else if (wait_data->result == HNS3_WAIT_REQUEST) 4974 return -EAGAIN; 4975 4976 wait_data->hns = hns; 4977 wait_data->check_completion = is_pf_reset_done; 4978 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * 4979 HNS3_RESET_WAIT_MS + get_timeofday_ms(); 4980 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; 4981 wait_data->count = HNS3_RESET_WAIT_CNT; 4982 wait_data->result = HNS3_WAIT_REQUEST; 4983 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 4984 return -EAGAIN; 4985 } 4986 4987 static int 4988 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id) 4989 { 4990 struct hns3_cmd_desc desc; 4991 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data; 4992 4993 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 4994 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1); 4995 req->fun_reset_vfid = func_id; 4996 4997 return hns3_cmd_send(hw, &desc, 1); 4998 } 4999 5000 static int 5001 hns3_imp_reset_cmd(struct hns3_hw *hw) 5002 { 5003 struct hns3_cmd_desc desc; 5004 5005 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false); 5006 desc.data[0] = 0xeedd; 5007 5008 return hns3_cmd_send(hw, &desc, 1); 5009 } 5010 5011 static void 5012 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) 5013 { 5014 struct hns3_hw *hw = &hns->hw; 5015 struct timeval tv; 5016 uint32_t val; 5017 5018 gettimeofday(&tv, NULL); 5019 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || 5020 hns3_read_dev(hw, HNS3_FUN_RST_ING)) { 5021 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", 5022 tv.tv_sec, tv.tv_usec); 5023 return; 5024 } 5025 5026 switch (reset_level) { 5027 case HNS3_IMP_RESET: 5028 hns3_imp_reset_cmd(hw); 5029 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld", 5030 tv.tv_sec, tv.tv_usec); 5031 break; 5032 case HNS3_GLOBAL_RESET: 5033 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG); 5034 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1); 5035 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val); 5036 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld", 5037 tv.tv_sec, tv.tv_usec); 5038 break; 5039 case HNS3_FUNC_RESET: 5040 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld", 5041 tv.tv_sec, tv.tv_usec); 5042 /* schedule again to check later */ 5043 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending); 5044 hns3_schedule_reset(hns); 5045 break; 5046 default: 5047 hns3_warn(hw, "Unsupported reset level: %d", reset_level); 5048 return; 5049 } 5050 hns3_atomic_clear_bit(reset_level, &hw->reset.request); 5051 } 5052 5053 static enum hns3_reset_level 5054 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) 5055 { 5056 struct hns3_hw *hw = &hns->hw; 5057 enum hns3_reset_level reset_level = HNS3_NONE_RESET; 5058 5059 /* Return the highest priority reset level amongst all */ 5060 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels)) 5061 reset_level = HNS3_IMP_RESET; 5062 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels)) 5063 reset_level = HNS3_GLOBAL_RESET; 5064 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels)) 5065 reset_level = HNS3_FUNC_RESET; 5066 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 5067 reset_level = HNS3_FLR_RESET; 5068 5069 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 5070 return HNS3_NONE_RESET; 5071 5072 return reset_level; 5073 } 5074 5075 static int 5076 hns3_prepare_reset(struct hns3_adapter *hns) 5077 { 5078 struct hns3_hw *hw = &hns->hw; 5079 uint32_t reg_val; 5080 int ret; 5081 5082 switch (hw->reset.level) { 5083 case HNS3_FUNC_RESET: 5084 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID); 5085 if (ret) 5086 return ret; 5087 5088 /* 5089 * After performaning pf reset, it is not necessary to do the 5090 * mailbox handling or send any command to firmware, because 5091 * any mailbox handling or command to firmware is only valid 5092 * after hns3_cmd_init is called. 5093 */ 5094 rte_atomic16_set(&hw->reset.disable_cmd, 1); 5095 hw->reset.stats.request_cnt++; 5096 break; 5097 case HNS3_IMP_RESET: 5098 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5099 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val | 5100 BIT(HNS3_VECTOR0_IMP_RESET_INT_B)); 5101 break; 5102 default: 5103 break; 5104 } 5105 return 0; 5106 } 5107 5108 static int 5109 hns3_set_rst_done(struct hns3_hw *hw) 5110 { 5111 struct hns3_pf_rst_done_cmd *req; 5112 struct hns3_cmd_desc desc; 5113 5114 req = (struct hns3_pf_rst_done_cmd *)desc.data; 5115 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false); 5116 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT; 5117 return hns3_cmd_send(hw, &desc, 1); 5118 } 5119 5120 static int 5121 hns3_stop_service(struct hns3_adapter *hns) 5122 { 5123 struct hns3_hw *hw = &hns->hw; 5124 struct rte_eth_dev *eth_dev; 5125 5126 eth_dev = &rte_eth_devices[hw->data->port_id]; 5127 if (hw->adapter_state == HNS3_NIC_STARTED) 5128 rte_eal_alarm_cancel(hns3_service_handler, eth_dev); 5129 hw->mac.link_status = ETH_LINK_DOWN; 5130 5131 hns3_set_rxtx_function(eth_dev); 5132 rte_wmb(); 5133 /* Disable datapath on secondary process. */ 5134 hns3_mp_req_stop_rxtx(eth_dev); 5135 rte_delay_ms(hw->tqps_num); 5136 5137 rte_spinlock_lock(&hw->lock); 5138 if (hns->hw.adapter_state == HNS3_NIC_STARTED || 5139 hw->adapter_state == HNS3_NIC_STOPPING) { 5140 hns3_do_stop(hns); 5141 hw->reset.mbuf_deferred_free = true; 5142 } else 5143 hw->reset.mbuf_deferred_free = false; 5144 5145 /* 5146 * It is cumbersome for hardware to pick-and-choose entries for deletion 5147 * from table space. Hence, for function reset software intervention is 5148 * required to delete the entries 5149 */ 5150 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) 5151 hns3_configure_all_mc_mac_addr(hns, true); 5152 rte_spinlock_unlock(&hw->lock); 5153 5154 return 0; 5155 } 5156 5157 static int 5158 hns3_start_service(struct hns3_adapter *hns) 5159 { 5160 struct hns3_hw *hw = &hns->hw; 5161 struct rte_eth_dev *eth_dev; 5162 5163 if (hw->reset.level == HNS3_IMP_RESET || 5164 hw->reset.level == HNS3_GLOBAL_RESET) 5165 hns3_set_rst_done(hw); 5166 eth_dev = &rte_eth_devices[hw->data->port_id]; 5167 hns3_set_rxtx_function(eth_dev); 5168 hns3_mp_req_start_rxtx(eth_dev); 5169 if (hw->adapter_state == HNS3_NIC_STARTED) { 5170 hns3_service_handler(eth_dev); 5171 5172 /* Enable interrupt of all rx queues before enabling queues */ 5173 hns3_dev_all_rx_queue_intr_enable(hw, true); 5174 /* 5175 * When finished the initialization, enable queues to receive 5176 * and transmit packets. 5177 */ 5178 hns3_enable_all_queues(hw, true); 5179 } 5180 5181 return 0; 5182 } 5183 5184 static int 5185 hns3_restore_conf(struct hns3_adapter *hns) 5186 { 5187 struct hns3_hw *hw = &hns->hw; 5188 int ret; 5189 5190 ret = hns3_configure_all_mac_addr(hns, false); 5191 if (ret) 5192 return ret; 5193 5194 ret = hns3_configure_all_mc_mac_addr(hns, false); 5195 if (ret) 5196 goto err_mc_mac; 5197 5198 ret = hns3_dev_promisc_restore(hns); 5199 if (ret) 5200 goto err_promisc; 5201 5202 ret = hns3_restore_vlan_table(hns); 5203 if (ret) 5204 goto err_promisc; 5205 5206 ret = hns3_restore_vlan_conf(hns); 5207 if (ret) 5208 goto err_promisc; 5209 5210 ret = hns3_restore_all_fdir_filter(hns); 5211 if (ret) 5212 goto err_promisc; 5213 5214 ret = hns3_restore_rx_interrupt(hw); 5215 if (ret) 5216 goto err_promisc; 5217 5218 if (hns->hw.adapter_state == HNS3_NIC_STARTED) { 5219 ret = hns3_do_start(hns, false); 5220 if (ret) 5221 goto err_promisc; 5222 hns3_info(hw, "hns3 dev restart successful!"); 5223 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 5224 hw->adapter_state = HNS3_NIC_CONFIGURED; 5225 return 0; 5226 5227 err_promisc: 5228 hns3_configure_all_mc_mac_addr(hns, true); 5229 err_mc_mac: 5230 hns3_configure_all_mac_addr(hns, true); 5231 return ret; 5232 } 5233 5234 static void 5235 hns3_reset_service(void *param) 5236 { 5237 struct hns3_adapter *hns = (struct hns3_adapter *)param; 5238 struct hns3_hw *hw = &hns->hw; 5239 enum hns3_reset_level reset_level; 5240 struct timeval tv_delta; 5241 struct timeval tv_start; 5242 struct timeval tv; 5243 uint64_t msec; 5244 int ret; 5245 5246 /* 5247 * The interrupt is not triggered within the delay time. 5248 * The interrupt may have been lost. It is necessary to handle 5249 * the interrupt to recover from the error. 5250 */ 5251 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) { 5252 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED); 5253 hns3_err(hw, "Handling interrupts in delayed tasks"); 5254 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 5255 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 5256 if (reset_level == HNS3_NONE_RESET) { 5257 hns3_err(hw, "No reset level is set, try IMP reset"); 5258 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 5259 } 5260 } 5261 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE); 5262 5263 /* 5264 * Check if there is any ongoing reset in the hardware. This status can 5265 * be checked from reset_pending. If there is then, we need to wait for 5266 * hardware to complete reset. 5267 * a. If we are able to figure out in reasonable time that hardware 5268 * has fully resetted then, we can proceed with driver, client 5269 * reset. 5270 * b. else, we can come back later to check this status so re-sched 5271 * now. 5272 */ 5273 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 5274 if (reset_level != HNS3_NONE_RESET) { 5275 gettimeofday(&tv_start, NULL); 5276 ret = hns3_reset_process(hns, reset_level); 5277 gettimeofday(&tv, NULL); 5278 timersub(&tv, &tv_start, &tv_delta); 5279 msec = tv_delta.tv_sec * MSEC_PER_SEC + 5280 tv_delta.tv_usec / USEC_PER_MSEC; 5281 if (msec > HNS3_RESET_PROCESS_MS) 5282 hns3_err(hw, "%d handle long time delta %" PRIx64 5283 " ms time=%ld.%.6ld", 5284 hw->reset.level, msec, 5285 tv.tv_sec, tv.tv_usec); 5286 if (ret == -EAGAIN) 5287 return; 5288 } 5289 5290 /* Check if we got any *new* reset requests to be honored */ 5291 reset_level = hns3_get_reset_level(hns, &hw->reset.request); 5292 if (reset_level != HNS3_NONE_RESET) 5293 hns3_msix_process(hns, reset_level); 5294 } 5295 5296 static const struct eth_dev_ops hns3_eth_dev_ops = { 5297 .dev_start = hns3_dev_start, 5298 .dev_stop = hns3_dev_stop, 5299 .dev_close = hns3_dev_close, 5300 .promiscuous_enable = hns3_dev_promiscuous_enable, 5301 .promiscuous_disable = hns3_dev_promiscuous_disable, 5302 .allmulticast_enable = hns3_dev_allmulticast_enable, 5303 .allmulticast_disable = hns3_dev_allmulticast_disable, 5304 .mtu_set = hns3_dev_mtu_set, 5305 .stats_get = hns3_stats_get, 5306 .stats_reset = hns3_stats_reset, 5307 .xstats_get = hns3_dev_xstats_get, 5308 .xstats_get_names = hns3_dev_xstats_get_names, 5309 .xstats_reset = hns3_dev_xstats_reset, 5310 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 5311 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 5312 .dev_infos_get = hns3_dev_infos_get, 5313 .fw_version_get = hns3_fw_version_get, 5314 .rx_queue_setup = hns3_rx_queue_setup, 5315 .tx_queue_setup = hns3_tx_queue_setup, 5316 .rx_queue_release = hns3_dev_rx_queue_release, 5317 .tx_queue_release = hns3_dev_tx_queue_release, 5318 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 5319 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 5320 .dev_configure = hns3_dev_configure, 5321 .flow_ctrl_get = hns3_flow_ctrl_get, 5322 .flow_ctrl_set = hns3_flow_ctrl_set, 5323 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set, 5324 .mac_addr_add = hns3_add_mac_addr, 5325 .mac_addr_remove = hns3_remove_mac_addr, 5326 .mac_addr_set = hns3_set_default_mac_addr, 5327 .set_mc_addr_list = hns3_set_mc_mac_addr_list, 5328 .link_update = hns3_dev_link_update, 5329 .rss_hash_update = hns3_dev_rss_hash_update, 5330 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 5331 .reta_update = hns3_dev_rss_reta_update, 5332 .reta_query = hns3_dev_rss_reta_query, 5333 .filter_ctrl = hns3_dev_filter_ctrl, 5334 .vlan_filter_set = hns3_vlan_filter_set, 5335 .vlan_tpid_set = hns3_vlan_tpid_set, 5336 .vlan_offload_set = hns3_vlan_offload_set, 5337 .vlan_pvid_set = hns3_vlan_pvid_set, 5338 .get_reg = hns3_get_regs, 5339 .get_dcb_info = hns3_get_dcb_info, 5340 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 5341 }; 5342 5343 static const struct hns3_reset_ops hns3_reset_ops = { 5344 .reset_service = hns3_reset_service, 5345 .stop_service = hns3_stop_service, 5346 .prepare_reset = hns3_prepare_reset, 5347 .wait_hardware_ready = hns3_wait_hardware_ready, 5348 .reinit_dev = hns3_reinit_dev, 5349 .restore_conf = hns3_restore_conf, 5350 .start_service = hns3_start_service, 5351 }; 5352 5353 static int 5354 hns3_dev_init(struct rte_eth_dev *eth_dev) 5355 { 5356 struct rte_device *dev = eth_dev->device; 5357 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 5358 struct hns3_adapter *hns = eth_dev->data->dev_private; 5359 struct hns3_hw *hw = &hns->hw; 5360 uint16_t device_id = pci_dev->id.device_id; 5361 uint8_t revision; 5362 int ret; 5363 5364 PMD_INIT_FUNC_TRACE(); 5365 5366 /* Get PCI revision id */ 5367 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 5368 HNS3_PCI_REVISION_ID); 5369 if (ret != HNS3_PCI_REVISION_ID_LEN) { 5370 PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d", 5371 ret); 5372 return -EIO; 5373 } 5374 hw->revision = revision; 5375 5376 eth_dev->process_private = (struct hns3_process_private *) 5377 rte_zmalloc_socket("hns3_filter_list", 5378 sizeof(struct hns3_process_private), 5379 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 5380 if (eth_dev->process_private == NULL) { 5381 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 5382 return -ENOMEM; 5383 } 5384 /* initialize flow filter lists */ 5385 hns3_filterlist_init(eth_dev); 5386 5387 hns3_set_rxtx_function(eth_dev); 5388 eth_dev->dev_ops = &hns3_eth_dev_ops; 5389 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 5390 hns3_mp_init_secondary(); 5391 hw->secondary_cnt++; 5392 return 0; 5393 } 5394 5395 hns3_mp_init_primary(); 5396 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 5397 5398 if (device_id == HNS3_DEV_ID_25GE_RDMA || 5399 device_id == HNS3_DEV_ID_50GE_RDMA || 5400 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC) 5401 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1); 5402 5403 hns->is_vf = false; 5404 hw->data = eth_dev->data; 5405 5406 /* 5407 * Set default max packet size according to the mtu 5408 * default vale in DPDK frame. 5409 */ 5410 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD; 5411 5412 ret = hns3_reset_init(hw); 5413 if (ret) 5414 goto err_init_reset; 5415 hw->reset.ops = &hns3_reset_ops; 5416 5417 ret = hns3_init_pf(eth_dev); 5418 if (ret) { 5419 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret); 5420 goto err_init_pf; 5421 } 5422 5423 /* Allocate memory for storing MAC addresses */ 5424 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac", 5425 sizeof(struct rte_ether_addr) * 5426 HNS3_UC_MACADDR_NUM, 0); 5427 if (eth_dev->data->mac_addrs == NULL) { 5428 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 5429 "to store MAC addresses", 5430 sizeof(struct rte_ether_addr) * 5431 HNS3_UC_MACADDR_NUM); 5432 ret = -ENOMEM; 5433 goto err_rte_zmalloc; 5434 } 5435 5436 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 5437 ð_dev->data->mac_addrs[0]); 5438 5439 hw->adapter_state = HNS3_NIC_INITIALIZED; 5440 /* 5441 * Pass the information to the rte_eth_dev_close() that it should also 5442 * release the private port resources. 5443 */ 5444 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 5445 5446 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) { 5447 hns3_err(hw, "Reschedule reset service after dev_init"); 5448 hns3_schedule_reset(hns); 5449 } else { 5450 /* IMP will wait ready flag before reset */ 5451 hns3_notify_reset_ready(hw, false); 5452 } 5453 5454 hns3_info(hw, "hns3 dev initialization successful!"); 5455 return 0; 5456 5457 err_rte_zmalloc: 5458 hns3_uninit_pf(eth_dev); 5459 5460 err_init_pf: 5461 rte_free(hw->reset.wait_data); 5462 err_init_reset: 5463 eth_dev->dev_ops = NULL; 5464 eth_dev->rx_pkt_burst = NULL; 5465 eth_dev->tx_pkt_burst = NULL; 5466 eth_dev->tx_pkt_prepare = NULL; 5467 rte_free(eth_dev->process_private); 5468 eth_dev->process_private = NULL; 5469 return ret; 5470 } 5471 5472 static int 5473 hns3_dev_uninit(struct rte_eth_dev *eth_dev) 5474 { 5475 struct hns3_adapter *hns = eth_dev->data->dev_private; 5476 struct hns3_hw *hw = &hns->hw; 5477 5478 PMD_INIT_FUNC_TRACE(); 5479 5480 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5481 return -EPERM; 5482 5483 eth_dev->dev_ops = NULL; 5484 eth_dev->rx_pkt_burst = NULL; 5485 eth_dev->tx_pkt_burst = NULL; 5486 eth_dev->tx_pkt_prepare = NULL; 5487 if (hw->adapter_state < HNS3_NIC_CLOSING) 5488 hns3_dev_close(eth_dev); 5489 5490 hw->adapter_state = HNS3_NIC_REMOVED; 5491 return 0; 5492 } 5493 5494 static int 5495 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 5496 struct rte_pci_device *pci_dev) 5497 { 5498 return rte_eth_dev_pci_generic_probe(pci_dev, 5499 sizeof(struct hns3_adapter), 5500 hns3_dev_init); 5501 } 5502 5503 static int 5504 eth_hns3_pci_remove(struct rte_pci_device *pci_dev) 5505 { 5506 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit); 5507 } 5508 5509 static const struct rte_pci_id pci_id_hns3_map[] = { 5510 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) }, 5511 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) }, 5512 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) }, 5513 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) }, 5514 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) }, 5515 { .vendor_id = 0, /* sentinel */ }, 5516 }; 5517 5518 static struct rte_pci_driver rte_hns3_pmd = { 5519 .id_table = pci_id_hns3_map, 5520 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 5521 .probe = eth_hns3_pci_probe, 5522 .remove = eth_hns3_pci_remove, 5523 }; 5524 5525 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); 5526 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); 5527 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); 5528 5529 RTE_INIT(hns3_init_log) 5530 { 5531 hns3_logtype_init = rte_log_register("pmd.net.hns3.init"); 5532 if (hns3_logtype_init >= 0) 5533 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE); 5534 hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver"); 5535 if (hns3_logtype_driver >= 0) 5536 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE); 5537 } 5538