1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #include <errno.h> 6 #include <stdarg.h> 7 #include <stdbool.h> 8 #include <stdio.h> 9 #include <stdint.h> 10 #include <inttypes.h> 11 #include <unistd.h> 12 #include <rte_atomic.h> 13 #include <rte_bus_pci.h> 14 #include <rte_common.h> 15 #include <rte_cycles.h> 16 #include <rte_dev.h> 17 #include <rte_eal.h> 18 #include <rte_ether.h> 19 #include <rte_ethdev_driver.h> 20 #include <rte_ethdev_pci.h> 21 #include <rte_interrupts.h> 22 #include <rte_io.h> 23 #include <rte_log.h> 24 #include <rte_pci.h> 25 26 #include "hns3_ethdev.h" 27 #include "hns3_logs.h" 28 #include "hns3_rxtx.h" 29 #include "hns3_intr.h" 30 #include "hns3_regs.h" 31 #include "hns3_dcb.h" 32 #include "hns3_mp.h" 33 34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32 35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1 36 37 #define HNS3_SERVICE_INTERVAL 1000000 /* us */ 38 #define HNS3_INVLID_PVID 0xFFFF 39 40 #define HNS3_FILTER_TYPE_VF 0 41 #define HNS3_FILTER_TYPE_PORT 1 42 #define HNS3_FILTER_FE_EGRESS_V1_B BIT(0) 43 #define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0) 44 #define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1) 45 #define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2) 46 #define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3) 47 #define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \ 48 | HNS3_FILTER_FE_ROCE_EGRESS_B) 49 #define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \ 50 | HNS3_FILTER_FE_ROCE_INGRESS_B) 51 52 /* Reset related Registers */ 53 #define HNS3_GLOBAL_RESET_BIT 0 54 #define HNS3_CORE_RESET_BIT 1 55 #define HNS3_IMP_RESET_BIT 2 56 #define HNS3_FUN_RST_ING_B 0 57 58 #define HNS3_VECTOR0_IMP_RESET_INT_B 1 59 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U 60 #define HNS3_VECTOR0_IMP_RD_POISON_B 5U 61 #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U 62 63 #define HNS3_RESET_WAIT_MS 100 64 #define HNS3_RESET_WAIT_CNT 200 65 66 enum hns3_evt_cause { 67 HNS3_VECTOR0_EVENT_RST, 68 HNS3_VECTOR0_EVENT_MBX, 69 HNS3_VECTOR0_EVENT_ERR, 70 HNS3_VECTOR0_EVENT_OTHER, 71 }; 72 73 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns, 74 uint64_t *levels); 75 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 76 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, 77 int on); 78 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev); 79 80 static int hns3_add_mc_addr(struct hns3_hw *hw, 81 struct rte_ether_addr *mac_addr); 82 static int hns3_remove_mc_addr(struct hns3_hw *hw, 83 struct rte_ether_addr *mac_addr); 84 85 static void 86 hns3_pf_disable_irq0(struct hns3_hw *hw) 87 { 88 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0); 89 } 90 91 static void 92 hns3_pf_enable_irq0(struct hns3_hw *hw) 93 { 94 hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1); 95 } 96 97 static enum hns3_evt_cause 98 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) 99 { 100 struct hns3_hw *hw = &hns->hw; 101 uint32_t vector0_int_stats; 102 uint32_t cmdq_src_val; 103 uint32_t hw_err_src_reg; 104 uint32_t val; 105 enum hns3_evt_cause ret; 106 107 /* fetch the events from their corresponding regs */ 108 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 109 cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); 110 hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 111 112 /* 113 * Assumption: If by any chance reset and mailbox events are reported 114 * together then we will only process reset event and defer the 115 * processing of the mailbox events. Since, we would have not cleared 116 * RX CMDQ event this time we would receive again another interrupt 117 * from H/W just for the mailbox. 118 */ 119 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ 120 rte_atomic16_set(&hw->reset.disable_cmd, 1); 121 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 122 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); 123 if (clearval) { 124 hw->reset.stats.imp_cnt++; 125 hns3_warn(hw, "IMP reset detected, clear reset status"); 126 } else { 127 hns3_schedule_delayed_reset(hns); 128 hns3_warn(hw, "IMP reset detected, don't clear reset status"); 129 } 130 131 ret = HNS3_VECTOR0_EVENT_RST; 132 goto out; 133 } 134 135 /* Global reset */ 136 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { 137 rte_atomic16_set(&hw->reset.disable_cmd, 1); 138 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); 139 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); 140 if (clearval) { 141 hw->reset.stats.global_cnt++; 142 hns3_warn(hw, "Global reset detected, clear reset status"); 143 } else { 144 hns3_schedule_delayed_reset(hns); 145 hns3_warn(hw, "Global reset detected, don't clear reset status"); 146 } 147 148 ret = HNS3_VECTOR0_EVENT_RST; 149 goto out; 150 } 151 152 /* check for vector0 msix event source */ 153 if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK || 154 hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) { 155 val = vector0_int_stats | hw_err_src_reg; 156 ret = HNS3_VECTOR0_EVENT_ERR; 157 goto out; 158 } 159 160 /* check for vector0 mailbox(=CMDQ RX) event source */ 161 if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) { 162 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B); 163 val = cmdq_src_val; 164 ret = HNS3_VECTOR0_EVENT_MBX; 165 goto out; 166 } 167 168 if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg)) 169 hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x", 170 vector0_int_stats, cmdq_src_val, hw_err_src_reg); 171 val = vector0_int_stats; 172 ret = HNS3_VECTOR0_EVENT_OTHER; 173 out: 174 175 if (clearval) 176 *clearval = val; 177 return ret; 178 } 179 180 static void 181 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) 182 { 183 if (event_type == HNS3_VECTOR0_EVENT_RST) 184 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr); 185 else if (event_type == HNS3_VECTOR0_EVENT_MBX) 186 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr); 187 } 188 189 static void 190 hns3_clear_all_event_cause(struct hns3_hw *hw) 191 { 192 uint32_t vector0_int_stats; 193 vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); 194 195 if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) 196 hns3_warn(hw, "Probe during IMP reset interrupt"); 197 198 if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) 199 hns3_warn(hw, "Probe during Global reset interrupt"); 200 201 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST, 202 BIT(HNS3_VECTOR0_IMPRESET_INT_B) | 203 BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | 204 BIT(HNS3_VECTOR0_CORERESET_INT_B)); 205 hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); 206 } 207 208 static void 209 hns3_interrupt_handler(void *param) 210 { 211 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 212 struct hns3_adapter *hns = dev->data->dev_private; 213 struct hns3_hw *hw = &hns->hw; 214 enum hns3_evt_cause event_cause; 215 uint32_t clearval = 0; 216 217 /* Disable interrupt */ 218 hns3_pf_disable_irq0(hw); 219 220 event_cause = hns3_check_event_cause(hns, &clearval); 221 222 /* vector 0 interrupt is shared with reset and mailbox source events. */ 223 if (event_cause == HNS3_VECTOR0_EVENT_ERR) { 224 hns3_warn(hw, "Received err interrupt"); 225 hns3_handle_msix_error(hns, &hw->reset.request); 226 hns3_handle_ras_error(hns, &hw->reset.request); 227 hns3_schedule_reset(hns); 228 } else if (event_cause == HNS3_VECTOR0_EVENT_RST) { 229 hns3_warn(hw, "Received reset interrupt"); 230 hns3_schedule_reset(hns); 231 } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) 232 hns3_dev_handle_mbx_msg(hw); 233 else 234 hns3_err(hw, "Received unknown event"); 235 236 hns3_clear_event_cause(hw, event_cause, clearval); 237 /* Enable interrupt if it is not cause by reset */ 238 hns3_pf_enable_irq0(hw); 239 } 240 241 static int 242 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on) 243 { 244 #define HNS3_VLAN_ID_OFFSET_STEP 160 245 #define HNS3_VLAN_BYTE_SIZE 8 246 struct hns3_vlan_filter_pf_cfg_cmd *req; 247 struct hns3_hw *hw = &hns->hw; 248 uint8_t vlan_offset_byte_val; 249 struct hns3_cmd_desc desc; 250 uint8_t vlan_offset_byte; 251 uint8_t vlan_offset_base; 252 int ret; 253 254 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false); 255 256 vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP; 257 vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) / 258 HNS3_VLAN_BYTE_SIZE; 259 vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE); 260 261 req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data; 262 req->vlan_offset = vlan_offset_base; 263 req->vlan_cfg = on ? 0 : 1; 264 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; 265 266 ret = hns3_cmd_send(hw, &desc, 1); 267 if (ret) 268 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d", 269 vlan_id, ret); 270 271 return ret; 272 } 273 274 static void 275 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id) 276 { 277 struct hns3_user_vlan_table *vlan_entry; 278 struct hns3_pf *pf = &hns->pf; 279 280 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 281 if (vlan_entry->vlan_id == vlan_id) { 282 if (vlan_entry->hd_tbl_status) 283 hns3_set_port_vlan_filter(hns, vlan_id, 0); 284 LIST_REMOVE(vlan_entry, next); 285 rte_free(vlan_entry); 286 break; 287 } 288 } 289 } 290 291 static void 292 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id, 293 bool writen_to_tbl) 294 { 295 struct hns3_user_vlan_table *vlan_entry; 296 struct hns3_hw *hw = &hns->hw; 297 struct hns3_pf *pf = &hns->pf; 298 299 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 300 if (vlan_entry->vlan_id == vlan_id) 301 return; 302 } 303 304 vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0); 305 if (vlan_entry == NULL) { 306 hns3_err(hw, "Failed to malloc hns3 vlan table"); 307 return; 308 } 309 310 vlan_entry->hd_tbl_status = writen_to_tbl; 311 vlan_entry->vlan_id = vlan_id; 312 313 LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next); 314 } 315 316 static int 317 hns3_restore_vlan_table(struct hns3_adapter *hns) 318 { 319 struct hns3_user_vlan_table *vlan_entry; 320 struct hns3_hw *hw = &hns->hw; 321 struct hns3_pf *pf = &hns->pf; 322 uint16_t vlan_id; 323 int ret = 0; 324 325 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) 326 return hns3_vlan_pvid_configure(hns, 327 hw->port_base_vlan_cfg.pvid, 1); 328 329 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 330 if (vlan_entry->hd_tbl_status) { 331 vlan_id = vlan_entry->vlan_id; 332 ret = hns3_set_port_vlan_filter(hns, vlan_id, 1); 333 if (ret) 334 break; 335 } 336 } 337 338 return ret; 339 } 340 341 static int 342 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on) 343 { 344 struct hns3_hw *hw = &hns->hw; 345 bool writen_to_tbl = false; 346 int ret = 0; 347 348 /* 349 * When vlan filter is enabled, hardware regards vlan id 0 as the entry 350 * for normal packet, deleting vlan id 0 is not allowed. 351 */ 352 if (on == 0 && vlan_id == 0) 353 return 0; 354 355 /* 356 * When port base vlan enabled, we use port base vlan as the vlan 357 * filter condition. In this case, we don't update vlan filter table 358 * when user add new vlan or remove exist vlan, just update the 359 * vlan list. The vlan id in vlan list will be writen in vlan filter 360 * table until port base vlan disabled 361 */ 362 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 363 ret = hns3_set_port_vlan_filter(hns, vlan_id, on); 364 writen_to_tbl = true; 365 } 366 367 if (ret == 0 && vlan_id) { 368 if (on) 369 hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl); 370 else 371 hns3_rm_dev_vlan_table(hns, vlan_id); 372 } 373 return ret; 374 } 375 376 static int 377 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 378 { 379 struct hns3_adapter *hns = dev->data->dev_private; 380 struct hns3_hw *hw = &hns->hw; 381 int ret; 382 383 rte_spinlock_lock(&hw->lock); 384 ret = hns3_vlan_filter_configure(hns, vlan_id, on); 385 rte_spinlock_unlock(&hw->lock); 386 return ret; 387 } 388 389 static int 390 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type, 391 uint16_t tpid) 392 { 393 struct hns3_rx_vlan_type_cfg_cmd *rx_req; 394 struct hns3_tx_vlan_type_cfg_cmd *tx_req; 395 struct hns3_hw *hw = &hns->hw; 396 struct hns3_cmd_desc desc; 397 int ret; 398 399 if ((vlan_type != ETH_VLAN_TYPE_INNER && 400 vlan_type != ETH_VLAN_TYPE_OUTER)) { 401 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type); 402 return -EINVAL; 403 } 404 405 if (tpid != RTE_ETHER_TYPE_VLAN) { 406 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type); 407 return -EINVAL; 408 } 409 410 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false); 411 rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data; 412 413 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 414 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 415 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 416 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 417 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid); 418 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid); 419 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid); 420 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid); 421 } 422 423 ret = hns3_cmd_send(hw, &desc, 1); 424 if (ret) { 425 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d", 426 ret); 427 return ret; 428 } 429 430 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false); 431 432 tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data; 433 tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid); 434 tx_req->in_vlan_type = rte_cpu_to_le_16(tpid); 435 436 ret = hns3_cmd_send(hw, &desc, 1); 437 if (ret) 438 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d", 439 ret); 440 return ret; 441 } 442 443 static int 444 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 445 uint16_t tpid) 446 { 447 struct hns3_adapter *hns = dev->data->dev_private; 448 struct hns3_hw *hw = &hns->hw; 449 int ret; 450 451 rte_spinlock_lock(&hw->lock); 452 ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid); 453 rte_spinlock_unlock(&hw->lock); 454 return ret; 455 } 456 457 static int 458 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns, 459 struct hns3_rx_vtag_cfg *vcfg) 460 { 461 struct hns3_vport_vtag_rx_cfg_cmd *req; 462 struct hns3_hw *hw = &hns->hw; 463 struct hns3_cmd_desc desc; 464 uint16_t vport_id; 465 uint8_t bitmap; 466 int ret; 467 468 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false); 469 470 req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data; 471 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B, 472 vcfg->strip_tag1_en ? 1 : 0); 473 hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B, 474 vcfg->strip_tag2_en ? 1 : 0); 475 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B, 476 vcfg->vlan1_vlan_prionly ? 1 : 0); 477 hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B, 478 vcfg->vlan2_vlan_prionly ? 1 : 0); 479 480 /* 481 * In current version VF is not supported when PF is driven by DPDK 482 * driver, just need to configure parameters for PF vport. 483 */ 484 vport_id = HNS3_PF_FUNC_ID; 485 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 486 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 487 req->vf_bitmap[req->vf_offset] = bitmap; 488 489 ret = hns3_cmd_send(hw, &desc, 1); 490 if (ret) 491 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret); 492 return ret; 493 } 494 495 static void 496 hns3_update_rx_offload_cfg(struct hns3_adapter *hns, 497 struct hns3_rx_vtag_cfg *vcfg) 498 { 499 struct hns3_pf *pf = &hns->pf; 500 memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg)); 501 } 502 503 static void 504 hns3_update_tx_offload_cfg(struct hns3_adapter *hns, 505 struct hns3_tx_vtag_cfg *vcfg) 506 { 507 struct hns3_pf *pf = &hns->pf; 508 memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg)); 509 } 510 511 static int 512 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable) 513 { 514 struct hns3_rx_vtag_cfg rxvlan_cfg; 515 struct hns3_hw *hw = &hns->hw; 516 int ret; 517 518 if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) { 519 rxvlan_cfg.strip_tag1_en = false; 520 rxvlan_cfg.strip_tag2_en = enable; 521 } else { 522 rxvlan_cfg.strip_tag1_en = enable; 523 rxvlan_cfg.strip_tag2_en = true; 524 } 525 526 rxvlan_cfg.vlan1_vlan_prionly = false; 527 rxvlan_cfg.vlan2_vlan_prionly = false; 528 rxvlan_cfg.rx_vlan_offload_en = enable; 529 530 ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg); 531 if (ret) { 532 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret); 533 return ret; 534 } 535 536 hns3_update_rx_offload_cfg(hns, &rxvlan_cfg); 537 538 return ret; 539 } 540 541 static int 542 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type, 543 uint8_t fe_type, bool filter_en, uint8_t vf_id) 544 { 545 struct hns3_vlan_filter_ctrl_cmd *req; 546 struct hns3_cmd_desc desc; 547 int ret; 548 549 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false); 550 551 req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data; 552 req->vlan_type = vlan_type; 553 req->vlan_fe = filter_en ? fe_type : 0; 554 req->vf_id = vf_id; 555 556 ret = hns3_cmd_send(hw, &desc, 1); 557 if (ret) 558 hns3_err(hw, "set vlan filter fail, ret =%d", ret); 559 560 return ret; 561 } 562 563 static int 564 hns3_vlan_filter_init(struct hns3_adapter *hns) 565 { 566 struct hns3_hw *hw = &hns->hw; 567 int ret; 568 569 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF, 570 HNS3_FILTER_FE_EGRESS, false, 571 HNS3_PF_FUNC_ID); 572 if (ret) { 573 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret); 574 return ret; 575 } 576 577 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 578 HNS3_FILTER_FE_INGRESS, false, 579 HNS3_PF_FUNC_ID); 580 if (ret) 581 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret); 582 583 return ret; 584 } 585 586 static int 587 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable) 588 { 589 struct hns3_hw *hw = &hns->hw; 590 int ret; 591 592 ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT, 593 HNS3_FILTER_FE_INGRESS, enable, 594 HNS3_PF_FUNC_ID); 595 if (ret) 596 hns3_err(hw, "failed to %s port vlan filter, ret = %d", 597 enable ? "enable" : "disable", ret); 598 599 return ret; 600 } 601 602 static int 603 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask) 604 { 605 struct hns3_adapter *hns = dev->data->dev_private; 606 struct hns3_hw *hw = &hns->hw; 607 struct rte_eth_rxmode *rxmode; 608 unsigned int tmp_mask; 609 bool enable; 610 int ret = 0; 611 612 rte_spinlock_lock(&hw->lock); 613 rxmode = &dev->data->dev_conf.rxmode; 614 tmp_mask = (unsigned int)mask; 615 if (tmp_mask & ETH_VLAN_FILTER_MASK) { 616 /* ignore vlan filter configuration during promiscuous mode */ 617 if (!dev->data->promiscuous) { 618 /* Enable or disable VLAN filter */ 619 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? 620 true : false; 621 622 ret = hns3_enable_vlan_filter(hns, enable); 623 if (ret) { 624 rte_spinlock_unlock(&hw->lock); 625 hns3_err(hw, "failed to %s rx filter, ret = %d", 626 enable ? "enable" : "disable", ret); 627 return ret; 628 } 629 } 630 } 631 632 if (tmp_mask & ETH_VLAN_STRIP_MASK) { 633 /* Enable or disable VLAN stripping */ 634 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? 635 true : false; 636 637 ret = hns3_en_hw_strip_rxvtag(hns, enable); 638 if (ret) { 639 rte_spinlock_unlock(&hw->lock); 640 hns3_err(hw, "failed to %s rx strip, ret = %d", 641 enable ? "enable" : "disable", ret); 642 return ret; 643 } 644 } 645 646 rte_spinlock_unlock(&hw->lock); 647 648 return ret; 649 } 650 651 static int 652 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns, 653 struct hns3_tx_vtag_cfg *vcfg) 654 { 655 struct hns3_vport_vtag_tx_cfg_cmd *req; 656 struct hns3_cmd_desc desc; 657 struct hns3_hw *hw = &hns->hw; 658 uint16_t vport_id; 659 uint8_t bitmap; 660 int ret; 661 662 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false); 663 664 req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data; 665 req->def_vlan_tag1 = vcfg->default_tag1; 666 req->def_vlan_tag2 = vcfg->default_tag2; 667 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B, 668 vcfg->accept_tag1 ? 1 : 0); 669 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B, 670 vcfg->accept_untag1 ? 1 : 0); 671 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B, 672 vcfg->accept_tag2 ? 1 : 0); 673 hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B, 674 vcfg->accept_untag2 ? 1 : 0); 675 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B, 676 vcfg->insert_tag1_en ? 1 : 0); 677 hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B, 678 vcfg->insert_tag2_en ? 1 : 0); 679 hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0); 680 681 /* 682 * In current version VF is not supported when PF is driven by DPDK 683 * driver, just need to configure parameters for PF vport. 684 */ 685 vport_id = HNS3_PF_FUNC_ID; 686 req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD; 687 bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE); 688 req->vf_bitmap[req->vf_offset] = bitmap; 689 690 ret = hns3_cmd_send(hw, &desc, 1); 691 if (ret) 692 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret); 693 694 return ret; 695 } 696 697 static int 698 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state, 699 uint16_t pvid) 700 { 701 struct hns3_hw *hw = &hns->hw; 702 struct hns3_tx_vtag_cfg txvlan_cfg; 703 int ret; 704 705 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) { 706 txvlan_cfg.accept_tag1 = true; 707 txvlan_cfg.insert_tag1_en = false; 708 txvlan_cfg.default_tag1 = 0; 709 } else { 710 txvlan_cfg.accept_tag1 = false; 711 txvlan_cfg.insert_tag1_en = true; 712 txvlan_cfg.default_tag1 = pvid; 713 } 714 715 txvlan_cfg.accept_untag1 = true; 716 txvlan_cfg.accept_tag2 = true; 717 txvlan_cfg.accept_untag2 = true; 718 txvlan_cfg.insert_tag2_en = false; 719 txvlan_cfg.default_tag2 = 0; 720 721 ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg); 722 if (ret) { 723 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid, 724 ret); 725 return ret; 726 } 727 728 hns3_update_tx_offload_cfg(hns, &txvlan_cfg); 729 return ret; 730 } 731 732 static void 733 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on) 734 { 735 struct hns3_hw *hw = &hns->hw; 736 737 hw->port_base_vlan_cfg.state = on ? 738 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE; 739 740 hw->port_base_vlan_cfg.pvid = pvid; 741 } 742 743 static void 744 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list) 745 { 746 struct hns3_user_vlan_table *vlan_entry; 747 struct hns3_pf *pf = &hns->pf; 748 749 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 750 if (vlan_entry->hd_tbl_status) 751 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0); 752 753 vlan_entry->hd_tbl_status = false; 754 } 755 756 if (is_del_list) { 757 vlan_entry = LIST_FIRST(&pf->vlan_list); 758 while (vlan_entry) { 759 LIST_REMOVE(vlan_entry, next); 760 rte_free(vlan_entry); 761 vlan_entry = LIST_FIRST(&pf->vlan_list); 762 } 763 } 764 } 765 766 static void 767 hns3_add_all_vlan_table(struct hns3_adapter *hns) 768 { 769 struct hns3_user_vlan_table *vlan_entry; 770 struct hns3_pf *pf = &hns->pf; 771 772 LIST_FOREACH(vlan_entry, &pf->vlan_list, next) { 773 if (!vlan_entry->hd_tbl_status) 774 hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1); 775 776 vlan_entry->hd_tbl_status = true; 777 } 778 } 779 780 static void 781 hns3_remove_all_vlan_table(struct hns3_adapter *hns) 782 { 783 struct hns3_hw *hw = &hns->hw; 784 int ret; 785 786 hns3_rm_all_vlan_table(hns, true); 787 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) { 788 ret = hns3_set_port_vlan_filter(hns, 789 hw->port_base_vlan_cfg.pvid, 0); 790 if (ret) { 791 hns3_err(hw, "Failed to remove all vlan table, ret =%d", 792 ret); 793 return; 794 } 795 } 796 } 797 798 static int 799 hns3_update_vlan_filter_entries(struct hns3_adapter *hns, 800 uint16_t port_base_vlan_state, 801 uint16_t new_pvid, uint16_t old_pvid) 802 { 803 struct hns3_hw *hw = &hns->hw; 804 int ret = 0; 805 806 if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) { 807 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) { 808 ret = hns3_set_port_vlan_filter(hns, old_pvid, 0); 809 if (ret) { 810 hns3_err(hw, 811 "Failed to clear clear old pvid filter, ret =%d", 812 ret); 813 return ret; 814 } 815 } 816 817 hns3_rm_all_vlan_table(hns, false); 818 return hns3_set_port_vlan_filter(hns, new_pvid, 1); 819 } 820 821 if (new_pvid != 0) { 822 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0); 823 if (ret) { 824 hns3_err(hw, "Failed to set port vlan filter, ret =%d", 825 ret); 826 return ret; 827 } 828 } 829 830 if (new_pvid == hw->port_base_vlan_cfg.pvid) 831 hns3_add_all_vlan_table(hns); 832 833 return ret; 834 } 835 836 static int 837 hns3_en_pvid_strip(struct hns3_adapter *hns, int on) 838 { 839 struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg; 840 struct hns3_rx_vtag_cfg rx_vlan_cfg; 841 bool rx_strip_en; 842 int ret; 843 844 rx_strip_en = old_cfg->rx_vlan_offload_en ? true : false; 845 if (on) { 846 rx_vlan_cfg.strip_tag1_en = rx_strip_en; 847 rx_vlan_cfg.strip_tag2_en = true; 848 } else { 849 rx_vlan_cfg.strip_tag1_en = false; 850 rx_vlan_cfg.strip_tag2_en = rx_strip_en; 851 } 852 rx_vlan_cfg.vlan1_vlan_prionly = false; 853 rx_vlan_cfg.vlan2_vlan_prionly = false; 854 rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en; 855 856 ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg); 857 if (ret) 858 return ret; 859 860 hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg); 861 return ret; 862 } 863 864 static int 865 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on) 866 { 867 struct hns3_hw *hw = &hns->hw; 868 uint16_t port_base_vlan_state; 869 uint16_t old_pvid; 870 int ret; 871 872 if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) { 873 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) 874 hns3_warn(hw, "Invalid operation! As current pvid set " 875 "is %u, disable pvid %u is invalid", 876 hw->port_base_vlan_cfg.pvid, pvid); 877 return 0; 878 } 879 880 port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE : 881 HNS3_PORT_BASE_VLAN_DISABLE; 882 ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid); 883 if (ret) { 884 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d", 885 ret); 886 return ret; 887 } 888 889 ret = hns3_en_pvid_strip(hns, on); 890 if (ret) { 891 hns3_err(hw, "failed to config rx vlan strip for pvid, " 892 "ret = %d", ret); 893 return ret; 894 } 895 896 if (pvid == HNS3_INVLID_PVID) 897 goto out; 898 old_pvid = hw->port_base_vlan_cfg.pvid; 899 ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid, 900 old_pvid); 901 if (ret) { 902 hns3_err(hw, "Failed to update vlan filter entries, ret =%d", 903 ret); 904 return ret; 905 } 906 907 out: 908 hns3_store_port_base_vlan_info(hns, pvid, on); 909 return ret; 910 } 911 912 static int 913 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on) 914 { 915 struct hns3_adapter *hns = dev->data->dev_private; 916 struct hns3_hw *hw = &hns->hw; 917 bool pvid_en_state_change; 918 uint16_t pvid_state; 919 int ret; 920 921 if (pvid > RTE_ETHER_MAX_VLAN_ID) { 922 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid, 923 RTE_ETHER_MAX_VLAN_ID); 924 return -EINVAL; 925 } 926 927 /* 928 * If PVID configuration state change, should refresh the PVID 929 * configuration state in struct hns3_tx_queue/hns3_rx_queue. 930 */ 931 pvid_state = hw->port_base_vlan_cfg.state; 932 if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) || 933 (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE)) 934 pvid_en_state_change = false; 935 else 936 pvid_en_state_change = true; 937 938 rte_spinlock_lock(&hw->lock); 939 ret = hns3_vlan_pvid_configure(hns, pvid, on); 940 rte_spinlock_unlock(&hw->lock); 941 if (ret) 942 return ret; 943 944 if (pvid_en_state_change) 945 hns3_update_all_queues_pvid_state(hw); 946 947 return 0; 948 } 949 950 static void 951 init_port_base_vlan_info(struct hns3_hw *hw) 952 { 953 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE; 954 hw->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID; 955 } 956 957 static int 958 hns3_default_vlan_config(struct hns3_adapter *hns) 959 { 960 struct hns3_hw *hw = &hns->hw; 961 int ret; 962 963 ret = hns3_set_port_vlan_filter(hns, 0, 1); 964 if (ret) 965 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret); 966 return ret; 967 } 968 969 static int 970 hns3_init_vlan_config(struct hns3_adapter *hns) 971 { 972 struct hns3_hw *hw = &hns->hw; 973 int ret; 974 975 /* 976 * This function can be called in the initialization and reset process, 977 * when in reset process, it means that hardware had been reseted 978 * successfully and we need to restore the hardware configuration to 979 * ensure that the hardware configuration remains unchanged before and 980 * after reset. 981 */ 982 if (rte_atomic16_read(&hw->reset.resetting) == 0) 983 init_port_base_vlan_info(hw); 984 985 ret = hns3_vlan_filter_init(hns); 986 if (ret) { 987 hns3_err(hw, "vlan init fail in pf, ret =%d", ret); 988 return ret; 989 } 990 991 ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER, 992 RTE_ETHER_TYPE_VLAN); 993 if (ret) { 994 hns3_err(hw, "tpid set fail in pf, ret =%d", ret); 995 return ret; 996 } 997 998 /* 999 * When in the reinit dev stage of the reset process, the following 1000 * vlan-related configurations may differ from those at initialization, 1001 * we will restore configurations to hardware in hns3_restore_vlan_table 1002 * and hns3_restore_vlan_conf later. 1003 */ 1004 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 1005 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0); 1006 if (ret) { 1007 hns3_err(hw, "pvid set fail in pf, ret =%d", ret); 1008 return ret; 1009 } 1010 1011 ret = hns3_en_hw_strip_rxvtag(hns, false); 1012 if (ret) { 1013 hns3_err(hw, "rx strip configure fail in pf, ret =%d", 1014 ret); 1015 return ret; 1016 } 1017 } 1018 1019 return hns3_default_vlan_config(hns); 1020 } 1021 1022 static int 1023 hns3_restore_vlan_conf(struct hns3_adapter *hns) 1024 { 1025 struct hns3_pf *pf = &hns->pf; 1026 struct hns3_hw *hw = &hns->hw; 1027 uint64_t offloads; 1028 bool enable; 1029 int ret; 1030 1031 if (!hw->data->promiscuous) { 1032 /* restore vlan filter states */ 1033 offloads = hw->data->dev_conf.rxmode.offloads; 1034 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false; 1035 ret = hns3_enable_vlan_filter(hns, enable); 1036 if (ret) { 1037 hns3_err(hw, "failed to restore vlan rx filter conf, " 1038 "ret = %d", ret); 1039 return ret; 1040 } 1041 } 1042 1043 ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg); 1044 if (ret) { 1045 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret); 1046 return ret; 1047 } 1048 1049 ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg); 1050 if (ret) 1051 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret); 1052 1053 return ret; 1054 } 1055 1056 static int 1057 hns3_dev_configure_vlan(struct rte_eth_dev *dev) 1058 { 1059 struct hns3_adapter *hns = dev->data->dev_private; 1060 struct rte_eth_dev_data *data = dev->data; 1061 struct rte_eth_txmode *txmode; 1062 struct hns3_hw *hw = &hns->hw; 1063 int mask; 1064 int ret; 1065 1066 txmode = &data->dev_conf.txmode; 1067 if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged) 1068 hns3_warn(hw, 1069 "hw_vlan_reject_tagged or hw_vlan_reject_untagged " 1070 "configuration is not supported! Ignore these two " 1071 "parameters: hw_vlan_reject_tagged(%d), " 1072 "hw_vlan_reject_untagged(%d)", 1073 txmode->hw_vlan_reject_tagged, 1074 txmode->hw_vlan_reject_untagged); 1075 1076 /* Apply vlan offload setting */ 1077 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK; 1078 ret = hns3_vlan_offload_set(dev, mask); 1079 if (ret) { 1080 hns3_err(hw, "dev config rx vlan offload failed, ret = %d", 1081 ret); 1082 return ret; 1083 } 1084 1085 /* 1086 * If pvid config is not set in rte_eth_conf, driver needn't to set 1087 * VLAN pvid related configuration to hardware. 1088 */ 1089 if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0) 1090 return 0; 1091 1092 /* Apply pvid setting */ 1093 ret = hns3_vlan_pvid_set(dev, txmode->pvid, 1094 txmode->hw_vlan_insert_pvid); 1095 if (ret) 1096 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d", 1097 txmode->pvid, ret); 1098 1099 return ret; 1100 } 1101 1102 static int 1103 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min, 1104 unsigned int tso_mss_max) 1105 { 1106 struct hns3_cfg_tso_status_cmd *req; 1107 struct hns3_cmd_desc desc; 1108 uint16_t tso_mss; 1109 1110 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false); 1111 1112 req = (struct hns3_cfg_tso_status_cmd *)desc.data; 1113 1114 tso_mss = 0; 1115 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1116 tso_mss_min); 1117 req->tso_mss_min = rte_cpu_to_le_16(tso_mss); 1118 1119 tso_mss = 0; 1120 hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S, 1121 tso_mss_max); 1122 req->tso_mss_max = rte_cpu_to_le_16(tso_mss); 1123 1124 return hns3_cmd_send(hw, &desc, 1); 1125 } 1126 1127 static int 1128 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size, 1129 uint16_t *allocated_size, bool is_alloc) 1130 { 1131 struct hns3_umv_spc_alc_cmd *req; 1132 struct hns3_cmd_desc desc; 1133 int ret; 1134 1135 req = (struct hns3_umv_spc_alc_cmd *)desc.data; 1136 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false); 1137 hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1); 1138 req->space_size = rte_cpu_to_le_32(space_size); 1139 1140 ret = hns3_cmd_send(hw, &desc, 1); 1141 if (ret) { 1142 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d", 1143 is_alloc ? "allocate" : "free", ret); 1144 return ret; 1145 } 1146 1147 if (is_alloc && allocated_size) 1148 *allocated_size = rte_le_to_cpu_32(desc.data[1]); 1149 1150 return 0; 1151 } 1152 1153 static int 1154 hns3_init_umv_space(struct hns3_hw *hw) 1155 { 1156 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1157 struct hns3_pf *pf = &hns->pf; 1158 uint16_t allocated_size = 0; 1159 int ret; 1160 1161 ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size, 1162 true); 1163 if (ret) 1164 return ret; 1165 1166 if (allocated_size < pf->wanted_umv_size) 1167 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u", 1168 pf->wanted_umv_size, allocated_size); 1169 1170 pf->max_umv_size = (!!allocated_size) ? allocated_size : 1171 pf->wanted_umv_size; 1172 pf->used_umv_size = 0; 1173 return 0; 1174 } 1175 1176 static int 1177 hns3_uninit_umv_space(struct hns3_hw *hw) 1178 { 1179 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1180 struct hns3_pf *pf = &hns->pf; 1181 int ret; 1182 1183 if (pf->max_umv_size == 0) 1184 return 0; 1185 1186 ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false); 1187 if (ret) 1188 return ret; 1189 1190 pf->max_umv_size = 0; 1191 1192 return 0; 1193 } 1194 1195 static bool 1196 hns3_is_umv_space_full(struct hns3_hw *hw) 1197 { 1198 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1199 struct hns3_pf *pf = &hns->pf; 1200 bool is_full; 1201 1202 is_full = (pf->used_umv_size >= pf->max_umv_size); 1203 1204 return is_full; 1205 } 1206 1207 static void 1208 hns3_update_umv_space(struct hns3_hw *hw, bool is_free) 1209 { 1210 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1211 struct hns3_pf *pf = &hns->pf; 1212 1213 if (is_free) { 1214 if (pf->used_umv_size > 0) 1215 pf->used_umv_size--; 1216 } else 1217 pf->used_umv_size++; 1218 } 1219 1220 static void 1221 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req, 1222 const uint8_t *addr, bool is_mc) 1223 { 1224 const unsigned char *mac_addr = addr; 1225 uint32_t high_val = ((uint32_t)mac_addr[3] << 24) | 1226 ((uint32_t)mac_addr[2] << 16) | 1227 ((uint32_t)mac_addr[1] << 8) | 1228 (uint32_t)mac_addr[0]; 1229 uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4]; 1230 1231 hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1232 if (is_mc) { 1233 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1234 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1); 1235 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1); 1236 } 1237 1238 new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val); 1239 new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff); 1240 } 1241 1242 static int 1243 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp, 1244 uint8_t resp_code, 1245 enum hns3_mac_vlan_tbl_opcode op) 1246 { 1247 if (cmdq_resp) { 1248 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u", 1249 cmdq_resp); 1250 return -EIO; 1251 } 1252 1253 if (op == HNS3_MAC_VLAN_ADD) { 1254 if (resp_code == 0 || resp_code == 1) { 1255 return 0; 1256 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) { 1257 hns3_err(hw, "add mac addr failed for uc_overflow"); 1258 return -ENOSPC; 1259 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) { 1260 hns3_err(hw, "add mac addr failed for mc_overflow"); 1261 return -ENOSPC; 1262 } 1263 1264 hns3_err(hw, "add mac addr failed for undefined, code=%u", 1265 resp_code); 1266 return -EIO; 1267 } else if (op == HNS3_MAC_VLAN_REMOVE) { 1268 if (resp_code == 0) { 1269 return 0; 1270 } else if (resp_code == 1) { 1271 hns3_dbg(hw, "remove mac addr failed for miss"); 1272 return -ENOENT; 1273 } 1274 1275 hns3_err(hw, "remove mac addr failed for undefined, code=%u", 1276 resp_code); 1277 return -EIO; 1278 } else if (op == HNS3_MAC_VLAN_LKUP) { 1279 if (resp_code == 0) { 1280 return 0; 1281 } else if (resp_code == 1) { 1282 hns3_dbg(hw, "lookup mac addr failed for miss"); 1283 return -ENOENT; 1284 } 1285 1286 hns3_err(hw, "lookup mac addr failed for undefined, code=%u", 1287 resp_code); 1288 return -EIO; 1289 } 1290 1291 hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u", 1292 op); 1293 1294 return -EINVAL; 1295 } 1296 1297 static int 1298 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw, 1299 struct hns3_mac_vlan_tbl_entry_cmd *req, 1300 struct hns3_cmd_desc *desc, bool is_mc) 1301 { 1302 uint8_t resp_code; 1303 uint16_t retval; 1304 int ret; 1305 1306 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true); 1307 if (is_mc) { 1308 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1309 memcpy(desc[0].data, req, 1310 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1311 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD, 1312 true); 1313 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1314 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD, 1315 true); 1316 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1317 } else { 1318 memcpy(desc[0].data, req, 1319 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1320 ret = hns3_cmd_send(hw, desc, 1); 1321 } 1322 if (ret) { 1323 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.", 1324 ret); 1325 return ret; 1326 } 1327 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff; 1328 retval = rte_le_to_cpu_16(desc[0].retval); 1329 1330 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1331 HNS3_MAC_VLAN_LKUP); 1332 } 1333 1334 static int 1335 hns3_add_mac_vlan_tbl(struct hns3_hw *hw, 1336 struct hns3_mac_vlan_tbl_entry_cmd *req, 1337 struct hns3_cmd_desc *mc_desc) 1338 { 1339 uint8_t resp_code; 1340 uint16_t retval; 1341 int cfg_status; 1342 int ret; 1343 1344 if (mc_desc == NULL) { 1345 struct hns3_cmd_desc desc; 1346 1347 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false); 1348 memcpy(desc.data, req, 1349 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1350 ret = hns3_cmd_send(hw, &desc, 1); 1351 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1352 retval = rte_le_to_cpu_16(desc.retval); 1353 1354 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1355 HNS3_MAC_VLAN_ADD); 1356 } else { 1357 hns3_cmd_reuse_desc(&mc_desc[0], false); 1358 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1359 hns3_cmd_reuse_desc(&mc_desc[1], false); 1360 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1361 hns3_cmd_reuse_desc(&mc_desc[2], false); 1362 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT); 1363 memcpy(mc_desc[0].data, req, 1364 sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1365 mc_desc[0].retval = 0; 1366 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM); 1367 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff; 1368 retval = rte_le_to_cpu_16(mc_desc[0].retval); 1369 1370 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1371 HNS3_MAC_VLAN_ADD); 1372 } 1373 1374 if (ret) { 1375 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret); 1376 return ret; 1377 } 1378 1379 return cfg_status; 1380 } 1381 1382 static int 1383 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw, 1384 struct hns3_mac_vlan_tbl_entry_cmd *req) 1385 { 1386 struct hns3_cmd_desc desc; 1387 uint8_t resp_code; 1388 uint16_t retval; 1389 int ret; 1390 1391 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false); 1392 1393 memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd)); 1394 1395 ret = hns3_cmd_send(hw, &desc, 1); 1396 if (ret) { 1397 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret); 1398 return ret; 1399 } 1400 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 1401 retval = rte_le_to_cpu_16(desc.retval); 1402 1403 return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code, 1404 HNS3_MAC_VLAN_REMOVE); 1405 } 1406 1407 static int 1408 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1409 { 1410 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 1411 struct hns3_mac_vlan_tbl_entry_cmd req; 1412 struct hns3_pf *pf = &hns->pf; 1413 struct hns3_cmd_desc desc[3]; 1414 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1415 uint16_t egress_port = 0; 1416 uint8_t vf_id; 1417 int ret; 1418 1419 /* check if mac addr is valid */ 1420 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1421 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1422 mac_addr); 1423 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid", 1424 mac_str); 1425 return -EINVAL; 1426 } 1427 1428 memset(&req, 0, sizeof(req)); 1429 1430 /* 1431 * In current version VF is not supported when PF is driven by DPDK 1432 * driver, just need to configure parameters for PF vport. 1433 */ 1434 vf_id = HNS3_PF_FUNC_ID; 1435 hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M, 1436 HNS3_MAC_EPORT_VFID_S, vf_id); 1437 1438 req.egress_port = rte_cpu_to_le_16(egress_port); 1439 1440 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1441 1442 /* 1443 * Lookup the mac address in the mac_vlan table, and add 1444 * it if the entry is inexistent. Repeated unicast entry 1445 * is not allowed in the mac vlan table. 1446 */ 1447 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false); 1448 if (ret == -ENOENT) { 1449 if (!hns3_is_umv_space_full(hw)) { 1450 ret = hns3_add_mac_vlan_tbl(hw, &req, NULL); 1451 if (!ret) 1452 hns3_update_umv_space(hw, false); 1453 return ret; 1454 } 1455 1456 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size); 1457 1458 return -ENOSPC; 1459 } 1460 1461 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr); 1462 1463 /* check if we just hit the duplicate */ 1464 if (ret == 0) { 1465 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str); 1466 return 0; 1467 } 1468 1469 hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table", 1470 mac_str); 1471 1472 return ret; 1473 } 1474 1475 static int 1476 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1477 { 1478 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1479 struct rte_ether_addr *addr; 1480 int ret; 1481 int i; 1482 1483 for (i = 0; i < hw->mc_addrs_num; i++) { 1484 addr = &hw->mc_addrs[i]; 1485 /* Check if there are duplicate addresses */ 1486 if (rte_is_same_ether_addr(addr, mac_addr)) { 1487 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1488 addr); 1489 hns3_err(hw, "failed to add mc mac addr, same addrs" 1490 "(%s) is added by the set_mc_mac_addr_list " 1491 "API", mac_str); 1492 return -EINVAL; 1493 } 1494 } 1495 1496 ret = hns3_add_mc_addr(hw, mac_addr); 1497 if (ret) { 1498 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1499 mac_addr); 1500 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d", 1501 mac_str, ret); 1502 } 1503 return ret; 1504 } 1505 1506 static int 1507 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1508 { 1509 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1510 int ret; 1511 1512 ret = hns3_remove_mc_addr(hw, mac_addr); 1513 if (ret) { 1514 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1515 mac_addr); 1516 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d", 1517 mac_str, ret); 1518 } 1519 return ret; 1520 } 1521 1522 static int 1523 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1524 uint32_t idx, __rte_unused uint32_t pool) 1525 { 1526 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1527 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1528 int ret; 1529 1530 rte_spinlock_lock(&hw->lock); 1531 1532 /* 1533 * In hns3 network engine adding UC and MC mac address with different 1534 * commands with firmware. We need to determine whether the input 1535 * address is a UC or a MC address to call different commands. 1536 * By the way, it is recommended calling the API function named 1537 * rte_eth_dev_set_mc_addr_list to set the MC mac address, because 1538 * using the rte_eth_dev_mac_addr_add API function to set MC mac address 1539 * may affect the specifications of UC mac addresses. 1540 */ 1541 if (rte_is_multicast_ether_addr(mac_addr)) 1542 ret = hns3_add_mc_addr_common(hw, mac_addr); 1543 else 1544 ret = hns3_add_uc_addr_common(hw, mac_addr); 1545 1546 if (ret) { 1547 rte_spinlock_unlock(&hw->lock); 1548 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1549 mac_addr); 1550 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str, 1551 ret); 1552 return ret; 1553 } 1554 1555 if (idx == 0) 1556 hw->mac.default_addr_setted = true; 1557 rte_spinlock_unlock(&hw->lock); 1558 1559 return ret; 1560 } 1561 1562 static int 1563 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1564 { 1565 struct hns3_mac_vlan_tbl_entry_cmd req; 1566 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1567 int ret; 1568 1569 /* check if mac addr is valid */ 1570 if (!rte_is_valid_assigned_ether_addr(mac_addr)) { 1571 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1572 mac_addr); 1573 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid", 1574 mac_str); 1575 return -EINVAL; 1576 } 1577 1578 memset(&req, 0, sizeof(req)); 1579 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1580 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false); 1581 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1582 if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */ 1583 return 0; 1584 else if (ret == 0) 1585 hns3_update_umv_space(hw, true); 1586 1587 return ret; 1588 } 1589 1590 static void 1591 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx) 1592 { 1593 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1594 /* index will be checked by upper level rte interface */ 1595 struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx]; 1596 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1597 int ret; 1598 1599 rte_spinlock_lock(&hw->lock); 1600 1601 if (rte_is_multicast_ether_addr(mac_addr)) 1602 ret = hns3_remove_mc_addr_common(hw, mac_addr); 1603 else 1604 ret = hns3_remove_uc_addr_common(hw, mac_addr); 1605 rte_spinlock_unlock(&hw->lock); 1606 if (ret) { 1607 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1608 mac_addr); 1609 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str, 1610 ret); 1611 } 1612 } 1613 1614 static int 1615 hns3_set_default_mac_addr(struct rte_eth_dev *dev, 1616 struct rte_ether_addr *mac_addr) 1617 { 1618 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1619 struct rte_ether_addr *oaddr; 1620 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1621 bool default_addr_setted; 1622 bool rm_succes = false; 1623 int ret, ret_val; 1624 1625 /* 1626 * It has been guaranteed that input parameter named mac_addr is valid 1627 * address in the rte layer of DPDK framework. 1628 */ 1629 oaddr = (struct rte_ether_addr *)hw->mac.mac_addr; 1630 default_addr_setted = hw->mac.default_addr_setted; 1631 if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr)) 1632 return 0; 1633 1634 rte_spinlock_lock(&hw->lock); 1635 if (default_addr_setted) { 1636 ret = hns3_remove_uc_addr_common(hw, oaddr); 1637 if (ret) { 1638 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1639 oaddr); 1640 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d", 1641 mac_str, ret); 1642 rm_succes = false; 1643 } else 1644 rm_succes = true; 1645 } 1646 1647 ret = hns3_add_uc_addr_common(hw, mac_addr); 1648 if (ret) { 1649 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1650 mac_addr); 1651 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret); 1652 goto err_add_uc_addr; 1653 } 1654 1655 ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes); 1656 if (ret) { 1657 hns3_err(hw, "Failed to configure mac pause address: %d", ret); 1658 goto err_pause_addr_cfg; 1659 } 1660 1661 rte_ether_addr_copy(mac_addr, 1662 (struct rte_ether_addr *)hw->mac.mac_addr); 1663 hw->mac.default_addr_setted = true; 1664 rte_spinlock_unlock(&hw->lock); 1665 1666 return 0; 1667 1668 err_pause_addr_cfg: 1669 ret_val = hns3_remove_uc_addr_common(hw, mac_addr); 1670 if (ret_val) { 1671 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1672 mac_addr); 1673 hns3_warn(hw, 1674 "Failed to roll back to del setted mac addr(%s): %d", 1675 mac_str, ret_val); 1676 } 1677 1678 err_add_uc_addr: 1679 if (rm_succes) { 1680 ret_val = hns3_add_uc_addr_common(hw, oaddr); 1681 if (ret_val) { 1682 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1683 oaddr); 1684 hns3_warn(hw, 1685 "Failed to restore old uc mac addr(%s): %d", 1686 mac_str, ret_val); 1687 hw->mac.default_addr_setted = false; 1688 } 1689 } 1690 rte_spinlock_unlock(&hw->lock); 1691 1692 return ret; 1693 } 1694 1695 static int 1696 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del) 1697 { 1698 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1699 struct hns3_hw *hw = &hns->hw; 1700 struct rte_ether_addr *addr; 1701 int err = 0; 1702 int ret; 1703 int i; 1704 1705 for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) { 1706 addr = &hw->data->mac_addrs[i]; 1707 if (rte_is_zero_ether_addr(addr)) 1708 continue; 1709 if (rte_is_multicast_ether_addr(addr)) 1710 ret = del ? hns3_remove_mc_addr(hw, addr) : 1711 hns3_add_mc_addr(hw, addr); 1712 else 1713 ret = del ? hns3_remove_uc_addr_common(hw, addr) : 1714 hns3_add_uc_addr_common(hw, addr); 1715 1716 if (ret) { 1717 err = ret; 1718 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1719 addr); 1720 hns3_err(hw, "failed to %s mac addr(%s) index:%d " 1721 "ret = %d.", del ? "remove" : "restore", 1722 mac_str, i, ret); 1723 } 1724 } 1725 return err; 1726 } 1727 1728 static void 1729 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr) 1730 { 1731 #define HNS3_VF_NUM_IN_FIRST_DESC 192 1732 uint8_t word_num; 1733 uint8_t bit_num; 1734 1735 if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) { 1736 word_num = vfid / 32; 1737 bit_num = vfid % 32; 1738 if (clr) 1739 desc[1].data[word_num] &= 1740 rte_cpu_to_le_32(~(1UL << bit_num)); 1741 else 1742 desc[1].data[word_num] |= 1743 rte_cpu_to_le_32(1UL << bit_num); 1744 } else { 1745 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32; 1746 bit_num = vfid % 32; 1747 if (clr) 1748 desc[2].data[word_num] &= 1749 rte_cpu_to_le_32(~(1UL << bit_num)); 1750 else 1751 desc[2].data[word_num] |= 1752 rte_cpu_to_le_32(1UL << bit_num); 1753 } 1754 } 1755 1756 static int 1757 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1758 { 1759 struct hns3_mac_vlan_tbl_entry_cmd req; 1760 struct hns3_cmd_desc desc[3]; 1761 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1762 uint8_t vf_id; 1763 int ret; 1764 1765 /* Check if mac addr is valid */ 1766 if (!rte_is_multicast_ether_addr(mac_addr)) { 1767 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1768 mac_addr); 1769 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid", 1770 mac_str); 1771 return -EINVAL; 1772 } 1773 1774 memset(&req, 0, sizeof(req)); 1775 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1776 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1777 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1778 if (ret) { 1779 /* This mac addr do not exist, add new entry for it */ 1780 memset(desc[0].data, 0, sizeof(desc[0].data)); 1781 memset(desc[1].data, 0, sizeof(desc[0].data)); 1782 memset(desc[2].data, 0, sizeof(desc[0].data)); 1783 } 1784 1785 /* 1786 * In current version VF is not supported when PF is driven by DPDK 1787 * driver, just need to configure parameters for PF vport. 1788 */ 1789 vf_id = HNS3_PF_FUNC_ID; 1790 hns3_update_desc_vfid(desc, vf_id, false); 1791 ret = hns3_add_mac_vlan_tbl(hw, &req, desc); 1792 if (ret) { 1793 if (ret == -ENOSPC) 1794 hns3_err(hw, "mc mac vlan table is full"); 1795 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1796 mac_addr); 1797 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret); 1798 } 1799 1800 return ret; 1801 } 1802 1803 static int 1804 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr) 1805 { 1806 struct hns3_mac_vlan_tbl_entry_cmd req; 1807 struct hns3_cmd_desc desc[3]; 1808 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1809 uint8_t vf_id; 1810 int ret; 1811 1812 /* Check if mac addr is valid */ 1813 if (!rte_is_multicast_ether_addr(mac_addr)) { 1814 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1815 mac_addr); 1816 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid", 1817 mac_str); 1818 return -EINVAL; 1819 } 1820 1821 memset(&req, 0, sizeof(req)); 1822 hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0); 1823 hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true); 1824 ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true); 1825 if (ret == 0) { 1826 /* 1827 * This mac addr exist, remove this handle's VFID for it. 1828 * In current version VF is not supported when PF is driven by 1829 * DPDK driver, just need to configure parameters for PF vport. 1830 */ 1831 vf_id = HNS3_PF_FUNC_ID; 1832 hns3_update_desc_vfid(desc, vf_id, true); 1833 1834 /* All the vfid is zero, so need to delete this entry */ 1835 ret = hns3_remove_mac_vlan_tbl(hw, &req); 1836 } else if (ret == -ENOENT) { 1837 /* This mac addr doesn't exist. */ 1838 return 0; 1839 } 1840 1841 if (ret) { 1842 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1843 mac_addr); 1844 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret); 1845 } 1846 1847 return ret; 1848 } 1849 1850 static int 1851 hns3_set_mc_addr_chk_param(struct hns3_hw *hw, 1852 struct rte_ether_addr *mc_addr_set, 1853 uint32_t nb_mc_addr) 1854 { 1855 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 1856 struct rte_ether_addr *addr; 1857 uint32_t i; 1858 uint32_t j; 1859 1860 if (nb_mc_addr > HNS3_MC_MACADDR_NUM) { 1861 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) " 1862 "invalid. valid range: 0~%d", 1863 nb_mc_addr, HNS3_MC_MACADDR_NUM); 1864 return -EINVAL; 1865 } 1866 1867 /* Check if input mac addresses are valid */ 1868 for (i = 0; i < nb_mc_addr; i++) { 1869 addr = &mc_addr_set[i]; 1870 if (!rte_is_multicast_ether_addr(addr)) { 1871 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 1872 addr); 1873 hns3_err(hw, 1874 "failed to set mc mac addr, addr(%s) invalid.", 1875 mac_str); 1876 return -EINVAL; 1877 } 1878 1879 /* Check if there are duplicate addresses */ 1880 for (j = i + 1; j < nb_mc_addr; j++) { 1881 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 1882 rte_ether_format_addr(mac_str, 1883 RTE_ETHER_ADDR_FMT_SIZE, 1884 addr); 1885 hns3_err(hw, "failed to set mc mac addr, " 1886 "addrs invalid. two same addrs(%s).", 1887 mac_str); 1888 return -EINVAL; 1889 } 1890 } 1891 1892 /* 1893 * Check if there are duplicate addresses between mac_addrs 1894 * and mc_addr_set 1895 */ 1896 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) { 1897 if (rte_is_same_ether_addr(addr, 1898 &hw->data->mac_addrs[j])) { 1899 rte_ether_format_addr(mac_str, 1900 RTE_ETHER_ADDR_FMT_SIZE, 1901 addr); 1902 hns3_err(hw, "failed to set mc mac addr, " 1903 "addrs invalid. addrs(%s) has already " 1904 "configured in mac_addr add API", 1905 mac_str); 1906 return -EINVAL; 1907 } 1908 } 1909 } 1910 1911 return 0; 1912 } 1913 1914 static void 1915 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw, 1916 struct rte_ether_addr *mc_addr_set, 1917 int mc_addr_num, 1918 struct rte_ether_addr *reserved_addr_list, 1919 int *reserved_addr_num, 1920 struct rte_ether_addr *add_addr_list, 1921 int *add_addr_num, 1922 struct rte_ether_addr *rm_addr_list, 1923 int *rm_addr_num) 1924 { 1925 struct rte_ether_addr *addr; 1926 int current_addr_num; 1927 int reserved_num = 0; 1928 int add_num = 0; 1929 int rm_num = 0; 1930 int num; 1931 int i; 1932 int j; 1933 bool same_addr; 1934 1935 /* Calculate the mc mac address list that should be removed */ 1936 current_addr_num = hw->mc_addrs_num; 1937 for (i = 0; i < current_addr_num; i++) { 1938 addr = &hw->mc_addrs[i]; 1939 same_addr = false; 1940 for (j = 0; j < mc_addr_num; j++) { 1941 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) { 1942 same_addr = true; 1943 break; 1944 } 1945 } 1946 1947 if (!same_addr) { 1948 rte_ether_addr_copy(addr, &rm_addr_list[rm_num]); 1949 rm_num++; 1950 } else { 1951 rte_ether_addr_copy(addr, 1952 &reserved_addr_list[reserved_num]); 1953 reserved_num++; 1954 } 1955 } 1956 1957 /* Calculate the mc mac address list that should be added */ 1958 for (i = 0; i < mc_addr_num; i++) { 1959 addr = &mc_addr_set[i]; 1960 same_addr = false; 1961 for (j = 0; j < current_addr_num; j++) { 1962 if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) { 1963 same_addr = true; 1964 break; 1965 } 1966 } 1967 1968 if (!same_addr) { 1969 rte_ether_addr_copy(addr, &add_addr_list[add_num]); 1970 add_num++; 1971 } 1972 } 1973 1974 /* Reorder the mc mac address list maintained by driver */ 1975 for (i = 0; i < reserved_num; i++) 1976 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]); 1977 1978 for (i = 0; i < rm_num; i++) { 1979 num = reserved_num + i; 1980 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]); 1981 } 1982 1983 *reserved_addr_num = reserved_num; 1984 *add_addr_num = add_num; 1985 *rm_addr_num = rm_num; 1986 } 1987 1988 static int 1989 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev, 1990 struct rte_ether_addr *mc_addr_set, 1991 uint32_t nb_mc_addr) 1992 { 1993 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1994 struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM]; 1995 struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM]; 1996 struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM]; 1997 struct rte_ether_addr *addr; 1998 int reserved_addr_num; 1999 int add_addr_num; 2000 int rm_addr_num; 2001 int mc_addr_num; 2002 int num; 2003 int ret; 2004 int i; 2005 2006 /* Check if input parameters are valid */ 2007 ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr); 2008 if (ret) 2009 return ret; 2010 2011 rte_spinlock_lock(&hw->lock); 2012 2013 /* 2014 * Calculate the mc mac address lists those should be removed and be 2015 * added, Reorder the mc mac address list maintained by driver. 2016 */ 2017 mc_addr_num = (int)nb_mc_addr; 2018 hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num, 2019 reserved_addr_list, &reserved_addr_num, 2020 add_addr_list, &add_addr_num, 2021 rm_addr_list, &rm_addr_num); 2022 2023 /* Remove mc mac addresses */ 2024 for (i = 0; i < rm_addr_num; i++) { 2025 num = rm_addr_num - i - 1; 2026 addr = &rm_addr_list[num]; 2027 ret = hns3_remove_mc_addr(hw, addr); 2028 if (ret) { 2029 rte_spinlock_unlock(&hw->lock); 2030 return ret; 2031 } 2032 hw->mc_addrs_num--; 2033 } 2034 2035 /* Add mc mac addresses */ 2036 for (i = 0; i < add_addr_num; i++) { 2037 addr = &add_addr_list[i]; 2038 ret = hns3_add_mc_addr(hw, addr); 2039 if (ret) { 2040 rte_spinlock_unlock(&hw->lock); 2041 return ret; 2042 } 2043 2044 num = reserved_addr_num + i; 2045 rte_ether_addr_copy(addr, &hw->mc_addrs[num]); 2046 hw->mc_addrs_num++; 2047 } 2048 rte_spinlock_unlock(&hw->lock); 2049 2050 return 0; 2051 } 2052 2053 static int 2054 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del) 2055 { 2056 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 2057 struct hns3_hw *hw = &hns->hw; 2058 struct rte_ether_addr *addr; 2059 int err = 0; 2060 int ret; 2061 int i; 2062 2063 for (i = 0; i < hw->mc_addrs_num; i++) { 2064 addr = &hw->mc_addrs[i]; 2065 if (!rte_is_multicast_ether_addr(addr)) 2066 continue; 2067 if (del) 2068 ret = hns3_remove_mc_addr(hw, addr); 2069 else 2070 ret = hns3_add_mc_addr(hw, addr); 2071 if (ret) { 2072 err = ret; 2073 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 2074 addr); 2075 hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d", 2076 del ? "Remove" : "Restore", mac_str, ret); 2077 } 2078 } 2079 return err; 2080 } 2081 2082 static int 2083 hns3_check_mq_mode(struct rte_eth_dev *dev) 2084 { 2085 enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode; 2086 enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode; 2087 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2088 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 2089 struct rte_eth_dcb_rx_conf *dcb_rx_conf; 2090 struct rte_eth_dcb_tx_conf *dcb_tx_conf; 2091 uint8_t num_tc; 2092 int max_tc = 0; 2093 int i; 2094 2095 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 2096 dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf; 2097 2098 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2099 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. " 2100 "rx_mq_mode = %d", rx_mq_mode); 2101 return -EINVAL; 2102 } 2103 2104 if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB || 2105 tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2106 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB " 2107 "is not supported. rx_mq_mode = %d, tx_mq_mode = %d", 2108 rx_mq_mode, tx_mq_mode); 2109 return -EINVAL; 2110 } 2111 2112 if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) { 2113 if (dcb_rx_conf->nb_tcs > pf->tc_max) { 2114 hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.", 2115 dcb_rx_conf->nb_tcs, pf->tc_max); 2116 return -EINVAL; 2117 } 2118 2119 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS || 2120 dcb_rx_conf->nb_tcs == HNS3_8_TCS)) { 2121 hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, " 2122 "nb_tcs(%d) != %d or %d in rx direction.", 2123 dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS); 2124 return -EINVAL; 2125 } 2126 2127 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) { 2128 hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)", 2129 dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs); 2130 return -EINVAL; 2131 } 2132 2133 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) { 2134 if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) { 2135 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, " 2136 "is not equal to one in tx direction.", 2137 i, dcb_rx_conf->dcb_tc[i]); 2138 return -EINVAL; 2139 } 2140 if (dcb_rx_conf->dcb_tc[i] > max_tc) 2141 max_tc = dcb_rx_conf->dcb_tc[i]; 2142 } 2143 2144 num_tc = max_tc + 1; 2145 if (num_tc > dcb_rx_conf->nb_tcs) { 2146 hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)", 2147 num_tc, dcb_rx_conf->nb_tcs); 2148 return -EINVAL; 2149 } 2150 } 2151 2152 return 0; 2153 } 2154 2155 static int 2156 hns3_check_dcb_cfg(struct rte_eth_dev *dev) 2157 { 2158 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2159 2160 if (!hns3_dev_dcb_supported(hw)) { 2161 hns3_err(hw, "this port does not support dcb configurations."); 2162 return -EOPNOTSUPP; 2163 } 2164 2165 if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) { 2166 hns3_err(hw, "MAC pause enabled, cannot config dcb info."); 2167 return -EOPNOTSUPP; 2168 } 2169 2170 /* Check multiple queue mode */ 2171 return hns3_check_mq_mode(dev); 2172 } 2173 2174 static int 2175 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap, 2176 enum hns3_ring_type queue_type, uint16_t queue_id) 2177 { 2178 struct hns3_cmd_desc desc; 2179 struct hns3_ctrl_vector_chain_cmd *req = 2180 (struct hns3_ctrl_vector_chain_cmd *)desc.data; 2181 enum hns3_cmd_status status; 2182 enum hns3_opcode_type op; 2183 uint16_t tqp_type_and_id = 0; 2184 const char *op_str; 2185 uint16_t type; 2186 uint16_t gl; 2187 2188 op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR; 2189 hns3_cmd_setup_basic_desc(&desc, op, false); 2190 req->int_vector_id = vector_id; 2191 2192 if (queue_type == HNS3_RING_TYPE_RX) 2193 gl = HNS3_RING_GL_RX; 2194 else 2195 gl = HNS3_RING_GL_TX; 2196 2197 type = queue_type; 2198 2199 hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S, 2200 type); 2201 hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id); 2202 hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S, 2203 gl); 2204 req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id); 2205 req->int_cause_num = 1; 2206 op_str = mmap ? "Map" : "Unmap"; 2207 status = hns3_cmd_send(hw, &desc, 1); 2208 if (status) { 2209 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.", 2210 op_str, queue_id, req->int_vector_id, status); 2211 return status; 2212 } 2213 2214 return 0; 2215 } 2216 2217 static int 2218 hns3_init_ring_with_vector(struct hns3_hw *hw) 2219 { 2220 uint16_t vec; 2221 int ret; 2222 int i; 2223 2224 /* 2225 * In hns3 network engine, vector 0 is always the misc interrupt of this 2226 * function, vector 1~N can be used respectively for the queues of the 2227 * function. Tx and Rx queues with the same number share the interrupt 2228 * vector. In the initialization clearing the all hardware mapping 2229 * relationship configurations between queues and interrupt vectors is 2230 * needed, so some error caused by the residual configurations, such as 2231 * the unexpected Tx interrupt, can be avoid. 2232 */ 2233 vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */ 2234 if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE) 2235 vec = vec - 1; /* the last interrupt is reserved */ 2236 hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num); 2237 for (i = 0; i < hw->intr_tqps_num; i++) { 2238 /* 2239 * Set gap limiter/rate limiter/quanity limiter algorithm 2240 * configuration for interrupt coalesce of queue's interrupt. 2241 */ 2242 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX, 2243 HNS3_TQP_INTR_GL_DEFAULT); 2244 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX, 2245 HNS3_TQP_INTR_GL_DEFAULT); 2246 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT); 2247 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT); 2248 2249 ret = hns3_bind_ring_with_vector(hw, vec, false, 2250 HNS3_RING_TYPE_TX, i); 2251 if (ret) { 2252 PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with " 2253 "vector: %d, ret=%d", i, vec, ret); 2254 return ret; 2255 } 2256 2257 ret = hns3_bind_ring_with_vector(hw, vec, false, 2258 HNS3_RING_TYPE_RX, i); 2259 if (ret) { 2260 PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with " 2261 "vector: %d, ret=%d", i, vec, ret); 2262 return ret; 2263 } 2264 } 2265 2266 return 0; 2267 } 2268 2269 static int 2270 hns3_dev_configure(struct rte_eth_dev *dev) 2271 { 2272 struct hns3_adapter *hns = dev->data->dev_private; 2273 struct rte_eth_conf *conf = &dev->data->dev_conf; 2274 enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode; 2275 struct hns3_hw *hw = &hns->hw; 2276 struct hns3_rss_conf *rss_cfg = &hw->rss_info; 2277 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2278 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2279 struct rte_eth_rss_conf rss_conf; 2280 uint16_t mtu; 2281 bool gro_en; 2282 int ret; 2283 2284 /* 2285 * Hardware does not support individually enable/disable/reset the Tx or 2286 * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx 2287 * and Rx queues at the same time. When the numbers of Tx queues 2288 * allocated by upper applications are not equal to the numbers of Rx 2289 * queues, driver needs to setup fake Tx or Rx queues to adjust numbers 2290 * of Tx/Rx queues. otherwise, network engine can not work as usual. But 2291 * these fake queues are imperceptible, and can not be used by upper 2292 * applications. 2293 */ 2294 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q); 2295 if (ret) { 2296 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret); 2297 return ret; 2298 } 2299 2300 hw->adapter_state = HNS3_NIC_CONFIGURING; 2301 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) { 2302 hns3_err(hw, "setting link speed/duplex not supported"); 2303 ret = -EINVAL; 2304 goto cfg_err; 2305 } 2306 2307 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) { 2308 ret = hns3_check_dcb_cfg(dev); 2309 if (ret) 2310 goto cfg_err; 2311 } 2312 2313 /* When RSS is not configured, redirect the packet queue 0 */ 2314 if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) { 2315 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 2316 rss_conf = conf->rx_adv_conf.rss_conf; 2317 if (rss_conf.rss_key == NULL) { 2318 rss_conf.rss_key = rss_cfg->key; 2319 rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE; 2320 } 2321 2322 ret = hns3_dev_rss_hash_update(dev, &rss_conf); 2323 if (ret) 2324 goto cfg_err; 2325 } 2326 2327 /* 2328 * If jumbo frames are enabled, MTU needs to be refreshed 2329 * according to the maximum RX packet length. 2330 */ 2331 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 2332 /* 2333 * Security of max_rx_pkt_len is guaranteed in dpdk frame. 2334 * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it 2335 * can safely assign to "uint16_t" type variable. 2336 */ 2337 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len); 2338 ret = hns3_dev_mtu_set(dev, mtu); 2339 if (ret) 2340 goto cfg_err; 2341 dev->data->mtu = mtu; 2342 } 2343 2344 ret = hns3_dev_configure_vlan(dev); 2345 if (ret) 2346 goto cfg_err; 2347 2348 /* config hardware GRO */ 2349 gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false; 2350 ret = hns3_config_gro(hw, gro_en); 2351 if (ret) 2352 goto cfg_err; 2353 2354 hns->rx_simple_allowed = true; 2355 hns->rx_vec_allowed = true; 2356 hns->tx_simple_allowed = true; 2357 hns->tx_vec_allowed = true; 2358 2359 hns3_init_rx_ptype_tble(dev); 2360 hw->adapter_state = HNS3_NIC_CONFIGURED; 2361 2362 return 0; 2363 2364 cfg_err: 2365 (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0); 2366 hw->adapter_state = HNS3_NIC_INITIALIZED; 2367 2368 return ret; 2369 } 2370 2371 static int 2372 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps) 2373 { 2374 struct hns3_config_max_frm_size_cmd *req; 2375 struct hns3_cmd_desc desc; 2376 2377 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false); 2378 2379 req = (struct hns3_config_max_frm_size_cmd *)desc.data; 2380 req->max_frm_size = rte_cpu_to_le_16(new_mps); 2381 req->min_frm_size = RTE_ETHER_MIN_LEN; 2382 2383 return hns3_cmd_send(hw, &desc, 1); 2384 } 2385 2386 static int 2387 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps) 2388 { 2389 int ret; 2390 2391 ret = hns3_set_mac_mtu(hw, mps); 2392 if (ret) { 2393 hns3_err(hw, "Failed to set mtu, ret = %d", ret); 2394 return ret; 2395 } 2396 2397 ret = hns3_buffer_alloc(hw); 2398 if (ret) 2399 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret); 2400 2401 return ret; 2402 } 2403 2404 static int 2405 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 2406 { 2407 struct hns3_adapter *hns = dev->data->dev_private; 2408 uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD; 2409 struct hns3_hw *hw = &hns->hw; 2410 bool is_jumbo_frame; 2411 int ret; 2412 2413 if (dev->data->dev_started) { 2414 hns3_err(hw, "Failed to set mtu, port %u must be stopped " 2415 "before configuration", dev->data->port_id); 2416 return -EBUSY; 2417 } 2418 2419 rte_spinlock_lock(&hw->lock); 2420 is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false; 2421 frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN); 2422 2423 /* 2424 * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely 2425 * assign to "uint16_t" type variable. 2426 */ 2427 ret = hns3_config_mtu(hw, (uint16_t)frame_size); 2428 if (ret) { 2429 rte_spinlock_unlock(&hw->lock); 2430 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d", 2431 dev->data->port_id, mtu, ret); 2432 return ret; 2433 } 2434 hns->pf.mps = (uint16_t)frame_size; 2435 if (is_jumbo_frame) 2436 dev->data->dev_conf.rxmode.offloads |= 2437 DEV_RX_OFFLOAD_JUMBO_FRAME; 2438 else 2439 dev->data->dev_conf.rxmode.offloads &= 2440 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2441 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 2442 rte_spinlock_unlock(&hw->lock); 2443 2444 return 0; 2445 } 2446 2447 static int 2448 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) 2449 { 2450 struct hns3_adapter *hns = eth_dev->data->dev_private; 2451 struct hns3_hw *hw = &hns->hw; 2452 uint16_t queue_num = hw->tqps_num; 2453 2454 /* 2455 * In interrupt mode, 'max_rx_queues' is set based on the number of 2456 * MSI-X interrupt resources of the hardware. 2457 */ 2458 if (hw->data->dev_conf.intr_conf.rxq == 1) 2459 queue_num = hw->intr_tqps_num; 2460 2461 info->max_rx_queues = queue_num; 2462 info->max_tx_queues = hw->tqps_num; 2463 info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */ 2464 info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE; 2465 info->max_mac_addrs = HNS3_UC_MACADDR_NUM; 2466 info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD; 2467 info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE; 2468 info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM | 2469 DEV_RX_OFFLOAD_TCP_CKSUM | 2470 DEV_RX_OFFLOAD_UDP_CKSUM | 2471 DEV_RX_OFFLOAD_SCTP_CKSUM | 2472 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 2473 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 2474 DEV_RX_OFFLOAD_KEEP_CRC | 2475 DEV_RX_OFFLOAD_SCATTER | 2476 DEV_RX_OFFLOAD_VLAN_STRIP | 2477 DEV_RX_OFFLOAD_VLAN_FILTER | 2478 DEV_RX_OFFLOAD_JUMBO_FRAME | 2479 DEV_RX_OFFLOAD_RSS_HASH | 2480 DEV_RX_OFFLOAD_TCP_LRO); 2481 info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 2482 DEV_TX_OFFLOAD_IPV4_CKSUM | 2483 DEV_TX_OFFLOAD_TCP_CKSUM | 2484 DEV_TX_OFFLOAD_UDP_CKSUM | 2485 DEV_TX_OFFLOAD_SCTP_CKSUM | 2486 DEV_TX_OFFLOAD_MULTI_SEGS | 2487 DEV_TX_OFFLOAD_TCP_TSO | 2488 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 2489 DEV_TX_OFFLOAD_GRE_TNL_TSO | 2490 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | 2491 DEV_TX_OFFLOAD_MBUF_FAST_FREE | 2492 hns3_txvlan_cap_get(hw)); 2493 2494 info->rx_desc_lim = (struct rte_eth_desc_lim) { 2495 .nb_max = HNS3_MAX_RING_DESC, 2496 .nb_min = HNS3_MIN_RING_DESC, 2497 .nb_align = HNS3_ALIGN_RING_DESC, 2498 }; 2499 2500 info->tx_desc_lim = (struct rte_eth_desc_lim) { 2501 .nb_max = HNS3_MAX_RING_DESC, 2502 .nb_min = HNS3_MIN_RING_DESC, 2503 .nb_align = HNS3_ALIGN_RING_DESC, 2504 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT, 2505 .nb_mtu_seg_max = HNS3_MAX_NON_TSO_BD_PER_PKT, 2506 }; 2507 2508 info->default_rxconf = (struct rte_eth_rxconf) { 2509 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH, 2510 /* 2511 * If there are no available Rx buffer descriptors, incoming 2512 * packets are always dropped by hardware based on hns3 network 2513 * engine. 2514 */ 2515 .rx_drop_en = 1, 2516 .offloads = 0, 2517 }; 2518 info->default_txconf = (struct rte_eth_txconf) { 2519 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH, 2520 .offloads = 0, 2521 }; 2522 2523 info->vmdq_queue_num = 0; 2524 2525 info->reta_size = HNS3_RSS_IND_TBL_SIZE; 2526 info->hash_key_size = HNS3_RSS_KEY_SIZE; 2527 info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT; 2528 2529 info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2530 info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE; 2531 info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2532 info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM; 2533 info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2534 info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC; 2535 2536 return 0; 2537 } 2538 2539 static int 2540 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 2541 size_t fw_size) 2542 { 2543 struct hns3_adapter *hns = eth_dev->data->dev_private; 2544 struct hns3_hw *hw = &hns->hw; 2545 uint32_t version = hw->fw_version; 2546 int ret; 2547 2548 ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu", 2549 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 2550 HNS3_FW_VERSION_BYTE3_S), 2551 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 2552 HNS3_FW_VERSION_BYTE2_S), 2553 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 2554 HNS3_FW_VERSION_BYTE1_S), 2555 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 2556 HNS3_FW_VERSION_BYTE0_S)); 2557 ret += 1; /* add the size of '\0' */ 2558 if (fw_size < (uint32_t)ret) 2559 return ret; 2560 else 2561 return 0; 2562 } 2563 2564 static int 2565 hns3_dev_link_update(struct rte_eth_dev *eth_dev, 2566 __rte_unused int wait_to_complete) 2567 { 2568 struct hns3_adapter *hns = eth_dev->data->dev_private; 2569 struct hns3_hw *hw = &hns->hw; 2570 struct hns3_mac *mac = &hw->mac; 2571 struct rte_eth_link new_link; 2572 2573 if (!hns3_is_reset_pending(hns)) { 2574 hns3_update_speed_duplex(eth_dev); 2575 hns3_update_link_status(hw); 2576 } 2577 2578 memset(&new_link, 0, sizeof(new_link)); 2579 switch (mac->link_speed) { 2580 case ETH_SPEED_NUM_10M: 2581 case ETH_SPEED_NUM_100M: 2582 case ETH_SPEED_NUM_1G: 2583 case ETH_SPEED_NUM_10G: 2584 case ETH_SPEED_NUM_25G: 2585 case ETH_SPEED_NUM_40G: 2586 case ETH_SPEED_NUM_50G: 2587 case ETH_SPEED_NUM_100G: 2588 case ETH_SPEED_NUM_200G: 2589 new_link.link_speed = mac->link_speed; 2590 break; 2591 default: 2592 new_link.link_speed = ETH_SPEED_NUM_100M; 2593 break; 2594 } 2595 2596 new_link.link_duplex = mac->link_duplex; 2597 new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 2598 new_link.link_autoneg = 2599 !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED); 2600 2601 return rte_eth_linkstatus_set(eth_dev, &new_link); 2602 } 2603 2604 static int 2605 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status) 2606 { 2607 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2608 struct hns3_pf *pf = &hns->pf; 2609 2610 if (!(status->pf_state & HNS3_PF_STATE_DONE)) 2611 return -EINVAL; 2612 2613 pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false; 2614 2615 return 0; 2616 } 2617 2618 static int 2619 hns3_query_function_status(struct hns3_hw *hw) 2620 { 2621 #define HNS3_QUERY_MAX_CNT 10 2622 #define HNS3_QUERY_SLEEP_MSCOEND 1 2623 struct hns3_func_status_cmd *req; 2624 struct hns3_cmd_desc desc; 2625 int timeout = 0; 2626 int ret; 2627 2628 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true); 2629 req = (struct hns3_func_status_cmd *)desc.data; 2630 2631 do { 2632 ret = hns3_cmd_send(hw, &desc, 1); 2633 if (ret) { 2634 PMD_INIT_LOG(ERR, "query function status failed %d", 2635 ret); 2636 return ret; 2637 } 2638 2639 /* Check pf reset is done */ 2640 if (req->pf_state) 2641 break; 2642 2643 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND); 2644 } while (timeout++ < HNS3_QUERY_MAX_CNT); 2645 2646 return hns3_parse_func_status(hw, req); 2647 } 2648 2649 static int 2650 hns3_query_pf_resource(struct hns3_hw *hw) 2651 { 2652 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2653 struct hns3_pf *pf = &hns->pf; 2654 struct hns3_pf_res_cmd *req; 2655 struct hns3_cmd_desc desc; 2656 int ret; 2657 2658 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true); 2659 ret = hns3_cmd_send(hw, &desc, 1); 2660 if (ret) { 2661 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret); 2662 return ret; 2663 } 2664 2665 req = (struct hns3_pf_res_cmd *)desc.data; 2666 hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num); 2667 pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S; 2668 hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC); 2669 pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number); 2670 2671 if (req->tx_buf_size) 2672 pf->tx_buf_size = 2673 rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S; 2674 else 2675 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF; 2676 2677 pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT); 2678 2679 if (req->dv_buf_size) 2680 pf->dv_buf_size = 2681 rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S; 2682 else 2683 pf->dv_buf_size = HNS3_DEFAULT_DV; 2684 2685 pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT); 2686 2687 hw->num_msi = 2688 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number), 2689 HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S); 2690 2691 return 0; 2692 } 2693 2694 static void 2695 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc) 2696 { 2697 struct hns3_cfg_param_cmd *req; 2698 uint64_t mac_addr_tmp_high; 2699 uint64_t mac_addr_tmp; 2700 uint32_t i; 2701 2702 req = (struct hns3_cfg_param_cmd *)desc[0].data; 2703 2704 /* get the configuration */ 2705 cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2706 HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S); 2707 cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2708 HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S); 2709 cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]), 2710 HNS3_CFG_TQP_DESC_N_M, 2711 HNS3_CFG_TQP_DESC_N_S); 2712 2713 cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2714 HNS3_CFG_PHY_ADDR_M, 2715 HNS3_CFG_PHY_ADDR_S); 2716 cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2717 HNS3_CFG_MEDIA_TP_M, 2718 HNS3_CFG_MEDIA_TP_S); 2719 cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2720 HNS3_CFG_RX_BUF_LEN_M, 2721 HNS3_CFG_RX_BUF_LEN_S); 2722 /* get mac address */ 2723 mac_addr_tmp = rte_le_to_cpu_32(req->param[2]); 2724 mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2725 HNS3_CFG_MAC_ADDR_H_M, 2726 HNS3_CFG_MAC_ADDR_H_S); 2727 2728 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; 2729 2730 cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2731 HNS3_CFG_DEFAULT_SPEED_M, 2732 HNS3_CFG_DEFAULT_SPEED_S); 2733 cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]), 2734 HNS3_CFG_RSS_SIZE_M, 2735 HNS3_CFG_RSS_SIZE_S); 2736 2737 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 2738 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; 2739 2740 req = (struct hns3_cfg_param_cmd *)desc[1].data; 2741 cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]); 2742 2743 cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2744 HNS3_CFG_SPEED_ABILITY_M, 2745 HNS3_CFG_SPEED_ABILITY_S); 2746 cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]), 2747 HNS3_CFG_UMV_TBL_SPACE_M, 2748 HNS3_CFG_UMV_TBL_SPACE_S); 2749 if (!cfg->umv_space) 2750 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF; 2751 } 2752 2753 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash 2754 * @hw: pointer to struct hns3_hw 2755 * @hcfg: the config structure to be getted 2756 */ 2757 static int 2758 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg) 2759 { 2760 struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM]; 2761 struct hns3_cfg_param_cmd *req; 2762 uint32_t offset; 2763 uint32_t i; 2764 int ret; 2765 2766 for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) { 2767 offset = 0; 2768 req = (struct hns3_cfg_param_cmd *)desc[i].data; 2769 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM, 2770 true); 2771 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S, 2772 i * HNS3_CFG_RD_LEN_BYTES); 2773 /* Len should be divided by 4 when send to hardware */ 2774 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S, 2775 HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT); 2776 req->offset = rte_cpu_to_le_32(offset); 2777 } 2778 2779 ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM); 2780 if (ret) { 2781 PMD_INIT_LOG(ERR, "get config failed %d.", ret); 2782 return ret; 2783 } 2784 2785 hns3_parse_cfg(hcfg, desc); 2786 2787 return 0; 2788 } 2789 2790 static int 2791 hns3_parse_speed(int speed_cmd, uint32_t *speed) 2792 { 2793 switch (speed_cmd) { 2794 case HNS3_CFG_SPEED_10M: 2795 *speed = ETH_SPEED_NUM_10M; 2796 break; 2797 case HNS3_CFG_SPEED_100M: 2798 *speed = ETH_SPEED_NUM_100M; 2799 break; 2800 case HNS3_CFG_SPEED_1G: 2801 *speed = ETH_SPEED_NUM_1G; 2802 break; 2803 case HNS3_CFG_SPEED_10G: 2804 *speed = ETH_SPEED_NUM_10G; 2805 break; 2806 case HNS3_CFG_SPEED_25G: 2807 *speed = ETH_SPEED_NUM_25G; 2808 break; 2809 case HNS3_CFG_SPEED_40G: 2810 *speed = ETH_SPEED_NUM_40G; 2811 break; 2812 case HNS3_CFG_SPEED_50G: 2813 *speed = ETH_SPEED_NUM_50G; 2814 break; 2815 case HNS3_CFG_SPEED_100G: 2816 *speed = ETH_SPEED_NUM_100G; 2817 break; 2818 case HNS3_CFG_SPEED_200G: 2819 *speed = ETH_SPEED_NUM_200G; 2820 break; 2821 default: 2822 return -EINVAL; 2823 } 2824 2825 return 0; 2826 } 2827 2828 static void 2829 hns3_set_default_dev_specifications(struct hns3_hw *hw) 2830 { 2831 hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT; 2832 hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE; 2833 hw->rss_key_size = HNS3_RSS_KEY_SIZE; 2834 hw->max_tm_rate = HNS3_ETHER_MAX_RATE; 2835 } 2836 2837 static void 2838 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc) 2839 { 2840 struct hns3_dev_specs_0_cmd *req0; 2841 2842 req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data; 2843 2844 hw->max_non_tso_bd_num = req0->max_non_tso_bd_num; 2845 hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size); 2846 hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size); 2847 hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate); 2848 } 2849 2850 static int 2851 hns3_query_dev_specifications(struct hns3_hw *hw) 2852 { 2853 struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM]; 2854 int ret; 2855 int i; 2856 2857 for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) { 2858 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, 2859 true); 2860 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 2861 } 2862 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true); 2863 2864 ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM); 2865 if (ret) 2866 return ret; 2867 2868 hns3_parse_dev_specifications(hw, desc); 2869 2870 return 0; 2871 } 2872 2873 static int 2874 hns3_get_capability(struct hns3_hw *hw) 2875 { 2876 struct rte_pci_device *pci_dev; 2877 struct rte_eth_dev *eth_dev; 2878 uint16_t device_id; 2879 uint8_t revision; 2880 int ret; 2881 2882 eth_dev = &rte_eth_devices[hw->data->port_id]; 2883 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2884 device_id = pci_dev->id.device_id; 2885 2886 if (device_id == HNS3_DEV_ID_25GE_RDMA || 2887 device_id == HNS3_DEV_ID_50GE_RDMA || 2888 device_id == HNS3_DEV_ID_100G_RDMA_MACSEC || 2889 device_id == HNS3_DEV_ID_200G_RDMA) 2890 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); 2891 2892 /* Get PCI revision id */ 2893 ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN, 2894 HNS3_PCI_REVISION_ID); 2895 if (ret != HNS3_PCI_REVISION_ID_LEN) { 2896 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d", 2897 ret); 2898 return -EIO; 2899 } 2900 hw->revision = revision; 2901 2902 if (revision < PCI_REVISION_ID_HIP09_A) { 2903 hns3_set_default_dev_specifications(hw); 2904 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; 2905 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_NON_QL; 2906 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US; 2907 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; 2908 return 0; 2909 } 2910 2911 ret = hns3_query_dev_specifications(hw); 2912 if (ret) { 2913 PMD_INIT_LOG(ERR, 2914 "failed to query dev specifications, ret = %d", 2915 ret); 2916 return ret; 2917 } 2918 2919 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL; 2920 hw->intr.coalesce_mode = HNS3_INTR_COALESCE_QL; 2921 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US; 2922 hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN; 2923 2924 return 0; 2925 } 2926 2927 static int 2928 hns3_get_board_configuration(struct hns3_hw *hw) 2929 { 2930 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 2931 struct hns3_pf *pf = &hns->pf; 2932 struct hns3_cfg cfg; 2933 int ret; 2934 2935 ret = hns3_get_board_cfg(hw, &cfg); 2936 if (ret) { 2937 PMD_INIT_LOG(ERR, "get board config failed %d", ret); 2938 return ret; 2939 } 2940 2941 if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER && 2942 !hns3_dev_copper_supported(hw)) { 2943 PMD_INIT_LOG(ERR, "media type is copper, not supported."); 2944 return -EOPNOTSUPP; 2945 } 2946 2947 hw->mac.media_type = cfg.media_type; 2948 hw->rss_size_max = cfg.rss_size_max; 2949 hw->rss_dis_flag = false; 2950 memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN); 2951 hw->mac.phy_addr = cfg.phy_addr; 2952 hw->mac.default_addr_setted = false; 2953 hw->num_tx_desc = cfg.tqp_desc_num; 2954 hw->num_rx_desc = cfg.tqp_desc_num; 2955 hw->dcb_info.num_pg = 1; 2956 hw->dcb_info.hw_pfc_map = 0; 2957 2958 ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed); 2959 if (ret) { 2960 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d", 2961 cfg.default_speed, ret); 2962 return ret; 2963 } 2964 2965 pf->tc_max = cfg.tc_num; 2966 if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) { 2967 PMD_INIT_LOG(WARNING, 2968 "Get TC num(%u) from flash, set TC num to 1", 2969 pf->tc_max); 2970 pf->tc_max = 1; 2971 } 2972 2973 /* Dev does not support DCB */ 2974 if (!hns3_dev_dcb_supported(hw)) { 2975 pf->tc_max = 1; 2976 pf->pfc_max = 0; 2977 } else 2978 pf->pfc_max = pf->tc_max; 2979 2980 hw->dcb_info.num_tc = 1; 2981 hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, 2982 hw->tqps_num / hw->dcb_info.num_tc); 2983 hns3_set_bit(hw->hw_tc_map, 0, 1); 2984 pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE; 2985 2986 pf->wanted_umv_size = cfg.umv_space; 2987 2988 return ret; 2989 } 2990 2991 static int 2992 hns3_get_configuration(struct hns3_hw *hw) 2993 { 2994 int ret; 2995 2996 ret = hns3_query_function_status(hw); 2997 if (ret) { 2998 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret); 2999 return ret; 3000 } 3001 3002 /* Get device capability */ 3003 ret = hns3_get_capability(hw); 3004 if (ret) { 3005 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret); 3006 return ret; 3007 } 3008 3009 /* Get pf resource */ 3010 ret = hns3_query_pf_resource(hw); 3011 if (ret) { 3012 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret); 3013 return ret; 3014 } 3015 3016 ret = hns3_get_board_configuration(hw); 3017 if (ret) 3018 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret); 3019 3020 return ret; 3021 } 3022 3023 static int 3024 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid, 3025 uint16_t tqp_vid, bool is_pf) 3026 { 3027 struct hns3_tqp_map_cmd *req; 3028 struct hns3_cmd_desc desc; 3029 int ret; 3030 3031 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false); 3032 3033 req = (struct hns3_tqp_map_cmd *)desc.data; 3034 req->tqp_id = rte_cpu_to_le_16(tqp_pid); 3035 req->tqp_vf = func_id; 3036 req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B; 3037 if (!is_pf) 3038 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B); 3039 req->tqp_vid = rte_cpu_to_le_16(tqp_vid); 3040 3041 ret = hns3_cmd_send(hw, &desc, 1); 3042 if (ret) 3043 PMD_INIT_LOG(ERR, "TQP map failed %d", ret); 3044 3045 return ret; 3046 } 3047 3048 static int 3049 hns3_map_tqp(struct hns3_hw *hw) 3050 { 3051 uint16_t tqps_num = hw->total_tqps_num; 3052 uint16_t func_id; 3053 uint16_t tqp_id; 3054 bool is_pf; 3055 int num; 3056 int ret; 3057 int i; 3058 3059 /* 3060 * In current version VF is not supported when PF is driven by DPDK 3061 * driver, so we allocate tqps to PF as much as possible. 3062 */ 3063 tqp_id = 0; 3064 num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC); 3065 for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) { 3066 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false; 3067 for (i = 0; 3068 i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) { 3069 ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i, 3070 is_pf); 3071 if (ret) 3072 return ret; 3073 } 3074 } 3075 3076 return 0; 3077 } 3078 3079 static int 3080 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 3081 { 3082 struct hns3_config_mac_speed_dup_cmd *req; 3083 struct hns3_cmd_desc desc; 3084 int ret; 3085 3086 req = (struct hns3_config_mac_speed_dup_cmd *)desc.data; 3087 3088 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false); 3089 3090 hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0); 3091 3092 switch (speed) { 3093 case ETH_SPEED_NUM_10M: 3094 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3095 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M); 3096 break; 3097 case ETH_SPEED_NUM_100M: 3098 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3099 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M); 3100 break; 3101 case ETH_SPEED_NUM_1G: 3102 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3103 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G); 3104 break; 3105 case ETH_SPEED_NUM_10G: 3106 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3107 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G); 3108 break; 3109 case ETH_SPEED_NUM_25G: 3110 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3111 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G); 3112 break; 3113 case ETH_SPEED_NUM_40G: 3114 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3115 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G); 3116 break; 3117 case ETH_SPEED_NUM_50G: 3118 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3119 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G); 3120 break; 3121 case ETH_SPEED_NUM_100G: 3122 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3123 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G); 3124 break; 3125 case ETH_SPEED_NUM_200G: 3126 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M, 3127 HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G); 3128 break; 3129 default: 3130 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed); 3131 return -EINVAL; 3132 } 3133 3134 hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1); 3135 3136 ret = hns3_cmd_send(hw, &desc, 1); 3137 if (ret) 3138 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret); 3139 3140 return ret; 3141 } 3142 3143 static int 3144 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3145 { 3146 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3147 struct hns3_pf *pf = &hns->pf; 3148 struct hns3_priv_buf *priv; 3149 uint32_t i, total_size; 3150 3151 total_size = pf->pkt_buf_size; 3152 3153 /* alloc tx buffer for all enabled tc */ 3154 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3155 priv = &buf_alloc->priv_buf[i]; 3156 3157 if (hw->hw_tc_map & BIT(i)) { 3158 if (total_size < pf->tx_buf_size) 3159 return -ENOMEM; 3160 3161 priv->tx_buf_size = pf->tx_buf_size; 3162 } else 3163 priv->tx_buf_size = 0; 3164 3165 total_size -= priv->tx_buf_size; 3166 } 3167 3168 return 0; 3169 } 3170 3171 static int 3172 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3173 { 3174 /* TX buffer size is unit by 128 byte */ 3175 #define HNS3_BUF_SIZE_UNIT_SHIFT 7 3176 #define HNS3_BUF_SIZE_UPDATE_EN_MSK BIT(15) 3177 struct hns3_tx_buff_alloc_cmd *req; 3178 struct hns3_cmd_desc desc; 3179 uint32_t buf_size; 3180 uint32_t i; 3181 int ret; 3182 3183 req = (struct hns3_tx_buff_alloc_cmd *)desc.data; 3184 3185 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0); 3186 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3187 buf_size = buf_alloc->priv_buf[i].tx_buf_size; 3188 3189 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT; 3190 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size | 3191 HNS3_BUF_SIZE_UPDATE_EN_MSK); 3192 } 3193 3194 ret = hns3_cmd_send(hw, &desc, 1); 3195 if (ret) 3196 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret); 3197 3198 return ret; 3199 } 3200 3201 static int 3202 hns3_get_tc_num(struct hns3_hw *hw) 3203 { 3204 int cnt = 0; 3205 uint8_t i; 3206 3207 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3208 if (hw->hw_tc_map & BIT(i)) 3209 cnt++; 3210 return cnt; 3211 } 3212 3213 static uint32_t 3214 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3215 { 3216 struct hns3_priv_buf *priv; 3217 uint32_t rx_priv = 0; 3218 int i; 3219 3220 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3221 priv = &buf_alloc->priv_buf[i]; 3222 if (priv->enable) 3223 rx_priv += priv->buf_size; 3224 } 3225 return rx_priv; 3226 } 3227 3228 static uint32_t 3229 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc) 3230 { 3231 uint32_t total_tx_size = 0; 3232 uint32_t i; 3233 3234 for (i = 0; i < HNS3_MAX_TC_NUM; i++) 3235 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; 3236 3237 return total_tx_size; 3238 } 3239 3240 /* Get the number of pfc enabled TCs, which have private buffer */ 3241 static int 3242 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3243 { 3244 struct hns3_priv_buf *priv; 3245 int cnt = 0; 3246 uint8_t i; 3247 3248 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3249 priv = &buf_alloc->priv_buf[i]; 3250 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3251 cnt++; 3252 } 3253 3254 return cnt; 3255 } 3256 3257 /* Get the number of pfc disabled TCs, which have private buffer */ 3258 static int 3259 hns3_get_no_pfc_priv_num(struct hns3_hw *hw, 3260 struct hns3_pkt_buf_alloc *buf_alloc) 3261 { 3262 struct hns3_priv_buf *priv; 3263 int cnt = 0; 3264 uint8_t i; 3265 3266 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3267 priv = &buf_alloc->priv_buf[i]; 3268 if (hw->hw_tc_map & BIT(i) && 3269 !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable) 3270 cnt++; 3271 } 3272 3273 return cnt; 3274 } 3275 3276 static bool 3277 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc, 3278 uint32_t rx_all) 3279 { 3280 uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd; 3281 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3282 struct hns3_pf *pf = &hns->pf; 3283 uint32_t shared_buf, aligned_mps; 3284 uint32_t rx_priv; 3285 uint8_t tc_num; 3286 uint8_t i; 3287 3288 tc_num = hns3_get_tc_num(hw); 3289 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3290 3291 if (hns3_dev_dcb_supported(hw)) 3292 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps + 3293 pf->dv_buf_size; 3294 else 3295 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF 3296 + pf->dv_buf_size; 3297 3298 shared_buf_tc = tc_num * aligned_mps + aligned_mps; 3299 shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc), 3300 HNS3_BUF_SIZE_UNIT); 3301 3302 rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc); 3303 if (rx_all < rx_priv + shared_std) 3304 return false; 3305 3306 shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT); 3307 buf_alloc->s_buf.buf_size = shared_buf; 3308 if (hns3_dev_dcb_supported(hw)) { 3309 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size; 3310 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high 3311 - roundup(aligned_mps / HNS3_BUF_DIV_BY, 3312 HNS3_BUF_SIZE_UNIT); 3313 } else { 3314 buf_alloc->s_buf.self.high = 3315 aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3316 buf_alloc->s_buf.self.low = aligned_mps; 3317 } 3318 3319 if (hns3_dev_dcb_supported(hw)) { 3320 hi_thrd = shared_buf - pf->dv_buf_size; 3321 3322 if (tc_num <= NEED_RESERVE_TC_NUM) 3323 hi_thrd = hi_thrd * BUF_RESERVE_PERCENT 3324 / BUF_MAX_PERCENT; 3325 3326 if (tc_num) 3327 hi_thrd = hi_thrd / tc_num; 3328 3329 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps); 3330 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT); 3331 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY; 3332 } else { 3333 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF; 3334 lo_thrd = aligned_mps; 3335 } 3336 3337 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3338 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd; 3339 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd; 3340 } 3341 3342 return true; 3343 } 3344 3345 static bool 3346 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max, 3347 struct hns3_pkt_buf_alloc *buf_alloc) 3348 { 3349 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3350 struct hns3_pf *pf = &hns->pf; 3351 struct hns3_priv_buf *priv; 3352 uint32_t aligned_mps; 3353 uint32_t rx_all; 3354 uint8_t i; 3355 3356 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3357 aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT); 3358 3359 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3360 priv = &buf_alloc->priv_buf[i]; 3361 3362 priv->enable = 0; 3363 priv->wl.low = 0; 3364 priv->wl.high = 0; 3365 priv->buf_size = 0; 3366 3367 if (!(hw->hw_tc_map & BIT(i))) 3368 continue; 3369 3370 priv->enable = 1; 3371 if (hw->dcb_info.hw_pfc_map & BIT(i)) { 3372 priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT; 3373 priv->wl.high = roundup(priv->wl.low + aligned_mps, 3374 HNS3_BUF_SIZE_UNIT); 3375 } else { 3376 priv->wl.low = 0; 3377 priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) : 3378 aligned_mps; 3379 } 3380 3381 priv->buf_size = priv->wl.high + pf->dv_buf_size; 3382 } 3383 3384 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3385 } 3386 3387 static bool 3388 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw, 3389 struct hns3_pkt_buf_alloc *buf_alloc) 3390 { 3391 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3392 struct hns3_pf *pf = &hns->pf; 3393 struct hns3_priv_buf *priv; 3394 int no_pfc_priv_num; 3395 uint32_t rx_all; 3396 uint8_t mask; 3397 int i; 3398 3399 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3400 no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc); 3401 3402 /* let the last to be cleared first */ 3403 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3404 priv = &buf_alloc->priv_buf[i]; 3405 mask = BIT((uint8_t)i); 3406 3407 if (hw->hw_tc_map & mask && 3408 !(hw->dcb_info.hw_pfc_map & mask)) { 3409 /* Clear the no pfc TC private buffer */ 3410 priv->wl.low = 0; 3411 priv->wl.high = 0; 3412 priv->buf_size = 0; 3413 priv->enable = 0; 3414 no_pfc_priv_num--; 3415 } 3416 3417 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3418 no_pfc_priv_num == 0) 3419 break; 3420 } 3421 3422 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3423 } 3424 3425 static bool 3426 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw, 3427 struct hns3_pkt_buf_alloc *buf_alloc) 3428 { 3429 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3430 struct hns3_pf *pf = &hns->pf; 3431 struct hns3_priv_buf *priv; 3432 uint32_t rx_all; 3433 int pfc_priv_num; 3434 uint8_t mask; 3435 int i; 3436 3437 rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3438 pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc); 3439 3440 /* let the last to be cleared first */ 3441 for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) { 3442 priv = &buf_alloc->priv_buf[i]; 3443 mask = BIT((uint8_t)i); 3444 3445 if (hw->hw_tc_map & mask && 3446 hw->dcb_info.hw_pfc_map & mask) { 3447 /* Reduce the number of pfc TC with private buffer */ 3448 priv->wl.low = 0; 3449 priv->enable = 0; 3450 priv->wl.high = 0; 3451 priv->buf_size = 0; 3452 pfc_priv_num--; 3453 } 3454 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) || 3455 pfc_priv_num == 0) 3456 break; 3457 } 3458 3459 return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all); 3460 } 3461 3462 static bool 3463 hns3_only_alloc_priv_buff(struct hns3_hw *hw, 3464 struct hns3_pkt_buf_alloc *buf_alloc) 3465 { 3466 #define COMPENSATE_BUFFER 0x3C00 3467 #define COMPENSATE_HALF_MPS_NUM 5 3468 #define PRIV_WL_GAP 0x1800 3469 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3470 struct hns3_pf *pf = &hns->pf; 3471 uint32_t tc_num = hns3_get_tc_num(hw); 3472 uint32_t half_mps = pf->mps >> 1; 3473 struct hns3_priv_buf *priv; 3474 uint32_t min_rx_priv; 3475 uint32_t rx_priv; 3476 uint8_t i; 3477 3478 rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc); 3479 if (tc_num) 3480 rx_priv = rx_priv / tc_num; 3481 3482 if (tc_num <= NEED_RESERVE_TC_NUM) 3483 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT; 3484 3485 /* 3486 * Minimum value of private buffer in rx direction (min_rx_priv) is 3487 * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private 3488 * buffer if rx_priv is greater than min_rx_priv. 3489 */ 3490 min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER + 3491 COMPENSATE_HALF_MPS_NUM * half_mps; 3492 min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT); 3493 rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT); 3494 3495 if (rx_priv < min_rx_priv) 3496 return false; 3497 3498 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3499 priv = &buf_alloc->priv_buf[i]; 3500 3501 priv->enable = 0; 3502 priv->wl.low = 0; 3503 priv->wl.high = 0; 3504 priv->buf_size = 0; 3505 3506 if (!(hw->hw_tc_map & BIT(i))) 3507 continue; 3508 3509 priv->enable = 1; 3510 priv->buf_size = rx_priv; 3511 priv->wl.high = rx_priv - pf->dv_buf_size; 3512 priv->wl.low = priv->wl.high - PRIV_WL_GAP; 3513 } 3514 3515 buf_alloc->s_buf.buf_size = 0; 3516 3517 return true; 3518 } 3519 3520 /* 3521 * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs 3522 * @hw: pointer to struct hns3_hw 3523 * @buf_alloc: pointer to buffer calculation data 3524 * @return: 0: calculate sucessful, negative: fail 3525 */ 3526 static int 3527 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3528 { 3529 /* When DCB is not supported, rx private buffer is not allocated. */ 3530 if (!hns3_dev_dcb_supported(hw)) { 3531 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3532 struct hns3_pf *pf = &hns->pf; 3533 uint32_t rx_all = pf->pkt_buf_size; 3534 3535 rx_all -= hns3_get_tx_buff_alloced(buf_alloc); 3536 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all)) 3537 return -ENOMEM; 3538 3539 return 0; 3540 } 3541 3542 /* 3543 * Try to allocate privated packet buffer for all TCs without share 3544 * buffer. 3545 */ 3546 if (hns3_only_alloc_priv_buff(hw, buf_alloc)) 3547 return 0; 3548 3549 /* 3550 * Try to allocate privated packet buffer for all TCs with share 3551 * buffer. 3552 */ 3553 if (hns3_rx_buf_calc_all(hw, true, buf_alloc)) 3554 return 0; 3555 3556 /* 3557 * For different application scenes, the enabled port number, TC number 3558 * and no_drop TC number are different. In order to obtain the better 3559 * performance, software could allocate the buffer size and configure 3560 * the waterline by tring to decrease the private buffer size according 3561 * to the order, namely, waterline of valided tc, pfc disabled tc, pfc 3562 * enabled tc. 3563 */ 3564 if (hns3_rx_buf_calc_all(hw, false, buf_alloc)) 3565 return 0; 3566 3567 if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc)) 3568 return 0; 3569 3570 if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc)) 3571 return 0; 3572 3573 return -ENOMEM; 3574 } 3575 3576 static int 3577 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3578 { 3579 struct hns3_rx_priv_buff_cmd *req; 3580 struct hns3_cmd_desc desc; 3581 uint32_t buf_size; 3582 int ret; 3583 int i; 3584 3585 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false); 3586 req = (struct hns3_rx_priv_buff_cmd *)desc.data; 3587 3588 /* Alloc private buffer TCs */ 3589 for (i = 0; i < HNS3_MAX_TC_NUM; i++) { 3590 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i]; 3591 3592 req->buf_num[i] = 3593 rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S); 3594 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B); 3595 } 3596 3597 buf_size = buf_alloc->s_buf.buf_size; 3598 req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) | 3599 (1 << HNS3_TC0_PRI_BUF_EN_B)); 3600 3601 ret = hns3_cmd_send(hw, &desc, 1); 3602 if (ret) 3603 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret); 3604 3605 return ret; 3606 } 3607 3608 static int 3609 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3610 { 3611 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2 3612 struct hns3_rx_priv_wl_buf *req; 3613 struct hns3_priv_buf *priv; 3614 struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM]; 3615 int i, j; 3616 int ret; 3617 3618 for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) { 3619 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC, 3620 false); 3621 req = (struct hns3_rx_priv_wl_buf *)desc[i].data; 3622 3623 /* The first descriptor set the NEXT bit to 1 */ 3624 if (i == 0) 3625 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3626 else 3627 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3628 3629 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3630 uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j; 3631 3632 priv = &buf_alloc->priv_buf[idx]; 3633 req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >> 3634 HNS3_BUF_UNIT_S); 3635 req->tc_wl[j].high |= 3636 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3637 req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >> 3638 HNS3_BUF_UNIT_S); 3639 req->tc_wl[j].low |= 3640 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3641 } 3642 } 3643 3644 /* Send 2 descriptor at one time */ 3645 ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM); 3646 if (ret) 3647 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d", 3648 ret); 3649 return ret; 3650 } 3651 3652 static int 3653 hns3_common_thrd_config(struct hns3_hw *hw, 3654 struct hns3_pkt_buf_alloc *buf_alloc) 3655 { 3656 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2 3657 struct hns3_shared_buf *s_buf = &buf_alloc->s_buf; 3658 struct hns3_rx_com_thrd *req; 3659 struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM]; 3660 struct hns3_tc_thrd *tc; 3661 int tc_idx; 3662 int i, j; 3663 int ret; 3664 3665 for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) { 3666 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC, 3667 false); 3668 req = (struct hns3_rx_com_thrd *)&desc[i].data; 3669 3670 /* The first descriptor set the NEXT bit to 1 */ 3671 if (i == 0) 3672 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3673 else 3674 desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 3675 3676 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) { 3677 tc_idx = i * HNS3_TC_NUM_ONE_DESC + j; 3678 tc = &s_buf->tc_thrd[tc_idx]; 3679 3680 req->com_thrd[j].high = 3681 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S); 3682 req->com_thrd[j].high |= 3683 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3684 req->com_thrd[j].low = 3685 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S); 3686 req->com_thrd[j].low |= 3687 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3688 } 3689 } 3690 3691 /* Send 2 descriptors at one time */ 3692 ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM); 3693 if (ret) 3694 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret); 3695 3696 return ret; 3697 } 3698 3699 static int 3700 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc) 3701 { 3702 struct hns3_shared_buf *buf = &buf_alloc->s_buf; 3703 struct hns3_rx_com_wl *req; 3704 struct hns3_cmd_desc desc; 3705 int ret; 3706 3707 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false); 3708 3709 req = (struct hns3_rx_com_wl *)desc.data; 3710 req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S); 3711 req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3712 3713 req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S); 3714 req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B)); 3715 3716 ret = hns3_cmd_send(hw, &desc, 1); 3717 if (ret) 3718 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret); 3719 3720 return ret; 3721 } 3722 3723 int 3724 hns3_buffer_alloc(struct hns3_hw *hw) 3725 { 3726 struct hns3_pkt_buf_alloc pkt_buf; 3727 int ret; 3728 3729 memset(&pkt_buf, 0, sizeof(pkt_buf)); 3730 ret = hns3_tx_buffer_calc(hw, &pkt_buf); 3731 if (ret) { 3732 PMD_INIT_LOG(ERR, 3733 "could not calc tx buffer size for all TCs %d", 3734 ret); 3735 return ret; 3736 } 3737 3738 ret = hns3_tx_buffer_alloc(hw, &pkt_buf); 3739 if (ret) { 3740 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret); 3741 return ret; 3742 } 3743 3744 ret = hns3_rx_buffer_calc(hw, &pkt_buf); 3745 if (ret) { 3746 PMD_INIT_LOG(ERR, 3747 "could not calc rx priv buffer size for all TCs %d", 3748 ret); 3749 return ret; 3750 } 3751 3752 ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf); 3753 if (ret) { 3754 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret); 3755 return ret; 3756 } 3757 3758 if (hns3_dev_dcb_supported(hw)) { 3759 ret = hns3_rx_priv_wl_config(hw, &pkt_buf); 3760 if (ret) { 3761 PMD_INIT_LOG(ERR, 3762 "could not configure rx private waterline %d", 3763 ret); 3764 return ret; 3765 } 3766 3767 ret = hns3_common_thrd_config(hw, &pkt_buf); 3768 if (ret) { 3769 PMD_INIT_LOG(ERR, 3770 "could not configure common threshold %d", 3771 ret); 3772 return ret; 3773 } 3774 } 3775 3776 ret = hns3_common_wl_config(hw, &pkt_buf); 3777 if (ret) 3778 PMD_INIT_LOG(ERR, "could not configure common waterline %d", 3779 ret); 3780 3781 return ret; 3782 } 3783 3784 static int 3785 hns3_mac_init(struct hns3_hw *hw) 3786 { 3787 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3788 struct hns3_mac *mac = &hw->mac; 3789 struct hns3_pf *pf = &hns->pf; 3790 int ret; 3791 3792 pf->support_sfp_query = true; 3793 mac->link_duplex = ETH_LINK_FULL_DUPLEX; 3794 ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex); 3795 if (ret) { 3796 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret); 3797 return ret; 3798 } 3799 3800 mac->link_status = ETH_LINK_DOWN; 3801 3802 return hns3_config_mtu(hw, pf->mps); 3803 } 3804 3805 static int 3806 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code) 3807 { 3808 #define HNS3_ETHERTYPE_SUCCESS_ADD 0 3809 #define HNS3_ETHERTYPE_ALREADY_ADD 1 3810 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW 2 3811 #define HNS3_ETHERTYPE_KEY_CONFLICT 3 3812 int return_status; 3813 3814 if (cmdq_resp) { 3815 PMD_INIT_LOG(ERR, 3816 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", 3817 cmdq_resp); 3818 return -EIO; 3819 } 3820 3821 switch (resp_code) { 3822 case HNS3_ETHERTYPE_SUCCESS_ADD: 3823 case HNS3_ETHERTYPE_ALREADY_ADD: 3824 return_status = 0; 3825 break; 3826 case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW: 3827 PMD_INIT_LOG(ERR, 3828 "add mac ethertype failed for manager table overflow."); 3829 return_status = -EIO; 3830 break; 3831 case HNS3_ETHERTYPE_KEY_CONFLICT: 3832 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict."); 3833 return_status = -EIO; 3834 break; 3835 default: 3836 PMD_INIT_LOG(ERR, 3837 "add mac ethertype failed for undefined, code=%d.", 3838 resp_code); 3839 return_status = -EIO; 3840 break; 3841 } 3842 3843 return return_status; 3844 } 3845 3846 static int 3847 hns3_add_mgr_tbl(struct hns3_hw *hw, 3848 const struct hns3_mac_mgr_tbl_entry_cmd *req) 3849 { 3850 struct hns3_cmd_desc desc; 3851 uint8_t resp_code; 3852 uint16_t retval; 3853 int ret; 3854 3855 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false); 3856 memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd)); 3857 3858 ret = hns3_cmd_send(hw, &desc, 1); 3859 if (ret) { 3860 PMD_INIT_LOG(ERR, 3861 "add mac ethertype failed for cmd_send, ret =%d.", 3862 ret); 3863 return ret; 3864 } 3865 3866 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff; 3867 retval = rte_le_to_cpu_16(desc.retval); 3868 3869 return hns3_get_mac_ethertype_cmd_status(retval, resp_code); 3870 } 3871 3872 static void 3873 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table, 3874 int *table_item_num) 3875 { 3876 struct hns3_mac_mgr_tbl_entry_cmd *tbl; 3877 3878 /* 3879 * In current version, we add one item in management table as below: 3880 * 0x0180C200000E -- LLDP MC address 3881 */ 3882 tbl = mgr_table; 3883 tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B; 3884 tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP); 3885 tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200)); 3886 tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E)); 3887 tbl->i_port_bitmap = 0x1; 3888 *table_item_num = 1; 3889 } 3890 3891 static int 3892 hns3_init_mgr_tbl(struct hns3_hw *hw) 3893 { 3894 #define HNS_MAC_MGR_TBL_MAX_SIZE 16 3895 struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE]; 3896 int table_item_num; 3897 int ret; 3898 int i; 3899 3900 memset(mgr_table, 0, sizeof(mgr_table)); 3901 hns3_prepare_mgr_tbl(mgr_table, &table_item_num); 3902 for (i = 0; i < table_item_num; i++) { 3903 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]); 3904 if (ret) { 3905 PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d", 3906 ret); 3907 return ret; 3908 } 3909 } 3910 3911 return 0; 3912 } 3913 3914 static void 3915 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc, 3916 bool en_mc, bool en_bc, int vport_id) 3917 { 3918 if (!param) 3919 return; 3920 3921 memset(param, 0, sizeof(struct hns3_promisc_param)); 3922 if (en_uc) 3923 param->enable = HNS3_PROMISC_EN_UC; 3924 if (en_mc) 3925 param->enable |= HNS3_PROMISC_EN_MC; 3926 if (en_bc) 3927 param->enable |= HNS3_PROMISC_EN_BC; 3928 param->vf_id = vport_id; 3929 } 3930 3931 static int 3932 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param) 3933 { 3934 struct hns3_promisc_cfg_cmd *req; 3935 struct hns3_cmd_desc desc; 3936 int ret; 3937 3938 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false); 3939 3940 req = (struct hns3_promisc_cfg_cmd *)desc.data; 3941 req->vf_id = param->vf_id; 3942 req->flag = (param->enable << HNS3_PROMISC_EN_B) | 3943 HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B; 3944 3945 ret = hns3_cmd_send(hw, &desc, 1); 3946 if (ret) 3947 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret); 3948 3949 return ret; 3950 } 3951 3952 static int 3953 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc) 3954 { 3955 struct hns3_promisc_param param; 3956 bool en_bc_pmc = true; 3957 uint8_t vf_id; 3958 3959 /* 3960 * In current version VF is not supported when PF is driven by DPDK 3961 * driver, just need to configure parameters for PF vport. 3962 */ 3963 vf_id = HNS3_PF_FUNC_ID; 3964 3965 hns3_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id); 3966 return hns3_cmd_set_promisc_mode(hw, ¶m); 3967 } 3968 3969 static int 3970 hns3_promisc_init(struct hns3_hw *hw) 3971 { 3972 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 3973 struct hns3_pf *pf = &hns->pf; 3974 struct hns3_promisc_param param; 3975 uint16_t func_id; 3976 int ret; 3977 3978 ret = hns3_set_promisc_mode(hw, false, false); 3979 if (ret) { 3980 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret); 3981 return ret; 3982 } 3983 3984 /* 3985 * In current version VFs are not supported when PF is driven by DPDK 3986 * driver. After PF has been taken over by DPDK, the original VF will 3987 * be invalid. So, there is a possibility of entry residues. It should 3988 * clear VFs's promisc mode to avoid unnecessary bandwidth usage 3989 * during init. 3990 */ 3991 for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) { 3992 hns3_promisc_param_init(¶m, false, false, false, func_id); 3993 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 3994 if (ret) { 3995 PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode," 3996 " ret = %d", func_id, ret); 3997 return ret; 3998 } 3999 } 4000 4001 return 0; 4002 } 4003 4004 static void 4005 hns3_promisc_uninit(struct hns3_hw *hw) 4006 { 4007 struct hns3_promisc_param param; 4008 uint16_t func_id; 4009 int ret; 4010 4011 func_id = HNS3_PF_FUNC_ID; 4012 4013 /* 4014 * In current version VFs are not supported when PF is driven by 4015 * DPDK driver, and VFs' promisc mode status has been cleared during 4016 * init and their status will not change. So just clear PF's promisc 4017 * mode status during uninit. 4018 */ 4019 hns3_promisc_param_init(¶m, false, false, false, func_id); 4020 ret = hns3_cmd_set_promisc_mode(hw, ¶m); 4021 if (ret) 4022 PMD_INIT_LOG(ERR, "failed to clear promisc status during" 4023 " uninit, ret = %d", ret); 4024 } 4025 4026 static int 4027 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev) 4028 { 4029 bool allmulti = dev->data->all_multicast ? true : false; 4030 struct hns3_adapter *hns = dev->data->dev_private; 4031 struct hns3_hw *hw = &hns->hw; 4032 uint64_t offloads; 4033 int err; 4034 int ret; 4035 4036 rte_spinlock_lock(&hw->lock); 4037 ret = hns3_set_promisc_mode(hw, true, true); 4038 if (ret) { 4039 rte_spinlock_unlock(&hw->lock); 4040 hns3_err(hw, "failed to enable promiscuous mode, ret = %d", 4041 ret); 4042 return ret; 4043 } 4044 4045 /* 4046 * When promiscuous mode was enabled, disable the vlan filter to let 4047 * all packets coming in in the receiving direction. 4048 */ 4049 offloads = dev->data->dev_conf.rxmode.offloads; 4050 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4051 ret = hns3_enable_vlan_filter(hns, false); 4052 if (ret) { 4053 hns3_err(hw, "failed to enable promiscuous mode due to " 4054 "failure to disable vlan filter, ret = %d", 4055 ret); 4056 err = hns3_set_promisc_mode(hw, false, allmulti); 4057 if (err) 4058 hns3_err(hw, "failed to restore promiscuous " 4059 "status after disable vlan filter " 4060 "failed during enabling promiscuous " 4061 "mode, ret = %d", ret); 4062 } 4063 } 4064 4065 rte_spinlock_unlock(&hw->lock); 4066 4067 return ret; 4068 } 4069 4070 static int 4071 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev) 4072 { 4073 bool allmulti = dev->data->all_multicast ? true : false; 4074 struct hns3_adapter *hns = dev->data->dev_private; 4075 struct hns3_hw *hw = &hns->hw; 4076 uint64_t offloads; 4077 int err; 4078 int ret; 4079 4080 /* If now in all_multicast mode, must remain in all_multicast mode. */ 4081 rte_spinlock_lock(&hw->lock); 4082 ret = hns3_set_promisc_mode(hw, false, allmulti); 4083 if (ret) { 4084 rte_spinlock_unlock(&hw->lock); 4085 hns3_err(hw, "failed to disable promiscuous mode, ret = %d", 4086 ret); 4087 return ret; 4088 } 4089 /* when promiscuous mode was disabled, restore the vlan filter status */ 4090 offloads = dev->data->dev_conf.rxmode.offloads; 4091 if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 4092 ret = hns3_enable_vlan_filter(hns, true); 4093 if (ret) { 4094 hns3_err(hw, "failed to disable promiscuous mode due to" 4095 " failure to restore vlan filter, ret = %d", 4096 ret); 4097 err = hns3_set_promisc_mode(hw, true, true); 4098 if (err) 4099 hns3_err(hw, "failed to restore promiscuous " 4100 "status after enabling vlan filter " 4101 "failed during disabling promiscuous " 4102 "mode, ret = %d", ret); 4103 } 4104 } 4105 rte_spinlock_unlock(&hw->lock); 4106 4107 return ret; 4108 } 4109 4110 static int 4111 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev) 4112 { 4113 struct hns3_adapter *hns = dev->data->dev_private; 4114 struct hns3_hw *hw = &hns->hw; 4115 int ret; 4116 4117 if (dev->data->promiscuous) 4118 return 0; 4119 4120 rte_spinlock_lock(&hw->lock); 4121 ret = hns3_set_promisc_mode(hw, false, true); 4122 rte_spinlock_unlock(&hw->lock); 4123 if (ret) 4124 hns3_err(hw, "failed to enable allmulticast mode, ret = %d", 4125 ret); 4126 4127 return ret; 4128 } 4129 4130 static int 4131 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev) 4132 { 4133 struct hns3_adapter *hns = dev->data->dev_private; 4134 struct hns3_hw *hw = &hns->hw; 4135 int ret; 4136 4137 /* If now in promiscuous mode, must remain in all_multicast mode. */ 4138 if (dev->data->promiscuous) 4139 return 0; 4140 4141 rte_spinlock_lock(&hw->lock); 4142 ret = hns3_set_promisc_mode(hw, false, false); 4143 rte_spinlock_unlock(&hw->lock); 4144 if (ret) 4145 hns3_err(hw, "failed to disable allmulticast mode, ret = %d", 4146 ret); 4147 4148 return ret; 4149 } 4150 4151 static int 4152 hns3_dev_promisc_restore(struct hns3_adapter *hns) 4153 { 4154 struct hns3_hw *hw = &hns->hw; 4155 bool allmulti = hw->data->all_multicast ? true : false; 4156 int ret; 4157 4158 if (hw->data->promiscuous) { 4159 ret = hns3_set_promisc_mode(hw, true, true); 4160 if (ret) 4161 hns3_err(hw, "failed to restore promiscuous mode, " 4162 "ret = %d", ret); 4163 return ret; 4164 } 4165 4166 ret = hns3_set_promisc_mode(hw, false, allmulti); 4167 if (ret) 4168 hns3_err(hw, "failed to restore allmulticast mode, ret = %d", 4169 ret); 4170 return ret; 4171 } 4172 4173 static int 4174 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed) 4175 { 4176 struct hns3_sfp_speed_cmd *resp; 4177 struct hns3_cmd_desc desc; 4178 int ret; 4179 4180 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true); 4181 resp = (struct hns3_sfp_speed_cmd *)desc.data; 4182 ret = hns3_cmd_send(hw, &desc, 1); 4183 if (ret == -EOPNOTSUPP) { 4184 hns3_err(hw, "IMP do not support get SFP speed %d", ret); 4185 return ret; 4186 } else if (ret) { 4187 hns3_err(hw, "get sfp speed failed %d", ret); 4188 return ret; 4189 } 4190 4191 *speed = resp->sfp_speed; 4192 4193 return 0; 4194 } 4195 4196 static uint8_t 4197 hns3_check_speed_dup(uint8_t duplex, uint32_t speed) 4198 { 4199 if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M)) 4200 duplex = ETH_LINK_FULL_DUPLEX; 4201 4202 return duplex; 4203 } 4204 4205 static int 4206 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex) 4207 { 4208 struct hns3_mac *mac = &hw->mac; 4209 int ret; 4210 4211 duplex = hns3_check_speed_dup(duplex, speed); 4212 if (mac->link_speed == speed && mac->link_duplex == duplex) 4213 return 0; 4214 4215 ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex); 4216 if (ret) 4217 return ret; 4218 4219 mac->link_speed = speed; 4220 mac->link_duplex = duplex; 4221 4222 return 0; 4223 } 4224 4225 static int 4226 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev) 4227 { 4228 struct hns3_adapter *hns = eth_dev->data->dev_private; 4229 struct hns3_hw *hw = &hns->hw; 4230 struct hns3_pf *pf = &hns->pf; 4231 uint32_t speed; 4232 int ret; 4233 4234 /* If IMP do not support get SFP/qSFP speed, return directly */ 4235 if (!pf->support_sfp_query) 4236 return 0; 4237 4238 ret = hns3_get_sfp_speed(hw, &speed); 4239 if (ret == -EOPNOTSUPP) { 4240 pf->support_sfp_query = false; 4241 return ret; 4242 } else if (ret) 4243 return ret; 4244 4245 if (speed == ETH_SPEED_NUM_NONE) 4246 return 0; /* do nothing if no SFP */ 4247 4248 /* Config full duplex for SFP */ 4249 return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX); 4250 } 4251 4252 static int 4253 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable) 4254 { 4255 struct hns3_config_mac_mode_cmd *req; 4256 struct hns3_cmd_desc desc; 4257 uint32_t loop_en = 0; 4258 uint8_t val = 0; 4259 int ret; 4260 4261 req = (struct hns3_config_mac_mode_cmd *)desc.data; 4262 4263 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false); 4264 if (enable) 4265 val = 1; 4266 hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val); 4267 hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val); 4268 hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val); 4269 hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val); 4270 hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0); 4271 hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0); 4272 hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0); 4273 hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0); 4274 hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val); 4275 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val); 4276 4277 /* 4278 * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC 4279 * when receiving frames. Otherwise, CRC will be stripped. 4280 */ 4281 if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) 4282 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0); 4283 else 4284 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val); 4285 hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val); 4286 hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val); 4287 hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val); 4288 req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en); 4289 4290 ret = hns3_cmd_send(hw, &desc, 1); 4291 if (ret) 4292 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret); 4293 4294 return ret; 4295 } 4296 4297 static int 4298 hns3_get_mac_link_status(struct hns3_hw *hw) 4299 { 4300 struct hns3_link_status_cmd *req; 4301 struct hns3_cmd_desc desc; 4302 int link_status; 4303 int ret; 4304 4305 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true); 4306 ret = hns3_cmd_send(hw, &desc, 1); 4307 if (ret) { 4308 hns3_err(hw, "get link status cmd failed %d", ret); 4309 return ETH_LINK_DOWN; 4310 } 4311 4312 req = (struct hns3_link_status_cmd *)desc.data; 4313 link_status = req->status & HNS3_LINK_STATUS_UP_M; 4314 4315 return !!link_status; 4316 } 4317 4318 void 4319 hns3_update_link_status(struct hns3_hw *hw) 4320 { 4321 int state; 4322 4323 state = hns3_get_mac_link_status(hw); 4324 if (state != hw->mac.link_status) { 4325 hw->mac.link_status = state; 4326 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down"); 4327 } 4328 } 4329 4330 static void 4331 hns3_service_handler(void *param) 4332 { 4333 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param; 4334 struct hns3_adapter *hns = eth_dev->data->dev_private; 4335 struct hns3_hw *hw = &hns->hw; 4336 4337 if (!hns3_is_reset_pending(hns)) { 4338 hns3_update_speed_duplex(eth_dev); 4339 hns3_update_link_status(hw); 4340 } else 4341 hns3_warn(hw, "Cancel the query when reset is pending"); 4342 4343 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev); 4344 } 4345 4346 static int 4347 hns3_init_hardware(struct hns3_adapter *hns) 4348 { 4349 struct hns3_hw *hw = &hns->hw; 4350 int ret; 4351 4352 ret = hns3_map_tqp(hw); 4353 if (ret) { 4354 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret); 4355 return ret; 4356 } 4357 4358 ret = hns3_init_umv_space(hw); 4359 if (ret) { 4360 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret); 4361 return ret; 4362 } 4363 4364 ret = hns3_mac_init(hw); 4365 if (ret) { 4366 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret); 4367 goto err_mac_init; 4368 } 4369 4370 ret = hns3_init_mgr_tbl(hw); 4371 if (ret) { 4372 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret); 4373 goto err_mac_init; 4374 } 4375 4376 ret = hns3_promisc_init(hw); 4377 if (ret) { 4378 PMD_INIT_LOG(ERR, "Failed to init promisc: %d", 4379 ret); 4380 goto err_mac_init; 4381 } 4382 4383 ret = hns3_init_vlan_config(hns); 4384 if (ret) { 4385 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret); 4386 goto err_mac_init; 4387 } 4388 4389 ret = hns3_dcb_init(hw); 4390 if (ret) { 4391 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret); 4392 goto err_mac_init; 4393 } 4394 4395 ret = hns3_init_fd_config(hns); 4396 if (ret) { 4397 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret); 4398 goto err_mac_init; 4399 } 4400 4401 ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX); 4402 if (ret) { 4403 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret); 4404 goto err_mac_init; 4405 } 4406 4407 ret = hns3_config_gro(hw, false); 4408 if (ret) { 4409 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret); 4410 goto err_mac_init; 4411 } 4412 4413 /* 4414 * In the initialization clearing the all hardware mapping relationship 4415 * configurations between queues and interrupt vectors is needed, so 4416 * some error caused by the residual configurations, such as the 4417 * unexpected interrupt, can be avoid. 4418 */ 4419 ret = hns3_init_ring_with_vector(hw); 4420 if (ret) { 4421 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret); 4422 goto err_mac_init; 4423 } 4424 4425 return 0; 4426 4427 err_mac_init: 4428 hns3_uninit_umv_space(hw); 4429 return ret; 4430 } 4431 4432 static int 4433 hns3_clear_hw(struct hns3_hw *hw) 4434 { 4435 struct hns3_cmd_desc desc; 4436 int ret; 4437 4438 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false); 4439 4440 ret = hns3_cmd_send(hw, &desc, 1); 4441 if (ret && ret != -EOPNOTSUPP) 4442 return ret; 4443 4444 return 0; 4445 } 4446 4447 static void 4448 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable) 4449 { 4450 uint32_t val; 4451 4452 /* 4453 * The new firmware support report more hardware error types by 4454 * msix mode. These errors are defined as RAS errors in hardware 4455 * and belong to a different type from the MSI-x errors processed 4456 * by the network driver. 4457 * 4458 * Network driver should open the new error report on initialition 4459 */ 4460 val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 4461 hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0); 4462 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val); 4463 } 4464 4465 static int 4466 hns3_init_pf(struct rte_eth_dev *eth_dev) 4467 { 4468 struct rte_device *dev = eth_dev->device; 4469 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4470 struct hns3_adapter *hns = eth_dev->data->dev_private; 4471 struct hns3_hw *hw = &hns->hw; 4472 int ret; 4473 4474 PMD_INIT_FUNC_TRACE(); 4475 4476 /* Get hardware io base address from pcie BAR2 IO space */ 4477 hw->io_base = pci_dev->mem_resource[2].addr; 4478 4479 /* Firmware command queue initialize */ 4480 ret = hns3_cmd_init_queue(hw); 4481 if (ret) { 4482 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret); 4483 goto err_cmd_init_queue; 4484 } 4485 4486 hns3_clear_all_event_cause(hw); 4487 4488 /* Firmware command initialize */ 4489 ret = hns3_cmd_init(hw); 4490 if (ret) { 4491 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret); 4492 goto err_cmd_init; 4493 } 4494 4495 /* 4496 * To ensure that the hardware environment is clean during 4497 * initialization, the driver actively clear the hardware environment 4498 * during initialization, including PF and corresponding VFs' vlan, mac, 4499 * flow table configurations, etc. 4500 */ 4501 ret = hns3_clear_hw(hw); 4502 if (ret) { 4503 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret); 4504 goto err_cmd_init; 4505 } 4506 4507 hns3_config_all_msix_error(hw, true); 4508 4509 ret = rte_intr_callback_register(&pci_dev->intr_handle, 4510 hns3_interrupt_handler, 4511 eth_dev); 4512 if (ret) { 4513 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret); 4514 goto err_intr_callback_register; 4515 } 4516 4517 /* Enable interrupt */ 4518 rte_intr_enable(&pci_dev->intr_handle); 4519 hns3_pf_enable_irq0(hw); 4520 4521 /* Get configuration */ 4522 ret = hns3_get_configuration(hw); 4523 if (ret) { 4524 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret); 4525 goto err_get_config; 4526 } 4527 4528 ret = hns3_init_hardware(hns); 4529 if (ret) { 4530 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret); 4531 goto err_get_config; 4532 } 4533 4534 /* Initialize flow director filter list & hash */ 4535 ret = hns3_fdir_filter_init(hns); 4536 if (ret) { 4537 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret); 4538 goto err_hw_init; 4539 } 4540 4541 hns3_set_default_rss_args(hw); 4542 4543 ret = hns3_enable_hw_error_intr(hns, true); 4544 if (ret) { 4545 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d", 4546 ret); 4547 goto err_fdir; 4548 } 4549 4550 return 0; 4551 4552 err_fdir: 4553 hns3_fdir_filter_uninit(hns); 4554 err_hw_init: 4555 hns3_uninit_umv_space(hw); 4556 4557 err_get_config: 4558 hns3_pf_disable_irq0(hw); 4559 rte_intr_disable(&pci_dev->intr_handle); 4560 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 4561 eth_dev); 4562 err_intr_callback_register: 4563 err_cmd_init: 4564 hns3_cmd_uninit(hw); 4565 hns3_cmd_destroy_queue(hw); 4566 err_cmd_init_queue: 4567 hw->io_base = NULL; 4568 4569 return ret; 4570 } 4571 4572 static void 4573 hns3_uninit_pf(struct rte_eth_dev *eth_dev) 4574 { 4575 struct hns3_adapter *hns = eth_dev->data->dev_private; 4576 struct rte_device *dev = eth_dev->device; 4577 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev); 4578 struct hns3_hw *hw = &hns->hw; 4579 4580 PMD_INIT_FUNC_TRACE(); 4581 4582 hns3_enable_hw_error_intr(hns, false); 4583 hns3_rss_uninit(hns); 4584 (void)hns3_config_gro(hw, false); 4585 hns3_promisc_uninit(hw); 4586 hns3_fdir_filter_uninit(hns); 4587 hns3_uninit_umv_space(hw); 4588 hns3_pf_disable_irq0(hw); 4589 rte_intr_disable(&pci_dev->intr_handle); 4590 hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler, 4591 eth_dev); 4592 hns3_config_all_msix_error(hw, false); 4593 hns3_cmd_uninit(hw); 4594 hns3_cmd_destroy_queue(hw); 4595 hw->io_base = NULL; 4596 } 4597 4598 static int 4599 hns3_do_start(struct hns3_adapter *hns, bool reset_queue) 4600 { 4601 struct hns3_hw *hw = &hns->hw; 4602 int ret; 4603 4604 ret = hns3_dcb_cfg_update(hns); 4605 if (ret) 4606 return ret; 4607 4608 /* Enable queues */ 4609 ret = hns3_start_queues(hns, reset_queue); 4610 if (ret) { 4611 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret); 4612 return ret; 4613 } 4614 4615 /* Enable MAC */ 4616 ret = hns3_cfg_mac_mode(hw, true); 4617 if (ret) { 4618 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret); 4619 goto err_config_mac_mode; 4620 } 4621 return 0; 4622 4623 err_config_mac_mode: 4624 hns3_stop_queues(hns, true); 4625 return ret; 4626 } 4627 4628 static int 4629 hns3_map_rx_interrupt(struct rte_eth_dev *dev) 4630 { 4631 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4632 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4633 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4634 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 4635 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 4636 uint32_t intr_vector; 4637 uint16_t q_id; 4638 int ret; 4639 4640 if (dev->data->dev_conf.intr_conf.rxq == 0) 4641 return 0; 4642 4643 /* disable uio/vfio intr/eventfd mapping */ 4644 rte_intr_disable(intr_handle); 4645 4646 /* check and configure queue intr-vector mapping */ 4647 if (rte_intr_cap_multiple(intr_handle) || 4648 !RTE_ETH_DEV_SRIOV(dev).active) { 4649 intr_vector = hw->used_rx_queues; 4650 /* creates event fd for each intr vector when MSIX is used */ 4651 if (rte_intr_efd_enable(intr_handle, intr_vector)) 4652 return -EINVAL; 4653 } 4654 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 4655 intr_handle->intr_vec = 4656 rte_zmalloc("intr_vec", 4657 hw->used_rx_queues * sizeof(int), 0); 4658 if (intr_handle->intr_vec == NULL) { 4659 hns3_err(hw, "Failed to allocate %d rx_queues" 4660 " intr_vec", hw->used_rx_queues); 4661 ret = -ENOMEM; 4662 goto alloc_intr_vec_error; 4663 } 4664 } 4665 4666 if (rte_intr_allow_others(intr_handle)) { 4667 vec = RTE_INTR_VEC_RXTX_OFFSET; 4668 base = RTE_INTR_VEC_RXTX_OFFSET; 4669 } 4670 if (rte_intr_dp_is_en(intr_handle)) { 4671 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 4672 ret = hns3_bind_ring_with_vector(hw, vec, true, 4673 HNS3_RING_TYPE_RX, 4674 q_id); 4675 if (ret) 4676 goto bind_vector_error; 4677 intr_handle->intr_vec[q_id] = vec; 4678 if (vec < base + intr_handle->nb_efd - 1) 4679 vec++; 4680 } 4681 } 4682 rte_intr_enable(intr_handle); 4683 return 0; 4684 4685 bind_vector_error: 4686 rte_intr_efd_disable(intr_handle); 4687 if (intr_handle->intr_vec) { 4688 free(intr_handle->intr_vec); 4689 intr_handle->intr_vec = NULL; 4690 } 4691 return ret; 4692 alloc_intr_vec_error: 4693 rte_intr_efd_disable(intr_handle); 4694 return ret; 4695 } 4696 4697 static int 4698 hns3_restore_rx_interrupt(struct hns3_hw *hw) 4699 { 4700 struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id]; 4701 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4702 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4703 uint16_t q_id; 4704 int ret; 4705 4706 if (dev->data->dev_conf.intr_conf.rxq == 0) 4707 return 0; 4708 4709 if (rte_intr_dp_is_en(intr_handle)) { 4710 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 4711 ret = hns3_bind_ring_with_vector(hw, 4712 intr_handle->intr_vec[q_id], true, 4713 HNS3_RING_TYPE_RX, q_id); 4714 if (ret) 4715 return ret; 4716 } 4717 } 4718 4719 return 0; 4720 } 4721 4722 static void 4723 hns3_restore_filter(struct rte_eth_dev *dev) 4724 { 4725 hns3_restore_rss_filter(dev); 4726 } 4727 4728 static int 4729 hns3_dev_start(struct rte_eth_dev *dev) 4730 { 4731 struct hns3_adapter *hns = dev->data->dev_private; 4732 struct hns3_hw *hw = &hns->hw; 4733 int ret; 4734 4735 PMD_INIT_FUNC_TRACE(); 4736 if (rte_atomic16_read(&hw->reset.resetting)) 4737 return -EBUSY; 4738 4739 rte_spinlock_lock(&hw->lock); 4740 hw->adapter_state = HNS3_NIC_STARTING; 4741 4742 ret = hns3_do_start(hns, true); 4743 if (ret) { 4744 hw->adapter_state = HNS3_NIC_CONFIGURED; 4745 rte_spinlock_unlock(&hw->lock); 4746 return ret; 4747 } 4748 ret = hns3_map_rx_interrupt(dev); 4749 if (ret) { 4750 hw->adapter_state = HNS3_NIC_CONFIGURED; 4751 rte_spinlock_unlock(&hw->lock); 4752 return ret; 4753 } 4754 4755 hw->adapter_state = HNS3_NIC_STARTED; 4756 rte_spinlock_unlock(&hw->lock); 4757 4758 hns3_rx_scattered_calc(dev); 4759 hns3_set_rxtx_function(dev); 4760 hns3_mp_req_start_rxtx(dev); 4761 rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev); 4762 4763 hns3_restore_filter(dev); 4764 4765 /* Enable interrupt of all rx queues before enabling queues */ 4766 hns3_dev_all_rx_queue_intr_enable(hw, true); 4767 /* 4768 * When finished the initialization, enable queues to receive/transmit 4769 * packets. 4770 */ 4771 hns3_enable_all_queues(hw, true); 4772 4773 hns3_info(hw, "hns3 dev start successful!"); 4774 return 0; 4775 } 4776 4777 static int 4778 hns3_do_stop(struct hns3_adapter *hns) 4779 { 4780 struct hns3_hw *hw = &hns->hw; 4781 bool reset_queue; 4782 int ret; 4783 4784 ret = hns3_cfg_mac_mode(hw, false); 4785 if (ret) 4786 return ret; 4787 hw->mac.link_status = ETH_LINK_DOWN; 4788 4789 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) { 4790 hns3_configure_all_mac_addr(hns, true); 4791 reset_queue = true; 4792 } else 4793 reset_queue = false; 4794 hw->mac.default_addr_setted = false; 4795 return hns3_stop_queues(hns, reset_queue); 4796 } 4797 4798 static void 4799 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev) 4800 { 4801 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4802 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4803 struct hns3_adapter *hns = dev->data->dev_private; 4804 struct hns3_hw *hw = &hns->hw; 4805 uint8_t base = RTE_INTR_VEC_ZERO_OFFSET; 4806 uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET; 4807 uint16_t q_id; 4808 4809 if (dev->data->dev_conf.intr_conf.rxq == 0) 4810 return; 4811 4812 /* unmap the ring with vector */ 4813 if (rte_intr_allow_others(intr_handle)) { 4814 vec = RTE_INTR_VEC_RXTX_OFFSET; 4815 base = RTE_INTR_VEC_RXTX_OFFSET; 4816 } 4817 if (rte_intr_dp_is_en(intr_handle)) { 4818 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) { 4819 (void)hns3_bind_ring_with_vector(hw, vec, false, 4820 HNS3_RING_TYPE_RX, 4821 q_id); 4822 if (vec < base + intr_handle->nb_efd - 1) 4823 vec++; 4824 } 4825 } 4826 /* Clean datapath event and queue/vec mapping */ 4827 rte_intr_efd_disable(intr_handle); 4828 if (intr_handle->intr_vec) { 4829 rte_free(intr_handle->intr_vec); 4830 intr_handle->intr_vec = NULL; 4831 } 4832 } 4833 4834 static void 4835 hns3_dev_stop(struct rte_eth_dev *dev) 4836 { 4837 struct hns3_adapter *hns = dev->data->dev_private; 4838 struct hns3_hw *hw = &hns->hw; 4839 4840 PMD_INIT_FUNC_TRACE(); 4841 4842 hw->adapter_state = HNS3_NIC_STOPPING; 4843 hns3_set_rxtx_function(dev); 4844 rte_wmb(); 4845 /* Disable datapath on secondary process. */ 4846 hns3_mp_req_stop_rxtx(dev); 4847 /* Prevent crashes when queues are still in use. */ 4848 rte_delay_ms(hw->tqps_num); 4849 4850 rte_spinlock_lock(&hw->lock); 4851 if (rte_atomic16_read(&hw->reset.resetting) == 0) { 4852 hns3_do_stop(hns); 4853 hns3_unmap_rx_interrupt(dev); 4854 hns3_dev_release_mbufs(hns); 4855 hw->adapter_state = HNS3_NIC_CONFIGURED; 4856 } 4857 hns3_rx_scattered_reset(dev); 4858 rte_eal_alarm_cancel(hns3_service_handler, dev); 4859 rte_spinlock_unlock(&hw->lock); 4860 } 4861 4862 static void 4863 hns3_dev_close(struct rte_eth_dev *eth_dev) 4864 { 4865 struct hns3_adapter *hns = eth_dev->data->dev_private; 4866 struct hns3_hw *hw = &hns->hw; 4867 4868 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 4869 rte_free(eth_dev->process_private); 4870 eth_dev->process_private = NULL; 4871 return; 4872 } 4873 4874 if (hw->adapter_state == HNS3_NIC_STARTED) 4875 hns3_dev_stop(eth_dev); 4876 4877 hw->adapter_state = HNS3_NIC_CLOSING; 4878 hns3_reset_abort(hns); 4879 hw->adapter_state = HNS3_NIC_CLOSED; 4880 4881 hns3_configure_all_mc_mac_addr(hns, true); 4882 hns3_remove_all_vlan_table(hns); 4883 hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0); 4884 hns3_uninit_pf(eth_dev); 4885 hns3_free_all_queues(eth_dev); 4886 rte_free(hw->reset.wait_data); 4887 rte_free(eth_dev->process_private); 4888 eth_dev->process_private = NULL; 4889 hns3_mp_uninit_primary(); 4890 hns3_warn(hw, "Close port %d finished", hw->data->port_id); 4891 } 4892 4893 static int 4894 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4895 { 4896 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4897 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4898 4899 fc_conf->pause_time = pf->pause_time; 4900 4901 /* return fc current mode */ 4902 switch (hw->current_mode) { 4903 case HNS3_FC_FULL: 4904 fc_conf->mode = RTE_FC_FULL; 4905 break; 4906 case HNS3_FC_TX_PAUSE: 4907 fc_conf->mode = RTE_FC_TX_PAUSE; 4908 break; 4909 case HNS3_FC_RX_PAUSE: 4910 fc_conf->mode = RTE_FC_RX_PAUSE; 4911 break; 4912 case HNS3_FC_NONE: 4913 default: 4914 fc_conf->mode = RTE_FC_NONE; 4915 break; 4916 } 4917 4918 return 0; 4919 } 4920 4921 static void 4922 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode) 4923 { 4924 switch (mode) { 4925 case RTE_FC_NONE: 4926 hw->requested_mode = HNS3_FC_NONE; 4927 break; 4928 case RTE_FC_RX_PAUSE: 4929 hw->requested_mode = HNS3_FC_RX_PAUSE; 4930 break; 4931 case RTE_FC_TX_PAUSE: 4932 hw->requested_mode = HNS3_FC_TX_PAUSE; 4933 break; 4934 case RTE_FC_FULL: 4935 hw->requested_mode = HNS3_FC_FULL; 4936 break; 4937 default: 4938 hw->requested_mode = HNS3_FC_NONE; 4939 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is " 4940 "configured to RTE_FC_NONE", mode); 4941 break; 4942 } 4943 } 4944 4945 static int 4946 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4947 { 4948 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4949 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4950 int ret; 4951 4952 if (fc_conf->high_water || fc_conf->low_water || 4953 fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) { 4954 hns3_err(hw, "Unsupported flow control settings specified, " 4955 "high_water(%u), low_water(%u), send_xon(%u) and " 4956 "mac_ctrl_frame_fwd(%u) must be set to '0'", 4957 fc_conf->high_water, fc_conf->low_water, 4958 fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd); 4959 return -EINVAL; 4960 } 4961 if (fc_conf->autoneg) { 4962 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 4963 return -EINVAL; 4964 } 4965 if (!fc_conf->pause_time) { 4966 hns3_err(hw, "Invalid pause time %d setting.", 4967 fc_conf->pause_time); 4968 return -EINVAL; 4969 } 4970 4971 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 4972 hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) { 4973 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. " 4974 "current_fc_status = %d", hw->current_fc_status); 4975 return -EOPNOTSUPP; 4976 } 4977 4978 hns3_get_fc_mode(hw, fc_conf->mode); 4979 if (hw->requested_mode == hw->current_mode && 4980 pf->pause_time == fc_conf->pause_time) 4981 return 0; 4982 4983 rte_spinlock_lock(&hw->lock); 4984 ret = hns3_fc_enable(dev, fc_conf); 4985 rte_spinlock_unlock(&hw->lock); 4986 4987 return ret; 4988 } 4989 4990 static int 4991 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev, 4992 struct rte_eth_pfc_conf *pfc_conf) 4993 { 4994 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4995 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 4996 uint8_t priority; 4997 int ret; 4998 4999 if (!hns3_dev_dcb_supported(hw)) { 5000 hns3_err(hw, "This port does not support dcb configurations."); 5001 return -EOPNOTSUPP; 5002 } 5003 5004 if (pfc_conf->fc.high_water || pfc_conf->fc.low_water || 5005 pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) { 5006 hns3_err(hw, "Unsupported flow control settings specified, " 5007 "high_water(%u), low_water(%u), send_xon(%u) and " 5008 "mac_ctrl_frame_fwd(%u) must be set to '0'", 5009 pfc_conf->fc.high_water, pfc_conf->fc.low_water, 5010 pfc_conf->fc.send_xon, 5011 pfc_conf->fc.mac_ctrl_frame_fwd); 5012 return -EINVAL; 5013 } 5014 if (pfc_conf->fc.autoneg) { 5015 hns3_err(hw, "Unsupported fc auto-negotiation setting."); 5016 return -EINVAL; 5017 } 5018 if (pfc_conf->fc.pause_time == 0) { 5019 hns3_err(hw, "Invalid pause time %d setting.", 5020 pfc_conf->fc.pause_time); 5021 return -EINVAL; 5022 } 5023 5024 if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE || 5025 hw->current_fc_status == HNS3_FC_STATUS_PFC)) { 5026 hns3_err(hw, "MAC pause is enabled. Cannot set PFC." 5027 "current_fc_status = %d", hw->current_fc_status); 5028 return -EOPNOTSUPP; 5029 } 5030 5031 priority = pfc_conf->priority; 5032 hns3_get_fc_mode(hw, pfc_conf->fc.mode); 5033 if (hw->dcb_info.pfc_en & BIT(priority) && 5034 hw->requested_mode == hw->current_mode && 5035 pfc_conf->fc.pause_time == pf->pause_time) 5036 return 0; 5037 5038 rte_spinlock_lock(&hw->lock); 5039 ret = hns3_dcb_pfc_enable(dev, pfc_conf); 5040 rte_spinlock_unlock(&hw->lock); 5041 5042 return ret; 5043 } 5044 5045 static int 5046 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info) 5047 { 5048 struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5049 struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private); 5050 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode; 5051 int i; 5052 5053 rte_spinlock_lock(&hw->lock); 5054 if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) 5055 dcb_info->nb_tcs = pf->local_max_tc; 5056 else 5057 dcb_info->nb_tcs = 1; 5058 5059 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) 5060 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i]; 5061 for (i = 0; i < dcb_info->nb_tcs; i++) 5062 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i]; 5063 5064 for (i = 0; i < hw->num_tc; i++) { 5065 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i; 5066 dcb_info->tc_queue.tc_txq[0][i].base = 5067 hw->tc_queue[i].tqp_offset; 5068 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size; 5069 dcb_info->tc_queue.tc_txq[0][i].nb_queue = 5070 hw->tc_queue[i].tqp_count; 5071 } 5072 rte_spinlock_unlock(&hw->lock); 5073 5074 return 0; 5075 } 5076 5077 static int 5078 hns3_reinit_dev(struct hns3_adapter *hns) 5079 { 5080 struct hns3_hw *hw = &hns->hw; 5081 int ret; 5082 5083 ret = hns3_cmd_init(hw); 5084 if (ret) { 5085 hns3_err(hw, "Failed to init cmd: %d", ret); 5086 return ret; 5087 } 5088 5089 ret = hns3_reset_all_queues(hns); 5090 if (ret) { 5091 hns3_err(hw, "Failed to reset all queues: %d", ret); 5092 return ret; 5093 } 5094 5095 ret = hns3_init_hardware(hns); 5096 if (ret) { 5097 hns3_err(hw, "Failed to init hardware: %d", ret); 5098 return ret; 5099 } 5100 5101 ret = hns3_enable_hw_error_intr(hns, true); 5102 if (ret) { 5103 hns3_err(hw, "fail to enable hw error interrupts: %d", 5104 ret); 5105 return ret; 5106 } 5107 hns3_info(hw, "Reset done, driver initialization finished."); 5108 5109 return 0; 5110 } 5111 5112 static bool 5113 is_pf_reset_done(struct hns3_hw *hw) 5114 { 5115 uint32_t val, reg, reg_bit; 5116 5117 switch (hw->reset.level) { 5118 case HNS3_IMP_RESET: 5119 reg = HNS3_GLOBAL_RESET_REG; 5120 reg_bit = HNS3_IMP_RESET_BIT; 5121 break; 5122 case HNS3_GLOBAL_RESET: 5123 reg = HNS3_GLOBAL_RESET_REG; 5124 reg_bit = HNS3_GLOBAL_RESET_BIT; 5125 break; 5126 case HNS3_FUNC_RESET: 5127 reg = HNS3_FUN_RST_ING; 5128 reg_bit = HNS3_FUN_RST_ING_B; 5129 break; 5130 case HNS3_FLR_RESET: 5131 default: 5132 hns3_err(hw, "Wait for unsupported reset level: %d", 5133 hw->reset.level); 5134 return true; 5135 } 5136 val = hns3_read_dev(hw, reg); 5137 if (hns3_get_bit(val, reg_bit)) 5138 return false; 5139 else 5140 return true; 5141 } 5142 5143 bool 5144 hns3_is_reset_pending(struct hns3_adapter *hns) 5145 { 5146 struct hns3_hw *hw = &hns->hw; 5147 enum hns3_reset_level reset; 5148 5149 hns3_check_event_cause(hns, NULL); 5150 reset = hns3_get_reset_level(hns, &hw->reset.pending); 5151 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 5152 hns3_warn(hw, "High level reset %d is pending", reset); 5153 return true; 5154 } 5155 reset = hns3_get_reset_level(hns, &hw->reset.request); 5156 if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { 5157 hns3_warn(hw, "High level reset %d is request", reset); 5158 return true; 5159 } 5160 return false; 5161 } 5162 5163 static int 5164 hns3_wait_hardware_ready(struct hns3_adapter *hns) 5165 { 5166 struct hns3_hw *hw = &hns->hw; 5167 struct hns3_wait_data *wait_data = hw->reset.wait_data; 5168 struct timeval tv; 5169 5170 if (wait_data->result == HNS3_WAIT_SUCCESS) 5171 return 0; 5172 else if (wait_data->result == HNS3_WAIT_TIMEOUT) { 5173 gettimeofday(&tv, NULL); 5174 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld", 5175 tv.tv_sec, tv.tv_usec); 5176 return -ETIME; 5177 } else if (wait_data->result == HNS3_WAIT_REQUEST) 5178 return -EAGAIN; 5179 5180 wait_data->hns = hns; 5181 wait_data->check_completion = is_pf_reset_done; 5182 wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT * 5183 HNS3_RESET_WAIT_MS + get_timeofday_ms(); 5184 wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC; 5185 wait_data->count = HNS3_RESET_WAIT_CNT; 5186 wait_data->result = HNS3_WAIT_REQUEST; 5187 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data); 5188 return -EAGAIN; 5189 } 5190 5191 static int 5192 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id) 5193 { 5194 struct hns3_cmd_desc desc; 5195 struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data; 5196 5197 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); 5198 hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1); 5199 req->fun_reset_vfid = func_id; 5200 5201 return hns3_cmd_send(hw, &desc, 1); 5202 } 5203 5204 static int 5205 hns3_imp_reset_cmd(struct hns3_hw *hw) 5206 { 5207 struct hns3_cmd_desc desc; 5208 5209 hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false); 5210 desc.data[0] = 0xeedd; 5211 5212 return hns3_cmd_send(hw, &desc, 1); 5213 } 5214 5215 static void 5216 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) 5217 { 5218 struct hns3_hw *hw = &hns->hw; 5219 struct timeval tv; 5220 uint32_t val; 5221 5222 gettimeofday(&tv, NULL); 5223 if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) || 5224 hns3_read_dev(hw, HNS3_FUN_RST_ING)) { 5225 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld", 5226 tv.tv_sec, tv.tv_usec); 5227 return; 5228 } 5229 5230 switch (reset_level) { 5231 case HNS3_IMP_RESET: 5232 hns3_imp_reset_cmd(hw); 5233 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld", 5234 tv.tv_sec, tv.tv_usec); 5235 break; 5236 case HNS3_GLOBAL_RESET: 5237 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG); 5238 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1); 5239 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val); 5240 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld", 5241 tv.tv_sec, tv.tv_usec); 5242 break; 5243 case HNS3_FUNC_RESET: 5244 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld", 5245 tv.tv_sec, tv.tv_usec); 5246 /* schedule again to check later */ 5247 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending); 5248 hns3_schedule_reset(hns); 5249 break; 5250 default: 5251 hns3_warn(hw, "Unsupported reset level: %d", reset_level); 5252 return; 5253 } 5254 hns3_atomic_clear_bit(reset_level, &hw->reset.request); 5255 } 5256 5257 static enum hns3_reset_level 5258 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels) 5259 { 5260 struct hns3_hw *hw = &hns->hw; 5261 enum hns3_reset_level reset_level = HNS3_NONE_RESET; 5262 5263 /* Return the highest priority reset level amongst all */ 5264 if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels)) 5265 reset_level = HNS3_IMP_RESET; 5266 else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels)) 5267 reset_level = HNS3_GLOBAL_RESET; 5268 else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels)) 5269 reset_level = HNS3_FUNC_RESET; 5270 else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels)) 5271 reset_level = HNS3_FLR_RESET; 5272 5273 if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level) 5274 return HNS3_NONE_RESET; 5275 5276 return reset_level; 5277 } 5278 5279 static void 5280 hns3_record_imp_error(struct hns3_adapter *hns) 5281 { 5282 struct hns3_hw *hw = &hns->hw; 5283 uint32_t reg_val; 5284 5285 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5286 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) { 5287 hns3_warn(hw, "Detected IMP RD poison!"); 5288 hns3_error_int_stats_add(hns, "IMP_RD_POISON_INT_STS"); 5289 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0); 5290 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 5291 } 5292 5293 if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) { 5294 hns3_warn(hw, "Detected IMP CMDQ error!"); 5295 hns3_error_int_stats_add(hns, "CMDQ_MEM_ECC_INT_STS"); 5296 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0); 5297 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val); 5298 } 5299 } 5300 5301 static int 5302 hns3_prepare_reset(struct hns3_adapter *hns) 5303 { 5304 struct hns3_hw *hw = &hns->hw; 5305 uint32_t reg_val; 5306 int ret; 5307 5308 switch (hw->reset.level) { 5309 case HNS3_FUNC_RESET: 5310 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID); 5311 if (ret) 5312 return ret; 5313 5314 /* 5315 * After performaning pf reset, it is not necessary to do the 5316 * mailbox handling or send any command to firmware, because 5317 * any mailbox handling or command to firmware is only valid 5318 * after hns3_cmd_init is called. 5319 */ 5320 rte_atomic16_set(&hw->reset.disable_cmd, 1); 5321 hw->reset.stats.request_cnt++; 5322 break; 5323 case HNS3_IMP_RESET: 5324 hns3_record_imp_error(hns); 5325 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); 5326 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val | 5327 BIT(HNS3_VECTOR0_IMP_RESET_INT_B)); 5328 break; 5329 default: 5330 break; 5331 } 5332 return 0; 5333 } 5334 5335 static int 5336 hns3_set_rst_done(struct hns3_hw *hw) 5337 { 5338 struct hns3_pf_rst_done_cmd *req; 5339 struct hns3_cmd_desc desc; 5340 5341 req = (struct hns3_pf_rst_done_cmd *)desc.data; 5342 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false); 5343 req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT; 5344 return hns3_cmd_send(hw, &desc, 1); 5345 } 5346 5347 static int 5348 hns3_stop_service(struct hns3_adapter *hns) 5349 { 5350 struct hns3_hw *hw = &hns->hw; 5351 struct rte_eth_dev *eth_dev; 5352 5353 eth_dev = &rte_eth_devices[hw->data->port_id]; 5354 if (hw->adapter_state == HNS3_NIC_STARTED) 5355 rte_eal_alarm_cancel(hns3_service_handler, eth_dev); 5356 hw->mac.link_status = ETH_LINK_DOWN; 5357 5358 hns3_set_rxtx_function(eth_dev); 5359 rte_wmb(); 5360 /* Disable datapath on secondary process. */ 5361 hns3_mp_req_stop_rxtx(eth_dev); 5362 rte_delay_ms(hw->tqps_num); 5363 5364 rte_spinlock_lock(&hw->lock); 5365 if (hns->hw.adapter_state == HNS3_NIC_STARTED || 5366 hw->adapter_state == HNS3_NIC_STOPPING) { 5367 hns3_do_stop(hns); 5368 hw->reset.mbuf_deferred_free = true; 5369 } else 5370 hw->reset.mbuf_deferred_free = false; 5371 5372 /* 5373 * It is cumbersome for hardware to pick-and-choose entries for deletion 5374 * from table space. Hence, for function reset software intervention is 5375 * required to delete the entries 5376 */ 5377 if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) 5378 hns3_configure_all_mc_mac_addr(hns, true); 5379 rte_spinlock_unlock(&hw->lock); 5380 5381 return 0; 5382 } 5383 5384 static int 5385 hns3_start_service(struct hns3_adapter *hns) 5386 { 5387 struct hns3_hw *hw = &hns->hw; 5388 struct rte_eth_dev *eth_dev; 5389 5390 if (hw->reset.level == HNS3_IMP_RESET || 5391 hw->reset.level == HNS3_GLOBAL_RESET) 5392 hns3_set_rst_done(hw); 5393 eth_dev = &rte_eth_devices[hw->data->port_id]; 5394 hns3_set_rxtx_function(eth_dev); 5395 hns3_mp_req_start_rxtx(eth_dev); 5396 if (hw->adapter_state == HNS3_NIC_STARTED) { 5397 hns3_service_handler(eth_dev); 5398 5399 /* Enable interrupt of all rx queues before enabling queues */ 5400 hns3_dev_all_rx_queue_intr_enable(hw, true); 5401 /* 5402 * When finished the initialization, enable queues to receive 5403 * and transmit packets. 5404 */ 5405 hns3_enable_all_queues(hw, true); 5406 } 5407 5408 return 0; 5409 } 5410 5411 static int 5412 hns3_restore_conf(struct hns3_adapter *hns) 5413 { 5414 struct hns3_hw *hw = &hns->hw; 5415 int ret; 5416 5417 ret = hns3_configure_all_mac_addr(hns, false); 5418 if (ret) 5419 return ret; 5420 5421 ret = hns3_configure_all_mc_mac_addr(hns, false); 5422 if (ret) 5423 goto err_mc_mac; 5424 5425 ret = hns3_dev_promisc_restore(hns); 5426 if (ret) 5427 goto err_promisc; 5428 5429 ret = hns3_restore_vlan_table(hns); 5430 if (ret) 5431 goto err_promisc; 5432 5433 ret = hns3_restore_vlan_conf(hns); 5434 if (ret) 5435 goto err_promisc; 5436 5437 ret = hns3_restore_all_fdir_filter(hns); 5438 if (ret) 5439 goto err_promisc; 5440 5441 ret = hns3_restore_rx_interrupt(hw); 5442 if (ret) 5443 goto err_promisc; 5444 5445 ret = hns3_restore_gro_conf(hw); 5446 if (ret) 5447 goto err_promisc; 5448 5449 if (hns->hw.adapter_state == HNS3_NIC_STARTED) { 5450 ret = hns3_do_start(hns, false); 5451 if (ret) 5452 goto err_promisc; 5453 hns3_info(hw, "hns3 dev restart successful!"); 5454 } else if (hw->adapter_state == HNS3_NIC_STOPPING) 5455 hw->adapter_state = HNS3_NIC_CONFIGURED; 5456 return 0; 5457 5458 err_promisc: 5459 hns3_configure_all_mc_mac_addr(hns, true); 5460 err_mc_mac: 5461 hns3_configure_all_mac_addr(hns, true); 5462 return ret; 5463 } 5464 5465 static void 5466 hns3_reset_service(void *param) 5467 { 5468 struct hns3_adapter *hns = (struct hns3_adapter *)param; 5469 struct hns3_hw *hw = &hns->hw; 5470 enum hns3_reset_level reset_level; 5471 struct timeval tv_delta; 5472 struct timeval tv_start; 5473 struct timeval tv; 5474 uint64_t msec; 5475 int ret; 5476 5477 /* 5478 * The interrupt is not triggered within the delay time. 5479 * The interrupt may have been lost. It is necessary to handle 5480 * the interrupt to recover from the error. 5481 */ 5482 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) { 5483 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED); 5484 hns3_err(hw, "Handling interrupts in delayed tasks"); 5485 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]); 5486 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 5487 if (reset_level == HNS3_NONE_RESET) { 5488 hns3_err(hw, "No reset level is set, try IMP reset"); 5489 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); 5490 } 5491 } 5492 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE); 5493 5494 /* 5495 * Check if there is any ongoing reset in the hardware. This status can 5496 * be checked from reset_pending. If there is then, we need to wait for 5497 * hardware to complete reset. 5498 * a. If we are able to figure out in reasonable time that hardware 5499 * has fully resetted then, we can proceed with driver, client 5500 * reset. 5501 * b. else, we can come back later to check this status so re-sched 5502 * now. 5503 */ 5504 reset_level = hns3_get_reset_level(hns, &hw->reset.pending); 5505 if (reset_level != HNS3_NONE_RESET) { 5506 gettimeofday(&tv_start, NULL); 5507 ret = hns3_reset_process(hns, reset_level); 5508 gettimeofday(&tv, NULL); 5509 timersub(&tv, &tv_start, &tv_delta); 5510 msec = tv_delta.tv_sec * MSEC_PER_SEC + 5511 tv_delta.tv_usec / USEC_PER_MSEC; 5512 if (msec > HNS3_RESET_PROCESS_MS) 5513 hns3_err(hw, "%d handle long time delta %" PRIx64 5514 " ms time=%ld.%.6ld", 5515 hw->reset.level, msec, 5516 tv.tv_sec, tv.tv_usec); 5517 if (ret == -EAGAIN) 5518 return; 5519 } 5520 5521 /* Check if we got any *new* reset requests to be honored */ 5522 reset_level = hns3_get_reset_level(hns, &hw->reset.request); 5523 if (reset_level != HNS3_NONE_RESET) 5524 hns3_msix_process(hns, reset_level); 5525 } 5526 5527 static const struct eth_dev_ops hns3_eth_dev_ops = { 5528 .dev_configure = hns3_dev_configure, 5529 .dev_start = hns3_dev_start, 5530 .dev_stop = hns3_dev_stop, 5531 .dev_close = hns3_dev_close, 5532 .promiscuous_enable = hns3_dev_promiscuous_enable, 5533 .promiscuous_disable = hns3_dev_promiscuous_disable, 5534 .allmulticast_enable = hns3_dev_allmulticast_enable, 5535 .allmulticast_disable = hns3_dev_allmulticast_disable, 5536 .mtu_set = hns3_dev_mtu_set, 5537 .stats_get = hns3_stats_get, 5538 .stats_reset = hns3_stats_reset, 5539 .xstats_get = hns3_dev_xstats_get, 5540 .xstats_get_names = hns3_dev_xstats_get_names, 5541 .xstats_reset = hns3_dev_xstats_reset, 5542 .xstats_get_by_id = hns3_dev_xstats_get_by_id, 5543 .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id, 5544 .dev_infos_get = hns3_dev_infos_get, 5545 .fw_version_get = hns3_fw_version_get, 5546 .rx_queue_setup = hns3_rx_queue_setup, 5547 .tx_queue_setup = hns3_tx_queue_setup, 5548 .rx_queue_release = hns3_dev_rx_queue_release, 5549 .tx_queue_release = hns3_dev_tx_queue_release, 5550 .rx_queue_intr_enable = hns3_dev_rx_queue_intr_enable, 5551 .rx_queue_intr_disable = hns3_dev_rx_queue_intr_disable, 5552 .rxq_info_get = hns3_rxq_info_get, 5553 .txq_info_get = hns3_txq_info_get, 5554 .rx_burst_mode_get = hns3_rx_burst_mode_get, 5555 .tx_burst_mode_get = hns3_tx_burst_mode_get, 5556 .flow_ctrl_get = hns3_flow_ctrl_get, 5557 .flow_ctrl_set = hns3_flow_ctrl_set, 5558 .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set, 5559 .mac_addr_add = hns3_add_mac_addr, 5560 .mac_addr_remove = hns3_remove_mac_addr, 5561 .mac_addr_set = hns3_set_default_mac_addr, 5562 .set_mc_addr_list = hns3_set_mc_mac_addr_list, 5563 .link_update = hns3_dev_link_update, 5564 .rss_hash_update = hns3_dev_rss_hash_update, 5565 .rss_hash_conf_get = hns3_dev_rss_hash_conf_get, 5566 .reta_update = hns3_dev_rss_reta_update, 5567 .reta_query = hns3_dev_rss_reta_query, 5568 .filter_ctrl = hns3_dev_filter_ctrl, 5569 .vlan_filter_set = hns3_vlan_filter_set, 5570 .vlan_tpid_set = hns3_vlan_tpid_set, 5571 .vlan_offload_set = hns3_vlan_offload_set, 5572 .vlan_pvid_set = hns3_vlan_pvid_set, 5573 .get_reg = hns3_get_regs, 5574 .get_dcb_info = hns3_get_dcb_info, 5575 .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get, 5576 }; 5577 5578 static const struct hns3_reset_ops hns3_reset_ops = { 5579 .reset_service = hns3_reset_service, 5580 .stop_service = hns3_stop_service, 5581 .prepare_reset = hns3_prepare_reset, 5582 .wait_hardware_ready = hns3_wait_hardware_ready, 5583 .reinit_dev = hns3_reinit_dev, 5584 .restore_conf = hns3_restore_conf, 5585 .start_service = hns3_start_service, 5586 }; 5587 5588 static int 5589 hns3_dev_init(struct rte_eth_dev *eth_dev) 5590 { 5591 struct hns3_adapter *hns = eth_dev->data->dev_private; 5592 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 5593 struct rte_ether_addr *eth_addr; 5594 struct hns3_hw *hw = &hns->hw; 5595 int ret; 5596 5597 PMD_INIT_FUNC_TRACE(); 5598 5599 eth_dev->process_private = (struct hns3_process_private *) 5600 rte_zmalloc_socket("hns3_filter_list", 5601 sizeof(struct hns3_process_private), 5602 RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node); 5603 if (eth_dev->process_private == NULL) { 5604 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private"); 5605 return -ENOMEM; 5606 } 5607 /* initialize flow filter lists */ 5608 hns3_filterlist_init(eth_dev); 5609 5610 hns3_set_rxtx_function(eth_dev); 5611 eth_dev->dev_ops = &hns3_eth_dev_ops; 5612 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 5613 ret = hns3_mp_init_secondary(); 5614 if (ret) { 5615 PMD_INIT_LOG(ERR, "Failed to init for secondary " 5616 "process, ret = %d", ret); 5617 goto err_mp_init_secondary; 5618 } 5619 5620 hw->secondary_cnt++; 5621 return 0; 5622 } 5623 5624 ret = hns3_mp_init_primary(); 5625 if (ret) { 5626 PMD_INIT_LOG(ERR, 5627 "Failed to init for primary process, ret = %d", 5628 ret); 5629 goto err_mp_init_primary; 5630 } 5631 5632 hw->adapter_state = HNS3_NIC_UNINITIALIZED; 5633 hns->is_vf = false; 5634 hw->data = eth_dev->data; 5635 5636 /* 5637 * Set default max packet size according to the mtu 5638 * default vale in DPDK frame. 5639 */ 5640 hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD; 5641 5642 ret = hns3_reset_init(hw); 5643 if (ret) 5644 goto err_init_reset; 5645 hw->reset.ops = &hns3_reset_ops; 5646 5647 ret = hns3_init_pf(eth_dev); 5648 if (ret) { 5649 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret); 5650 goto err_init_pf; 5651 } 5652 5653 /* Allocate memory for storing MAC addresses */ 5654 eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac", 5655 sizeof(struct rte_ether_addr) * 5656 HNS3_UC_MACADDR_NUM, 0); 5657 if (eth_dev->data->mac_addrs == NULL) { 5658 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed " 5659 "to store MAC addresses", 5660 sizeof(struct rte_ether_addr) * 5661 HNS3_UC_MACADDR_NUM); 5662 ret = -ENOMEM; 5663 goto err_rte_zmalloc; 5664 } 5665 5666 eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr; 5667 if (!rte_is_valid_assigned_ether_addr(eth_addr)) { 5668 rte_eth_random_addr(hw->mac.mac_addr); 5669 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, 5670 (struct rte_ether_addr *)hw->mac.mac_addr); 5671 hns3_warn(hw, "default mac_addr from firmware is an invalid " 5672 "unicast address, using random MAC address %s", 5673 mac_str); 5674 } 5675 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr, 5676 ð_dev->data->mac_addrs[0]); 5677 5678 hw->adapter_state = HNS3_NIC_INITIALIZED; 5679 /* 5680 * Pass the information to the rte_eth_dev_close() that it should also 5681 * release the private port resources. 5682 */ 5683 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 5684 5685 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) { 5686 hns3_err(hw, "Reschedule reset service after dev_init"); 5687 hns3_schedule_reset(hns); 5688 } else { 5689 /* IMP will wait ready flag before reset */ 5690 hns3_notify_reset_ready(hw, false); 5691 } 5692 5693 hns3_info(hw, "hns3 dev initialization successful!"); 5694 return 0; 5695 5696 err_rte_zmalloc: 5697 hns3_uninit_pf(eth_dev); 5698 5699 err_init_pf: 5700 rte_free(hw->reset.wait_data); 5701 5702 err_init_reset: 5703 hns3_mp_uninit_primary(); 5704 5705 err_mp_init_primary: 5706 err_mp_init_secondary: 5707 eth_dev->dev_ops = NULL; 5708 eth_dev->rx_pkt_burst = NULL; 5709 eth_dev->tx_pkt_burst = NULL; 5710 eth_dev->tx_pkt_prepare = NULL; 5711 rte_free(eth_dev->process_private); 5712 eth_dev->process_private = NULL; 5713 return ret; 5714 } 5715 5716 static int 5717 hns3_dev_uninit(struct rte_eth_dev *eth_dev) 5718 { 5719 struct hns3_adapter *hns = eth_dev->data->dev_private; 5720 struct hns3_hw *hw = &hns->hw; 5721 5722 PMD_INIT_FUNC_TRACE(); 5723 5724 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5725 return -EPERM; 5726 5727 eth_dev->dev_ops = NULL; 5728 eth_dev->rx_pkt_burst = NULL; 5729 eth_dev->tx_pkt_burst = NULL; 5730 eth_dev->tx_pkt_prepare = NULL; 5731 if (hw->adapter_state < HNS3_NIC_CLOSING) 5732 hns3_dev_close(eth_dev); 5733 5734 hw->adapter_state = HNS3_NIC_REMOVED; 5735 return 0; 5736 } 5737 5738 static int 5739 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 5740 struct rte_pci_device *pci_dev) 5741 { 5742 return rte_eth_dev_pci_generic_probe(pci_dev, 5743 sizeof(struct hns3_adapter), 5744 hns3_dev_init); 5745 } 5746 5747 static int 5748 eth_hns3_pci_remove(struct rte_pci_device *pci_dev) 5749 { 5750 return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit); 5751 } 5752 5753 static const struct rte_pci_id pci_id_hns3_map[] = { 5754 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) }, 5755 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) }, 5756 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) }, 5757 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) }, 5758 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) }, 5759 { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) }, 5760 { .vendor_id = 0, /* sentinel */ }, 5761 }; 5762 5763 static struct rte_pci_driver rte_hns3_pmd = { 5764 .id_table = pci_id_hns3_map, 5765 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 5766 .probe = eth_hns3_pci_probe, 5767 .remove = eth_hns3_pci_remove, 5768 }; 5769 5770 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd); 5771 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map); 5772 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci"); 5773 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE); 5774 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE); 5775