xref: /dpdk/drivers/net/hinic/hinic_pmd_ethdev.h (revision 0d09cbc7)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2017 Huawei Technologies Co., Ltd
3  */
4 
5 #ifndef _HINIC_PMD_ETHDEV_H_
6 #define _HINIC_PMD_ETHDEV_H_
7 
8 #include <rte_ethdev.h>
9 #include <rte_ethdev_core.h>
10 
11 #include "base/hinic_compat.h"
12 #include "base/hinic_pmd_cfg.h"
13 
14 #define HINIC_DEV_NAME_LEN	32
15 #define HINIC_MAX_RX_QUEUES	64
16 
17 /* mbuf pool for copy invalid mbuf segs */
18 #define HINIC_COPY_MEMPOOL_DEPTH	128
19 #define HINIC_COPY_MBUF_SIZE		4096
20 
21 #define SIZE_8BYTES(size)	(ALIGN((u32)(size), 8) >> 3)
22 
23 #define HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev) \
24 	((struct hinic_nic_dev *)(dev)->data->dev_private)
25 
26 #define HINIC_MAX_QUEUE_DEPTH		4096
27 #define HINIC_MIN_QUEUE_DEPTH		128
28 #define HINIC_TXD_ALIGN                 1
29 #define HINIC_RXD_ALIGN                 1
30 
31 #define HINIC_UINT32_BIT_SIZE      (CHAR_BIT * sizeof(uint32_t))
32 #define HINIC_VFTA_SIZE            (4096 / HINIC_UINT32_BIT_SIZE)
33 
34 enum hinic_dev_status {
35 	HINIC_DEV_INIT,
36 	HINIC_DEV_CLOSE,
37 	HINIC_DEV_START,
38 	HINIC_DEV_INTR_EN,
39 };
40 
41 #define HINIC_MAX_Q_FILTERS	64 /* hinic just support 64 filter types */
42 #define HINIC_PKT_TYPE_FIND_ID(pkt_type) ((pkt_type) - HINIC_MAX_Q_FILTERS)
43 
44 /* 5tuple filter info */
45 struct hinic_5tuple_filter_info {
46 	uint32_t dst_ip;
47 	uint32_t src_ip;
48 	uint16_t dst_port;
49 	uint16_t src_port;
50 	uint8_t proto; /* l4 protocol. */
51 	/*
52 	 * seven levels (001b-111b), 111b is highest,
53 	 * used when more than one filter matches.
54 	 */
55 	uint8_t priority;
56 
57 	/* if mask is 1b, do not compare the response bit domain */
58 	uint8_t dst_ip_mask:1,
59 		src_ip_mask:1,
60 		dst_port_mask:1,
61 		src_port_mask:1,
62 		proto_mask:1;
63 };
64 
65 /* 5tuple filter structure */
66 struct hinic_5tuple_filter {
67 	TAILQ_ENTRY(hinic_5tuple_filter) entries;
68 	uint16_t index;       /* the index of 5tuple filter */
69 	struct hinic_5tuple_filter_info filter_info;
70 	uint16_t queue;       /* rx queue assigned to */
71 };
72 
73 TAILQ_HEAD(hinic_5tuple_filter_list, hinic_5tuple_filter);
74 
75 /*
76  * If this filter is added by configuration,
77  * it should not be removed.
78  */
79 struct hinic_pkt_filter {
80 	uint16_t pkt_proto;
81 	uint8_t qid;
82 	bool	enable;
83 };
84 
85 /* Structure to store filters' info. */
86 struct hinic_filter_info {
87 	uint8_t pkt_type;
88 	uint8_t qid;
89 	uint64_t type_mask;  /* Bit mask for every used filter */
90 	struct hinic_5tuple_filter_list fivetuple_list;
91 	struct hinic_pkt_filter pkt_filters[HINIC_MAX_Q_FILTERS];
92 };
93 
94 /* Information about the fdir mode. */
95 struct hinic_hw_fdir_mask {
96 	uint32_t src_ipv4_mask;
97 	uint32_t dst_ipv4_mask;
98 	uint16_t src_port_mask;
99 	uint16_t dst_port_mask;
100 	uint16_t proto_mask;
101 	uint16_t tunnel_flag;
102 	uint16_t tunnel_inner_src_port_mask;
103 	uint16_t tunnel_inner_dst_port_mask;
104 	uint16_t dst_ipv6_mask;
105 };
106 
107 /* Flow Director attribute */
108 struct hinic_atr_input {
109 	uint32_t dst_ip;
110 	uint32_t src_ip;
111 	uint16_t src_port;
112 	uint16_t dst_port;
113 	uint16_t proto;
114 	uint16_t tunnel_flag;
115 	uint16_t tunnel_inner_src_port;
116 	uint16_t tunnel_inner_dst_port;
117 	uint8_t  dst_ipv6[16];
118 };
119 
120 enum hinic_fdir_mode {
121 	HINIC_FDIR_MODE_NORMAL      = 0,
122 	HINIC_FDIR_MODE_TCAM        = 1,
123 };
124 
125 #define HINIC_PF_MAX_TCAM_FILTERS	1024
126 #define HINIC_VF_MAX_TCAM_FILTERS	128
127 #define HINIC_SUPPORT_PF_MAX_NUM	4
128 #define HINIC_TOTAL_PF_MAX_NUM		16
129 #define HINIC_SUPPORT_VF_MAX_NUM	32
130 #define HINIC_TCAM_BLOCK_TYPE_PF	0 /* 1024 tcam index of a block */
131 #define HINIC_TCAM_BLOCK_TYPE_VF	1 /* 128 tcam index of a block */
132 
133 #define HINIC_PKT_VF_TCAM_INDEX_START(block_index)  \
134 		(HINIC_PF_MAX_TCAM_FILTERS * HINIC_SUPPORT_PF_MAX_NUM + \
135 		HINIC_VF_MAX_TCAM_FILTERS * (block_index))
136 
137 TAILQ_HEAD(hinic_tcam_filter_list, hinic_tcam_filter);
138 
139 struct hinic_tcam_info {
140 	struct hinic_tcam_filter_list tcam_list;
141 	u8 tcam_index_array[HINIC_PF_MAX_TCAM_FILTERS];
142 	u16 tcam_block_index;
143 	u16 tcam_rule_nums;
144 };
145 
146 struct tag_tcam_key_mem {
147 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN)
148 
149 		u32 rsvd0:16;
150 		u32 function_id:16;
151 
152 		u32 protocol:8;
153 		/*
154 		 * tunnel packet, mask must be 0xff, spec value is 1;
155 		 * normal packet, mask must be 0, spec value is 0;
156 		 * if tunnal packet, ucode use
157 		 * sip/dip/protocol/src_port/dst_dport from inner packet
158 		 */
159 		u32 tunnel_flag:8;
160 		u32 sip_h:16;
161 
162 		u32 sip_l:16;
163 		u32 dip_h:16;
164 
165 		u32 dip_l:16;
166 		u32 src_port:16;
167 
168 		u32 dst_port:16;
169 		/*
170 		 * tunnel packet and normal packet,
171 		 * ext_dip mask must be 0xffffffff
172 		 */
173 		u32 ext_dip_h:16;
174 		u32 ext_dip_l:16;
175 		u32 rsvd2:16;
176 #else
177 		u32 function_id:16;
178 		u32 rsvd0:16;
179 
180 		u32 sip_h:16;
181 		u32 tunnel_flag:8;
182 		u32 protocol:8;
183 
184 		u32 dip_h:16;
185 		u32 sip_l:16;
186 
187 		u32 src_port:16;
188 		u32 dip_l:16;
189 
190 		u32 ext_dip_h:16;
191 		u32 dst_port:16;
192 
193 		u32 rsvd2:16;
194 		u32 ext_dip_l:16;
195 #endif
196 };
197 
198 struct tag_tcam_key_ipv6_mem {
199 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN)
200 		u32 rsvd0:16;
201 		u32 ipv6_flag:1;
202 		u32 protocol:7;
203 		u32 function_id:8;
204 
205 		u32 dst_port:16;
206 		u32 ipv6_key0:16;
207 
208 		u32 ipv6_key1:16;
209 		u32 ipv6_key2:16;
210 
211 		u32 ipv6_key3:16;
212 		u32 ipv6_key4:16;
213 
214 		u32 ipv6_key5:16;
215 		u32 ipv6_key6:16;
216 
217 		u32 ipv6_key7:16;
218 		u32 rsvd2:16;
219 #else
220 		u32 function_id:8;
221 		u32 protocol:7;
222 		u32 ipv6_flag:1;
223 		u32 rsvd0:16;
224 
225 		u32 ipv6_key0:16;
226 		u32 dst_port:16;
227 
228 		u32 ipv6_key2:16;
229 		u32 ipv6_key1:16;
230 
231 		u32 ipv6_key4:16;
232 		u32 ipv6_key3:16;
233 
234 		u32 ipv6_key6:16;
235 		u32 ipv6_key5:16;
236 
237 		u32 rsvd2:16;
238 		u32 ipv6_key7:16;
239 #endif
240 };
241 
242 struct tag_tcam_key {
243 	union {
244 		struct tag_tcam_key_mem key_info;
245 		struct tag_tcam_key_ipv6_mem key_info_ipv6;
246 	};
247 
248 	union {
249 		struct tag_tcam_key_mem key_mask;
250 		struct tag_tcam_key_ipv6_mem key_mask_ipv6;
251 	};
252 };
253 
254 struct hinic_fdir_rule {
255 	struct hinic_hw_fdir_mask mask;
256 	struct hinic_atr_input hinic_fdir; /* key of fdir filter */
257 	uint8_t queue; /* queue assigned when matched */
258 	enum hinic_fdir_mode mode; /* fdir type */
259 	u16 tcam_index;
260 };
261 
262 /* ntuple filter list structure */
263 struct hinic_ntuple_filter_ele {
264 	TAILQ_ENTRY(hinic_ntuple_filter_ele) entries;
265 	struct rte_eth_ntuple_filter filter_info;
266 };
267 
268 /* ethertype filter list structure */
269 struct hinic_ethertype_filter_ele {
270 	TAILQ_ENTRY(hinic_ethertype_filter_ele) entries;
271 	struct rte_eth_ethertype_filter filter_info;
272 };
273 
274 /* fdir filter list structure */
275 struct hinic_fdir_rule_ele {
276 	TAILQ_ENTRY(hinic_fdir_rule_ele) entries;
277 	struct hinic_fdir_rule filter_info;
278 };
279 
280 struct hinic_tcam_filter {
281 	TAILQ_ENTRY(hinic_tcam_filter) entries;
282 	uint16_t index; /* tcam index */
283 	struct tag_tcam_key tcam_key;
284 	uint16_t queue; /* rx queue assigned to */
285 };
286 
287 struct rte_flow {
288 	enum rte_filter_type filter_type;
289 	void *rule;
290 };
291 
292 /* hinic_flow memory list structure */
293 struct hinic_flow_mem {
294 	TAILQ_ENTRY(hinic_flow_mem) entries;
295 	struct rte_flow *flow;
296 };
297 
298 TAILQ_HEAD(hinic_ntuple_filter_list, hinic_ntuple_filter_ele);
299 TAILQ_HEAD(hinic_ethertype_filter_list, hinic_ethertype_filter_ele);
300 TAILQ_HEAD(hinic_fdir_rule_filter_list, hinic_fdir_rule_ele);
301 TAILQ_HEAD(hinic_flow_mem_list, hinic_flow_mem);
302 
303 extern const struct rte_flow_ops hinic_flow_ops;
304 
305 /* hinic nic_device */
306 struct hinic_nic_dev {
307 	/* hardware device */
308 	struct hinic_hwdev *hwdev;
309 	struct hinic_txq **txqs;
310 	struct hinic_rxq **rxqs;
311 	struct rte_mempool *cpy_mpool;
312 	u16 num_qps;
313 	u16 num_sq;
314 	u16 num_rq;
315 	u16 mtu_size;
316 	u8 rss_tmpl_idx;
317 	u8 rss_indir_flag;
318 	u8 num_rss;
319 	u8 rx_queue_list[HINIC_MAX_RX_QUEUES];
320 
321 	bool pause_set;
322 	struct nic_pause_config nic_pause;
323 
324 	u32 vfta[HINIC_VFTA_SIZE];	/* VLAN bitmap */
325 
326 	struct rte_ether_addr default_addr;
327 	struct rte_ether_addr *mc_list;
328 	/* info */
329 	unsigned int flags;
330 	struct nic_service_cap nic_cap;
331 	u32 rx_mode_status;	/* promisc or allmulticast */
332 	pthread_mutex_t rx_mode_mutex;
333 	u32 dev_status;
334 
335 	char proc_dev_name[HINIC_DEV_NAME_LEN];
336 	/* PF0->COS4, PF1->COS5, PF2->COS6, PF3->COS7,
337 	 * vf: the same with associate pf
338 	 */
339 	u32 default_cos;
340 	u32 rx_csum_en;
341 
342 	struct hinic_filter_info    filter;
343 	struct hinic_tcam_info      tcam;
344 	struct hinic_ntuple_filter_list filter_ntuple_list;
345 	struct hinic_ethertype_filter_list filter_ethertype_list;
346 	struct hinic_fdir_rule_filter_list filter_fdir_rule_list;
347 	struct hinic_flow_mem_list hinic_flow_list;
348 };
349 
350 void hinic_free_fdir_filter(struct hinic_nic_dev *nic_dev);
351 
352 void hinic_destroy_fdir_filter(struct rte_eth_dev *dev);
353 #endif /* _HINIC_PMD_ETHDEV_H_ */
354