1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Huawei Technologies Co., Ltd 3 */ 4 5 #include <rte_pci.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev_pci.h> 8 #include <rte_mbuf.h> 9 #include <rte_malloc.h> 10 #include <rte_memcpy.h> 11 #include <rte_mempool.h> 12 #include <rte_errno.h> 13 #include <rte_ether.h> 14 15 #include "base/hinic_compat.h" 16 #include "base/hinic_pmd_hwdev.h" 17 #include "base/hinic_pmd_hwif.h" 18 #include "base/hinic_pmd_wq.h" 19 #include "base/hinic_pmd_cfg.h" 20 #include "base/hinic_pmd_mgmt.h" 21 #include "base/hinic_pmd_cmdq.h" 22 #include "base/hinic_pmd_niccfg.h" 23 #include "base/hinic_pmd_nicio.h" 24 #include "base/hinic_pmd_mbox.h" 25 #include "hinic_pmd_ethdev.h" 26 #include "hinic_pmd_tx.h" 27 #include "hinic_pmd_rx.h" 28 29 /* Vendor ID used by Huawei devices */ 30 #define HINIC_HUAWEI_VENDOR_ID 0x19E5 31 32 /* Hinic devices */ 33 #define HINIC_DEV_ID_PRD 0x1822 34 #define HINIC_DEV_ID_VF 0x375E 35 #define HINIC_DEV_ID_VF_HV 0x379E 36 37 /* Mezz card for Blade Server */ 38 #define HINIC_DEV_ID_MEZZ_25GE 0x0210 39 #define HINIC_DEV_ID_MEZZ_100GE 0x0205 40 41 /* 2*25G and 2*100G card */ 42 #define HINIC_DEV_ID_1822_DUAL_25GE 0x0206 43 #define HINIC_DEV_ID_1822_100GE 0x0200 44 45 #define HINIC_SERVICE_MODE_NIC 2 46 47 #define HINIC_INTR_CB_UNREG_MAX_RETRIES 10 48 49 #define DEFAULT_BASE_COS 4 50 #define NR_MAX_COS 8 51 52 #define HINIC_MIN_RX_BUF_SIZE 1024 53 #define HINIC_MAX_UC_MAC_ADDRS 128 54 #define HINIC_MAX_MC_MAC_ADDRS 2048 55 56 #define HINIC_DEFAULT_BURST_SIZE 32 57 #define HINIC_DEFAULT_NB_QUEUES 1 58 #define HINIC_DEFAULT_RING_SIZE 1024 59 #define HINIC_MAX_LRO_SIZE 65536 60 61 /* 62 * vlan_id is a 12 bit number. 63 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 64 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 65 * The higher 7 bit val specifies VFTA array index. 66 */ 67 #define HINIC_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 68 #define HINIC_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 69 70 #define HINIC_VLAN_FILTER_EN (1U << 0) 71 72 #define HINIC_MTU_TO_PKTLEN(mtu) \ 73 ((mtu) + ETH_HLEN + ETH_CRC_LEN) 74 75 #define HINIC_PKTLEN_TO_MTU(pktlen) \ 76 ((pktlen) - (ETH_HLEN + ETH_CRC_LEN)) 77 78 /* lro numer limit for one packet */ 79 #define HINIC_LRO_WQE_NUM_DEFAULT 8 80 81 /* Driver-specific log messages type */ 82 int hinic_logtype; 83 84 struct hinic_xstats_name_off { 85 char name[RTE_ETH_XSTATS_NAME_SIZE]; 86 u32 offset; 87 }; 88 89 #define HINIC_FUNC_STAT(_stat_item) { \ 90 .name = #_stat_item, \ 91 .offset = offsetof(struct hinic_vport_stats, _stat_item) \ 92 } 93 94 #define HINIC_PORT_STAT(_stat_item) { \ 95 .name = #_stat_item, \ 96 .offset = offsetof(struct hinic_phy_port_stats, _stat_item) \ 97 } 98 99 static const struct hinic_xstats_name_off hinic_vport_stats_strings[] = { 100 HINIC_FUNC_STAT(tx_unicast_pkts_vport), 101 HINIC_FUNC_STAT(tx_unicast_bytes_vport), 102 HINIC_FUNC_STAT(tx_multicast_pkts_vport), 103 HINIC_FUNC_STAT(tx_multicast_bytes_vport), 104 HINIC_FUNC_STAT(tx_broadcast_pkts_vport), 105 HINIC_FUNC_STAT(tx_broadcast_bytes_vport), 106 107 HINIC_FUNC_STAT(rx_unicast_pkts_vport), 108 HINIC_FUNC_STAT(rx_unicast_bytes_vport), 109 HINIC_FUNC_STAT(rx_multicast_pkts_vport), 110 HINIC_FUNC_STAT(rx_multicast_bytes_vport), 111 HINIC_FUNC_STAT(rx_broadcast_pkts_vport), 112 HINIC_FUNC_STAT(rx_broadcast_bytes_vport), 113 114 HINIC_FUNC_STAT(tx_discard_vport), 115 HINIC_FUNC_STAT(rx_discard_vport), 116 HINIC_FUNC_STAT(tx_err_vport), 117 HINIC_FUNC_STAT(rx_err_vport), 118 }; 119 120 #define HINIC_VPORT_XSTATS_NUM (sizeof(hinic_vport_stats_strings) / \ 121 sizeof(hinic_vport_stats_strings[0])) 122 123 static const struct hinic_xstats_name_off hinic_phyport_stats_strings[] = { 124 HINIC_PORT_STAT(mac_rx_total_pkt_num), 125 HINIC_PORT_STAT(mac_rx_total_oct_num), 126 HINIC_PORT_STAT(mac_rx_bad_pkt_num), 127 HINIC_PORT_STAT(mac_rx_bad_oct_num), 128 HINIC_PORT_STAT(mac_rx_good_pkt_num), 129 HINIC_PORT_STAT(mac_rx_good_oct_num), 130 HINIC_PORT_STAT(mac_rx_uni_pkt_num), 131 HINIC_PORT_STAT(mac_rx_multi_pkt_num), 132 HINIC_PORT_STAT(mac_rx_broad_pkt_num), 133 HINIC_PORT_STAT(mac_tx_total_pkt_num), 134 HINIC_PORT_STAT(mac_tx_total_oct_num), 135 HINIC_PORT_STAT(mac_tx_bad_pkt_num), 136 HINIC_PORT_STAT(mac_tx_bad_oct_num), 137 HINIC_PORT_STAT(mac_tx_good_pkt_num), 138 HINIC_PORT_STAT(mac_tx_good_oct_num), 139 HINIC_PORT_STAT(mac_tx_uni_pkt_num), 140 HINIC_PORT_STAT(mac_tx_multi_pkt_num), 141 HINIC_PORT_STAT(mac_tx_broad_pkt_num), 142 HINIC_PORT_STAT(mac_rx_fragment_pkt_num), 143 HINIC_PORT_STAT(mac_rx_undersize_pkt_num), 144 HINIC_PORT_STAT(mac_rx_undermin_pkt_num), 145 HINIC_PORT_STAT(mac_rx_64_oct_pkt_num), 146 HINIC_PORT_STAT(mac_rx_65_127_oct_pkt_num), 147 HINIC_PORT_STAT(mac_rx_128_255_oct_pkt_num), 148 HINIC_PORT_STAT(mac_rx_256_511_oct_pkt_num), 149 HINIC_PORT_STAT(mac_rx_512_1023_oct_pkt_num), 150 HINIC_PORT_STAT(mac_rx_1024_1518_oct_pkt_num), 151 HINIC_PORT_STAT(mac_rx_1519_2047_oct_pkt_num), 152 HINIC_PORT_STAT(mac_rx_2048_4095_oct_pkt_num), 153 HINIC_PORT_STAT(mac_rx_4096_8191_oct_pkt_num), 154 HINIC_PORT_STAT(mac_rx_8192_9216_oct_pkt_num), 155 HINIC_PORT_STAT(mac_rx_9217_12287_oct_pkt_num), 156 HINIC_PORT_STAT(mac_rx_12288_16383_oct_pkt_num), 157 HINIC_PORT_STAT(mac_rx_1519_max_bad_pkt_num), 158 HINIC_PORT_STAT(mac_rx_1519_max_good_pkt_num), 159 HINIC_PORT_STAT(mac_rx_oversize_pkt_num), 160 HINIC_PORT_STAT(mac_rx_jabber_pkt_num), 161 HINIC_PORT_STAT(mac_rx_mac_pause_num), 162 HINIC_PORT_STAT(mac_rx_pfc_pkt_num), 163 HINIC_PORT_STAT(mac_rx_pfc_pri0_pkt_num), 164 HINIC_PORT_STAT(mac_rx_pfc_pri1_pkt_num), 165 HINIC_PORT_STAT(mac_rx_pfc_pri2_pkt_num), 166 HINIC_PORT_STAT(mac_rx_pfc_pri3_pkt_num), 167 HINIC_PORT_STAT(mac_rx_pfc_pri4_pkt_num), 168 HINIC_PORT_STAT(mac_rx_pfc_pri5_pkt_num), 169 HINIC_PORT_STAT(mac_rx_pfc_pri6_pkt_num), 170 HINIC_PORT_STAT(mac_rx_pfc_pri7_pkt_num), 171 HINIC_PORT_STAT(mac_rx_mac_control_pkt_num), 172 HINIC_PORT_STAT(mac_rx_sym_err_pkt_num), 173 HINIC_PORT_STAT(mac_rx_fcs_err_pkt_num), 174 HINIC_PORT_STAT(mac_rx_send_app_good_pkt_num), 175 HINIC_PORT_STAT(mac_rx_send_app_bad_pkt_num), 176 HINIC_PORT_STAT(mac_tx_fragment_pkt_num), 177 HINIC_PORT_STAT(mac_tx_undersize_pkt_num), 178 HINIC_PORT_STAT(mac_tx_undermin_pkt_num), 179 HINIC_PORT_STAT(mac_tx_64_oct_pkt_num), 180 HINIC_PORT_STAT(mac_tx_65_127_oct_pkt_num), 181 HINIC_PORT_STAT(mac_tx_128_255_oct_pkt_num), 182 HINIC_PORT_STAT(mac_tx_256_511_oct_pkt_num), 183 HINIC_PORT_STAT(mac_tx_512_1023_oct_pkt_num), 184 HINIC_PORT_STAT(mac_tx_1024_1518_oct_pkt_num), 185 HINIC_PORT_STAT(mac_tx_1519_2047_oct_pkt_num), 186 HINIC_PORT_STAT(mac_tx_2048_4095_oct_pkt_num), 187 HINIC_PORT_STAT(mac_tx_4096_8191_oct_pkt_num), 188 HINIC_PORT_STAT(mac_tx_8192_9216_oct_pkt_num), 189 HINIC_PORT_STAT(mac_tx_9217_12287_oct_pkt_num), 190 HINIC_PORT_STAT(mac_tx_12288_16383_oct_pkt_num), 191 HINIC_PORT_STAT(mac_tx_1519_max_bad_pkt_num), 192 HINIC_PORT_STAT(mac_tx_1519_max_good_pkt_num), 193 HINIC_PORT_STAT(mac_tx_oversize_pkt_num), 194 HINIC_PORT_STAT(mac_trans_jabber_pkt_num), 195 HINIC_PORT_STAT(mac_tx_mac_pause_num), 196 HINIC_PORT_STAT(mac_tx_pfc_pkt_num), 197 HINIC_PORT_STAT(mac_tx_pfc_pri0_pkt_num), 198 HINIC_PORT_STAT(mac_tx_pfc_pri1_pkt_num), 199 HINIC_PORT_STAT(mac_tx_pfc_pri2_pkt_num), 200 HINIC_PORT_STAT(mac_tx_pfc_pri3_pkt_num), 201 HINIC_PORT_STAT(mac_tx_pfc_pri4_pkt_num), 202 HINIC_PORT_STAT(mac_tx_pfc_pri5_pkt_num), 203 HINIC_PORT_STAT(mac_tx_pfc_pri6_pkt_num), 204 HINIC_PORT_STAT(mac_tx_pfc_pri7_pkt_num), 205 HINIC_PORT_STAT(mac_tx_mac_control_pkt_num), 206 HINIC_PORT_STAT(mac_tx_err_all_pkt_num), 207 HINIC_PORT_STAT(mac_tx_from_app_good_pkt_num), 208 HINIC_PORT_STAT(mac_tx_from_app_bad_pkt_num), 209 }; 210 211 #define HINIC_PHYPORT_XSTATS_NUM (sizeof(hinic_phyport_stats_strings) / \ 212 sizeof(hinic_phyport_stats_strings[0])) 213 214 static const struct hinic_xstats_name_off hinic_rxq_stats_strings[] = { 215 {"rx_nombuf", offsetof(struct hinic_rxq_stats, rx_nombuf)}, 216 {"burst_pkt", offsetof(struct hinic_rxq_stats, burst_pkts)}, 217 }; 218 219 #define HINIC_RXQ_XSTATS_NUM (sizeof(hinic_rxq_stats_strings) / \ 220 sizeof(hinic_rxq_stats_strings[0])) 221 222 static const struct hinic_xstats_name_off hinic_txq_stats_strings[] = { 223 {"tx_busy", offsetof(struct hinic_txq_stats, tx_busy)}, 224 {"offload_errors", offsetof(struct hinic_txq_stats, off_errs)}, 225 {"copy_pkts", offsetof(struct hinic_txq_stats, cpy_pkts)}, 226 {"rl_drop", offsetof(struct hinic_txq_stats, rl_drop)}, 227 {"burst_pkts", offsetof(struct hinic_txq_stats, burst_pkts)}, 228 {"sge_len0", offsetof(struct hinic_txq_stats, sge_len0)}, 229 {"mbuf_null", offsetof(struct hinic_txq_stats, mbuf_null)}, 230 }; 231 232 #define HINIC_TXQ_XSTATS_NUM (sizeof(hinic_txq_stats_strings) / \ 233 sizeof(hinic_txq_stats_strings[0])) 234 235 static int hinic_xstats_calc_num(struct hinic_nic_dev *nic_dev) 236 { 237 if (HINIC_IS_VF(nic_dev->hwdev)) { 238 return (HINIC_VPORT_XSTATS_NUM + 239 HINIC_RXQ_XSTATS_NUM * nic_dev->num_rq + 240 HINIC_TXQ_XSTATS_NUM * nic_dev->num_sq); 241 } else { 242 return (HINIC_VPORT_XSTATS_NUM + 243 HINIC_PHYPORT_XSTATS_NUM + 244 HINIC_RXQ_XSTATS_NUM * nic_dev->num_rq + 245 HINIC_TXQ_XSTATS_NUM * nic_dev->num_sq); 246 } 247 } 248 249 static const struct rte_eth_desc_lim hinic_rx_desc_lim = { 250 .nb_max = HINIC_MAX_QUEUE_DEPTH, 251 .nb_min = HINIC_MIN_QUEUE_DEPTH, 252 .nb_align = HINIC_RXD_ALIGN, 253 }; 254 255 static const struct rte_eth_desc_lim hinic_tx_desc_lim = { 256 .nb_max = HINIC_MAX_QUEUE_DEPTH, 257 .nb_min = HINIC_MIN_QUEUE_DEPTH, 258 .nb_align = HINIC_TXD_ALIGN, 259 }; 260 261 static int hinic_vlan_offload_set(struct rte_eth_dev *dev, int mask); 262 263 /** 264 * Interrupt handler triggered by NIC for handling 265 * specific event. 266 * 267 * @param: The address of parameter (struct rte_eth_dev *) regsitered before. 268 */ 269 static void hinic_dev_interrupt_handler(void *param) 270 { 271 struct rte_eth_dev *dev = param; 272 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 273 274 if (!rte_bit_relaxed_get32(HINIC_DEV_INTR_EN, &nic_dev->dev_status)) { 275 PMD_DRV_LOG(WARNING, "Device's interrupt is disabled, ignore interrupt event, dev_name: %s, port_id: %d", 276 nic_dev->proc_dev_name, dev->data->port_id); 277 return; 278 } 279 280 /* aeq0 msg handler */ 281 hinic_dev_handle_aeq_event(nic_dev->hwdev, param); 282 } 283 284 /** 285 * Ethernet device configuration. 286 * 287 * Prepare the driver for a given number of TX and RX queues, mtu size 288 * and configure RSS. 289 * 290 * @param dev 291 * Pointer to Ethernet device structure. 292 * 293 * @return 294 * 0 on success, negative error value otherwise. 295 */ 296 static int hinic_dev_configure(struct rte_eth_dev *dev) 297 { 298 struct hinic_nic_dev *nic_dev; 299 struct hinic_nic_io *nic_io; 300 int err; 301 302 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 303 nic_io = nic_dev->hwdev->nic_io; 304 305 nic_dev->num_sq = dev->data->nb_tx_queues; 306 nic_dev->num_rq = dev->data->nb_rx_queues; 307 308 nic_io->num_sqs = dev->data->nb_tx_queues; 309 nic_io->num_rqs = dev->data->nb_rx_queues; 310 311 /* queue pair is max_num(sq, rq) */ 312 nic_dev->num_qps = (nic_dev->num_sq > nic_dev->num_rq) ? 313 nic_dev->num_sq : nic_dev->num_rq; 314 nic_io->num_qps = nic_dev->num_qps; 315 316 if (nic_dev->num_qps > nic_io->max_qps) { 317 PMD_DRV_LOG(ERR, 318 "Queue number out of range, get queue_num:%d, max_queue_num:%d", 319 nic_dev->num_qps, nic_io->max_qps); 320 return -EINVAL; 321 } 322 323 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 324 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 325 326 /* mtu size is 256~9600 */ 327 if (dev->data->dev_conf.rxmode.max_rx_pkt_len < HINIC_MIN_FRAME_SIZE || 328 dev->data->dev_conf.rxmode.max_rx_pkt_len > 329 HINIC_MAX_JUMBO_FRAME_SIZE) { 330 PMD_DRV_LOG(ERR, 331 "Max rx pkt len out of range, get max_rx_pkt_len:%d, " 332 "expect between %d and %d", 333 dev->data->dev_conf.rxmode.max_rx_pkt_len, 334 HINIC_MIN_FRAME_SIZE, HINIC_MAX_JUMBO_FRAME_SIZE); 335 return -EINVAL; 336 } 337 338 nic_dev->mtu_size = 339 HINIC_PKTLEN_TO_MTU(dev->data->dev_conf.rxmode.max_rx_pkt_len); 340 341 /* rss template */ 342 err = hinic_config_mq_mode(dev, TRUE); 343 if (err) { 344 PMD_DRV_LOG(ERR, "Config multi-queue failed"); 345 return err; 346 } 347 348 /* init vlan offoad */ 349 err = hinic_vlan_offload_set(dev, 350 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 351 if (err) { 352 PMD_DRV_LOG(ERR, "Initialize vlan filter and strip failed"); 353 (void)hinic_config_mq_mode(dev, FALSE); 354 return err; 355 } 356 357 /* clear fdir filter flag in function table */ 358 hinic_free_fdir_filter(nic_dev); 359 360 return HINIC_OK; 361 } 362 363 /** 364 * DPDK callback to create the receive queue. 365 * 366 * @param dev 367 * Pointer to Ethernet device structure. 368 * @param queue_idx 369 * RX queue index. 370 * @param nb_desc 371 * Number of descriptors for receive queue. 372 * @param socket_id 373 * NUMA socket on which memory must be allocated. 374 * @param rx_conf 375 * Thresholds parameters (unused_). 376 * @param mp 377 * Memory pool for buffer allocations. 378 * 379 * @return 380 * 0 on success, negative error value otherwise. 381 */ 382 static int hinic_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 383 uint16_t nb_desc, unsigned int socket_id, 384 __rte_unused const struct rte_eth_rxconf *rx_conf, 385 struct rte_mempool *mp) 386 { 387 int rc; 388 struct hinic_nic_dev *nic_dev; 389 struct hinic_hwdev *hwdev; 390 struct hinic_rxq *rxq; 391 u16 rq_depth, rx_free_thresh; 392 u32 buf_size; 393 394 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 395 hwdev = nic_dev->hwdev; 396 397 /* queue depth must be power of 2, otherwise will be aligned up */ 398 rq_depth = (nb_desc & (nb_desc - 1)) ? 399 ((u16)(1U << (ilog2(nb_desc) + 1))) : nb_desc; 400 401 /* 402 * Validate number of receive descriptors. 403 * It must not exceed hardware maximum and minimum. 404 */ 405 if (rq_depth > HINIC_MAX_QUEUE_DEPTH || 406 rq_depth < HINIC_MIN_QUEUE_DEPTH) { 407 PMD_DRV_LOG(ERR, "RX queue depth is out of range from %d to %d, (nb_desc=%d, q_depth=%d, port=%d queue=%d)", 408 HINIC_MIN_QUEUE_DEPTH, HINIC_MAX_QUEUE_DEPTH, 409 (int)nb_desc, (int)rq_depth, 410 (int)dev->data->port_id, (int)queue_idx); 411 return -EINVAL; 412 } 413 414 /* 415 * The RX descriptor ring will be cleaned after rxq->rx_free_thresh 416 * descriptors are used or if the number of descriptors required 417 * to transmit a packet is greater than the number of free RX 418 * descriptors. 419 * The following constraints must be satisfied: 420 * rx_free_thresh must be greater than 0. 421 * rx_free_thresh must be less than the size of the ring minus 1. 422 * When set to zero use default values. 423 */ 424 rx_free_thresh = (u16)((rx_conf->rx_free_thresh) ? 425 rx_conf->rx_free_thresh : HINIC_DEFAULT_RX_FREE_THRESH); 426 if (rx_free_thresh >= (rq_depth - 1)) { 427 PMD_DRV_LOG(ERR, "rx_free_thresh must be less than the number of RX descriptors minus 1. (rx_free_thresh=%u port=%d queue=%d)", 428 (unsigned int)rx_free_thresh, 429 (int)dev->data->port_id, 430 (int)queue_idx); 431 return -EINVAL; 432 } 433 434 rxq = rte_zmalloc_socket("hinic_rx_queue", sizeof(struct hinic_rxq), 435 RTE_CACHE_LINE_SIZE, socket_id); 436 if (!rxq) { 437 PMD_DRV_LOG(ERR, "Allocate rxq[%d] failed, dev_name: %s", 438 queue_idx, dev->data->name); 439 return -ENOMEM; 440 } 441 nic_dev->rxqs[queue_idx] = rxq; 442 443 /* alloc rx sq hw wqe page */ 444 rc = hinic_create_rq(hwdev, queue_idx, rq_depth, socket_id); 445 if (rc) { 446 PMD_DRV_LOG(ERR, "Create rxq[%d] failed, dev_name: %s, rq_depth: %d", 447 queue_idx, dev->data->name, rq_depth); 448 goto ceate_rq_fail; 449 } 450 451 /* mbuf pool must be assigned before setup rx resources */ 452 rxq->mb_pool = mp; 453 454 rc = 455 hinic_convert_rx_buf_size(rte_pktmbuf_data_room_size(rxq->mb_pool) - 456 RTE_PKTMBUF_HEADROOM, &buf_size); 457 if (rc) { 458 PMD_DRV_LOG(ERR, "Adjust buf size failed, dev_name: %s", 459 dev->data->name); 460 goto adjust_bufsize_fail; 461 } 462 463 /* rx queue info, rearm control */ 464 rxq->wq = &hwdev->nic_io->rq_wq[queue_idx]; 465 rxq->pi_virt_addr = hwdev->nic_io->qps[queue_idx].rq.pi_virt_addr; 466 rxq->nic_dev = nic_dev; 467 rxq->q_id = queue_idx; 468 rxq->q_depth = rq_depth; 469 rxq->buf_len = (u16)buf_size; 470 rxq->rx_free_thresh = rx_free_thresh; 471 rxq->socket_id = socket_id; 472 473 /* the last point cant do mbuf rearm in bulk */ 474 rxq->rxinfo_align_end = rxq->q_depth - rxq->rx_free_thresh; 475 476 /* device port identifier */ 477 rxq->port_id = dev->data->port_id; 478 479 /* alloc rx_cqe and prepare rq_wqe */ 480 rc = hinic_setup_rx_resources(rxq); 481 if (rc) { 482 PMD_DRV_LOG(ERR, "Setup rxq[%d] rx_resources failed, dev_name: %s", 483 queue_idx, dev->data->name); 484 goto setup_rx_res_err; 485 } 486 487 /* record nic_dev rxq in rte_eth rx_queues */ 488 dev->data->rx_queues[queue_idx] = rxq; 489 490 return 0; 491 492 setup_rx_res_err: 493 adjust_bufsize_fail: 494 hinic_destroy_rq(hwdev, queue_idx); 495 496 ceate_rq_fail: 497 rte_free(rxq); 498 499 return rc; 500 } 501 502 static void hinic_reset_rx_queue(struct rte_eth_dev *dev) 503 { 504 struct hinic_rxq *rxq; 505 struct hinic_nic_dev *nic_dev; 506 int q_id = 0; 507 508 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 509 510 for (q_id = 0; q_id < nic_dev->num_rq; q_id++) { 511 rxq = dev->data->rx_queues[q_id]; 512 513 rxq->wq->cons_idx = 0; 514 rxq->wq->prod_idx = 0; 515 rxq->wq->delta = rxq->q_depth; 516 rxq->wq->mask = rxq->q_depth - 1; 517 518 /* alloc mbuf to rq */ 519 hinic_rx_alloc_pkts(rxq); 520 } 521 } 522 523 /** 524 * DPDK callback to configure the transmit queue. 525 * 526 * @param dev 527 * Pointer to Ethernet device structure. 528 * @param queue_idx 529 * Transmit queue index. 530 * @param nb_desc 531 * Number of descriptors for transmit queue. 532 * @param socket_id 533 * NUMA socket on which memory must be allocated. 534 * @param tx_conf 535 * Tx queue configuration parameters. 536 * 537 * @return 538 * 0 on success, negative error value otherwise. 539 */ 540 static int hinic_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 541 uint16_t nb_desc, unsigned int socket_id, 542 __rte_unused const struct rte_eth_txconf *tx_conf) 543 { 544 int rc; 545 struct hinic_nic_dev *nic_dev; 546 struct hinic_hwdev *hwdev; 547 struct hinic_txq *txq; 548 u16 sq_depth, tx_free_thresh; 549 550 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 551 hwdev = nic_dev->hwdev; 552 553 /* queue depth must be power of 2, otherwise will be aligned up */ 554 sq_depth = (nb_desc & (nb_desc - 1)) ? 555 ((u16)(1U << (ilog2(nb_desc) + 1))) : nb_desc; 556 557 /* 558 * Validate number of transmit descriptors. 559 * It must not exceed hardware maximum and minimum. 560 */ 561 if (sq_depth > HINIC_MAX_QUEUE_DEPTH || 562 sq_depth < HINIC_MIN_QUEUE_DEPTH) { 563 PMD_DRV_LOG(ERR, "TX queue depth is out of range from %d to %d, (nb_desc=%d, q_depth=%d, port=%d queue=%d)", 564 HINIC_MIN_QUEUE_DEPTH, HINIC_MAX_QUEUE_DEPTH, 565 (int)nb_desc, (int)sq_depth, 566 (int)dev->data->port_id, (int)queue_idx); 567 return -EINVAL; 568 } 569 570 /* 571 * The TX descriptor ring will be cleaned after txq->tx_free_thresh 572 * descriptors are used or if the number of descriptors required 573 * to transmit a packet is greater than the number of free TX 574 * descriptors. 575 * The following constraints must be satisfied: 576 * tx_free_thresh must be greater than 0. 577 * tx_free_thresh must be less than the size of the ring minus 1. 578 * When set to zero use default values. 579 */ 580 tx_free_thresh = (u16)((tx_conf->tx_free_thresh) ? 581 tx_conf->tx_free_thresh : HINIC_DEFAULT_TX_FREE_THRESH); 582 if (tx_free_thresh >= (sq_depth - 1)) { 583 PMD_DRV_LOG(ERR, "tx_free_thresh must be less than the number of TX descriptors minus 1. (tx_free_thresh=%u port=%d queue=%d)", 584 (unsigned int)tx_free_thresh, (int)dev->data->port_id, 585 (int)queue_idx); 586 return -EINVAL; 587 } 588 589 txq = rte_zmalloc_socket("hinic_tx_queue", sizeof(struct hinic_txq), 590 RTE_CACHE_LINE_SIZE, socket_id); 591 if (!txq) { 592 PMD_DRV_LOG(ERR, "Allocate txq[%d] failed, dev_name: %s", 593 queue_idx, dev->data->name); 594 return -ENOMEM; 595 } 596 nic_dev->txqs[queue_idx] = txq; 597 598 /* alloc tx sq hw wqepage */ 599 rc = hinic_create_sq(hwdev, queue_idx, sq_depth, socket_id); 600 if (rc) { 601 PMD_DRV_LOG(ERR, "Create txq[%d] failed, dev_name: %s, sq_depth: %d", 602 queue_idx, dev->data->name, sq_depth); 603 goto create_sq_fail; 604 } 605 606 txq->q_id = queue_idx; 607 txq->q_depth = sq_depth; 608 txq->port_id = dev->data->port_id; 609 txq->tx_free_thresh = tx_free_thresh; 610 txq->nic_dev = nic_dev; 611 txq->wq = &hwdev->nic_io->sq_wq[queue_idx]; 612 txq->sq = &hwdev->nic_io->qps[queue_idx].sq; 613 txq->cons_idx_addr = hwdev->nic_io->qps[queue_idx].sq.cons_idx_addr; 614 txq->sq_head_addr = HINIC_GET_WQ_HEAD(txq); 615 txq->sq_bot_sge_addr = HINIC_GET_WQ_TAIL(txq) - 616 sizeof(struct hinic_sq_bufdesc); 617 txq->cos = nic_dev->default_cos; 618 txq->socket_id = socket_id; 619 620 /* alloc software txinfo */ 621 rc = hinic_setup_tx_resources(txq); 622 if (rc) { 623 PMD_DRV_LOG(ERR, "Setup txq[%d] tx_resources failed, dev_name: %s", 624 queue_idx, dev->data->name); 625 goto setup_tx_res_fail; 626 } 627 628 /* record nic_dev txq in rte_eth tx_queues */ 629 dev->data->tx_queues[queue_idx] = txq; 630 631 return HINIC_OK; 632 633 setup_tx_res_fail: 634 hinic_destroy_sq(hwdev, queue_idx); 635 636 create_sq_fail: 637 rte_free(txq); 638 639 return rc; 640 } 641 642 static void hinic_reset_tx_queue(struct rte_eth_dev *dev) 643 { 644 struct hinic_nic_dev *nic_dev; 645 struct hinic_txq *txq; 646 struct hinic_nic_io *nic_io; 647 struct hinic_hwdev *hwdev; 648 volatile u32 *ci_addr; 649 int q_id = 0; 650 651 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 652 hwdev = nic_dev->hwdev; 653 nic_io = hwdev->nic_io; 654 655 for (q_id = 0; q_id < nic_dev->num_sq; q_id++) { 656 txq = dev->data->tx_queues[q_id]; 657 658 txq->wq->cons_idx = 0; 659 txq->wq->prod_idx = 0; 660 txq->wq->delta = txq->q_depth; 661 txq->wq->mask = txq->q_depth - 1; 662 663 /* clear hardware ci */ 664 ci_addr = (volatile u32 *)HINIC_CI_VADDR(nic_io->ci_vaddr_base, 665 q_id); 666 *ci_addr = 0; 667 } 668 } 669 670 /** 671 * Get link speed from NIC. 672 * 673 * @param dev 674 * Pointer to Ethernet device structure. 675 * @param speed_capa 676 * Pointer to link speed structure. 677 */ 678 static void hinic_get_speed_capa(struct rte_eth_dev *dev, uint32_t *speed_capa) 679 { 680 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 681 u32 supported_link, advertised_link; 682 int err; 683 684 #define HINIC_LINK_MODE_SUPPORT_1G (1U << HINIC_GE_BASE_KX) 685 686 #define HINIC_LINK_MODE_SUPPORT_10G (1U << HINIC_10GE_BASE_KR) 687 688 #define HINIC_LINK_MODE_SUPPORT_25G ((1U << HINIC_25GE_BASE_KR_S) | \ 689 (1U << HINIC_25GE_BASE_CR_S) | \ 690 (1U << HINIC_25GE_BASE_KR) | \ 691 (1U << HINIC_25GE_BASE_CR)) 692 693 #define HINIC_LINK_MODE_SUPPORT_40G ((1U << HINIC_40GE_BASE_KR4) | \ 694 (1U << HINIC_40GE_BASE_CR4)) 695 696 #define HINIC_LINK_MODE_SUPPORT_100G ((1U << HINIC_100GE_BASE_KR4) | \ 697 (1U << HINIC_100GE_BASE_CR4)) 698 699 err = hinic_get_link_mode(nic_dev->hwdev, 700 &supported_link, &advertised_link); 701 if (err || supported_link == HINIC_SUPPORTED_UNKNOWN || 702 advertised_link == HINIC_SUPPORTED_UNKNOWN) { 703 PMD_DRV_LOG(WARNING, "Get speed capability info failed, device: %s, port_id: %u", 704 nic_dev->proc_dev_name, dev->data->port_id); 705 } else { 706 *speed_capa = 0; 707 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_1G)) 708 *speed_capa |= ETH_LINK_SPEED_1G; 709 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_10G)) 710 *speed_capa |= ETH_LINK_SPEED_10G; 711 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_25G)) 712 *speed_capa |= ETH_LINK_SPEED_25G; 713 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_40G)) 714 *speed_capa |= ETH_LINK_SPEED_40G; 715 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_100G)) 716 *speed_capa |= ETH_LINK_SPEED_100G; 717 } 718 } 719 720 /** 721 * DPDK callback to get information about the device. 722 * 723 * @param dev 724 * Pointer to Ethernet device structure. 725 * @param info 726 * Pointer to Info structure output buffer. 727 */ 728 static int 729 hinic_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 730 { 731 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 732 733 info->max_rx_queues = nic_dev->nic_cap.max_rqs; 734 info->max_tx_queues = nic_dev->nic_cap.max_sqs; 735 info->min_rx_bufsize = HINIC_MIN_RX_BUF_SIZE; 736 info->max_rx_pktlen = HINIC_MAX_JUMBO_FRAME_SIZE; 737 info->max_mac_addrs = HINIC_MAX_UC_MAC_ADDRS; 738 info->min_mtu = HINIC_MIN_MTU_SIZE; 739 info->max_mtu = HINIC_MAX_MTU_SIZE; 740 info->max_lro_pkt_size = HINIC_MAX_LRO_SIZE; 741 742 hinic_get_speed_capa(dev, &info->speed_capa); 743 info->rx_queue_offload_capa = 0; 744 info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP | 745 DEV_RX_OFFLOAD_IPV4_CKSUM | 746 DEV_RX_OFFLOAD_UDP_CKSUM | 747 DEV_RX_OFFLOAD_TCP_CKSUM | 748 DEV_RX_OFFLOAD_VLAN_FILTER | 749 DEV_RX_OFFLOAD_SCATTER | 750 DEV_RX_OFFLOAD_JUMBO_FRAME | 751 DEV_RX_OFFLOAD_TCP_LRO | 752 DEV_RX_OFFLOAD_RSS_HASH; 753 754 info->tx_queue_offload_capa = 0; 755 info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT | 756 DEV_TX_OFFLOAD_IPV4_CKSUM | 757 DEV_TX_OFFLOAD_UDP_CKSUM | 758 DEV_TX_OFFLOAD_TCP_CKSUM | 759 DEV_TX_OFFLOAD_SCTP_CKSUM | 760 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 761 DEV_TX_OFFLOAD_TCP_TSO | 762 DEV_TX_OFFLOAD_MULTI_SEGS; 763 764 info->hash_key_size = HINIC_RSS_KEY_SIZE; 765 info->reta_size = HINIC_RSS_INDIR_SIZE; 766 info->flow_type_rss_offloads = HINIC_RSS_OFFLOAD_ALL; 767 info->rx_desc_lim = hinic_rx_desc_lim; 768 info->tx_desc_lim = hinic_tx_desc_lim; 769 770 /* Driver-preferred Rx/Tx parameters */ 771 info->default_rxportconf.burst_size = HINIC_DEFAULT_BURST_SIZE; 772 info->default_txportconf.burst_size = HINIC_DEFAULT_BURST_SIZE; 773 info->default_rxportconf.nb_queues = HINIC_DEFAULT_NB_QUEUES; 774 info->default_txportconf.nb_queues = HINIC_DEFAULT_NB_QUEUES; 775 info->default_rxportconf.ring_size = HINIC_DEFAULT_RING_SIZE; 776 info->default_txportconf.ring_size = HINIC_DEFAULT_RING_SIZE; 777 778 return 0; 779 } 780 781 static int hinic_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 782 size_t fw_size) 783 { 784 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 785 char fw_ver[HINIC_MGMT_VERSION_MAX_LEN] = {0}; 786 int err; 787 788 err = hinic_get_mgmt_version(nic_dev->hwdev, fw_ver); 789 if (err) { 790 PMD_DRV_LOG(ERR, "Failed to get fw version"); 791 return -EINVAL; 792 } 793 794 if (fw_size < strlen(fw_ver) + 1) 795 return (strlen(fw_ver) + 1); 796 797 snprintf(fw_version, fw_size, "%s", fw_ver); 798 799 return 0; 800 } 801 802 static int hinic_config_rx_mode(struct hinic_nic_dev *nic_dev, u32 rx_mode_ctrl) 803 { 804 int err; 805 806 err = hinic_set_rx_mode(nic_dev->hwdev, rx_mode_ctrl); 807 if (err) { 808 PMD_DRV_LOG(ERR, "Failed to set rx mode"); 809 return -EINVAL; 810 } 811 nic_dev->rx_mode_status = rx_mode_ctrl; 812 813 return 0; 814 } 815 816 static int hinic_rxtx_configure(struct rte_eth_dev *dev) 817 { 818 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 819 int err; 820 821 /* rx configure, if rss enable, need to init default configuration */ 822 err = hinic_rx_configure(dev); 823 if (err) { 824 PMD_DRV_LOG(ERR, "Configure rss failed"); 825 return err; 826 } 827 828 /* rx mode init */ 829 err = hinic_config_rx_mode(nic_dev, HINIC_DEFAULT_RX_MODE); 830 if (err) { 831 PMD_DRV_LOG(ERR, "Configure rx_mode:0x%x failed", 832 HINIC_DEFAULT_RX_MODE); 833 goto set_rx_mode_fail; 834 } 835 836 return HINIC_OK; 837 838 set_rx_mode_fail: 839 hinic_rx_remove_configure(dev); 840 841 return err; 842 } 843 844 static void hinic_remove_rxtx_configure(struct rte_eth_dev *dev) 845 { 846 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 847 848 (void)hinic_config_rx_mode(nic_dev, 0); 849 hinic_rx_remove_configure(dev); 850 } 851 852 static int hinic_priv_get_dev_link_status(struct hinic_nic_dev *nic_dev, 853 struct rte_eth_link *link) 854 { 855 int rc; 856 u8 port_link_status = 0; 857 struct nic_port_info port_link_info; 858 struct hinic_hwdev *nic_hwdev = nic_dev->hwdev; 859 uint32_t port_speed[LINK_SPEED_MAX] = {ETH_SPEED_NUM_10M, 860 ETH_SPEED_NUM_100M, ETH_SPEED_NUM_1G, 861 ETH_SPEED_NUM_10G, ETH_SPEED_NUM_25G, 862 ETH_SPEED_NUM_40G, ETH_SPEED_NUM_100G}; 863 864 rc = hinic_get_link_status(nic_hwdev, &port_link_status); 865 if (rc) 866 return rc; 867 868 if (!port_link_status) { 869 link->link_status = ETH_LINK_DOWN; 870 link->link_speed = 0; 871 link->link_duplex = ETH_LINK_HALF_DUPLEX; 872 link->link_autoneg = ETH_LINK_FIXED; 873 return HINIC_OK; 874 } 875 876 memset(&port_link_info, 0, sizeof(port_link_info)); 877 rc = hinic_get_port_info(nic_hwdev, &port_link_info); 878 if (rc) 879 return rc; 880 881 link->link_speed = port_speed[port_link_info.speed % LINK_SPEED_MAX]; 882 link->link_duplex = port_link_info.duplex; 883 link->link_autoneg = port_link_info.autoneg_state; 884 link->link_status = port_link_status; 885 886 return HINIC_OK; 887 } 888 889 /** 890 * DPDK callback to retrieve physical link information. 891 * 892 * @param dev 893 * Pointer to Ethernet device structure. 894 * @param wait_to_complete 895 * Wait for request completion. 896 * 897 * @return 898 * 0 link status changed, -1 link status not changed 899 */ 900 static int hinic_link_update(struct rte_eth_dev *dev, int wait_to_complete) 901 { 902 #define CHECK_INTERVAL 10 /* 10ms */ 903 #define MAX_REPEAT_TIME 100 /* 1s (100 * 10ms) in total */ 904 int rc = HINIC_OK; 905 struct rte_eth_link link; 906 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 907 unsigned int rep_cnt = MAX_REPEAT_TIME; 908 909 memset(&link, 0, sizeof(link)); 910 do { 911 /* Get link status information from hardware */ 912 rc = hinic_priv_get_dev_link_status(nic_dev, &link); 913 if (rc != HINIC_OK) { 914 link.link_speed = ETH_SPEED_NUM_NONE; 915 link.link_duplex = ETH_LINK_FULL_DUPLEX; 916 PMD_DRV_LOG(ERR, "Get link status failed"); 917 goto out; 918 } 919 920 if (!wait_to_complete || link.link_status) 921 break; 922 923 rte_delay_ms(CHECK_INTERVAL); 924 } while (rep_cnt--); 925 926 out: 927 rc = rte_eth_linkstatus_set(dev, &link); 928 return rc; 929 } 930 931 /** 932 * DPDK callback to bring the link UP. 933 * 934 * @param dev 935 * Pointer to Ethernet device structure. 936 * 937 * @return 938 * 0 on success, negative errno value on failure. 939 */ 940 static int hinic_dev_set_link_up(struct rte_eth_dev *dev) 941 { 942 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 943 int ret; 944 945 ret = hinic_set_xsfp_tx_status(nic_dev->hwdev, true); 946 if (ret) { 947 PMD_DRV_LOG(ERR, "Enable port tx xsfp failed, dev_name: %s, port_id: %d", 948 nic_dev->proc_dev_name, dev->data->port_id); 949 return ret; 950 } 951 952 /* link status follow phy port status, up will open pma */ 953 ret = hinic_set_port_enable(nic_dev->hwdev, true); 954 if (ret) 955 PMD_DRV_LOG(ERR, "Set mac link up failed, dev_name: %s, port_id: %d", 956 nic_dev->proc_dev_name, dev->data->port_id); 957 958 return ret; 959 } 960 961 /** 962 * DPDK callback to bring the link DOWN. 963 * 964 * @param dev 965 * Pointer to Ethernet device structure. 966 * 967 * @return 968 * 0 on success, negative errno value on failure. 969 */ 970 static int hinic_dev_set_link_down(struct rte_eth_dev *dev) 971 { 972 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 973 int ret; 974 975 ret = hinic_set_xsfp_tx_status(nic_dev->hwdev, false); 976 if (ret) { 977 PMD_DRV_LOG(ERR, "Disable port tx xsfp failed, dev_name: %s, port_id: %d", 978 nic_dev->proc_dev_name, dev->data->port_id); 979 return ret; 980 } 981 982 /* link status follow phy port status, up will close pma */ 983 ret = hinic_set_port_enable(nic_dev->hwdev, false); 984 if (ret) 985 PMD_DRV_LOG(ERR, "Set mac link down failed, dev_name: %s, port_id: %d", 986 nic_dev->proc_dev_name, dev->data->port_id); 987 988 return ret; 989 } 990 991 /** 992 * DPDK callback to start the device. 993 * 994 * @param dev 995 * Pointer to Ethernet device structure. 996 * 997 * @return 998 * 0 on success, negative errno value on failure. 999 */ 1000 static int hinic_dev_start(struct rte_eth_dev *dev) 1001 { 1002 int rc; 1003 char *name; 1004 struct hinic_nic_dev *nic_dev; 1005 1006 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1007 name = dev->data->name; 1008 1009 /* reset rx and tx queue */ 1010 hinic_reset_rx_queue(dev); 1011 hinic_reset_tx_queue(dev); 1012 1013 /* get func rx buf size */ 1014 hinic_get_func_rx_buf_size(nic_dev); 1015 1016 /* init txq and rxq context */ 1017 rc = hinic_init_qp_ctxts(nic_dev->hwdev); 1018 if (rc) { 1019 PMD_DRV_LOG(ERR, "Initialize qp context failed, dev_name: %s", 1020 name); 1021 goto init_qp_fail; 1022 } 1023 1024 /* rss template */ 1025 rc = hinic_config_mq_mode(dev, TRUE); 1026 if (rc) { 1027 PMD_DRV_LOG(ERR, "Configure mq mode failed, dev_name: %s", 1028 name); 1029 goto cfg_mq_mode_fail; 1030 } 1031 1032 /* set default mtu */ 1033 rc = hinic_set_port_mtu(nic_dev->hwdev, nic_dev->mtu_size); 1034 if (rc) { 1035 PMD_DRV_LOG(ERR, "Set mtu_size[%d] failed, dev_name: %s", 1036 nic_dev->mtu_size, name); 1037 goto set_mtu_fail; 1038 } 1039 1040 /* configure rss rx_mode and other rx or tx default feature */ 1041 rc = hinic_rxtx_configure(dev); 1042 if (rc) { 1043 PMD_DRV_LOG(ERR, "Configure tx and rx failed, dev_name: %s", 1044 name); 1045 goto cfg_rxtx_fail; 1046 } 1047 1048 /* reactive pf status, so that uP report asyn event */ 1049 hinic_set_pf_status(nic_dev->hwdev->hwif, HINIC_PF_STATUS_ACTIVE_FLAG); 1050 1051 /* open virtual port and ready to start packet receiving */ 1052 rc = hinic_set_vport_enable(nic_dev->hwdev, true); 1053 if (rc) { 1054 PMD_DRV_LOG(ERR, "Enable vport failed, dev_name:%s", name); 1055 goto en_vport_fail; 1056 } 1057 1058 /* open physical port and start packet receiving */ 1059 rc = hinic_set_port_enable(nic_dev->hwdev, true); 1060 if (rc) { 1061 PMD_DRV_LOG(ERR, "Enable physical port failed, dev_name: %s", 1062 name); 1063 goto en_port_fail; 1064 } 1065 1066 /* update eth_dev link status */ 1067 if (dev->data->dev_conf.intr_conf.lsc != 0) 1068 (void)hinic_link_update(dev, 0); 1069 1070 rte_bit_relaxed_set32(HINIC_DEV_START, &nic_dev->dev_status); 1071 1072 return 0; 1073 1074 en_port_fail: 1075 (void)hinic_set_vport_enable(nic_dev->hwdev, false); 1076 1077 en_vport_fail: 1078 hinic_set_pf_status(nic_dev->hwdev->hwif, HINIC_PF_STATUS_INIT); 1079 1080 /* Flush tx && rx chip resources in case of set vport fake fail */ 1081 (void)hinic_flush_qp_res(nic_dev->hwdev); 1082 rte_delay_ms(100); 1083 1084 hinic_remove_rxtx_configure(dev); 1085 1086 cfg_rxtx_fail: 1087 set_mtu_fail: 1088 cfg_mq_mode_fail: 1089 hinic_free_qp_ctxts(nic_dev->hwdev); 1090 1091 init_qp_fail: 1092 hinic_free_all_rx_mbuf(dev); 1093 hinic_free_all_tx_mbuf(dev); 1094 1095 return rc; 1096 } 1097 1098 /** 1099 * DPDK callback to release the receive queue. 1100 * 1101 * @param queue 1102 * Generic receive queue pointer. 1103 */ 1104 static void hinic_rx_queue_release(void *queue) 1105 { 1106 struct hinic_rxq *rxq = queue; 1107 struct hinic_nic_dev *nic_dev; 1108 1109 if (!rxq) { 1110 PMD_DRV_LOG(WARNING, "Rxq is null when release"); 1111 return; 1112 } 1113 nic_dev = rxq->nic_dev; 1114 1115 /* free rxq_pkt mbuf */ 1116 hinic_free_all_rx_mbufs(rxq); 1117 1118 /* free rxq_cqe, rxq_info */ 1119 hinic_free_rx_resources(rxq); 1120 1121 /* free root rq wq */ 1122 hinic_destroy_rq(nic_dev->hwdev, rxq->q_id); 1123 1124 nic_dev->rxqs[rxq->q_id] = NULL; 1125 1126 /* free rxq */ 1127 rte_free(rxq); 1128 } 1129 1130 /** 1131 * DPDK callback to release the transmit queue. 1132 * 1133 * @param queue 1134 * Generic transmit queue pointer. 1135 */ 1136 static void hinic_tx_queue_release(void *queue) 1137 { 1138 struct hinic_txq *txq = queue; 1139 struct hinic_nic_dev *nic_dev; 1140 1141 if (!txq) { 1142 PMD_DRV_LOG(WARNING, "Txq is null when release"); 1143 return; 1144 } 1145 nic_dev = txq->nic_dev; 1146 1147 /* free txq_pkt mbuf */ 1148 hinic_free_all_tx_mbufs(txq); 1149 1150 /* free txq_info */ 1151 hinic_free_tx_resources(txq); 1152 1153 /* free root sq wq */ 1154 hinic_destroy_sq(nic_dev->hwdev, txq->q_id); 1155 nic_dev->txqs[txq->q_id] = NULL; 1156 1157 /* free txq */ 1158 rte_free(txq); 1159 } 1160 1161 static void hinic_free_all_rq(struct hinic_nic_dev *nic_dev) 1162 { 1163 u16 q_id; 1164 1165 for (q_id = 0; q_id < nic_dev->num_rq; q_id++) 1166 hinic_destroy_rq(nic_dev->hwdev, q_id); 1167 } 1168 1169 static void hinic_free_all_sq(struct hinic_nic_dev *nic_dev) 1170 { 1171 u16 q_id; 1172 1173 for (q_id = 0; q_id < nic_dev->num_sq; q_id++) 1174 hinic_destroy_sq(nic_dev->hwdev, q_id); 1175 } 1176 1177 /** 1178 * DPDK callback to stop the device. 1179 * 1180 * @param dev 1181 * Pointer to Ethernet device structure. 1182 */ 1183 static void hinic_dev_stop(struct rte_eth_dev *dev) 1184 { 1185 int rc; 1186 char *name; 1187 uint16_t port_id; 1188 struct hinic_nic_dev *nic_dev; 1189 struct rte_eth_link link; 1190 1191 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1192 name = dev->data->name; 1193 port_id = dev->data->port_id; 1194 1195 if (!rte_bit_relaxed_test_and_clear32(HINIC_DEV_START, 1196 &nic_dev->dev_status)) { 1197 PMD_DRV_LOG(INFO, "Device %s already stopped", name); 1198 return; 1199 } 1200 1201 /* just stop phy port and vport */ 1202 rc = hinic_set_port_enable(nic_dev->hwdev, false); 1203 if (rc) 1204 PMD_DRV_LOG(WARNING, "Disable phy port failed, error: %d, dev_name: %s, port_id: %d", 1205 rc, name, port_id); 1206 1207 rc = hinic_set_vport_enable(nic_dev->hwdev, false); 1208 if (rc) 1209 PMD_DRV_LOG(WARNING, "Disable vport failed, error: %d, dev_name: %s, port_id: %d", 1210 rc, name, port_id); 1211 1212 /* Clear recorded link status */ 1213 memset(&link, 0, sizeof(link)); 1214 (void)rte_eth_linkstatus_set(dev, &link); 1215 1216 /* flush pending io request */ 1217 rc = hinic_rx_tx_flush(nic_dev->hwdev); 1218 if (rc) 1219 PMD_DRV_LOG(WARNING, "Flush pending io failed, error: %d, dev_name: %s, port_id: %d", 1220 rc, name, port_id); 1221 1222 /* clean rss table and rx_mode */ 1223 hinic_remove_rxtx_configure(dev); 1224 1225 /* clean root context */ 1226 hinic_free_qp_ctxts(nic_dev->hwdev); 1227 1228 hinic_destroy_fdir_filter(dev); 1229 1230 /* free mbuf */ 1231 hinic_free_all_rx_mbuf(dev); 1232 hinic_free_all_tx_mbuf(dev); 1233 } 1234 1235 static void hinic_disable_interrupt(struct rte_eth_dev *dev) 1236 { 1237 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1238 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1239 int ret, retries = 0; 1240 1241 rte_bit_relaxed_clear32(HINIC_DEV_INTR_EN, &nic_dev->dev_status); 1242 1243 /* disable msix interrupt in hardware */ 1244 hinic_set_msix_state(nic_dev->hwdev, 0, HINIC_MSIX_DISABLE); 1245 1246 /* disable rte interrupt */ 1247 ret = rte_intr_disable(&pci_dev->intr_handle); 1248 if (ret) 1249 PMD_DRV_LOG(ERR, "Disable intr failed: %d", ret); 1250 1251 do { 1252 ret = 1253 rte_intr_callback_unregister(&pci_dev->intr_handle, 1254 hinic_dev_interrupt_handler, dev); 1255 if (ret >= 0) { 1256 break; 1257 } else if (ret == -EAGAIN) { 1258 rte_delay_ms(100); 1259 retries++; 1260 } else { 1261 PMD_DRV_LOG(ERR, "intr callback unregister failed: %d", 1262 ret); 1263 break; 1264 } 1265 } while (retries < HINIC_INTR_CB_UNREG_MAX_RETRIES); 1266 1267 if (retries == HINIC_INTR_CB_UNREG_MAX_RETRIES) 1268 PMD_DRV_LOG(ERR, "Unregister intr callback failed after %d retries", 1269 retries); 1270 } 1271 1272 static int hinic_set_dev_promiscuous(struct hinic_nic_dev *nic_dev, bool enable) 1273 { 1274 u32 rx_mode_ctrl = nic_dev->rx_mode_status; 1275 1276 if (enable) 1277 rx_mode_ctrl |= HINIC_RX_MODE_PROMISC; 1278 else 1279 rx_mode_ctrl &= (~HINIC_RX_MODE_PROMISC); 1280 1281 return hinic_config_rx_mode(nic_dev, rx_mode_ctrl); 1282 } 1283 1284 /** 1285 * DPDK callback to get device statistics. 1286 * 1287 * @param dev 1288 * Pointer to Ethernet device structure. 1289 * @param stats 1290 * Stats structure output buffer. 1291 * 1292 * @return 1293 * 0 on success and stats is filled, 1294 * negative error value otherwise. 1295 */ 1296 static int 1297 hinic_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1298 { 1299 int i, err, q_num; 1300 u64 rx_discards_pmd = 0; 1301 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1302 struct hinic_vport_stats vport_stats; 1303 struct hinic_rxq *rxq = NULL; 1304 struct hinic_rxq_stats rxq_stats; 1305 struct hinic_txq *txq = NULL; 1306 struct hinic_txq_stats txq_stats; 1307 1308 err = hinic_get_vport_stats(nic_dev->hwdev, &vport_stats); 1309 if (err) { 1310 PMD_DRV_LOG(ERR, "Get vport stats from fw failed, nic_dev: %s", 1311 nic_dev->proc_dev_name); 1312 return err; 1313 } 1314 1315 /* rx queue stats */ 1316 q_num = (nic_dev->num_rq < RTE_ETHDEV_QUEUE_STAT_CNTRS) ? 1317 nic_dev->num_rq : RTE_ETHDEV_QUEUE_STAT_CNTRS; 1318 for (i = 0; i < q_num; i++) { 1319 rxq = nic_dev->rxqs[i]; 1320 hinic_rxq_get_stats(rxq, &rxq_stats); 1321 stats->q_ipackets[i] = rxq_stats.packets; 1322 stats->q_ibytes[i] = rxq_stats.bytes; 1323 stats->q_errors[i] = rxq_stats.rx_discards; 1324 1325 stats->ierrors += rxq_stats.errors; 1326 rx_discards_pmd += rxq_stats.rx_discards; 1327 dev->data->rx_mbuf_alloc_failed += rxq_stats.rx_nombuf; 1328 } 1329 1330 /* tx queue stats */ 1331 q_num = (nic_dev->num_sq < RTE_ETHDEV_QUEUE_STAT_CNTRS) ? 1332 nic_dev->num_sq : RTE_ETHDEV_QUEUE_STAT_CNTRS; 1333 for (i = 0; i < q_num; i++) { 1334 txq = nic_dev->txqs[i]; 1335 hinic_txq_get_stats(txq, &txq_stats); 1336 stats->q_opackets[i] = txq_stats.packets; 1337 stats->q_obytes[i] = txq_stats.bytes; 1338 stats->oerrors += (txq_stats.tx_busy + txq_stats.off_errs); 1339 } 1340 1341 /* vport stats */ 1342 stats->oerrors += vport_stats.tx_discard_vport; 1343 1344 stats->imissed = vport_stats.rx_discard_vport + rx_discards_pmd; 1345 1346 stats->ipackets = (vport_stats.rx_unicast_pkts_vport + 1347 vport_stats.rx_multicast_pkts_vport + 1348 vport_stats.rx_broadcast_pkts_vport - 1349 rx_discards_pmd); 1350 1351 stats->opackets = (vport_stats.tx_unicast_pkts_vport + 1352 vport_stats.tx_multicast_pkts_vport + 1353 vport_stats.tx_broadcast_pkts_vport); 1354 1355 stats->ibytes = (vport_stats.rx_unicast_bytes_vport + 1356 vport_stats.rx_multicast_bytes_vport + 1357 vport_stats.rx_broadcast_bytes_vport); 1358 1359 stats->obytes = (vport_stats.tx_unicast_bytes_vport + 1360 vport_stats.tx_multicast_bytes_vport + 1361 vport_stats.tx_broadcast_bytes_vport); 1362 return 0; 1363 } 1364 1365 /** 1366 * DPDK callback to clear device statistics. 1367 * 1368 * @param dev 1369 * Pointer to Ethernet device structure. 1370 */ 1371 static int hinic_dev_stats_reset(struct rte_eth_dev *dev) 1372 { 1373 int qid; 1374 struct hinic_rxq *rxq = NULL; 1375 struct hinic_txq *txq = NULL; 1376 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1377 int ret; 1378 1379 ret = hinic_clear_vport_stats(nic_dev->hwdev); 1380 if (ret != 0) 1381 return ret; 1382 1383 for (qid = 0; qid < nic_dev->num_rq; qid++) { 1384 rxq = nic_dev->rxqs[qid]; 1385 hinic_rxq_stats_reset(rxq); 1386 } 1387 1388 for (qid = 0; qid < nic_dev->num_sq; qid++) { 1389 txq = nic_dev->txqs[qid]; 1390 hinic_txq_stats_reset(txq); 1391 } 1392 1393 return 0; 1394 } 1395 1396 /** 1397 * DPDK callback to clear device extended statistics. 1398 * 1399 * @param dev 1400 * Pointer to Ethernet device structure. 1401 */ 1402 static int hinic_dev_xstats_reset(struct rte_eth_dev *dev) 1403 { 1404 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1405 int ret; 1406 1407 ret = hinic_dev_stats_reset(dev); 1408 if (ret != 0) 1409 return ret; 1410 1411 if (hinic_func_type(nic_dev->hwdev) != TYPE_VF) { 1412 ret = hinic_clear_phy_port_stats(nic_dev->hwdev); 1413 if (ret != 0) 1414 return ret; 1415 } 1416 1417 return 0; 1418 } 1419 1420 static void hinic_gen_random_mac_addr(struct rte_ether_addr *mac_addr) 1421 { 1422 uint64_t random_value; 1423 1424 /* Set Organizationally Unique Identifier (OUI) prefix */ 1425 mac_addr->addr_bytes[0] = 0x00; 1426 mac_addr->addr_bytes[1] = 0x09; 1427 mac_addr->addr_bytes[2] = 0xC0; 1428 /* Force indication of locally assigned MAC address. */ 1429 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR; 1430 /* Generate the last 3 bytes of the MAC address with a random number. */ 1431 random_value = rte_rand(); 1432 memcpy(&mac_addr->addr_bytes[3], &random_value, 3); 1433 } 1434 1435 /** 1436 * Init mac_vlan table in NIC. 1437 * 1438 * @param dev 1439 * Pointer to Ethernet device structure. 1440 * 1441 * @return 1442 * 0 on success and stats is filled, 1443 * negative error value otherwise. 1444 */ 1445 static int hinic_init_mac_addr(struct rte_eth_dev *eth_dev) 1446 { 1447 struct hinic_nic_dev *nic_dev = 1448 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); 1449 uint8_t addr_bytes[RTE_ETHER_ADDR_LEN]; 1450 u16 func_id = 0; 1451 int rc = 0; 1452 1453 rc = hinic_get_default_mac(nic_dev->hwdev, addr_bytes); 1454 if (rc) 1455 return rc; 1456 1457 rte_ether_addr_copy((struct rte_ether_addr *)addr_bytes, 1458 ð_dev->data->mac_addrs[0]); 1459 if (rte_is_zero_ether_addr(ð_dev->data->mac_addrs[0])) 1460 hinic_gen_random_mac_addr(ð_dev->data->mac_addrs[0]); 1461 1462 func_id = hinic_global_func_id(nic_dev->hwdev); 1463 rc = hinic_set_mac(nic_dev->hwdev, 1464 eth_dev->data->mac_addrs[0].addr_bytes, 1465 0, func_id); 1466 if (rc && rc != HINIC_PF_SET_VF_ALREADY) 1467 return rc; 1468 1469 rte_ether_addr_copy(ð_dev->data->mac_addrs[0], 1470 &nic_dev->default_addr); 1471 1472 return 0; 1473 } 1474 1475 static void hinic_delete_mc_addr_list(struct hinic_nic_dev *nic_dev) 1476 { 1477 u16 func_id; 1478 u32 i; 1479 1480 func_id = hinic_global_func_id(nic_dev->hwdev); 1481 1482 for (i = 0; i < HINIC_MAX_MC_MAC_ADDRS; i++) { 1483 if (rte_is_zero_ether_addr(&nic_dev->mc_list[i])) 1484 break; 1485 1486 hinic_del_mac(nic_dev->hwdev, nic_dev->mc_list[i].addr_bytes, 1487 0, func_id); 1488 memset(&nic_dev->mc_list[i], 0, sizeof(struct rte_ether_addr)); 1489 } 1490 } 1491 1492 /** 1493 * Deinit mac_vlan table in NIC. 1494 * 1495 * @param dev 1496 * Pointer to Ethernet device structure. 1497 * 1498 * @return 1499 * 0 on success and stats is filled, 1500 * negative error value otherwise. 1501 */ 1502 static void hinic_deinit_mac_addr(struct rte_eth_dev *eth_dev) 1503 { 1504 struct hinic_nic_dev *nic_dev = 1505 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); 1506 u16 func_id = 0; 1507 int rc; 1508 int i; 1509 1510 func_id = hinic_global_func_id(nic_dev->hwdev); 1511 1512 for (i = 0; i < HINIC_MAX_UC_MAC_ADDRS; i++) { 1513 if (rte_is_zero_ether_addr(ð_dev->data->mac_addrs[i])) 1514 continue; 1515 1516 rc = hinic_del_mac(nic_dev->hwdev, 1517 eth_dev->data->mac_addrs[i].addr_bytes, 1518 0, func_id); 1519 if (rc && rc != HINIC_PF_SET_VF_ALREADY) 1520 PMD_DRV_LOG(ERR, "Delete mac table failed, dev_name: %s", 1521 eth_dev->data->name); 1522 1523 memset(ð_dev->data->mac_addrs[i], 0, 1524 sizeof(struct rte_ether_addr)); 1525 } 1526 1527 /* delete multicast mac addrs */ 1528 hinic_delete_mc_addr_list(nic_dev); 1529 } 1530 1531 static int hinic_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 1532 { 1533 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1534 uint32_t frame_size; 1535 int ret = 0; 1536 1537 PMD_DRV_LOG(INFO, "Set port mtu, port_id: %d, mtu: %d, max_pkt_len: %d", 1538 dev->data->port_id, mtu, HINIC_MTU_TO_PKTLEN(mtu)); 1539 1540 if (mtu < HINIC_MIN_MTU_SIZE || mtu > HINIC_MAX_MTU_SIZE) { 1541 PMD_DRV_LOG(ERR, "Invalid mtu: %d, must between %d and %d", 1542 mtu, HINIC_MIN_MTU_SIZE, HINIC_MAX_MTU_SIZE); 1543 return -EINVAL; 1544 } 1545 1546 ret = hinic_set_port_mtu(nic_dev->hwdev, mtu); 1547 if (ret) { 1548 PMD_DRV_LOG(ERR, "Set port mtu failed, ret: %d", ret); 1549 return ret; 1550 } 1551 1552 /* update max frame size */ 1553 frame_size = HINIC_MTU_TO_PKTLEN(mtu); 1554 if (frame_size > RTE_ETHER_MAX_LEN) 1555 dev->data->dev_conf.rxmode.offloads |= 1556 DEV_RX_OFFLOAD_JUMBO_FRAME; 1557 else 1558 dev->data->dev_conf.rxmode.offloads &= 1559 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1560 1561 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1562 nic_dev->mtu_size = mtu; 1563 1564 return ret; 1565 } 1566 1567 static void hinic_store_vlan_filter(struct hinic_nic_dev *nic_dev, 1568 u16 vlan_id, bool on) 1569 { 1570 u32 vid_idx, vid_bit; 1571 1572 vid_idx = HINIC_VFTA_IDX(vlan_id); 1573 vid_bit = HINIC_VFTA_BIT(vlan_id); 1574 1575 if (on) 1576 nic_dev->vfta[vid_idx] |= vid_bit; 1577 else 1578 nic_dev->vfta[vid_idx] &= ~vid_bit; 1579 } 1580 1581 static bool hinic_find_vlan_filter(struct hinic_nic_dev *nic_dev, 1582 uint16_t vlan_id) 1583 { 1584 u32 vid_idx, vid_bit; 1585 1586 vid_idx = HINIC_VFTA_IDX(vlan_id); 1587 vid_bit = HINIC_VFTA_BIT(vlan_id); 1588 1589 return (nic_dev->vfta[vid_idx] & vid_bit) ? TRUE : FALSE; 1590 } 1591 1592 /** 1593 * DPDK callback to set vlan filter. 1594 * 1595 * @param dev 1596 * Pointer to Ethernet device structure. 1597 * @param vlan_id 1598 * vlan id is used to filter vlan packets 1599 * @param enable 1600 * enable disable or enable vlan filter function 1601 */ 1602 static int hinic_vlan_filter_set(struct rte_eth_dev *dev, 1603 uint16_t vlan_id, int enable) 1604 { 1605 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1606 int err = 0; 1607 u16 func_id; 1608 1609 if (vlan_id > RTE_ETHER_MAX_VLAN_ID) 1610 return -EINVAL; 1611 1612 func_id = hinic_global_func_id(nic_dev->hwdev); 1613 1614 if (enable) { 1615 /* If vlanid is already set, just return */ 1616 if (hinic_find_vlan_filter(nic_dev, vlan_id)) { 1617 PMD_DRV_LOG(INFO, "Vlan %u has been added, device: %s", 1618 vlan_id, nic_dev->proc_dev_name); 1619 return 0; 1620 } 1621 1622 err = hinic_add_remove_vlan(nic_dev->hwdev, vlan_id, 1623 func_id, TRUE); 1624 } else { 1625 /* If vlanid can't be found, just return */ 1626 if (!hinic_find_vlan_filter(nic_dev, vlan_id)) { 1627 PMD_DRV_LOG(INFO, "Vlan %u is not in the vlan filter list, device: %s", 1628 vlan_id, nic_dev->proc_dev_name); 1629 return 0; 1630 } 1631 1632 err = hinic_add_remove_vlan(nic_dev->hwdev, vlan_id, 1633 func_id, FALSE); 1634 } 1635 1636 if (err) { 1637 PMD_DRV_LOG(ERR, "%s vlan failed, func_id: %d, vlan_id: %d, err: %d", 1638 enable ? "Add" : "Remove", func_id, vlan_id, err); 1639 return err; 1640 } 1641 1642 hinic_store_vlan_filter(nic_dev, vlan_id, enable); 1643 1644 PMD_DRV_LOG(INFO, "%s vlan %u succeed, device: %s", 1645 enable ? "Add" : "Remove", vlan_id, nic_dev->proc_dev_name); 1646 return 0; 1647 } 1648 1649 /** 1650 * DPDK callback to enable or disable vlan offload. 1651 * 1652 * @param dev 1653 * Pointer to Ethernet device structure. 1654 * @param mask 1655 * Definitions used for VLAN setting 1656 */ 1657 static int hinic_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1658 { 1659 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1660 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1661 bool on; 1662 int err; 1663 1664 /* Enable or disable VLAN filter */ 1665 if (mask & ETH_VLAN_FILTER_MASK) { 1666 on = (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) ? 1667 TRUE : FALSE; 1668 err = hinic_config_vlan_filter(nic_dev->hwdev, on); 1669 if (err == HINIC_MGMT_CMD_UNSUPPORTED) { 1670 PMD_DRV_LOG(WARNING, 1671 "Current matching version does not support vlan filter configuration, device: %s, port_id: %d", 1672 nic_dev->proc_dev_name, dev->data->port_id); 1673 } else if (err) { 1674 PMD_DRV_LOG(ERR, "Failed to %s vlan filter, device: %s, port_id: %d, err: %d", 1675 on ? "enable" : "disable", 1676 nic_dev->proc_dev_name, 1677 dev->data->port_id, err); 1678 return err; 1679 } 1680 1681 PMD_DRV_LOG(INFO, "%s vlan filter succeed, device: %s, port_id: %d", 1682 on ? "Enable" : "Disable", 1683 nic_dev->proc_dev_name, dev->data->port_id); 1684 } 1685 1686 /* Enable or disable VLAN stripping */ 1687 if (mask & ETH_VLAN_STRIP_MASK) { 1688 on = (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) ? 1689 TRUE : FALSE; 1690 err = hinic_set_rx_vlan_offload(nic_dev->hwdev, on); 1691 if (err) { 1692 PMD_DRV_LOG(ERR, "Failed to %s vlan strip, device: %s, port_id: %d, err: %d", 1693 on ? "enable" : "disable", 1694 nic_dev->proc_dev_name, 1695 dev->data->port_id, err); 1696 return err; 1697 } 1698 1699 PMD_DRV_LOG(INFO, "%s vlan strip succeed, device: %s, port_id: %d", 1700 on ? "Enable" : "Disable", 1701 nic_dev->proc_dev_name, dev->data->port_id); 1702 } 1703 1704 if (mask & ETH_VLAN_EXTEND_MASK) { 1705 PMD_DRV_LOG(ERR, "Don't support vlan qinq, device: %s, port_id: %d", 1706 nic_dev->proc_dev_name, dev->data->port_id); 1707 return -ENOTSUP; 1708 } 1709 1710 return 0; 1711 } 1712 1713 static void hinic_remove_all_vlanid(struct rte_eth_dev *eth_dev) 1714 { 1715 struct hinic_nic_dev *nic_dev = 1716 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); 1717 u16 func_id; 1718 int i; 1719 1720 func_id = hinic_global_func_id(nic_dev->hwdev); 1721 for (i = 0; i <= RTE_ETHER_MAX_VLAN_ID; i++) { 1722 /* If can't find it, continue */ 1723 if (!hinic_find_vlan_filter(nic_dev, i)) 1724 continue; 1725 1726 (void)hinic_add_remove_vlan(nic_dev->hwdev, i, func_id, FALSE); 1727 hinic_store_vlan_filter(nic_dev, i, false); 1728 } 1729 } 1730 1731 static int hinic_set_dev_allmulticast(struct hinic_nic_dev *nic_dev, 1732 bool enable) 1733 { 1734 u32 rx_mode_ctrl = nic_dev->rx_mode_status; 1735 1736 if (enable) 1737 rx_mode_ctrl |= HINIC_RX_MODE_MC_ALL; 1738 else 1739 rx_mode_ctrl &= (~HINIC_RX_MODE_MC_ALL); 1740 1741 return hinic_config_rx_mode(nic_dev, rx_mode_ctrl); 1742 } 1743 1744 /** 1745 * DPDK callback to enable allmulticast mode. 1746 * 1747 * @param dev 1748 * Pointer to Ethernet device structure. 1749 * 1750 * @return 1751 * 0 on success, 1752 * negative error value otherwise. 1753 */ 1754 static int hinic_dev_allmulticast_enable(struct rte_eth_dev *dev) 1755 { 1756 int ret = HINIC_OK; 1757 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1758 1759 ret = hinic_set_dev_allmulticast(nic_dev, true); 1760 if (ret) { 1761 PMD_DRV_LOG(ERR, "Enable allmulticast failed, error: %d", ret); 1762 return ret; 1763 } 1764 1765 PMD_DRV_LOG(INFO, "Enable allmulticast succeed, nic_dev: %s, port_id: %d", 1766 nic_dev->proc_dev_name, dev->data->port_id); 1767 return 0; 1768 } 1769 1770 /** 1771 * DPDK callback to disable allmulticast mode. 1772 * 1773 * @param dev 1774 * Pointer to Ethernet device structure. 1775 * 1776 * @return 1777 * 0 on success, 1778 * negative error value otherwise. 1779 */ 1780 static int hinic_dev_allmulticast_disable(struct rte_eth_dev *dev) 1781 { 1782 int ret = HINIC_OK; 1783 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1784 1785 ret = hinic_set_dev_allmulticast(nic_dev, false); 1786 if (ret) { 1787 PMD_DRV_LOG(ERR, "Disable allmulticast failed, error: %d", ret); 1788 return ret; 1789 } 1790 1791 PMD_DRV_LOG(INFO, "Disable allmulticast succeed, nic_dev: %s, port_id: %d", 1792 nic_dev->proc_dev_name, dev->data->port_id); 1793 return 0; 1794 } 1795 1796 /** 1797 * DPDK callback to enable promiscuous mode. 1798 * 1799 * @param dev 1800 * Pointer to Ethernet device structure. 1801 * 1802 * @return 1803 * 0 on success, 1804 * negative error value otherwise. 1805 */ 1806 static int hinic_dev_promiscuous_enable(struct rte_eth_dev *dev) 1807 { 1808 int rc = HINIC_OK; 1809 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1810 1811 PMD_DRV_LOG(INFO, "Enable promiscuous, nic_dev: %s, port_id: %d, promisc: %d", 1812 nic_dev->proc_dev_name, dev->data->port_id, 1813 dev->data->promiscuous); 1814 1815 rc = hinic_set_dev_promiscuous(nic_dev, true); 1816 if (rc) 1817 PMD_DRV_LOG(ERR, "Enable promiscuous failed"); 1818 1819 return rc; 1820 } 1821 1822 /** 1823 * DPDK callback to disable promiscuous mode. 1824 * 1825 * @param dev 1826 * Pointer to Ethernet device structure. 1827 * 1828 * @return 1829 * 0 on success, 1830 * negative error value otherwise. 1831 */ 1832 static int hinic_dev_promiscuous_disable(struct rte_eth_dev *dev) 1833 { 1834 int rc = HINIC_OK; 1835 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1836 1837 PMD_DRV_LOG(INFO, "Disable promiscuous, nic_dev: %s, port_id: %d, promisc: %d", 1838 nic_dev->proc_dev_name, dev->data->port_id, 1839 dev->data->promiscuous); 1840 1841 rc = hinic_set_dev_promiscuous(nic_dev, false); 1842 if (rc) 1843 PMD_DRV_LOG(ERR, "Disable promiscuous failed"); 1844 1845 return rc; 1846 } 1847 1848 static int hinic_flow_ctrl_get(struct rte_eth_dev *dev, 1849 struct rte_eth_fc_conf *fc_conf) 1850 { 1851 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1852 struct nic_pause_config nic_pause; 1853 int err; 1854 1855 memset(&nic_pause, 0, sizeof(nic_pause)); 1856 1857 err = hinic_get_pause_info(nic_dev->hwdev, &nic_pause); 1858 if (err) 1859 return err; 1860 1861 if (nic_dev->pause_set || !nic_pause.auto_neg) { 1862 nic_pause.rx_pause = nic_dev->nic_pause.rx_pause; 1863 nic_pause.tx_pause = nic_dev->nic_pause.tx_pause; 1864 } 1865 1866 fc_conf->autoneg = nic_pause.auto_neg; 1867 1868 if (nic_pause.tx_pause && nic_pause.rx_pause) 1869 fc_conf->mode = RTE_FC_FULL; 1870 else if (nic_pause.tx_pause) 1871 fc_conf->mode = RTE_FC_TX_PAUSE; 1872 else if (nic_pause.rx_pause) 1873 fc_conf->mode = RTE_FC_RX_PAUSE; 1874 else 1875 fc_conf->mode = RTE_FC_NONE; 1876 1877 return 0; 1878 } 1879 1880 static int hinic_flow_ctrl_set(struct rte_eth_dev *dev, 1881 struct rte_eth_fc_conf *fc_conf) 1882 { 1883 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1884 struct nic_pause_config nic_pause; 1885 int err; 1886 1887 nic_pause.auto_neg = fc_conf->autoneg; 1888 1889 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 1890 (fc_conf->mode & RTE_FC_TX_PAUSE)) 1891 nic_pause.tx_pause = true; 1892 else 1893 nic_pause.tx_pause = false; 1894 1895 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 1896 (fc_conf->mode & RTE_FC_RX_PAUSE)) 1897 nic_pause.rx_pause = true; 1898 else 1899 nic_pause.rx_pause = false; 1900 1901 err = hinic_set_pause_config(nic_dev->hwdev, nic_pause); 1902 if (err) 1903 return err; 1904 1905 nic_dev->pause_set = true; 1906 nic_dev->nic_pause.auto_neg = nic_pause.auto_neg; 1907 nic_dev->nic_pause.rx_pause = nic_pause.rx_pause; 1908 nic_dev->nic_pause.tx_pause = nic_pause.tx_pause; 1909 1910 PMD_DRV_LOG(INFO, "Set pause options, tx: %s, rx: %s, auto: %s\n", 1911 nic_pause.tx_pause ? "on" : "off", 1912 nic_pause.rx_pause ? "on" : "off", 1913 nic_pause.auto_neg ? "on" : "off"); 1914 1915 return 0; 1916 } 1917 1918 /** 1919 * DPDK callback to update the RSS hash key and RSS hash type. 1920 * 1921 * @param dev 1922 * Pointer to Ethernet device structure. 1923 * @param rss_conf 1924 * RSS configuration data. 1925 * 1926 * @return 1927 * 0 on success, negative error value otherwise. 1928 */ 1929 static int hinic_rss_hash_update(struct rte_eth_dev *dev, 1930 struct rte_eth_rss_conf *rss_conf) 1931 { 1932 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1933 u8 tmpl_idx = nic_dev->rss_tmpl_idx; 1934 u8 hashkey[HINIC_RSS_KEY_SIZE] = {0}; 1935 u8 prio_tc[HINIC_DCB_UP_MAX] = {0}; 1936 u64 rss_hf = rss_conf->rss_hf; 1937 struct nic_rss_type rss_type = {0}; 1938 int err = 0; 1939 1940 if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) { 1941 PMD_DRV_LOG(WARNING, "RSS is not enabled"); 1942 return HINIC_OK; 1943 } 1944 1945 if (rss_conf->rss_key_len > HINIC_RSS_KEY_SIZE) { 1946 PMD_DRV_LOG(ERR, "Invalid rss key, rss_key_len: %d", 1947 rss_conf->rss_key_len); 1948 return HINIC_ERROR; 1949 } 1950 1951 if (rss_conf->rss_key) { 1952 memcpy(hashkey, rss_conf->rss_key, rss_conf->rss_key_len); 1953 err = hinic_rss_set_template_tbl(nic_dev->hwdev, tmpl_idx, 1954 hashkey); 1955 if (err) { 1956 PMD_DRV_LOG(ERR, "Set rss template table failed"); 1957 goto disable_rss; 1958 } 1959 } 1960 1961 rss_type.ipv4 = (rss_hf & (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4)) ? 1 : 0; 1962 rss_type.tcp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) ? 1 : 0; 1963 rss_type.ipv6 = (rss_hf & (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6)) ? 1 : 0; 1964 rss_type.ipv6_ext = (rss_hf & ETH_RSS_IPV6_EX) ? 1 : 0; 1965 rss_type.tcp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) ? 1 : 0; 1966 rss_type.tcp_ipv6_ext = (rss_hf & ETH_RSS_IPV6_TCP_EX) ? 1 : 0; 1967 rss_type.udp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) ? 1 : 0; 1968 rss_type.udp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) ? 1 : 0; 1969 1970 err = hinic_set_rss_type(nic_dev->hwdev, tmpl_idx, rss_type); 1971 if (err) { 1972 PMD_DRV_LOG(ERR, "Set rss type table failed"); 1973 goto disable_rss; 1974 } 1975 1976 return 0; 1977 1978 disable_rss: 1979 memset(prio_tc, 0, sizeof(prio_tc)); 1980 (void)hinic_rss_cfg(nic_dev->hwdev, 0, tmpl_idx, 0, prio_tc); 1981 return err; 1982 } 1983 1984 /** 1985 * DPDK callback to get the RSS hash configuration. 1986 * 1987 * @param dev 1988 * Pointer to Ethernet device structure. 1989 * @param rss_conf 1990 * RSS configuration data. 1991 * 1992 * @return 1993 * 0 on success, negative error value otherwise. 1994 */ 1995 static int hinic_rss_conf_get(struct rte_eth_dev *dev, 1996 struct rte_eth_rss_conf *rss_conf) 1997 { 1998 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1999 u8 tmpl_idx = nic_dev->rss_tmpl_idx; 2000 u8 hashkey[HINIC_RSS_KEY_SIZE] = {0}; 2001 struct nic_rss_type rss_type = {0}; 2002 int err; 2003 2004 if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) { 2005 PMD_DRV_LOG(WARNING, "RSS is not enabled"); 2006 return HINIC_ERROR; 2007 } 2008 2009 err = hinic_rss_get_template_tbl(nic_dev->hwdev, tmpl_idx, hashkey); 2010 if (err) 2011 return err; 2012 2013 if (rss_conf->rss_key && 2014 rss_conf->rss_key_len >= HINIC_RSS_KEY_SIZE) { 2015 memcpy(rss_conf->rss_key, hashkey, sizeof(hashkey)); 2016 rss_conf->rss_key_len = sizeof(hashkey); 2017 } 2018 2019 err = hinic_get_rss_type(nic_dev->hwdev, tmpl_idx, &rss_type); 2020 if (err) 2021 return err; 2022 2023 rss_conf->rss_hf = 0; 2024 rss_conf->rss_hf |= rss_type.ipv4 ? 2025 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4) : 0; 2026 rss_conf->rss_hf |= rss_type.tcp_ipv4 ? ETH_RSS_NONFRAG_IPV4_TCP : 0; 2027 rss_conf->rss_hf |= rss_type.ipv6 ? 2028 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6) : 0; 2029 rss_conf->rss_hf |= rss_type.ipv6_ext ? ETH_RSS_IPV6_EX : 0; 2030 rss_conf->rss_hf |= rss_type.tcp_ipv6 ? ETH_RSS_NONFRAG_IPV6_TCP : 0; 2031 rss_conf->rss_hf |= rss_type.tcp_ipv6_ext ? ETH_RSS_IPV6_TCP_EX : 0; 2032 rss_conf->rss_hf |= rss_type.udp_ipv4 ? ETH_RSS_NONFRAG_IPV4_UDP : 0; 2033 rss_conf->rss_hf |= rss_type.udp_ipv6 ? ETH_RSS_NONFRAG_IPV6_UDP : 0; 2034 2035 return HINIC_OK; 2036 } 2037 2038 /** 2039 * DPDK callback to update the RSS redirection table. 2040 * 2041 * @param dev 2042 * Pointer to Ethernet device structure. 2043 * @param reta_conf 2044 * Pointer to RSS reta configuration data. 2045 * @param reta_size 2046 * Size of the RETA table. 2047 * 2048 * @return 2049 * 0 on success, negative error value otherwise. 2050 */ 2051 static int hinic_rss_indirtbl_update(struct rte_eth_dev *dev, 2052 struct rte_eth_rss_reta_entry64 *reta_conf, 2053 uint16_t reta_size) 2054 { 2055 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2056 u8 tmpl_idx = nic_dev->rss_tmpl_idx; 2057 u8 prio_tc[HINIC_DCB_UP_MAX] = {0}; 2058 u32 indirtbl[NIC_RSS_INDIR_SIZE] = {0}; 2059 int err = 0; 2060 u16 i = 0; 2061 u16 idx, shift; 2062 2063 if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) 2064 return HINIC_OK; 2065 2066 if (reta_size != NIC_RSS_INDIR_SIZE) { 2067 PMD_DRV_LOG(ERR, "Invalid reta size, reta_size: %d", reta_size); 2068 return HINIC_ERROR; 2069 } 2070 2071 err = hinic_rss_get_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl); 2072 if (err) 2073 return err; 2074 2075 /* update rss indir_tbl */ 2076 for (i = 0; i < reta_size; i++) { 2077 idx = i / RTE_RETA_GROUP_SIZE; 2078 shift = i % RTE_RETA_GROUP_SIZE; 2079 2080 if (reta_conf[idx].reta[shift] >= nic_dev->num_rq) { 2081 PMD_DRV_LOG(ERR, "Invalid reta entry, indirtbl[%d]: %d " 2082 "exceeds the maximum rxq num: %d", i, 2083 reta_conf[idx].reta[shift], nic_dev->num_rq); 2084 return -EINVAL; 2085 } 2086 2087 if (reta_conf[idx].mask & (1ULL << shift)) 2088 indirtbl[i] = reta_conf[idx].reta[shift]; 2089 } 2090 2091 err = hinic_rss_set_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl); 2092 if (err) 2093 goto disable_rss; 2094 2095 nic_dev->rss_indir_flag = true; 2096 2097 return 0; 2098 2099 disable_rss: 2100 memset(prio_tc, 0, sizeof(prio_tc)); 2101 (void)hinic_rss_cfg(nic_dev->hwdev, 0, tmpl_idx, 0, prio_tc); 2102 2103 return HINIC_ERROR; 2104 } 2105 2106 /** 2107 * DPDK callback to get the RSS indirection table. 2108 * 2109 * @param dev 2110 * Pointer to Ethernet device structure. 2111 * @param reta_conf 2112 * Pointer to RSS reta configuration data. 2113 * @param reta_size 2114 * Size of the RETA table. 2115 * 2116 * @return 2117 * 0 on success, negative error value otherwise. 2118 */ 2119 static int hinic_rss_indirtbl_query(struct rte_eth_dev *dev, 2120 struct rte_eth_rss_reta_entry64 *reta_conf, 2121 uint16_t reta_size) 2122 { 2123 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2124 u8 tmpl_idx = nic_dev->rss_tmpl_idx; 2125 int err = 0; 2126 u32 indirtbl[NIC_RSS_INDIR_SIZE] = {0}; 2127 u16 idx, shift; 2128 u16 i = 0; 2129 2130 if (reta_size != NIC_RSS_INDIR_SIZE) { 2131 PMD_DRV_LOG(ERR, "Invalid reta size, reta_size: %d", reta_size); 2132 return HINIC_ERROR; 2133 } 2134 2135 err = hinic_rss_get_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl); 2136 if (err) { 2137 PMD_DRV_LOG(ERR, "Get rss indirect table failed, error: %d", 2138 err); 2139 return err; 2140 } 2141 2142 for (i = 0; i < reta_size; i++) { 2143 idx = i / RTE_RETA_GROUP_SIZE; 2144 shift = i % RTE_RETA_GROUP_SIZE; 2145 if (reta_conf[idx].mask & (1ULL << shift)) 2146 reta_conf[idx].reta[shift] = (uint16_t)indirtbl[i]; 2147 } 2148 2149 return HINIC_OK; 2150 } 2151 2152 /** 2153 * DPDK callback to get extended device statistics. 2154 * 2155 * @param dev 2156 * Pointer to Ethernet device. 2157 * @param xstats 2158 * Pointer to rte extended stats table. 2159 * @param n 2160 * The size of the stats table. 2161 * 2162 * @return 2163 * Number of extended stats on success and stats is filled, 2164 * negative error value otherwise. 2165 */ 2166 static int hinic_dev_xstats_get(struct rte_eth_dev *dev, 2167 struct rte_eth_xstat *xstats, 2168 unsigned int n) 2169 { 2170 u16 qid = 0; 2171 u32 i; 2172 int err, count; 2173 struct hinic_nic_dev *nic_dev; 2174 struct hinic_phy_port_stats port_stats; 2175 struct hinic_vport_stats vport_stats; 2176 struct hinic_rxq *rxq = NULL; 2177 struct hinic_rxq_stats rxq_stats; 2178 struct hinic_txq *txq = NULL; 2179 struct hinic_txq_stats txq_stats; 2180 2181 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2182 count = hinic_xstats_calc_num(nic_dev); 2183 if ((int)n < count) 2184 return count; 2185 2186 count = 0; 2187 2188 /* Get stats from hinic_rxq_stats */ 2189 for (qid = 0; qid < nic_dev->num_rq; qid++) { 2190 rxq = nic_dev->rxqs[qid]; 2191 hinic_rxq_get_stats(rxq, &rxq_stats); 2192 2193 for (i = 0; i < HINIC_RXQ_XSTATS_NUM; i++) { 2194 xstats[count].value = 2195 *(uint64_t *)(((char *)&rxq_stats) + 2196 hinic_rxq_stats_strings[i].offset); 2197 xstats[count].id = count; 2198 count++; 2199 } 2200 } 2201 2202 /* Get stats from hinic_txq_stats */ 2203 for (qid = 0; qid < nic_dev->num_sq; qid++) { 2204 txq = nic_dev->txqs[qid]; 2205 hinic_txq_get_stats(txq, &txq_stats); 2206 2207 for (i = 0; i < HINIC_TXQ_XSTATS_NUM; i++) { 2208 xstats[count].value = 2209 *(uint64_t *)(((char *)&txq_stats) + 2210 hinic_txq_stats_strings[i].offset); 2211 xstats[count].id = count; 2212 count++; 2213 } 2214 } 2215 2216 /* Get stats from hinic_vport_stats */ 2217 err = hinic_get_vport_stats(nic_dev->hwdev, &vport_stats); 2218 if (err) 2219 return err; 2220 2221 for (i = 0; i < HINIC_VPORT_XSTATS_NUM; i++) { 2222 xstats[count].value = 2223 *(uint64_t *)(((char *)&vport_stats) + 2224 hinic_vport_stats_strings[i].offset); 2225 xstats[count].id = count; 2226 count++; 2227 } 2228 2229 if (HINIC_IS_VF(nic_dev->hwdev)) 2230 return count; 2231 2232 /* Get stats from hinic_phy_port_stats */ 2233 err = hinic_get_phy_port_stats(nic_dev->hwdev, &port_stats); 2234 if (err) 2235 return err; 2236 2237 for (i = 0; i < HINIC_PHYPORT_XSTATS_NUM; i++) { 2238 xstats[count].value = *(uint64_t *)(((char *)&port_stats) + 2239 hinic_phyport_stats_strings[i].offset); 2240 xstats[count].id = count; 2241 count++; 2242 } 2243 2244 return count; 2245 } 2246 2247 static void hinic_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2248 struct rte_eth_rxq_info *qinfo) 2249 { 2250 struct hinic_rxq *rxq = dev->data->rx_queues[queue_id]; 2251 2252 qinfo->mp = rxq->mb_pool; 2253 qinfo->nb_desc = rxq->q_depth; 2254 } 2255 2256 static void hinic_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2257 struct rte_eth_txq_info *qinfo) 2258 { 2259 struct hinic_txq *txq = dev->data->tx_queues[queue_id]; 2260 2261 qinfo->nb_desc = txq->q_depth; 2262 } 2263 2264 /** 2265 * DPDK callback to retrieve names of extended device statistics 2266 * 2267 * @param dev 2268 * Pointer to Ethernet device structure. 2269 * @param xstats_names 2270 * Buffer to insert names into. 2271 * 2272 * @return 2273 * Number of xstats names. 2274 */ 2275 static int hinic_dev_xstats_get_names(struct rte_eth_dev *dev, 2276 struct rte_eth_xstat_name *xstats_names, 2277 __rte_unused unsigned int limit) 2278 { 2279 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2280 int count = 0; 2281 u16 i = 0, q_num; 2282 2283 if (xstats_names == NULL) 2284 return hinic_xstats_calc_num(nic_dev); 2285 2286 /* get pmd rxq stats */ 2287 for (q_num = 0; q_num < nic_dev->num_rq; q_num++) { 2288 for (i = 0; i < HINIC_RXQ_XSTATS_NUM; i++) { 2289 snprintf(xstats_names[count].name, 2290 sizeof(xstats_names[count].name), 2291 "rxq%d_%s_pmd", 2292 q_num, hinic_rxq_stats_strings[i].name); 2293 count++; 2294 } 2295 } 2296 2297 /* get pmd txq stats */ 2298 for (q_num = 0; q_num < nic_dev->num_sq; q_num++) { 2299 for (i = 0; i < HINIC_TXQ_XSTATS_NUM; i++) { 2300 snprintf(xstats_names[count].name, 2301 sizeof(xstats_names[count].name), 2302 "txq%d_%s_pmd", 2303 q_num, hinic_txq_stats_strings[i].name); 2304 count++; 2305 } 2306 } 2307 2308 /* get vport stats */ 2309 for (i = 0; i < HINIC_VPORT_XSTATS_NUM; i++) { 2310 snprintf(xstats_names[count].name, 2311 sizeof(xstats_names[count].name), 2312 "%s", hinic_vport_stats_strings[i].name); 2313 count++; 2314 } 2315 2316 if (HINIC_IS_VF(nic_dev->hwdev)) 2317 return count; 2318 2319 /* get phy port stats */ 2320 for (i = 0; i < HINIC_PHYPORT_XSTATS_NUM; i++) { 2321 snprintf(xstats_names[count].name, 2322 sizeof(xstats_names[count].name), 2323 "%s", hinic_phyport_stats_strings[i].name); 2324 count++; 2325 } 2326 2327 return count; 2328 } 2329 2330 /** 2331 * DPDK callback to set mac address 2332 * 2333 * @param dev 2334 * Pointer to Ethernet device structure. 2335 * @param addr 2336 * Pointer to mac address 2337 * @return 2338 * 0 on success, negative error value otherwise. 2339 */ 2340 static int hinic_set_mac_addr(struct rte_eth_dev *dev, 2341 struct rte_ether_addr *addr) 2342 { 2343 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2344 u16 func_id; 2345 int err; 2346 2347 func_id = hinic_global_func_id(nic_dev->hwdev); 2348 err = hinic_update_mac(nic_dev->hwdev, nic_dev->default_addr.addr_bytes, 2349 addr->addr_bytes, 0, func_id); 2350 if (err) 2351 return err; 2352 2353 rte_ether_addr_copy(addr, &nic_dev->default_addr); 2354 2355 PMD_DRV_LOG(INFO, "Set new mac address %02x:%02x:%02x:%02x:%02x:%02x", 2356 addr->addr_bytes[0], addr->addr_bytes[1], 2357 addr->addr_bytes[2], addr->addr_bytes[3], 2358 addr->addr_bytes[4], addr->addr_bytes[5]); 2359 2360 return 0; 2361 } 2362 2363 /** 2364 * DPDK callback to remove a MAC address. 2365 * 2366 * @param dev 2367 * Pointer to Ethernet device structure. 2368 * @param index 2369 * MAC address index, should less than 128. 2370 */ 2371 static void hinic_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2372 { 2373 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2374 u16 func_id; 2375 int ret; 2376 2377 if (index >= HINIC_MAX_UC_MAC_ADDRS) { 2378 PMD_DRV_LOG(INFO, "Remove mac index(%u) is out of range", 2379 index); 2380 return; 2381 } 2382 2383 func_id = hinic_global_func_id(nic_dev->hwdev); 2384 ret = hinic_del_mac(nic_dev->hwdev, 2385 dev->data->mac_addrs[index].addr_bytes, 0, func_id); 2386 if (ret) 2387 return; 2388 2389 memset(&dev->data->mac_addrs[index], 0, sizeof(struct rte_ether_addr)); 2390 } 2391 2392 /** 2393 * DPDK callback to add a MAC address. 2394 * 2395 * @param dev 2396 * Pointer to Ethernet device structure. 2397 * @param mac_addr 2398 * Pointer to MAC address 2399 * @param index 2400 * MAC address index, should less than 128. 2401 * @param vmdq 2402 * VMDq pool index(not used). 2403 * 2404 * @return 2405 * 0 on success, negative error value otherwise. 2406 */ 2407 static int hinic_mac_addr_add(struct rte_eth_dev *dev, 2408 struct rte_ether_addr *mac_addr, uint32_t index, 2409 __rte_unused uint32_t vmdq) 2410 { 2411 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2412 unsigned int i; 2413 u16 func_id; 2414 int ret; 2415 2416 if (index >= HINIC_MAX_UC_MAC_ADDRS) { 2417 PMD_DRV_LOG(INFO, "Add mac index(%u) is out of range", index); 2418 return -EINVAL; 2419 } 2420 2421 /* First, make sure this address isn't already configured. */ 2422 for (i = 0; (i != HINIC_MAX_UC_MAC_ADDRS); ++i) { 2423 /* Skip this index, it's going to be reconfigured. */ 2424 if (i == index) 2425 continue; 2426 2427 if (memcmp(&dev->data->mac_addrs[i], 2428 mac_addr, sizeof(*mac_addr))) 2429 continue; 2430 2431 PMD_DRV_LOG(INFO, "MAC address already configured"); 2432 return -EADDRINUSE; 2433 } 2434 2435 func_id = hinic_global_func_id(nic_dev->hwdev); 2436 ret = hinic_set_mac(nic_dev->hwdev, mac_addr->addr_bytes, 0, func_id); 2437 if (ret) 2438 return ret; 2439 2440 dev->data->mac_addrs[index] = *mac_addr; 2441 return 0; 2442 } 2443 2444 /** 2445 * DPDK callback to set multicast mac address 2446 * 2447 * @param dev 2448 * Pointer to Ethernet device structure. 2449 * @param mc_addr_set 2450 * Pointer to multicast mac address 2451 * @param nb_mc_addr 2452 * mc addr count 2453 * @return 2454 * 0 on success, negative error value otherwise. 2455 */ 2456 static int hinic_set_mc_addr_list(struct rte_eth_dev *dev, 2457 struct rte_ether_addr *mc_addr_set, 2458 uint32_t nb_mc_addr) 2459 { 2460 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2461 u16 func_id; 2462 int ret; 2463 u32 i; 2464 2465 func_id = hinic_global_func_id(nic_dev->hwdev); 2466 2467 /* delete old multi_cast addrs firstly */ 2468 hinic_delete_mc_addr_list(nic_dev); 2469 2470 if (nb_mc_addr > HINIC_MAX_MC_MAC_ADDRS) 2471 goto allmulti; 2472 2473 for (i = 0; i < nb_mc_addr; i++) { 2474 ret = hinic_set_mac(nic_dev->hwdev, mc_addr_set[i].addr_bytes, 2475 0, func_id); 2476 /* if add mc addr failed, set all multi_cast */ 2477 if (ret) { 2478 hinic_delete_mc_addr_list(nic_dev); 2479 goto allmulti; 2480 } 2481 2482 rte_ether_addr_copy(&mc_addr_set[i], &nic_dev->mc_list[i]); 2483 } 2484 2485 return 0; 2486 2487 allmulti: 2488 hinic_dev_allmulticast_enable(dev); 2489 2490 return 0; 2491 } 2492 2493 /** 2494 * DPDK callback to manage filter control operations 2495 * 2496 * @param dev 2497 * Pointer to Ethernet device structure. 2498 * @param filter_type 2499 * Filter type, which just supports generic type. 2500 * @param filter_op 2501 * Filter operation to perform. 2502 * @param arg 2503 * Pointer to operation-specific structure. 2504 * 2505 * @return 2506 * 0 on success, negative error value otherwise. 2507 */ 2508 static int hinic_dev_filter_ctrl(struct rte_eth_dev *dev, 2509 enum rte_filter_type filter_type, 2510 enum rte_filter_op filter_op, 2511 void *arg) 2512 { 2513 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2514 int func_id = hinic_global_func_id(nic_dev->hwdev); 2515 2516 switch (filter_type) { 2517 case RTE_ETH_FILTER_GENERIC: 2518 if (filter_op != RTE_ETH_FILTER_GET) 2519 return -EINVAL; 2520 *(const void **)arg = &hinic_flow_ops; 2521 break; 2522 default: 2523 PMD_DRV_LOG(INFO, "Filter type (%d) not supported", 2524 filter_type); 2525 return -EINVAL; 2526 } 2527 2528 PMD_DRV_LOG(INFO, "Set filter_ctrl succeed, func_id: 0x%x, filter_type: 0x%x," 2529 "filter_op: 0x%x.", func_id, filter_type, filter_op); 2530 return 0; 2531 } 2532 2533 static int hinic_set_default_pause_feature(struct hinic_nic_dev *nic_dev) 2534 { 2535 struct nic_pause_config pause_config = {0}; 2536 int err; 2537 2538 pause_config.auto_neg = 0; 2539 pause_config.rx_pause = HINIC_DEFAUT_PAUSE_CONFIG; 2540 pause_config.tx_pause = HINIC_DEFAUT_PAUSE_CONFIG; 2541 2542 err = hinic_set_pause_config(nic_dev->hwdev, pause_config); 2543 if (err) 2544 return err; 2545 2546 nic_dev->pause_set = true; 2547 nic_dev->nic_pause.auto_neg = pause_config.auto_neg; 2548 nic_dev->nic_pause.rx_pause = pause_config.rx_pause; 2549 nic_dev->nic_pause.tx_pause = pause_config.tx_pause; 2550 2551 return 0; 2552 } 2553 2554 static int hinic_set_default_dcb_feature(struct hinic_nic_dev *nic_dev) 2555 { 2556 u8 up_tc[HINIC_DCB_UP_MAX] = {0}; 2557 u8 up_pgid[HINIC_DCB_UP_MAX] = {0}; 2558 u8 up_bw[HINIC_DCB_UP_MAX] = {0}; 2559 u8 pg_bw[HINIC_DCB_UP_MAX] = {0}; 2560 u8 up_strict[HINIC_DCB_UP_MAX] = {0}; 2561 int i = 0; 2562 2563 pg_bw[0] = 100; 2564 for (i = 0; i < HINIC_DCB_UP_MAX; i++) 2565 up_bw[i] = 100; 2566 2567 return hinic_dcb_set_ets(nic_dev->hwdev, up_tc, pg_bw, 2568 up_pgid, up_bw, up_strict); 2569 } 2570 2571 static int hinic_init_default_cos(struct hinic_nic_dev *nic_dev) 2572 { 2573 u8 cos_id = 0; 2574 int err; 2575 2576 if (!HINIC_IS_VF(nic_dev->hwdev)) { 2577 nic_dev->default_cos = 2578 (hinic_global_func_id(nic_dev->hwdev) + 2579 DEFAULT_BASE_COS) % NR_MAX_COS; 2580 } else { 2581 err = hinic_vf_get_default_cos(nic_dev->hwdev, &cos_id); 2582 if (err) { 2583 PMD_DRV_LOG(ERR, "Get VF default cos failed, err: %d", 2584 err); 2585 return HINIC_ERROR; 2586 } 2587 2588 nic_dev->default_cos = cos_id; 2589 } 2590 2591 return 0; 2592 } 2593 2594 static int hinic_set_default_hw_feature(struct hinic_nic_dev *nic_dev) 2595 { 2596 int err; 2597 2598 err = hinic_init_default_cos(nic_dev); 2599 if (err) 2600 return err; 2601 2602 if (hinic_func_type(nic_dev->hwdev) == TYPE_VF) 2603 return 0; 2604 2605 /* Restore DCB configure to default status */ 2606 err = hinic_set_default_dcb_feature(nic_dev); 2607 if (err) 2608 return err; 2609 2610 /* Set pause enable, and up will disable pfc. */ 2611 err = hinic_set_default_pause_feature(nic_dev); 2612 if (err) 2613 return err; 2614 2615 err = hinic_reset_port_link_cfg(nic_dev->hwdev); 2616 if (err) 2617 return err; 2618 2619 err = hinic_set_link_status_follow(nic_dev->hwdev, 2620 HINIC_LINK_FOLLOW_PORT); 2621 if (err == HINIC_MGMT_CMD_UNSUPPORTED) 2622 PMD_DRV_LOG(WARNING, "Don't support to set link status follow phy port status"); 2623 else if (err) 2624 return err; 2625 2626 return hinic_set_anti_attack(nic_dev->hwdev, true); 2627 } 2628 2629 static int32_t hinic_card_workmode_check(struct hinic_nic_dev *nic_dev) 2630 { 2631 struct hinic_board_info info = { 0 }; 2632 int rc; 2633 2634 if (hinic_func_type(nic_dev->hwdev) == TYPE_VF) 2635 return 0; 2636 2637 rc = hinic_get_board_info(nic_dev->hwdev, &info); 2638 if (rc) 2639 return rc; 2640 2641 return (info.service_mode == HINIC_SERVICE_MODE_NIC ? HINIC_OK : 2642 HINIC_ERROR); 2643 } 2644 2645 static int hinic_copy_mempool_init(struct hinic_nic_dev *nic_dev) 2646 { 2647 nic_dev->cpy_mpool = rte_mempool_lookup(nic_dev->proc_dev_name); 2648 if (nic_dev->cpy_mpool == NULL) { 2649 nic_dev->cpy_mpool = 2650 rte_pktmbuf_pool_create(nic_dev->proc_dev_name, 2651 HINIC_COPY_MEMPOOL_DEPTH, 2652 0, 0, 2653 HINIC_COPY_MBUF_SIZE, 2654 rte_socket_id()); 2655 if (!nic_dev->cpy_mpool) { 2656 PMD_DRV_LOG(ERR, "Create copy mempool failed, errno: %d, dev_name: %s", 2657 rte_errno, nic_dev->proc_dev_name); 2658 return -ENOMEM; 2659 } 2660 } 2661 2662 return 0; 2663 } 2664 2665 static void hinic_copy_mempool_uninit(struct hinic_nic_dev *nic_dev) 2666 { 2667 if (nic_dev->cpy_mpool != NULL) 2668 rte_mempool_free(nic_dev->cpy_mpool); 2669 } 2670 2671 static int hinic_init_sw_rxtxqs(struct hinic_nic_dev *nic_dev) 2672 { 2673 u32 txq_size; 2674 u32 rxq_size; 2675 2676 /* allocate software txq array */ 2677 txq_size = nic_dev->nic_cap.max_sqs * sizeof(*nic_dev->txqs); 2678 nic_dev->txqs = kzalloc_aligned(txq_size, GFP_KERNEL); 2679 if (!nic_dev->txqs) { 2680 PMD_DRV_LOG(ERR, "Allocate txqs failed"); 2681 return -ENOMEM; 2682 } 2683 2684 /* allocate software rxq array */ 2685 rxq_size = nic_dev->nic_cap.max_rqs * sizeof(*nic_dev->rxqs); 2686 nic_dev->rxqs = kzalloc_aligned(rxq_size, GFP_KERNEL); 2687 if (!nic_dev->rxqs) { 2688 /* free txqs */ 2689 kfree(nic_dev->txqs); 2690 nic_dev->txqs = NULL; 2691 2692 PMD_DRV_LOG(ERR, "Allocate rxqs failed"); 2693 return -ENOMEM; 2694 } 2695 2696 return HINIC_OK; 2697 } 2698 2699 static void hinic_deinit_sw_rxtxqs(struct hinic_nic_dev *nic_dev) 2700 { 2701 kfree(nic_dev->txqs); 2702 nic_dev->txqs = NULL; 2703 2704 kfree(nic_dev->rxqs); 2705 nic_dev->rxqs = NULL; 2706 } 2707 2708 static int hinic_nic_dev_create(struct rte_eth_dev *eth_dev) 2709 { 2710 struct hinic_nic_dev *nic_dev = 2711 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); 2712 int rc; 2713 2714 nic_dev->hwdev = rte_zmalloc("hinic_hwdev", sizeof(*nic_dev->hwdev), 2715 RTE_CACHE_LINE_SIZE); 2716 if (!nic_dev->hwdev) { 2717 PMD_DRV_LOG(ERR, "Allocate hinic hwdev memory failed, dev_name: %s", 2718 eth_dev->data->name); 2719 return -ENOMEM; 2720 } 2721 nic_dev->hwdev->pcidev_hdl = RTE_ETH_DEV_TO_PCI(eth_dev); 2722 2723 /* init osdep*/ 2724 rc = hinic_osdep_init(nic_dev->hwdev); 2725 if (rc) { 2726 PMD_DRV_LOG(ERR, "Initialize os_dep failed, dev_name: %s", 2727 eth_dev->data->name); 2728 goto init_osdep_fail; 2729 } 2730 2731 /* init_hwif */ 2732 rc = hinic_hwif_res_init(nic_dev->hwdev); 2733 if (rc) { 2734 PMD_DRV_LOG(ERR, "Initialize hwif failed, dev_name: %s", 2735 eth_dev->data->name); 2736 goto init_hwif_fail; 2737 } 2738 2739 /* init_cfg_mgmt */ 2740 rc = init_cfg_mgmt(nic_dev->hwdev); 2741 if (rc) { 2742 PMD_DRV_LOG(ERR, "Initialize cfg_mgmt failed, dev_name: %s", 2743 eth_dev->data->name); 2744 goto init_cfgmgnt_fail; 2745 } 2746 2747 /* init_aeqs */ 2748 rc = hinic_comm_aeqs_init(nic_dev->hwdev); 2749 if (rc) { 2750 PMD_DRV_LOG(ERR, "Initialize aeqs failed, dev_name: %s", 2751 eth_dev->data->name); 2752 goto init_aeqs_fail; 2753 } 2754 2755 /* init_pf_to_mgnt */ 2756 rc = hinic_comm_pf_to_mgmt_init(nic_dev->hwdev); 2757 if (rc) { 2758 PMD_DRV_LOG(ERR, "Initialize pf_to_mgmt failed, dev_name: %s", 2759 eth_dev->data->name); 2760 goto init_pf_to_mgmt_fail; 2761 } 2762 2763 /* init mailbox */ 2764 rc = hinic_comm_func_to_func_init(nic_dev->hwdev); 2765 if (rc) { 2766 PMD_DRV_LOG(ERR, "Initialize func_to_func failed, dev_name: %s", 2767 eth_dev->data->name); 2768 goto init_func_to_func_fail; 2769 } 2770 2771 rc = hinic_card_workmode_check(nic_dev); 2772 if (rc) { 2773 PMD_DRV_LOG(ERR, "Check card workmode failed, dev_name: %s", 2774 eth_dev->data->name); 2775 goto workmode_check_fail; 2776 } 2777 2778 /* do l2nic reset to make chip clear */ 2779 rc = hinic_l2nic_reset(nic_dev->hwdev); 2780 if (rc) { 2781 PMD_DRV_LOG(ERR, "Do l2nic reset failed, dev_name: %s", 2782 eth_dev->data->name); 2783 goto l2nic_reset_fail; 2784 } 2785 2786 /* init dma and aeq msix attribute table */ 2787 (void)hinic_init_attr_table(nic_dev->hwdev); 2788 2789 /* init_cmdqs */ 2790 rc = hinic_comm_cmdqs_init(nic_dev->hwdev); 2791 if (rc) { 2792 PMD_DRV_LOG(ERR, "Initialize cmdq failed, dev_name: %s", 2793 eth_dev->data->name); 2794 goto init_cmdq_fail; 2795 } 2796 2797 /* set hardware state active */ 2798 rc = hinic_activate_hwdev_state(nic_dev->hwdev); 2799 if (rc) { 2800 PMD_DRV_LOG(ERR, "Initialize resources state failed, dev_name: %s", 2801 eth_dev->data->name); 2802 goto init_resources_state_fail; 2803 } 2804 2805 /* init_capability */ 2806 rc = hinic_init_capability(nic_dev->hwdev); 2807 if (rc) { 2808 PMD_DRV_LOG(ERR, "Initialize capability failed, dev_name: %s", 2809 eth_dev->data->name); 2810 goto init_cap_fail; 2811 } 2812 2813 /* get nic capability */ 2814 if (!hinic_support_nic(nic_dev->hwdev, &nic_dev->nic_cap)) { 2815 PMD_DRV_LOG(ERR, "Hw doesn't support nic, dev_name: %s", 2816 eth_dev->data->name); 2817 rc = -EINVAL; 2818 goto nic_check_fail; 2819 } 2820 2821 /* init root cla and function table */ 2822 rc = hinic_init_nicio(nic_dev->hwdev); 2823 if (rc) { 2824 PMD_DRV_LOG(ERR, "Initialize nic_io failed, dev_name: %s", 2825 eth_dev->data->name); 2826 goto init_nicio_fail; 2827 } 2828 2829 /* init_software_txrxq */ 2830 rc = hinic_init_sw_rxtxqs(nic_dev); 2831 if (rc) { 2832 PMD_DRV_LOG(ERR, "Initialize sw_rxtxqs failed, dev_name: %s", 2833 eth_dev->data->name); 2834 goto init_sw_rxtxqs_fail; 2835 } 2836 2837 rc = hinic_copy_mempool_init(nic_dev); 2838 if (rc) { 2839 PMD_DRV_LOG(ERR, "Create copy mempool failed, dev_name: %s", 2840 eth_dev->data->name); 2841 goto init_mpool_fail; 2842 } 2843 2844 /* set hardware feature to default status */ 2845 rc = hinic_set_default_hw_feature(nic_dev); 2846 if (rc) { 2847 PMD_DRV_LOG(ERR, "Initialize hardware default features failed, dev_name: %s", 2848 eth_dev->data->name); 2849 goto set_default_hw_feature_fail; 2850 } 2851 2852 return 0; 2853 2854 set_default_hw_feature_fail: 2855 hinic_copy_mempool_uninit(nic_dev); 2856 2857 init_mpool_fail: 2858 hinic_deinit_sw_rxtxqs(nic_dev); 2859 2860 init_sw_rxtxqs_fail: 2861 hinic_deinit_nicio(nic_dev->hwdev); 2862 2863 nic_check_fail: 2864 init_nicio_fail: 2865 init_cap_fail: 2866 hinic_deactivate_hwdev_state(nic_dev->hwdev); 2867 2868 init_resources_state_fail: 2869 hinic_comm_cmdqs_free(nic_dev->hwdev); 2870 2871 init_cmdq_fail: 2872 l2nic_reset_fail: 2873 workmode_check_fail: 2874 hinic_comm_func_to_func_free(nic_dev->hwdev); 2875 2876 init_func_to_func_fail: 2877 hinic_comm_pf_to_mgmt_free(nic_dev->hwdev); 2878 2879 init_pf_to_mgmt_fail: 2880 hinic_comm_aeqs_free(nic_dev->hwdev); 2881 2882 init_aeqs_fail: 2883 free_cfg_mgmt(nic_dev->hwdev); 2884 2885 init_cfgmgnt_fail: 2886 hinic_hwif_res_free(nic_dev->hwdev); 2887 2888 init_hwif_fail: 2889 hinic_osdep_deinit(nic_dev->hwdev); 2890 2891 init_osdep_fail: 2892 rte_free(nic_dev->hwdev); 2893 nic_dev->hwdev = NULL; 2894 2895 return rc; 2896 } 2897 2898 static void hinic_nic_dev_destroy(struct rte_eth_dev *eth_dev) 2899 { 2900 struct hinic_nic_dev *nic_dev = 2901 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); 2902 2903 (void)hinic_set_link_status_follow(nic_dev->hwdev, 2904 HINIC_LINK_FOLLOW_DEFAULT); 2905 hinic_copy_mempool_uninit(nic_dev); 2906 hinic_deinit_sw_rxtxqs(nic_dev); 2907 hinic_deinit_nicio(nic_dev->hwdev); 2908 hinic_deactivate_hwdev_state(nic_dev->hwdev); 2909 hinic_comm_cmdqs_free(nic_dev->hwdev); 2910 hinic_comm_func_to_func_free(nic_dev->hwdev); 2911 hinic_comm_pf_to_mgmt_free(nic_dev->hwdev); 2912 hinic_comm_aeqs_free(nic_dev->hwdev); 2913 free_cfg_mgmt(nic_dev->hwdev); 2914 hinic_hwif_res_free(nic_dev->hwdev); 2915 hinic_osdep_deinit(nic_dev->hwdev); 2916 rte_free(nic_dev->hwdev); 2917 nic_dev->hwdev = NULL; 2918 } 2919 2920 /** 2921 * DPDK callback to close the device. 2922 * 2923 * @param dev 2924 * Pointer to Ethernet device structure. 2925 */ 2926 static void hinic_dev_close(struct rte_eth_dev *dev) 2927 { 2928 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2929 2930 if (rte_bit_relaxed_test_and_set32(HINIC_DEV_CLOSE, 2931 &nic_dev->dev_status)) { 2932 PMD_DRV_LOG(WARNING, "Device %s already closed", 2933 dev->data->name); 2934 return; 2935 } 2936 2937 /* stop device first */ 2938 hinic_dev_stop(dev); 2939 2940 /* rx_cqe, rx_info */ 2941 hinic_free_all_rx_resources(dev); 2942 2943 /* tx_info */ 2944 hinic_free_all_tx_resources(dev); 2945 2946 /* free wq, pi_dma_addr */ 2947 hinic_free_all_rq(nic_dev); 2948 2949 /* free wq, db_addr */ 2950 hinic_free_all_sq(nic_dev); 2951 2952 /* deinit mac vlan tbl */ 2953 hinic_deinit_mac_addr(dev); 2954 hinic_remove_all_vlanid(dev); 2955 2956 /* disable hardware and uio interrupt */ 2957 hinic_disable_interrupt(dev); 2958 2959 /* deinit nic hardware device */ 2960 hinic_nic_dev_destroy(dev); 2961 } 2962 2963 static const struct eth_dev_ops hinic_pmd_ops = { 2964 .dev_configure = hinic_dev_configure, 2965 .dev_infos_get = hinic_dev_infos_get, 2966 .fw_version_get = hinic_fw_version_get, 2967 .rx_queue_setup = hinic_rx_queue_setup, 2968 .tx_queue_setup = hinic_tx_queue_setup, 2969 .dev_start = hinic_dev_start, 2970 .dev_set_link_up = hinic_dev_set_link_up, 2971 .dev_set_link_down = hinic_dev_set_link_down, 2972 .link_update = hinic_link_update, 2973 .rx_queue_release = hinic_rx_queue_release, 2974 .tx_queue_release = hinic_tx_queue_release, 2975 .dev_stop = hinic_dev_stop, 2976 .dev_close = hinic_dev_close, 2977 .mtu_set = hinic_dev_set_mtu, 2978 .vlan_filter_set = hinic_vlan_filter_set, 2979 .vlan_offload_set = hinic_vlan_offload_set, 2980 .allmulticast_enable = hinic_dev_allmulticast_enable, 2981 .allmulticast_disable = hinic_dev_allmulticast_disable, 2982 .promiscuous_enable = hinic_dev_promiscuous_enable, 2983 .promiscuous_disable = hinic_dev_promiscuous_disable, 2984 .flow_ctrl_get = hinic_flow_ctrl_get, 2985 .flow_ctrl_set = hinic_flow_ctrl_set, 2986 .rss_hash_update = hinic_rss_hash_update, 2987 .rss_hash_conf_get = hinic_rss_conf_get, 2988 .reta_update = hinic_rss_indirtbl_update, 2989 .reta_query = hinic_rss_indirtbl_query, 2990 .stats_get = hinic_dev_stats_get, 2991 .stats_reset = hinic_dev_stats_reset, 2992 .xstats_get = hinic_dev_xstats_get, 2993 .xstats_reset = hinic_dev_xstats_reset, 2994 .xstats_get_names = hinic_dev_xstats_get_names, 2995 .rxq_info_get = hinic_rxq_info_get, 2996 .txq_info_get = hinic_txq_info_get, 2997 .mac_addr_set = hinic_set_mac_addr, 2998 .mac_addr_remove = hinic_mac_addr_remove, 2999 .mac_addr_add = hinic_mac_addr_add, 3000 .set_mc_addr_list = hinic_set_mc_addr_list, 3001 .filter_ctrl = hinic_dev_filter_ctrl, 3002 }; 3003 3004 static const struct eth_dev_ops hinic_pmd_vf_ops = { 3005 .dev_configure = hinic_dev_configure, 3006 .dev_infos_get = hinic_dev_infos_get, 3007 .fw_version_get = hinic_fw_version_get, 3008 .rx_queue_setup = hinic_rx_queue_setup, 3009 .tx_queue_setup = hinic_tx_queue_setup, 3010 .dev_start = hinic_dev_start, 3011 .link_update = hinic_link_update, 3012 .rx_queue_release = hinic_rx_queue_release, 3013 .tx_queue_release = hinic_tx_queue_release, 3014 .dev_stop = hinic_dev_stop, 3015 .dev_close = hinic_dev_close, 3016 .mtu_set = hinic_dev_set_mtu, 3017 .vlan_filter_set = hinic_vlan_filter_set, 3018 .vlan_offload_set = hinic_vlan_offload_set, 3019 .allmulticast_enable = hinic_dev_allmulticast_enable, 3020 .allmulticast_disable = hinic_dev_allmulticast_disable, 3021 .rss_hash_update = hinic_rss_hash_update, 3022 .rss_hash_conf_get = hinic_rss_conf_get, 3023 .reta_update = hinic_rss_indirtbl_update, 3024 .reta_query = hinic_rss_indirtbl_query, 3025 .stats_get = hinic_dev_stats_get, 3026 .stats_reset = hinic_dev_stats_reset, 3027 .xstats_get = hinic_dev_xstats_get, 3028 .xstats_reset = hinic_dev_xstats_reset, 3029 .xstats_get_names = hinic_dev_xstats_get_names, 3030 .rxq_info_get = hinic_rxq_info_get, 3031 .txq_info_get = hinic_txq_info_get, 3032 .mac_addr_set = hinic_set_mac_addr, 3033 .mac_addr_remove = hinic_mac_addr_remove, 3034 .mac_addr_add = hinic_mac_addr_add, 3035 .set_mc_addr_list = hinic_set_mc_addr_list, 3036 .filter_ctrl = hinic_dev_filter_ctrl, 3037 }; 3038 3039 static int hinic_func_init(struct rte_eth_dev *eth_dev) 3040 { 3041 struct rte_pci_device *pci_dev; 3042 struct rte_ether_addr *eth_addr; 3043 struct hinic_nic_dev *nic_dev; 3044 struct hinic_filter_info *filter_info; 3045 struct hinic_tcam_info *tcam_info; 3046 u32 mac_size; 3047 int rc; 3048 3049 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3050 3051 /* EAL is SECONDARY and eth_dev is already created */ 3052 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 3053 PMD_DRV_LOG(INFO, "Initialize %s in secondary process", 3054 eth_dev->data->name); 3055 3056 return 0; 3057 } 3058 3059 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); 3060 memset(nic_dev, 0, sizeof(*nic_dev)); 3061 3062 snprintf(nic_dev->proc_dev_name, 3063 sizeof(nic_dev->proc_dev_name), 3064 "hinic-%.4x:%.2x:%.2x.%x", 3065 pci_dev->addr.domain, pci_dev->addr.bus, 3066 pci_dev->addr.devid, pci_dev->addr.function); 3067 3068 /* alloc mac_addrs */ 3069 mac_size = HINIC_MAX_UC_MAC_ADDRS * sizeof(struct rte_ether_addr); 3070 eth_addr = rte_zmalloc("hinic_mac", mac_size, 0); 3071 if (!eth_addr) { 3072 PMD_DRV_LOG(ERR, "Allocate ethernet addresses' memory failed, dev_name: %s", 3073 eth_dev->data->name); 3074 rc = -ENOMEM; 3075 goto eth_addr_fail; 3076 } 3077 eth_dev->data->mac_addrs = eth_addr; 3078 3079 mac_size = HINIC_MAX_MC_MAC_ADDRS * sizeof(struct rte_ether_addr); 3080 nic_dev->mc_list = rte_zmalloc("hinic_mc", mac_size, 0); 3081 if (!nic_dev->mc_list) { 3082 PMD_DRV_LOG(ERR, "Allocate mcast address' memory failed, dev_name: %s", 3083 eth_dev->data->name); 3084 rc = -ENOMEM; 3085 goto mc_addr_fail; 3086 } 3087 3088 /* 3089 * Pass the information to the rte_eth_dev_close() that it should also 3090 * release the private port resources. 3091 */ 3092 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 3093 3094 /* create hardware nic_device */ 3095 rc = hinic_nic_dev_create(eth_dev); 3096 if (rc) { 3097 PMD_DRV_LOG(ERR, "Create nic device failed, dev_name: %s", 3098 eth_dev->data->name); 3099 goto create_nic_dev_fail; 3100 } 3101 3102 if (HINIC_IS_VF(nic_dev->hwdev)) 3103 eth_dev->dev_ops = &hinic_pmd_vf_ops; 3104 else 3105 eth_dev->dev_ops = &hinic_pmd_ops; 3106 3107 rc = hinic_init_mac_addr(eth_dev); 3108 if (rc) { 3109 PMD_DRV_LOG(ERR, "Initialize mac table failed, dev_name: %s", 3110 eth_dev->data->name); 3111 goto init_mac_fail; 3112 } 3113 3114 /* register callback func to eal lib */ 3115 rc = rte_intr_callback_register(&pci_dev->intr_handle, 3116 hinic_dev_interrupt_handler, 3117 (void *)eth_dev); 3118 if (rc) { 3119 PMD_DRV_LOG(ERR, "Register rte interrupt callback failed, dev_name: %s", 3120 eth_dev->data->name); 3121 goto reg_intr_cb_fail; 3122 } 3123 3124 /* enable uio/vfio intr/eventfd mapping */ 3125 rc = rte_intr_enable(&pci_dev->intr_handle); 3126 if (rc) { 3127 PMD_DRV_LOG(ERR, "Enable rte interrupt failed, dev_name: %s", 3128 eth_dev->data->name); 3129 goto enable_intr_fail; 3130 } 3131 rte_bit_relaxed_set32(HINIC_DEV_INTR_EN, &nic_dev->dev_status); 3132 3133 /* initialize filter info */ 3134 filter_info = &nic_dev->filter; 3135 tcam_info = &nic_dev->tcam; 3136 memset(filter_info, 0, sizeof(struct hinic_filter_info)); 3137 memset(tcam_info, 0, sizeof(struct hinic_tcam_info)); 3138 /* initialize 5tuple filter list */ 3139 TAILQ_INIT(&filter_info->fivetuple_list); 3140 TAILQ_INIT(&tcam_info->tcam_list); 3141 TAILQ_INIT(&nic_dev->filter_ntuple_list); 3142 TAILQ_INIT(&nic_dev->filter_ethertype_list); 3143 TAILQ_INIT(&nic_dev->filter_fdir_rule_list); 3144 TAILQ_INIT(&nic_dev->hinic_flow_list); 3145 3146 rte_bit_relaxed_set32(HINIC_DEV_INIT, &nic_dev->dev_status); 3147 PMD_DRV_LOG(INFO, "Initialize %s in primary successfully", 3148 eth_dev->data->name); 3149 3150 return 0; 3151 3152 enable_intr_fail: 3153 (void)rte_intr_callback_unregister(&pci_dev->intr_handle, 3154 hinic_dev_interrupt_handler, 3155 (void *)eth_dev); 3156 3157 reg_intr_cb_fail: 3158 hinic_deinit_mac_addr(eth_dev); 3159 3160 init_mac_fail: 3161 eth_dev->dev_ops = NULL; 3162 hinic_nic_dev_destroy(eth_dev); 3163 3164 create_nic_dev_fail: 3165 rte_free(nic_dev->mc_list); 3166 nic_dev->mc_list = NULL; 3167 3168 mc_addr_fail: 3169 rte_free(eth_addr); 3170 eth_dev->data->mac_addrs = NULL; 3171 3172 eth_addr_fail: 3173 PMD_DRV_LOG(ERR, "Initialize %s in primary failed", 3174 eth_dev->data->name); 3175 return rc; 3176 } 3177 3178 static int hinic_dev_init(struct rte_eth_dev *eth_dev) 3179 { 3180 struct rte_pci_device *pci_dev; 3181 3182 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3183 3184 PMD_DRV_LOG(INFO, "Initializing pf hinic-%.4x:%.2x:%.2x.%x in %s process", 3185 pci_dev->addr.domain, pci_dev->addr.bus, 3186 pci_dev->addr.devid, pci_dev->addr.function, 3187 (rte_eal_process_type() == RTE_PROC_PRIMARY) ? 3188 "primary" : "secondary"); 3189 3190 /* rte_eth_dev rx_burst and tx_burst */ 3191 eth_dev->rx_pkt_burst = hinic_recv_pkts; 3192 eth_dev->tx_pkt_burst = hinic_xmit_pkts; 3193 3194 return hinic_func_init(eth_dev); 3195 } 3196 3197 static int hinic_dev_uninit(struct rte_eth_dev *dev) 3198 { 3199 struct hinic_nic_dev *nic_dev; 3200 3201 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 3202 rte_bit_relaxed_clear32(HINIC_DEV_INIT, &nic_dev->dev_status); 3203 3204 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3205 return 0; 3206 3207 hinic_dev_close(dev); 3208 3209 dev->dev_ops = NULL; 3210 dev->rx_pkt_burst = NULL; 3211 dev->tx_pkt_burst = NULL; 3212 3213 rte_free(nic_dev->mc_list); 3214 3215 rte_free(dev->data->mac_addrs); 3216 dev->data->mac_addrs = NULL; 3217 3218 return HINIC_OK; 3219 } 3220 3221 static struct rte_pci_id pci_id_hinic_map[] = { 3222 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_PRD) }, 3223 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_25GE) }, 3224 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_100GE) }, 3225 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_VF) }, 3226 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_VF_HV) }, 3227 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_1822_DUAL_25GE) }, 3228 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_1822_100GE) }, 3229 {.vendor_id = 0}, 3230 }; 3231 3232 static int hinic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3233 struct rte_pci_device *pci_dev) 3234 { 3235 return rte_eth_dev_pci_generic_probe(pci_dev, 3236 sizeof(struct hinic_nic_dev), hinic_dev_init); 3237 } 3238 3239 static int hinic_pci_remove(struct rte_pci_device *pci_dev) 3240 { 3241 return rte_eth_dev_pci_generic_remove(pci_dev, hinic_dev_uninit); 3242 } 3243 3244 static struct rte_pci_driver rte_hinic_pmd = { 3245 .id_table = pci_id_hinic_map, 3246 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 3247 .probe = hinic_pci_probe, 3248 .remove = hinic_pci_remove, 3249 }; 3250 3251 RTE_PMD_REGISTER_PCI(net_hinic, rte_hinic_pmd); 3252 RTE_PMD_REGISTER_PCI_TABLE(net_hinic, pci_id_hinic_map); 3253 3254 RTE_INIT(hinic_init_log) 3255 { 3256 hinic_logtype = rte_log_register("pmd.net.hinic"); 3257 if (hinic_logtype >= 0) 3258 rte_log_set_level(hinic_logtype, RTE_LOG_INFO); 3259 } 3260