1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Huawei Technologies Co., Ltd 3 */ 4 5 #include <rte_pci.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev_pci.h> 8 #include <rte_mbuf.h> 9 #include <rte_malloc.h> 10 #include <rte_memcpy.h> 11 #include <rte_mempool.h> 12 #include <rte_errno.h> 13 #include <rte_ether.h> 14 15 #include "base/hinic_compat.h" 16 #include "base/hinic_pmd_hwdev.h" 17 #include "base/hinic_pmd_hwif.h" 18 #include "base/hinic_pmd_wq.h" 19 #include "base/hinic_pmd_cfg.h" 20 #include "base/hinic_pmd_mgmt.h" 21 #include "base/hinic_pmd_cmdq.h" 22 #include "base/hinic_pmd_niccfg.h" 23 #include "base/hinic_pmd_nicio.h" 24 #include "base/hinic_pmd_mbox.h" 25 #include "hinic_pmd_ethdev.h" 26 #include "hinic_pmd_tx.h" 27 #include "hinic_pmd_rx.h" 28 29 /* Vendor ID used by Huawei devices */ 30 #define HINIC_HUAWEI_VENDOR_ID 0x19E5 31 32 /* Hinic devices */ 33 #define HINIC_DEV_ID_PRD 0x1822 34 #define HINIC_DEV_ID_VF 0x375E 35 #define HINIC_DEV_ID_VF_HV 0x379E 36 37 /* Mezz card for Blade Server */ 38 #define HINIC_DEV_ID_MEZZ_25GE 0x0210 39 #define HINIC_DEV_ID_MEZZ_100GE 0x0205 40 41 /* 2*25G and 2*100G card */ 42 #define HINIC_DEV_ID_1822_DUAL_25GE 0x0206 43 #define HINIC_DEV_ID_1822_100GE 0x0200 44 45 #define HINIC_SERVICE_MODE_NIC 2 46 47 #define HINIC_INTR_CB_UNREG_MAX_RETRIES 10 48 49 #define DEFAULT_BASE_COS 4 50 #define NR_MAX_COS 8 51 52 #define HINIC_MIN_RX_BUF_SIZE 1024 53 #define HINIC_MAX_UC_MAC_ADDRS 128 54 #define HINIC_MAX_MC_MAC_ADDRS 2048 55 56 #define HINIC_DEFAULT_BURST_SIZE 32 57 #define HINIC_DEFAULT_NB_QUEUES 1 58 #define HINIC_DEFAULT_RING_SIZE 1024 59 #define HINIC_MAX_LRO_SIZE 65536 60 61 /* 62 * vlan_id is a 12 bit number. 63 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. 64 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element. 65 * The higher 7 bit val specifies VFTA array index. 66 */ 67 #define HINIC_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F)) 68 #define HINIC_VFTA_IDX(vlan_id) ((vlan_id) >> 5) 69 70 #define HINIC_VLAN_FILTER_EN (1U << 0) 71 72 #define HINIC_MTU_TO_PKTLEN(mtu) \ 73 ((mtu) + ETH_HLEN + ETH_CRC_LEN) 74 75 #define HINIC_PKTLEN_TO_MTU(pktlen) \ 76 ((pktlen) - (ETH_HLEN + ETH_CRC_LEN)) 77 78 /* lro numer limit for one packet */ 79 #define HINIC_LRO_WQE_NUM_DEFAULT 8 80 81 struct hinic_xstats_name_off { 82 char name[RTE_ETH_XSTATS_NAME_SIZE]; 83 u32 offset; 84 }; 85 86 #define HINIC_FUNC_STAT(_stat_item) { \ 87 .name = #_stat_item, \ 88 .offset = offsetof(struct hinic_vport_stats, _stat_item) \ 89 } 90 91 #define HINIC_PORT_STAT(_stat_item) { \ 92 .name = #_stat_item, \ 93 .offset = offsetof(struct hinic_phy_port_stats, _stat_item) \ 94 } 95 96 static const struct hinic_xstats_name_off hinic_vport_stats_strings[] = { 97 HINIC_FUNC_STAT(tx_unicast_pkts_vport), 98 HINIC_FUNC_STAT(tx_unicast_bytes_vport), 99 HINIC_FUNC_STAT(tx_multicast_pkts_vport), 100 HINIC_FUNC_STAT(tx_multicast_bytes_vport), 101 HINIC_FUNC_STAT(tx_broadcast_pkts_vport), 102 HINIC_FUNC_STAT(tx_broadcast_bytes_vport), 103 104 HINIC_FUNC_STAT(rx_unicast_pkts_vport), 105 HINIC_FUNC_STAT(rx_unicast_bytes_vport), 106 HINIC_FUNC_STAT(rx_multicast_pkts_vport), 107 HINIC_FUNC_STAT(rx_multicast_bytes_vport), 108 HINIC_FUNC_STAT(rx_broadcast_pkts_vport), 109 HINIC_FUNC_STAT(rx_broadcast_bytes_vport), 110 111 HINIC_FUNC_STAT(tx_discard_vport), 112 HINIC_FUNC_STAT(rx_discard_vport), 113 HINIC_FUNC_STAT(tx_err_vport), 114 HINIC_FUNC_STAT(rx_err_vport), 115 }; 116 117 #define HINIC_VPORT_XSTATS_NUM (sizeof(hinic_vport_stats_strings) / \ 118 sizeof(hinic_vport_stats_strings[0])) 119 120 static const struct hinic_xstats_name_off hinic_phyport_stats_strings[] = { 121 HINIC_PORT_STAT(mac_rx_total_pkt_num), 122 HINIC_PORT_STAT(mac_rx_total_oct_num), 123 HINIC_PORT_STAT(mac_rx_bad_pkt_num), 124 HINIC_PORT_STAT(mac_rx_bad_oct_num), 125 HINIC_PORT_STAT(mac_rx_good_pkt_num), 126 HINIC_PORT_STAT(mac_rx_good_oct_num), 127 HINIC_PORT_STAT(mac_rx_uni_pkt_num), 128 HINIC_PORT_STAT(mac_rx_multi_pkt_num), 129 HINIC_PORT_STAT(mac_rx_broad_pkt_num), 130 HINIC_PORT_STAT(mac_tx_total_pkt_num), 131 HINIC_PORT_STAT(mac_tx_total_oct_num), 132 HINIC_PORT_STAT(mac_tx_bad_pkt_num), 133 HINIC_PORT_STAT(mac_tx_bad_oct_num), 134 HINIC_PORT_STAT(mac_tx_good_pkt_num), 135 HINIC_PORT_STAT(mac_tx_good_oct_num), 136 HINIC_PORT_STAT(mac_tx_uni_pkt_num), 137 HINIC_PORT_STAT(mac_tx_multi_pkt_num), 138 HINIC_PORT_STAT(mac_tx_broad_pkt_num), 139 HINIC_PORT_STAT(mac_rx_fragment_pkt_num), 140 HINIC_PORT_STAT(mac_rx_undersize_pkt_num), 141 HINIC_PORT_STAT(mac_rx_undermin_pkt_num), 142 HINIC_PORT_STAT(mac_rx_64_oct_pkt_num), 143 HINIC_PORT_STAT(mac_rx_65_127_oct_pkt_num), 144 HINIC_PORT_STAT(mac_rx_128_255_oct_pkt_num), 145 HINIC_PORT_STAT(mac_rx_256_511_oct_pkt_num), 146 HINIC_PORT_STAT(mac_rx_512_1023_oct_pkt_num), 147 HINIC_PORT_STAT(mac_rx_1024_1518_oct_pkt_num), 148 HINIC_PORT_STAT(mac_rx_1519_2047_oct_pkt_num), 149 HINIC_PORT_STAT(mac_rx_2048_4095_oct_pkt_num), 150 HINIC_PORT_STAT(mac_rx_4096_8191_oct_pkt_num), 151 HINIC_PORT_STAT(mac_rx_8192_9216_oct_pkt_num), 152 HINIC_PORT_STAT(mac_rx_9217_12287_oct_pkt_num), 153 HINIC_PORT_STAT(mac_rx_12288_16383_oct_pkt_num), 154 HINIC_PORT_STAT(mac_rx_1519_max_bad_pkt_num), 155 HINIC_PORT_STAT(mac_rx_1519_max_good_pkt_num), 156 HINIC_PORT_STAT(mac_rx_oversize_pkt_num), 157 HINIC_PORT_STAT(mac_rx_jabber_pkt_num), 158 HINIC_PORT_STAT(mac_rx_mac_pause_num), 159 HINIC_PORT_STAT(mac_rx_pfc_pkt_num), 160 HINIC_PORT_STAT(mac_rx_pfc_pri0_pkt_num), 161 HINIC_PORT_STAT(mac_rx_pfc_pri1_pkt_num), 162 HINIC_PORT_STAT(mac_rx_pfc_pri2_pkt_num), 163 HINIC_PORT_STAT(mac_rx_pfc_pri3_pkt_num), 164 HINIC_PORT_STAT(mac_rx_pfc_pri4_pkt_num), 165 HINIC_PORT_STAT(mac_rx_pfc_pri5_pkt_num), 166 HINIC_PORT_STAT(mac_rx_pfc_pri6_pkt_num), 167 HINIC_PORT_STAT(mac_rx_pfc_pri7_pkt_num), 168 HINIC_PORT_STAT(mac_rx_mac_control_pkt_num), 169 HINIC_PORT_STAT(mac_rx_sym_err_pkt_num), 170 HINIC_PORT_STAT(mac_rx_fcs_err_pkt_num), 171 HINIC_PORT_STAT(mac_rx_send_app_good_pkt_num), 172 HINIC_PORT_STAT(mac_rx_send_app_bad_pkt_num), 173 HINIC_PORT_STAT(mac_tx_fragment_pkt_num), 174 HINIC_PORT_STAT(mac_tx_undersize_pkt_num), 175 HINIC_PORT_STAT(mac_tx_undermin_pkt_num), 176 HINIC_PORT_STAT(mac_tx_64_oct_pkt_num), 177 HINIC_PORT_STAT(mac_tx_65_127_oct_pkt_num), 178 HINIC_PORT_STAT(mac_tx_128_255_oct_pkt_num), 179 HINIC_PORT_STAT(mac_tx_256_511_oct_pkt_num), 180 HINIC_PORT_STAT(mac_tx_512_1023_oct_pkt_num), 181 HINIC_PORT_STAT(mac_tx_1024_1518_oct_pkt_num), 182 HINIC_PORT_STAT(mac_tx_1519_2047_oct_pkt_num), 183 HINIC_PORT_STAT(mac_tx_2048_4095_oct_pkt_num), 184 HINIC_PORT_STAT(mac_tx_4096_8191_oct_pkt_num), 185 HINIC_PORT_STAT(mac_tx_8192_9216_oct_pkt_num), 186 HINIC_PORT_STAT(mac_tx_9217_12287_oct_pkt_num), 187 HINIC_PORT_STAT(mac_tx_12288_16383_oct_pkt_num), 188 HINIC_PORT_STAT(mac_tx_1519_max_bad_pkt_num), 189 HINIC_PORT_STAT(mac_tx_1519_max_good_pkt_num), 190 HINIC_PORT_STAT(mac_tx_oversize_pkt_num), 191 HINIC_PORT_STAT(mac_trans_jabber_pkt_num), 192 HINIC_PORT_STAT(mac_tx_mac_pause_num), 193 HINIC_PORT_STAT(mac_tx_pfc_pkt_num), 194 HINIC_PORT_STAT(mac_tx_pfc_pri0_pkt_num), 195 HINIC_PORT_STAT(mac_tx_pfc_pri1_pkt_num), 196 HINIC_PORT_STAT(mac_tx_pfc_pri2_pkt_num), 197 HINIC_PORT_STAT(mac_tx_pfc_pri3_pkt_num), 198 HINIC_PORT_STAT(mac_tx_pfc_pri4_pkt_num), 199 HINIC_PORT_STAT(mac_tx_pfc_pri5_pkt_num), 200 HINIC_PORT_STAT(mac_tx_pfc_pri6_pkt_num), 201 HINIC_PORT_STAT(mac_tx_pfc_pri7_pkt_num), 202 HINIC_PORT_STAT(mac_tx_mac_control_pkt_num), 203 HINIC_PORT_STAT(mac_tx_err_all_pkt_num), 204 HINIC_PORT_STAT(mac_tx_from_app_good_pkt_num), 205 HINIC_PORT_STAT(mac_tx_from_app_bad_pkt_num), 206 }; 207 208 #define HINIC_PHYPORT_XSTATS_NUM (sizeof(hinic_phyport_stats_strings) / \ 209 sizeof(hinic_phyport_stats_strings[0])) 210 211 static const struct hinic_xstats_name_off hinic_rxq_stats_strings[] = { 212 {"rx_nombuf", offsetof(struct hinic_rxq_stats, rx_nombuf)}, 213 {"burst_pkt", offsetof(struct hinic_rxq_stats, burst_pkts)}, 214 }; 215 216 #define HINIC_RXQ_XSTATS_NUM (sizeof(hinic_rxq_stats_strings) / \ 217 sizeof(hinic_rxq_stats_strings[0])) 218 219 static const struct hinic_xstats_name_off hinic_txq_stats_strings[] = { 220 {"tx_busy", offsetof(struct hinic_txq_stats, tx_busy)}, 221 {"offload_errors", offsetof(struct hinic_txq_stats, off_errs)}, 222 {"copy_pkts", offsetof(struct hinic_txq_stats, cpy_pkts)}, 223 {"rl_drop", offsetof(struct hinic_txq_stats, rl_drop)}, 224 {"burst_pkts", offsetof(struct hinic_txq_stats, burst_pkts)}, 225 {"sge_len0", offsetof(struct hinic_txq_stats, sge_len0)}, 226 {"mbuf_null", offsetof(struct hinic_txq_stats, mbuf_null)}, 227 }; 228 229 #define HINIC_TXQ_XSTATS_NUM (sizeof(hinic_txq_stats_strings) / \ 230 sizeof(hinic_txq_stats_strings[0])) 231 232 static int hinic_xstats_calc_num(struct hinic_nic_dev *nic_dev) 233 { 234 if (HINIC_IS_VF(nic_dev->hwdev)) { 235 return (HINIC_VPORT_XSTATS_NUM + 236 HINIC_RXQ_XSTATS_NUM * nic_dev->num_rq + 237 HINIC_TXQ_XSTATS_NUM * nic_dev->num_sq); 238 } else { 239 return (HINIC_VPORT_XSTATS_NUM + 240 HINIC_PHYPORT_XSTATS_NUM + 241 HINIC_RXQ_XSTATS_NUM * nic_dev->num_rq + 242 HINIC_TXQ_XSTATS_NUM * nic_dev->num_sq); 243 } 244 } 245 246 static const struct rte_eth_desc_lim hinic_rx_desc_lim = { 247 .nb_max = HINIC_MAX_QUEUE_DEPTH, 248 .nb_min = HINIC_MIN_QUEUE_DEPTH, 249 .nb_align = HINIC_RXD_ALIGN, 250 }; 251 252 static const struct rte_eth_desc_lim hinic_tx_desc_lim = { 253 .nb_max = HINIC_MAX_QUEUE_DEPTH, 254 .nb_min = HINIC_MIN_QUEUE_DEPTH, 255 .nb_align = HINIC_TXD_ALIGN, 256 }; 257 258 static int hinic_vlan_offload_set(struct rte_eth_dev *dev, int mask); 259 260 /** 261 * Interrupt handler triggered by NIC for handling 262 * specific event. 263 * 264 * @param: The address of parameter (struct rte_eth_dev *) regsitered before. 265 */ 266 static void hinic_dev_interrupt_handler(void *param) 267 { 268 struct rte_eth_dev *dev = param; 269 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 270 271 if (!rte_bit_relaxed_get32(HINIC_DEV_INTR_EN, &nic_dev->dev_status)) { 272 PMD_DRV_LOG(WARNING, "Device's interrupt is disabled, ignore interrupt event, dev_name: %s, port_id: %d", 273 nic_dev->proc_dev_name, dev->data->port_id); 274 return; 275 } 276 277 /* aeq0 msg handler */ 278 hinic_dev_handle_aeq_event(nic_dev->hwdev, param); 279 } 280 281 /** 282 * Ethernet device configuration. 283 * 284 * Prepare the driver for a given number of TX and RX queues, mtu size 285 * and configure RSS. 286 * 287 * @param dev 288 * Pointer to Ethernet device structure. 289 * 290 * @return 291 * 0 on success, negative error value otherwise. 292 */ 293 static int hinic_dev_configure(struct rte_eth_dev *dev) 294 { 295 struct hinic_nic_dev *nic_dev; 296 struct hinic_nic_io *nic_io; 297 int err; 298 299 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 300 nic_io = nic_dev->hwdev->nic_io; 301 302 nic_dev->num_sq = dev->data->nb_tx_queues; 303 nic_dev->num_rq = dev->data->nb_rx_queues; 304 305 nic_io->num_sqs = dev->data->nb_tx_queues; 306 nic_io->num_rqs = dev->data->nb_rx_queues; 307 308 /* queue pair is max_num(sq, rq) */ 309 nic_dev->num_qps = (nic_dev->num_sq > nic_dev->num_rq) ? 310 nic_dev->num_sq : nic_dev->num_rq; 311 nic_io->num_qps = nic_dev->num_qps; 312 313 if (nic_dev->num_qps > nic_io->max_qps) { 314 PMD_DRV_LOG(ERR, 315 "Queue number out of range, get queue_num:%d, max_queue_num:%d", 316 nic_dev->num_qps, nic_io->max_qps); 317 return -EINVAL; 318 } 319 320 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 321 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH; 322 323 /* mtu size is 256~9600 */ 324 if (dev->data->dev_conf.rxmode.max_rx_pkt_len < HINIC_MIN_FRAME_SIZE || 325 dev->data->dev_conf.rxmode.max_rx_pkt_len > 326 HINIC_MAX_JUMBO_FRAME_SIZE) { 327 PMD_DRV_LOG(ERR, 328 "Max rx pkt len out of range, get max_rx_pkt_len:%d, " 329 "expect between %d and %d", 330 dev->data->dev_conf.rxmode.max_rx_pkt_len, 331 HINIC_MIN_FRAME_SIZE, HINIC_MAX_JUMBO_FRAME_SIZE); 332 return -EINVAL; 333 } 334 335 nic_dev->mtu_size = 336 HINIC_PKTLEN_TO_MTU(dev->data->dev_conf.rxmode.max_rx_pkt_len); 337 338 /* rss template */ 339 err = hinic_config_mq_mode(dev, TRUE); 340 if (err) { 341 PMD_DRV_LOG(ERR, "Config multi-queue failed"); 342 return err; 343 } 344 345 /* init vlan offoad */ 346 err = hinic_vlan_offload_set(dev, 347 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK); 348 if (err) { 349 PMD_DRV_LOG(ERR, "Initialize vlan filter and strip failed"); 350 (void)hinic_config_mq_mode(dev, FALSE); 351 return err; 352 } 353 354 /* clear fdir filter flag in function table */ 355 hinic_free_fdir_filter(nic_dev); 356 357 return HINIC_OK; 358 } 359 360 /** 361 * DPDK callback to create the receive queue. 362 * 363 * @param dev 364 * Pointer to Ethernet device structure. 365 * @param queue_idx 366 * RX queue index. 367 * @param nb_desc 368 * Number of descriptors for receive queue. 369 * @param socket_id 370 * NUMA socket on which memory must be allocated. 371 * @param rx_conf 372 * Thresholds parameters (unused_). 373 * @param mp 374 * Memory pool for buffer allocations. 375 * 376 * @return 377 * 0 on success, negative error value otherwise. 378 */ 379 static int hinic_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 380 uint16_t nb_desc, unsigned int socket_id, 381 __rte_unused const struct rte_eth_rxconf *rx_conf, 382 struct rte_mempool *mp) 383 { 384 int rc; 385 struct hinic_nic_dev *nic_dev; 386 struct hinic_hwdev *hwdev; 387 struct hinic_rxq *rxq; 388 u16 rq_depth, rx_free_thresh; 389 u32 buf_size; 390 391 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 392 hwdev = nic_dev->hwdev; 393 394 /* queue depth must be power of 2, otherwise will be aligned up */ 395 rq_depth = (nb_desc & (nb_desc - 1)) ? 396 ((u16)(1U << (ilog2(nb_desc) + 1))) : nb_desc; 397 398 /* 399 * Validate number of receive descriptors. 400 * It must not exceed hardware maximum and minimum. 401 */ 402 if (rq_depth > HINIC_MAX_QUEUE_DEPTH || 403 rq_depth < HINIC_MIN_QUEUE_DEPTH) { 404 PMD_DRV_LOG(ERR, "RX queue depth is out of range from %d to %d, (nb_desc=%d, q_depth=%d, port=%d queue=%d)", 405 HINIC_MIN_QUEUE_DEPTH, HINIC_MAX_QUEUE_DEPTH, 406 (int)nb_desc, (int)rq_depth, 407 (int)dev->data->port_id, (int)queue_idx); 408 return -EINVAL; 409 } 410 411 /* 412 * The RX descriptor ring will be cleaned after rxq->rx_free_thresh 413 * descriptors are used or if the number of descriptors required 414 * to transmit a packet is greater than the number of free RX 415 * descriptors. 416 * The following constraints must be satisfied: 417 * rx_free_thresh must be greater than 0. 418 * rx_free_thresh must be less than the size of the ring minus 1. 419 * When set to zero use default values. 420 */ 421 rx_free_thresh = (u16)((rx_conf->rx_free_thresh) ? 422 rx_conf->rx_free_thresh : HINIC_DEFAULT_RX_FREE_THRESH); 423 if (rx_free_thresh >= (rq_depth - 1)) { 424 PMD_DRV_LOG(ERR, "rx_free_thresh must be less than the number of RX descriptors minus 1. (rx_free_thresh=%u port=%d queue=%d)", 425 (unsigned int)rx_free_thresh, 426 (int)dev->data->port_id, 427 (int)queue_idx); 428 return -EINVAL; 429 } 430 431 rxq = rte_zmalloc_socket("hinic_rx_queue", sizeof(struct hinic_rxq), 432 RTE_CACHE_LINE_SIZE, socket_id); 433 if (!rxq) { 434 PMD_DRV_LOG(ERR, "Allocate rxq[%d] failed, dev_name: %s", 435 queue_idx, dev->data->name); 436 return -ENOMEM; 437 } 438 nic_dev->rxqs[queue_idx] = rxq; 439 440 /* alloc rx sq hw wqe page */ 441 rc = hinic_create_rq(hwdev, queue_idx, rq_depth, socket_id); 442 if (rc) { 443 PMD_DRV_LOG(ERR, "Create rxq[%d] failed, dev_name: %s, rq_depth: %d", 444 queue_idx, dev->data->name, rq_depth); 445 goto ceate_rq_fail; 446 } 447 448 /* mbuf pool must be assigned before setup rx resources */ 449 rxq->mb_pool = mp; 450 451 rc = 452 hinic_convert_rx_buf_size(rte_pktmbuf_data_room_size(rxq->mb_pool) - 453 RTE_PKTMBUF_HEADROOM, &buf_size); 454 if (rc) { 455 PMD_DRV_LOG(ERR, "Adjust buf size failed, dev_name: %s", 456 dev->data->name); 457 goto adjust_bufsize_fail; 458 } 459 460 /* rx queue info, rearm control */ 461 rxq->wq = &hwdev->nic_io->rq_wq[queue_idx]; 462 rxq->pi_virt_addr = hwdev->nic_io->qps[queue_idx].rq.pi_virt_addr; 463 rxq->nic_dev = nic_dev; 464 rxq->q_id = queue_idx; 465 rxq->q_depth = rq_depth; 466 rxq->buf_len = (u16)buf_size; 467 rxq->rx_free_thresh = rx_free_thresh; 468 rxq->socket_id = socket_id; 469 470 /* the last point cant do mbuf rearm in bulk */ 471 rxq->rxinfo_align_end = rxq->q_depth - rxq->rx_free_thresh; 472 473 /* device port identifier */ 474 rxq->port_id = dev->data->port_id; 475 476 /* alloc rx_cqe and prepare rq_wqe */ 477 rc = hinic_setup_rx_resources(rxq); 478 if (rc) { 479 PMD_DRV_LOG(ERR, "Setup rxq[%d] rx_resources failed, dev_name: %s", 480 queue_idx, dev->data->name); 481 goto setup_rx_res_err; 482 } 483 484 /* record nic_dev rxq in rte_eth rx_queues */ 485 dev->data->rx_queues[queue_idx] = rxq; 486 487 return 0; 488 489 setup_rx_res_err: 490 adjust_bufsize_fail: 491 hinic_destroy_rq(hwdev, queue_idx); 492 493 ceate_rq_fail: 494 rte_free(rxq); 495 496 return rc; 497 } 498 499 static void hinic_reset_rx_queue(struct rte_eth_dev *dev) 500 { 501 struct hinic_rxq *rxq; 502 struct hinic_nic_dev *nic_dev; 503 int q_id = 0; 504 505 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 506 507 for (q_id = 0; q_id < nic_dev->num_rq; q_id++) { 508 rxq = dev->data->rx_queues[q_id]; 509 510 rxq->wq->cons_idx = 0; 511 rxq->wq->prod_idx = 0; 512 rxq->wq->delta = rxq->q_depth; 513 rxq->wq->mask = rxq->q_depth - 1; 514 515 /* alloc mbuf to rq */ 516 hinic_rx_alloc_pkts(rxq); 517 } 518 } 519 520 /** 521 * DPDK callback to configure the transmit queue. 522 * 523 * @param dev 524 * Pointer to Ethernet device structure. 525 * @param queue_idx 526 * Transmit queue index. 527 * @param nb_desc 528 * Number of descriptors for transmit queue. 529 * @param socket_id 530 * NUMA socket on which memory must be allocated. 531 * @param tx_conf 532 * Tx queue configuration parameters. 533 * 534 * @return 535 * 0 on success, negative error value otherwise. 536 */ 537 static int hinic_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 538 uint16_t nb_desc, unsigned int socket_id, 539 __rte_unused const struct rte_eth_txconf *tx_conf) 540 { 541 int rc; 542 struct hinic_nic_dev *nic_dev; 543 struct hinic_hwdev *hwdev; 544 struct hinic_txq *txq; 545 u16 sq_depth, tx_free_thresh; 546 547 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 548 hwdev = nic_dev->hwdev; 549 550 /* queue depth must be power of 2, otherwise will be aligned up */ 551 sq_depth = (nb_desc & (nb_desc - 1)) ? 552 ((u16)(1U << (ilog2(nb_desc) + 1))) : nb_desc; 553 554 /* 555 * Validate number of transmit descriptors. 556 * It must not exceed hardware maximum and minimum. 557 */ 558 if (sq_depth > HINIC_MAX_QUEUE_DEPTH || 559 sq_depth < HINIC_MIN_QUEUE_DEPTH) { 560 PMD_DRV_LOG(ERR, "TX queue depth is out of range from %d to %d, (nb_desc=%d, q_depth=%d, port=%d queue=%d)", 561 HINIC_MIN_QUEUE_DEPTH, HINIC_MAX_QUEUE_DEPTH, 562 (int)nb_desc, (int)sq_depth, 563 (int)dev->data->port_id, (int)queue_idx); 564 return -EINVAL; 565 } 566 567 /* 568 * The TX descriptor ring will be cleaned after txq->tx_free_thresh 569 * descriptors are used or if the number of descriptors required 570 * to transmit a packet is greater than the number of free TX 571 * descriptors. 572 * The following constraints must be satisfied: 573 * tx_free_thresh must be greater than 0. 574 * tx_free_thresh must be less than the size of the ring minus 1. 575 * When set to zero use default values. 576 */ 577 tx_free_thresh = (u16)((tx_conf->tx_free_thresh) ? 578 tx_conf->tx_free_thresh : HINIC_DEFAULT_TX_FREE_THRESH); 579 if (tx_free_thresh >= (sq_depth - 1)) { 580 PMD_DRV_LOG(ERR, "tx_free_thresh must be less than the number of TX descriptors minus 1. (tx_free_thresh=%u port=%d queue=%d)", 581 (unsigned int)tx_free_thresh, (int)dev->data->port_id, 582 (int)queue_idx); 583 return -EINVAL; 584 } 585 586 txq = rte_zmalloc_socket("hinic_tx_queue", sizeof(struct hinic_txq), 587 RTE_CACHE_LINE_SIZE, socket_id); 588 if (!txq) { 589 PMD_DRV_LOG(ERR, "Allocate txq[%d] failed, dev_name: %s", 590 queue_idx, dev->data->name); 591 return -ENOMEM; 592 } 593 nic_dev->txqs[queue_idx] = txq; 594 595 /* alloc tx sq hw wqepage */ 596 rc = hinic_create_sq(hwdev, queue_idx, sq_depth, socket_id); 597 if (rc) { 598 PMD_DRV_LOG(ERR, "Create txq[%d] failed, dev_name: %s, sq_depth: %d", 599 queue_idx, dev->data->name, sq_depth); 600 goto create_sq_fail; 601 } 602 603 txq->q_id = queue_idx; 604 txq->q_depth = sq_depth; 605 txq->port_id = dev->data->port_id; 606 txq->tx_free_thresh = tx_free_thresh; 607 txq->nic_dev = nic_dev; 608 txq->wq = &hwdev->nic_io->sq_wq[queue_idx]; 609 txq->sq = &hwdev->nic_io->qps[queue_idx].sq; 610 txq->cons_idx_addr = hwdev->nic_io->qps[queue_idx].sq.cons_idx_addr; 611 txq->sq_head_addr = HINIC_GET_WQ_HEAD(txq); 612 txq->sq_bot_sge_addr = HINIC_GET_WQ_TAIL(txq) - 613 sizeof(struct hinic_sq_bufdesc); 614 txq->cos = nic_dev->default_cos; 615 txq->socket_id = socket_id; 616 617 /* alloc software txinfo */ 618 rc = hinic_setup_tx_resources(txq); 619 if (rc) { 620 PMD_DRV_LOG(ERR, "Setup txq[%d] tx_resources failed, dev_name: %s", 621 queue_idx, dev->data->name); 622 goto setup_tx_res_fail; 623 } 624 625 /* record nic_dev txq in rte_eth tx_queues */ 626 dev->data->tx_queues[queue_idx] = txq; 627 628 return HINIC_OK; 629 630 setup_tx_res_fail: 631 hinic_destroy_sq(hwdev, queue_idx); 632 633 create_sq_fail: 634 rte_free(txq); 635 636 return rc; 637 } 638 639 static void hinic_reset_tx_queue(struct rte_eth_dev *dev) 640 { 641 struct hinic_nic_dev *nic_dev; 642 struct hinic_txq *txq; 643 struct hinic_nic_io *nic_io; 644 struct hinic_hwdev *hwdev; 645 volatile u32 *ci_addr; 646 int q_id = 0; 647 648 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 649 hwdev = nic_dev->hwdev; 650 nic_io = hwdev->nic_io; 651 652 for (q_id = 0; q_id < nic_dev->num_sq; q_id++) { 653 txq = dev->data->tx_queues[q_id]; 654 655 txq->wq->cons_idx = 0; 656 txq->wq->prod_idx = 0; 657 txq->wq->delta = txq->q_depth; 658 txq->wq->mask = txq->q_depth - 1; 659 660 /* clear hardware ci */ 661 ci_addr = (volatile u32 *)HINIC_CI_VADDR(nic_io->ci_vaddr_base, 662 q_id); 663 *ci_addr = 0; 664 } 665 } 666 667 /** 668 * Get link speed from NIC. 669 * 670 * @param dev 671 * Pointer to Ethernet device structure. 672 * @param speed_capa 673 * Pointer to link speed structure. 674 */ 675 static void hinic_get_speed_capa(struct rte_eth_dev *dev, uint32_t *speed_capa) 676 { 677 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 678 u32 supported_link, advertised_link; 679 int err; 680 681 #define HINIC_LINK_MODE_SUPPORT_1G (1U << HINIC_GE_BASE_KX) 682 683 #define HINIC_LINK_MODE_SUPPORT_10G (1U << HINIC_10GE_BASE_KR) 684 685 #define HINIC_LINK_MODE_SUPPORT_25G ((1U << HINIC_25GE_BASE_KR_S) | \ 686 (1U << HINIC_25GE_BASE_CR_S) | \ 687 (1U << HINIC_25GE_BASE_KR) | \ 688 (1U << HINIC_25GE_BASE_CR)) 689 690 #define HINIC_LINK_MODE_SUPPORT_40G ((1U << HINIC_40GE_BASE_KR4) | \ 691 (1U << HINIC_40GE_BASE_CR4)) 692 693 #define HINIC_LINK_MODE_SUPPORT_100G ((1U << HINIC_100GE_BASE_KR4) | \ 694 (1U << HINIC_100GE_BASE_CR4)) 695 696 err = hinic_get_link_mode(nic_dev->hwdev, 697 &supported_link, &advertised_link); 698 if (err || supported_link == HINIC_SUPPORTED_UNKNOWN || 699 advertised_link == HINIC_SUPPORTED_UNKNOWN) { 700 PMD_DRV_LOG(WARNING, "Get speed capability info failed, device: %s, port_id: %u", 701 nic_dev->proc_dev_name, dev->data->port_id); 702 } else { 703 *speed_capa = 0; 704 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_1G)) 705 *speed_capa |= ETH_LINK_SPEED_1G; 706 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_10G)) 707 *speed_capa |= ETH_LINK_SPEED_10G; 708 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_25G)) 709 *speed_capa |= ETH_LINK_SPEED_25G; 710 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_40G)) 711 *speed_capa |= ETH_LINK_SPEED_40G; 712 if (!!(supported_link & HINIC_LINK_MODE_SUPPORT_100G)) 713 *speed_capa |= ETH_LINK_SPEED_100G; 714 } 715 } 716 717 /** 718 * DPDK callback to get information about the device. 719 * 720 * @param dev 721 * Pointer to Ethernet device structure. 722 * @param info 723 * Pointer to Info structure output buffer. 724 */ 725 static int 726 hinic_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 727 { 728 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 729 730 info->max_rx_queues = nic_dev->nic_cap.max_rqs; 731 info->max_tx_queues = nic_dev->nic_cap.max_sqs; 732 info->min_rx_bufsize = HINIC_MIN_RX_BUF_SIZE; 733 info->max_rx_pktlen = HINIC_MAX_JUMBO_FRAME_SIZE; 734 info->max_mac_addrs = HINIC_MAX_UC_MAC_ADDRS; 735 info->min_mtu = HINIC_MIN_MTU_SIZE; 736 info->max_mtu = HINIC_MAX_MTU_SIZE; 737 info->max_lro_pkt_size = HINIC_MAX_LRO_SIZE; 738 739 hinic_get_speed_capa(dev, &info->speed_capa); 740 info->rx_queue_offload_capa = 0; 741 info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP | 742 DEV_RX_OFFLOAD_IPV4_CKSUM | 743 DEV_RX_OFFLOAD_UDP_CKSUM | 744 DEV_RX_OFFLOAD_TCP_CKSUM | 745 DEV_RX_OFFLOAD_VLAN_FILTER | 746 DEV_RX_OFFLOAD_SCATTER | 747 DEV_RX_OFFLOAD_JUMBO_FRAME | 748 DEV_RX_OFFLOAD_TCP_LRO | 749 DEV_RX_OFFLOAD_RSS_HASH; 750 751 info->tx_queue_offload_capa = 0; 752 info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT | 753 DEV_TX_OFFLOAD_IPV4_CKSUM | 754 DEV_TX_OFFLOAD_UDP_CKSUM | 755 DEV_TX_OFFLOAD_TCP_CKSUM | 756 DEV_TX_OFFLOAD_SCTP_CKSUM | 757 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 758 DEV_TX_OFFLOAD_TCP_TSO | 759 DEV_TX_OFFLOAD_MULTI_SEGS; 760 761 info->hash_key_size = HINIC_RSS_KEY_SIZE; 762 info->reta_size = HINIC_RSS_INDIR_SIZE; 763 info->flow_type_rss_offloads = HINIC_RSS_OFFLOAD_ALL; 764 info->rx_desc_lim = hinic_rx_desc_lim; 765 info->tx_desc_lim = hinic_tx_desc_lim; 766 767 /* Driver-preferred Rx/Tx parameters */ 768 info->default_rxportconf.burst_size = HINIC_DEFAULT_BURST_SIZE; 769 info->default_txportconf.burst_size = HINIC_DEFAULT_BURST_SIZE; 770 info->default_rxportconf.nb_queues = HINIC_DEFAULT_NB_QUEUES; 771 info->default_txportconf.nb_queues = HINIC_DEFAULT_NB_QUEUES; 772 info->default_rxportconf.ring_size = HINIC_DEFAULT_RING_SIZE; 773 info->default_txportconf.ring_size = HINIC_DEFAULT_RING_SIZE; 774 775 return 0; 776 } 777 778 static int hinic_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 779 size_t fw_size) 780 { 781 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 782 char fw_ver[HINIC_MGMT_VERSION_MAX_LEN] = {0}; 783 int err; 784 785 err = hinic_get_mgmt_version(nic_dev->hwdev, fw_ver); 786 if (err) { 787 PMD_DRV_LOG(ERR, "Failed to get fw version"); 788 return -EINVAL; 789 } 790 791 if (fw_size < strlen(fw_ver) + 1) 792 return (strlen(fw_ver) + 1); 793 794 snprintf(fw_version, fw_size, "%s", fw_ver); 795 796 return 0; 797 } 798 799 static int hinic_config_rx_mode(struct hinic_nic_dev *nic_dev, u32 rx_mode_ctrl) 800 { 801 int err; 802 803 err = hinic_set_rx_mode(nic_dev->hwdev, rx_mode_ctrl); 804 if (err) { 805 PMD_DRV_LOG(ERR, "Failed to set rx mode"); 806 return -EINVAL; 807 } 808 nic_dev->rx_mode_status = rx_mode_ctrl; 809 810 return 0; 811 } 812 813 static int hinic_rxtx_configure(struct rte_eth_dev *dev) 814 { 815 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 816 int err; 817 818 /* rx configure, if rss enable, need to init default configuration */ 819 err = hinic_rx_configure(dev); 820 if (err) { 821 PMD_DRV_LOG(ERR, "Configure rss failed"); 822 return err; 823 } 824 825 /* rx mode init */ 826 err = hinic_config_rx_mode(nic_dev, HINIC_DEFAULT_RX_MODE); 827 if (err) { 828 PMD_DRV_LOG(ERR, "Configure rx_mode:0x%x failed", 829 HINIC_DEFAULT_RX_MODE); 830 goto set_rx_mode_fail; 831 } 832 833 return HINIC_OK; 834 835 set_rx_mode_fail: 836 hinic_rx_remove_configure(dev); 837 838 return err; 839 } 840 841 static void hinic_remove_rxtx_configure(struct rte_eth_dev *dev) 842 { 843 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 844 845 (void)hinic_config_rx_mode(nic_dev, 0); 846 hinic_rx_remove_configure(dev); 847 } 848 849 static int hinic_priv_get_dev_link_status(struct hinic_nic_dev *nic_dev, 850 struct rte_eth_link *link) 851 { 852 int rc; 853 u8 port_link_status = 0; 854 struct nic_port_info port_link_info; 855 struct hinic_hwdev *nic_hwdev = nic_dev->hwdev; 856 uint32_t port_speed[LINK_SPEED_MAX] = {ETH_SPEED_NUM_10M, 857 ETH_SPEED_NUM_100M, ETH_SPEED_NUM_1G, 858 ETH_SPEED_NUM_10G, ETH_SPEED_NUM_25G, 859 ETH_SPEED_NUM_40G, ETH_SPEED_NUM_100G}; 860 861 rc = hinic_get_link_status(nic_hwdev, &port_link_status); 862 if (rc) 863 return rc; 864 865 if (!port_link_status) { 866 link->link_status = ETH_LINK_DOWN; 867 link->link_speed = 0; 868 link->link_duplex = ETH_LINK_HALF_DUPLEX; 869 link->link_autoneg = ETH_LINK_FIXED; 870 return HINIC_OK; 871 } 872 873 memset(&port_link_info, 0, sizeof(port_link_info)); 874 rc = hinic_get_port_info(nic_hwdev, &port_link_info); 875 if (rc) 876 return rc; 877 878 link->link_speed = port_speed[port_link_info.speed % LINK_SPEED_MAX]; 879 link->link_duplex = port_link_info.duplex; 880 link->link_autoneg = port_link_info.autoneg_state; 881 link->link_status = port_link_status; 882 883 return HINIC_OK; 884 } 885 886 /** 887 * DPDK callback to retrieve physical link information. 888 * 889 * @param dev 890 * Pointer to Ethernet device structure. 891 * @param wait_to_complete 892 * Wait for request completion. 893 * 894 * @return 895 * 0 link status changed, -1 link status not changed 896 */ 897 static int hinic_link_update(struct rte_eth_dev *dev, int wait_to_complete) 898 { 899 #define CHECK_INTERVAL 10 /* 10ms */ 900 #define MAX_REPEAT_TIME 100 /* 1s (100 * 10ms) in total */ 901 int rc = HINIC_OK; 902 struct rte_eth_link link; 903 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 904 unsigned int rep_cnt = MAX_REPEAT_TIME; 905 906 memset(&link, 0, sizeof(link)); 907 do { 908 /* Get link status information from hardware */ 909 rc = hinic_priv_get_dev_link_status(nic_dev, &link); 910 if (rc != HINIC_OK) { 911 link.link_speed = ETH_SPEED_NUM_NONE; 912 link.link_duplex = ETH_LINK_FULL_DUPLEX; 913 PMD_DRV_LOG(ERR, "Get link status failed"); 914 goto out; 915 } 916 917 if (!wait_to_complete || link.link_status) 918 break; 919 920 rte_delay_ms(CHECK_INTERVAL); 921 } while (rep_cnt--); 922 923 out: 924 rc = rte_eth_linkstatus_set(dev, &link); 925 return rc; 926 } 927 928 /** 929 * DPDK callback to bring the link UP. 930 * 931 * @param dev 932 * Pointer to Ethernet device structure. 933 * 934 * @return 935 * 0 on success, negative errno value on failure. 936 */ 937 static int hinic_dev_set_link_up(struct rte_eth_dev *dev) 938 { 939 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 940 int ret; 941 942 ret = hinic_set_xsfp_tx_status(nic_dev->hwdev, true); 943 if (ret) { 944 PMD_DRV_LOG(ERR, "Enable port tx xsfp failed, dev_name: %s, port_id: %d", 945 nic_dev->proc_dev_name, dev->data->port_id); 946 return ret; 947 } 948 949 /* link status follow phy port status, up will open pma */ 950 ret = hinic_set_port_enable(nic_dev->hwdev, true); 951 if (ret) 952 PMD_DRV_LOG(ERR, "Set mac link up failed, dev_name: %s, port_id: %d", 953 nic_dev->proc_dev_name, dev->data->port_id); 954 955 return ret; 956 } 957 958 /** 959 * DPDK callback to bring the link DOWN. 960 * 961 * @param dev 962 * Pointer to Ethernet device structure. 963 * 964 * @return 965 * 0 on success, negative errno value on failure. 966 */ 967 static int hinic_dev_set_link_down(struct rte_eth_dev *dev) 968 { 969 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 970 int ret; 971 972 ret = hinic_set_xsfp_tx_status(nic_dev->hwdev, false); 973 if (ret) { 974 PMD_DRV_LOG(ERR, "Disable port tx xsfp failed, dev_name: %s, port_id: %d", 975 nic_dev->proc_dev_name, dev->data->port_id); 976 return ret; 977 } 978 979 /* link status follow phy port status, up will close pma */ 980 ret = hinic_set_port_enable(nic_dev->hwdev, false); 981 if (ret) 982 PMD_DRV_LOG(ERR, "Set mac link down failed, dev_name: %s, port_id: %d", 983 nic_dev->proc_dev_name, dev->data->port_id); 984 985 return ret; 986 } 987 988 /** 989 * DPDK callback to start the device. 990 * 991 * @param dev 992 * Pointer to Ethernet device structure. 993 * 994 * @return 995 * 0 on success, negative errno value on failure. 996 */ 997 static int hinic_dev_start(struct rte_eth_dev *dev) 998 { 999 int rc; 1000 char *name; 1001 struct hinic_nic_dev *nic_dev; 1002 1003 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1004 name = dev->data->name; 1005 1006 /* reset rx and tx queue */ 1007 hinic_reset_rx_queue(dev); 1008 hinic_reset_tx_queue(dev); 1009 1010 /* get func rx buf size */ 1011 hinic_get_func_rx_buf_size(nic_dev); 1012 1013 /* init txq and rxq context */ 1014 rc = hinic_init_qp_ctxts(nic_dev->hwdev); 1015 if (rc) { 1016 PMD_DRV_LOG(ERR, "Initialize qp context failed, dev_name: %s", 1017 name); 1018 goto init_qp_fail; 1019 } 1020 1021 /* rss template */ 1022 rc = hinic_config_mq_mode(dev, TRUE); 1023 if (rc) { 1024 PMD_DRV_LOG(ERR, "Configure mq mode failed, dev_name: %s", 1025 name); 1026 goto cfg_mq_mode_fail; 1027 } 1028 1029 /* set default mtu */ 1030 rc = hinic_set_port_mtu(nic_dev->hwdev, nic_dev->mtu_size); 1031 if (rc) { 1032 PMD_DRV_LOG(ERR, "Set mtu_size[%d] failed, dev_name: %s", 1033 nic_dev->mtu_size, name); 1034 goto set_mtu_fail; 1035 } 1036 1037 /* configure rss rx_mode and other rx or tx default feature */ 1038 rc = hinic_rxtx_configure(dev); 1039 if (rc) { 1040 PMD_DRV_LOG(ERR, "Configure tx and rx failed, dev_name: %s", 1041 name); 1042 goto cfg_rxtx_fail; 1043 } 1044 1045 /* reactive pf status, so that uP report asyn event */ 1046 hinic_set_pf_status(nic_dev->hwdev->hwif, HINIC_PF_STATUS_ACTIVE_FLAG); 1047 1048 /* open virtual port and ready to start packet receiving */ 1049 rc = hinic_set_vport_enable(nic_dev->hwdev, true); 1050 if (rc) { 1051 PMD_DRV_LOG(ERR, "Enable vport failed, dev_name:%s", name); 1052 goto en_vport_fail; 1053 } 1054 1055 /* open physical port and start packet receiving */ 1056 rc = hinic_set_port_enable(nic_dev->hwdev, true); 1057 if (rc) { 1058 PMD_DRV_LOG(ERR, "Enable physical port failed, dev_name: %s", 1059 name); 1060 goto en_port_fail; 1061 } 1062 1063 /* update eth_dev link status */ 1064 if (dev->data->dev_conf.intr_conf.lsc != 0) 1065 (void)hinic_link_update(dev, 0); 1066 1067 rte_bit_relaxed_set32(HINIC_DEV_START, &nic_dev->dev_status); 1068 1069 return 0; 1070 1071 en_port_fail: 1072 (void)hinic_set_vport_enable(nic_dev->hwdev, false); 1073 1074 en_vport_fail: 1075 hinic_set_pf_status(nic_dev->hwdev->hwif, HINIC_PF_STATUS_INIT); 1076 1077 /* Flush tx && rx chip resources in case of set vport fake fail */ 1078 (void)hinic_flush_qp_res(nic_dev->hwdev); 1079 rte_delay_ms(100); 1080 1081 hinic_remove_rxtx_configure(dev); 1082 1083 cfg_rxtx_fail: 1084 set_mtu_fail: 1085 cfg_mq_mode_fail: 1086 hinic_free_qp_ctxts(nic_dev->hwdev); 1087 1088 init_qp_fail: 1089 hinic_free_all_rx_mbuf(dev); 1090 hinic_free_all_tx_mbuf(dev); 1091 1092 return rc; 1093 } 1094 1095 /** 1096 * DPDK callback to release the receive queue. 1097 * 1098 * @param queue 1099 * Generic receive queue pointer. 1100 */ 1101 static void hinic_rx_queue_release(void *queue) 1102 { 1103 struct hinic_rxq *rxq = queue; 1104 struct hinic_nic_dev *nic_dev; 1105 1106 if (!rxq) { 1107 PMD_DRV_LOG(WARNING, "Rxq is null when release"); 1108 return; 1109 } 1110 nic_dev = rxq->nic_dev; 1111 1112 /* free rxq_pkt mbuf */ 1113 hinic_free_all_rx_mbufs(rxq); 1114 1115 /* free rxq_cqe, rxq_info */ 1116 hinic_free_rx_resources(rxq); 1117 1118 /* free root rq wq */ 1119 hinic_destroy_rq(nic_dev->hwdev, rxq->q_id); 1120 1121 nic_dev->rxqs[rxq->q_id] = NULL; 1122 1123 /* free rxq */ 1124 rte_free(rxq); 1125 } 1126 1127 /** 1128 * DPDK callback to release the transmit queue. 1129 * 1130 * @param queue 1131 * Generic transmit queue pointer. 1132 */ 1133 static void hinic_tx_queue_release(void *queue) 1134 { 1135 struct hinic_txq *txq = queue; 1136 struct hinic_nic_dev *nic_dev; 1137 1138 if (!txq) { 1139 PMD_DRV_LOG(WARNING, "Txq is null when release"); 1140 return; 1141 } 1142 nic_dev = txq->nic_dev; 1143 1144 /* free txq_pkt mbuf */ 1145 hinic_free_all_tx_mbufs(txq); 1146 1147 /* free txq_info */ 1148 hinic_free_tx_resources(txq); 1149 1150 /* free root sq wq */ 1151 hinic_destroy_sq(nic_dev->hwdev, txq->q_id); 1152 nic_dev->txqs[txq->q_id] = NULL; 1153 1154 /* free txq */ 1155 rte_free(txq); 1156 } 1157 1158 static void hinic_free_all_rq(struct hinic_nic_dev *nic_dev) 1159 { 1160 u16 q_id; 1161 1162 for (q_id = 0; q_id < nic_dev->num_rq; q_id++) 1163 hinic_destroy_rq(nic_dev->hwdev, q_id); 1164 } 1165 1166 static void hinic_free_all_sq(struct hinic_nic_dev *nic_dev) 1167 { 1168 u16 q_id; 1169 1170 for (q_id = 0; q_id < nic_dev->num_sq; q_id++) 1171 hinic_destroy_sq(nic_dev->hwdev, q_id); 1172 } 1173 1174 /** 1175 * DPDK callback to stop the device. 1176 * 1177 * @param dev 1178 * Pointer to Ethernet device structure. 1179 */ 1180 static int hinic_dev_stop(struct rte_eth_dev *dev) 1181 { 1182 int rc; 1183 char *name; 1184 uint16_t port_id; 1185 struct hinic_nic_dev *nic_dev; 1186 struct rte_eth_link link; 1187 1188 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1189 name = dev->data->name; 1190 port_id = dev->data->port_id; 1191 1192 dev->data->dev_started = 0; 1193 1194 if (!rte_bit_relaxed_test_and_clear32(HINIC_DEV_START, 1195 &nic_dev->dev_status)) { 1196 PMD_DRV_LOG(INFO, "Device %s already stopped", name); 1197 return 0; 1198 } 1199 1200 /* just stop phy port and vport */ 1201 rc = hinic_set_port_enable(nic_dev->hwdev, false); 1202 if (rc) 1203 PMD_DRV_LOG(WARNING, "Disable phy port failed, error: %d, dev_name: %s, port_id: %d", 1204 rc, name, port_id); 1205 1206 rc = hinic_set_vport_enable(nic_dev->hwdev, false); 1207 if (rc) 1208 PMD_DRV_LOG(WARNING, "Disable vport failed, error: %d, dev_name: %s, port_id: %d", 1209 rc, name, port_id); 1210 1211 /* Clear recorded link status */ 1212 memset(&link, 0, sizeof(link)); 1213 (void)rte_eth_linkstatus_set(dev, &link); 1214 1215 /* flush pending io request */ 1216 rc = hinic_rx_tx_flush(nic_dev->hwdev); 1217 if (rc) 1218 PMD_DRV_LOG(WARNING, "Flush pending io failed, error: %d, dev_name: %s, port_id: %d", 1219 rc, name, port_id); 1220 1221 /* clean rss table and rx_mode */ 1222 hinic_remove_rxtx_configure(dev); 1223 1224 /* clean root context */ 1225 hinic_free_qp_ctxts(nic_dev->hwdev); 1226 1227 hinic_destroy_fdir_filter(dev); 1228 1229 /* free mbuf */ 1230 hinic_free_all_rx_mbuf(dev); 1231 hinic_free_all_tx_mbuf(dev); 1232 1233 return 0; 1234 } 1235 1236 static void hinic_disable_interrupt(struct rte_eth_dev *dev) 1237 { 1238 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1239 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1240 int ret, retries = 0; 1241 1242 rte_bit_relaxed_clear32(HINIC_DEV_INTR_EN, &nic_dev->dev_status); 1243 1244 /* disable msix interrupt in hardware */ 1245 hinic_set_msix_state(nic_dev->hwdev, 0, HINIC_MSIX_DISABLE); 1246 1247 /* disable rte interrupt */ 1248 ret = rte_intr_disable(&pci_dev->intr_handle); 1249 if (ret) 1250 PMD_DRV_LOG(ERR, "Disable intr failed: %d", ret); 1251 1252 do { 1253 ret = 1254 rte_intr_callback_unregister(&pci_dev->intr_handle, 1255 hinic_dev_interrupt_handler, dev); 1256 if (ret >= 0) { 1257 break; 1258 } else if (ret == -EAGAIN) { 1259 rte_delay_ms(100); 1260 retries++; 1261 } else { 1262 PMD_DRV_LOG(ERR, "intr callback unregister failed: %d", 1263 ret); 1264 break; 1265 } 1266 } while (retries < HINIC_INTR_CB_UNREG_MAX_RETRIES); 1267 1268 if (retries == HINIC_INTR_CB_UNREG_MAX_RETRIES) 1269 PMD_DRV_LOG(ERR, "Unregister intr callback failed after %d retries", 1270 retries); 1271 1272 rte_bit_relaxed_clear32(HINIC_DEV_INIT, &nic_dev->dev_status); 1273 } 1274 1275 static int hinic_set_dev_promiscuous(struct hinic_nic_dev *nic_dev, bool enable) 1276 { 1277 u32 rx_mode_ctrl; 1278 int err; 1279 1280 err = hinic_mutex_lock(&nic_dev->rx_mode_mutex); 1281 if (err) 1282 return err; 1283 1284 rx_mode_ctrl = nic_dev->rx_mode_status; 1285 1286 if (enable) 1287 rx_mode_ctrl |= HINIC_RX_MODE_PROMISC; 1288 else 1289 rx_mode_ctrl &= (~HINIC_RX_MODE_PROMISC); 1290 1291 err = hinic_config_rx_mode(nic_dev, rx_mode_ctrl); 1292 1293 (void)hinic_mutex_unlock(&nic_dev->rx_mode_mutex); 1294 1295 return err; 1296 } 1297 1298 /** 1299 * DPDK callback to get device statistics. 1300 * 1301 * @param dev 1302 * Pointer to Ethernet device structure. 1303 * @param stats 1304 * Stats structure output buffer. 1305 * 1306 * @return 1307 * 0 on success and stats is filled, 1308 * negative error value otherwise. 1309 */ 1310 static int 1311 hinic_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 1312 { 1313 int i, err, q_num; 1314 u64 rx_discards_pmd = 0; 1315 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1316 struct hinic_vport_stats vport_stats; 1317 struct hinic_rxq *rxq = NULL; 1318 struct hinic_rxq_stats rxq_stats; 1319 struct hinic_txq *txq = NULL; 1320 struct hinic_txq_stats txq_stats; 1321 1322 err = hinic_get_vport_stats(nic_dev->hwdev, &vport_stats); 1323 if (err) { 1324 PMD_DRV_LOG(ERR, "Get vport stats from fw failed, nic_dev: %s", 1325 nic_dev->proc_dev_name); 1326 return err; 1327 } 1328 1329 dev->data->rx_mbuf_alloc_failed = 0; 1330 1331 /* rx queue stats */ 1332 q_num = (nic_dev->num_rq < RTE_ETHDEV_QUEUE_STAT_CNTRS) ? 1333 nic_dev->num_rq : RTE_ETHDEV_QUEUE_STAT_CNTRS; 1334 for (i = 0; i < q_num; i++) { 1335 rxq = nic_dev->rxqs[i]; 1336 hinic_rxq_get_stats(rxq, &rxq_stats); 1337 stats->q_ipackets[i] = rxq_stats.packets; 1338 stats->q_ibytes[i] = rxq_stats.bytes; 1339 stats->q_errors[i] = rxq_stats.rx_discards; 1340 1341 stats->ierrors += rxq_stats.errors; 1342 rx_discards_pmd += rxq_stats.rx_discards; 1343 dev->data->rx_mbuf_alloc_failed += rxq_stats.rx_nombuf; 1344 } 1345 1346 /* tx queue stats */ 1347 q_num = (nic_dev->num_sq < RTE_ETHDEV_QUEUE_STAT_CNTRS) ? 1348 nic_dev->num_sq : RTE_ETHDEV_QUEUE_STAT_CNTRS; 1349 for (i = 0; i < q_num; i++) { 1350 txq = nic_dev->txqs[i]; 1351 hinic_txq_get_stats(txq, &txq_stats); 1352 stats->q_opackets[i] = txq_stats.packets; 1353 stats->q_obytes[i] = txq_stats.bytes; 1354 stats->oerrors += (txq_stats.tx_busy + txq_stats.off_errs); 1355 } 1356 1357 /* vport stats */ 1358 stats->oerrors += vport_stats.tx_discard_vport; 1359 1360 stats->imissed = vport_stats.rx_discard_vport + rx_discards_pmd; 1361 1362 stats->ipackets = (vport_stats.rx_unicast_pkts_vport + 1363 vport_stats.rx_multicast_pkts_vport + 1364 vport_stats.rx_broadcast_pkts_vport - 1365 rx_discards_pmd); 1366 1367 stats->opackets = (vport_stats.tx_unicast_pkts_vport + 1368 vport_stats.tx_multicast_pkts_vport + 1369 vport_stats.tx_broadcast_pkts_vport); 1370 1371 stats->ibytes = (vport_stats.rx_unicast_bytes_vport + 1372 vport_stats.rx_multicast_bytes_vport + 1373 vport_stats.rx_broadcast_bytes_vport); 1374 1375 stats->obytes = (vport_stats.tx_unicast_bytes_vport + 1376 vport_stats.tx_multicast_bytes_vport + 1377 vport_stats.tx_broadcast_bytes_vport); 1378 return 0; 1379 } 1380 1381 /** 1382 * DPDK callback to clear device statistics. 1383 * 1384 * @param dev 1385 * Pointer to Ethernet device structure. 1386 */ 1387 static int hinic_dev_stats_reset(struct rte_eth_dev *dev) 1388 { 1389 int qid; 1390 struct hinic_rxq *rxq = NULL; 1391 struct hinic_txq *txq = NULL; 1392 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1393 int ret; 1394 1395 ret = hinic_clear_vport_stats(nic_dev->hwdev); 1396 if (ret != 0) 1397 return ret; 1398 1399 for (qid = 0; qid < nic_dev->num_rq; qid++) { 1400 rxq = nic_dev->rxqs[qid]; 1401 hinic_rxq_stats_reset(rxq); 1402 } 1403 1404 for (qid = 0; qid < nic_dev->num_sq; qid++) { 1405 txq = nic_dev->txqs[qid]; 1406 hinic_txq_stats_reset(txq); 1407 } 1408 1409 return 0; 1410 } 1411 1412 /** 1413 * DPDK callback to clear device extended statistics. 1414 * 1415 * @param dev 1416 * Pointer to Ethernet device structure. 1417 */ 1418 static int hinic_dev_xstats_reset(struct rte_eth_dev *dev) 1419 { 1420 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1421 int ret; 1422 1423 ret = hinic_dev_stats_reset(dev); 1424 if (ret != 0) 1425 return ret; 1426 1427 if (hinic_func_type(nic_dev->hwdev) != TYPE_VF) { 1428 ret = hinic_clear_phy_port_stats(nic_dev->hwdev); 1429 if (ret != 0) 1430 return ret; 1431 } 1432 1433 return 0; 1434 } 1435 1436 static void hinic_gen_random_mac_addr(struct rte_ether_addr *mac_addr) 1437 { 1438 uint64_t random_value; 1439 1440 /* Set Organizationally Unique Identifier (OUI) prefix */ 1441 mac_addr->addr_bytes[0] = 0x00; 1442 mac_addr->addr_bytes[1] = 0x09; 1443 mac_addr->addr_bytes[2] = 0xC0; 1444 /* Force indication of locally assigned MAC address. */ 1445 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR; 1446 /* Generate the last 3 bytes of the MAC address with a random number. */ 1447 random_value = rte_rand(); 1448 memcpy(&mac_addr->addr_bytes[3], &random_value, 3); 1449 } 1450 1451 /** 1452 * Init mac_vlan table in NIC. 1453 * 1454 * @param dev 1455 * Pointer to Ethernet device structure. 1456 * 1457 * @return 1458 * 0 on success and stats is filled, 1459 * negative error value otherwise. 1460 */ 1461 static int hinic_init_mac_addr(struct rte_eth_dev *eth_dev) 1462 { 1463 struct hinic_nic_dev *nic_dev = 1464 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); 1465 uint8_t addr_bytes[RTE_ETHER_ADDR_LEN]; 1466 u16 func_id = 0; 1467 int rc = 0; 1468 1469 rc = hinic_get_default_mac(nic_dev->hwdev, addr_bytes); 1470 if (rc) 1471 return rc; 1472 1473 rte_ether_addr_copy((struct rte_ether_addr *)addr_bytes, 1474 ð_dev->data->mac_addrs[0]); 1475 if (rte_is_zero_ether_addr(ð_dev->data->mac_addrs[0])) 1476 hinic_gen_random_mac_addr(ð_dev->data->mac_addrs[0]); 1477 1478 func_id = hinic_global_func_id(nic_dev->hwdev); 1479 rc = hinic_set_mac(nic_dev->hwdev, 1480 eth_dev->data->mac_addrs[0].addr_bytes, 1481 0, func_id); 1482 if (rc && rc != HINIC_PF_SET_VF_ALREADY) 1483 return rc; 1484 1485 rte_ether_addr_copy(ð_dev->data->mac_addrs[0], 1486 &nic_dev->default_addr); 1487 1488 return 0; 1489 } 1490 1491 static void hinic_delete_mc_addr_list(struct hinic_nic_dev *nic_dev) 1492 { 1493 u16 func_id; 1494 u32 i; 1495 1496 func_id = hinic_global_func_id(nic_dev->hwdev); 1497 1498 for (i = 0; i < HINIC_MAX_MC_MAC_ADDRS; i++) { 1499 if (rte_is_zero_ether_addr(&nic_dev->mc_list[i])) 1500 break; 1501 1502 hinic_del_mac(nic_dev->hwdev, nic_dev->mc_list[i].addr_bytes, 1503 0, func_id); 1504 memset(&nic_dev->mc_list[i], 0, sizeof(struct rte_ether_addr)); 1505 } 1506 } 1507 1508 /** 1509 * Deinit mac_vlan table in NIC. 1510 * 1511 * @param dev 1512 * Pointer to Ethernet device structure. 1513 * 1514 * @return 1515 * 0 on success and stats is filled, 1516 * negative error value otherwise. 1517 */ 1518 static void hinic_deinit_mac_addr(struct rte_eth_dev *eth_dev) 1519 { 1520 struct hinic_nic_dev *nic_dev = 1521 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); 1522 u16 func_id = 0; 1523 int rc; 1524 int i; 1525 1526 func_id = hinic_global_func_id(nic_dev->hwdev); 1527 1528 for (i = 0; i < HINIC_MAX_UC_MAC_ADDRS; i++) { 1529 if (rte_is_zero_ether_addr(ð_dev->data->mac_addrs[i])) 1530 continue; 1531 1532 rc = hinic_del_mac(nic_dev->hwdev, 1533 eth_dev->data->mac_addrs[i].addr_bytes, 1534 0, func_id); 1535 if (rc && rc != HINIC_PF_SET_VF_ALREADY) 1536 PMD_DRV_LOG(ERR, "Delete mac table failed, dev_name: %s", 1537 eth_dev->data->name); 1538 1539 memset(ð_dev->data->mac_addrs[i], 0, 1540 sizeof(struct rte_ether_addr)); 1541 } 1542 1543 /* delete multicast mac addrs */ 1544 hinic_delete_mc_addr_list(nic_dev); 1545 1546 rte_free(nic_dev->mc_list); 1547 1548 } 1549 1550 static int hinic_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 1551 { 1552 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1553 uint32_t frame_size; 1554 int ret = 0; 1555 1556 PMD_DRV_LOG(INFO, "Set port mtu, port_id: %d, mtu: %d, max_pkt_len: %d", 1557 dev->data->port_id, mtu, HINIC_MTU_TO_PKTLEN(mtu)); 1558 1559 if (mtu < HINIC_MIN_MTU_SIZE || mtu > HINIC_MAX_MTU_SIZE) { 1560 PMD_DRV_LOG(ERR, "Invalid mtu: %d, must between %d and %d", 1561 mtu, HINIC_MIN_MTU_SIZE, HINIC_MAX_MTU_SIZE); 1562 return -EINVAL; 1563 } 1564 1565 ret = hinic_set_port_mtu(nic_dev->hwdev, mtu); 1566 if (ret) { 1567 PMD_DRV_LOG(ERR, "Set port mtu failed, ret: %d", ret); 1568 return ret; 1569 } 1570 1571 /* update max frame size */ 1572 frame_size = HINIC_MTU_TO_PKTLEN(mtu); 1573 if (frame_size > RTE_ETHER_MAX_LEN) 1574 dev->data->dev_conf.rxmode.offloads |= 1575 DEV_RX_OFFLOAD_JUMBO_FRAME; 1576 else 1577 dev->data->dev_conf.rxmode.offloads &= 1578 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1579 1580 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1581 nic_dev->mtu_size = mtu; 1582 1583 return ret; 1584 } 1585 1586 static void hinic_store_vlan_filter(struct hinic_nic_dev *nic_dev, 1587 u16 vlan_id, bool on) 1588 { 1589 u32 vid_idx, vid_bit; 1590 1591 vid_idx = HINIC_VFTA_IDX(vlan_id); 1592 vid_bit = HINIC_VFTA_BIT(vlan_id); 1593 1594 if (on) 1595 nic_dev->vfta[vid_idx] |= vid_bit; 1596 else 1597 nic_dev->vfta[vid_idx] &= ~vid_bit; 1598 } 1599 1600 static bool hinic_find_vlan_filter(struct hinic_nic_dev *nic_dev, 1601 uint16_t vlan_id) 1602 { 1603 u32 vid_idx, vid_bit; 1604 1605 vid_idx = HINIC_VFTA_IDX(vlan_id); 1606 vid_bit = HINIC_VFTA_BIT(vlan_id); 1607 1608 return (nic_dev->vfta[vid_idx] & vid_bit) ? TRUE : FALSE; 1609 } 1610 1611 /** 1612 * DPDK callback to set vlan filter. 1613 * 1614 * @param dev 1615 * Pointer to Ethernet device structure. 1616 * @param vlan_id 1617 * vlan id is used to filter vlan packets 1618 * @param enable 1619 * enable disable or enable vlan filter function 1620 */ 1621 static int hinic_vlan_filter_set(struct rte_eth_dev *dev, 1622 uint16_t vlan_id, int enable) 1623 { 1624 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1625 int err = 0; 1626 u16 func_id; 1627 1628 if (vlan_id > RTE_ETHER_MAX_VLAN_ID) 1629 return -EINVAL; 1630 1631 func_id = hinic_global_func_id(nic_dev->hwdev); 1632 1633 if (enable) { 1634 /* If vlanid is already set, just return */ 1635 if (hinic_find_vlan_filter(nic_dev, vlan_id)) { 1636 PMD_DRV_LOG(INFO, "Vlan %u has been added, device: %s", 1637 vlan_id, nic_dev->proc_dev_name); 1638 return 0; 1639 } 1640 1641 err = hinic_add_remove_vlan(nic_dev->hwdev, vlan_id, 1642 func_id, TRUE); 1643 } else { 1644 /* If vlanid can't be found, just return */ 1645 if (!hinic_find_vlan_filter(nic_dev, vlan_id)) { 1646 PMD_DRV_LOG(INFO, "Vlan %u is not in the vlan filter list, device: %s", 1647 vlan_id, nic_dev->proc_dev_name); 1648 return 0; 1649 } 1650 1651 err = hinic_add_remove_vlan(nic_dev->hwdev, vlan_id, 1652 func_id, FALSE); 1653 } 1654 1655 if (err) { 1656 PMD_DRV_LOG(ERR, "%s vlan failed, func_id: %d, vlan_id: %d, err: %d", 1657 enable ? "Add" : "Remove", func_id, vlan_id, err); 1658 return err; 1659 } 1660 1661 hinic_store_vlan_filter(nic_dev, vlan_id, enable); 1662 1663 PMD_DRV_LOG(INFO, "%s vlan %u succeed, device: %s", 1664 enable ? "Add" : "Remove", vlan_id, nic_dev->proc_dev_name); 1665 return 0; 1666 } 1667 1668 /** 1669 * DPDK callback to enable or disable vlan offload. 1670 * 1671 * @param dev 1672 * Pointer to Ethernet device structure. 1673 * @param mask 1674 * Definitions used for VLAN setting 1675 */ 1676 static int hinic_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1677 { 1678 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1679 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1680 bool on; 1681 int err; 1682 1683 /* Enable or disable VLAN filter */ 1684 if (mask & ETH_VLAN_FILTER_MASK) { 1685 on = (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) ? 1686 TRUE : FALSE; 1687 err = hinic_config_vlan_filter(nic_dev->hwdev, on); 1688 if (err == HINIC_MGMT_CMD_UNSUPPORTED) { 1689 PMD_DRV_LOG(WARNING, 1690 "Current matching version does not support vlan filter configuration, device: %s, port_id: %d", 1691 nic_dev->proc_dev_name, dev->data->port_id); 1692 } else if (err) { 1693 PMD_DRV_LOG(ERR, "Failed to %s vlan filter, device: %s, port_id: %d, err: %d", 1694 on ? "enable" : "disable", 1695 nic_dev->proc_dev_name, 1696 dev->data->port_id, err); 1697 return err; 1698 } 1699 1700 PMD_DRV_LOG(INFO, "%s vlan filter succeed, device: %s, port_id: %d", 1701 on ? "Enable" : "Disable", 1702 nic_dev->proc_dev_name, dev->data->port_id); 1703 } 1704 1705 /* Enable or disable VLAN stripping */ 1706 if (mask & ETH_VLAN_STRIP_MASK) { 1707 on = (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) ? 1708 TRUE : FALSE; 1709 err = hinic_set_rx_vlan_offload(nic_dev->hwdev, on); 1710 if (err) { 1711 PMD_DRV_LOG(ERR, "Failed to %s vlan strip, device: %s, port_id: %d, err: %d", 1712 on ? "enable" : "disable", 1713 nic_dev->proc_dev_name, 1714 dev->data->port_id, err); 1715 return err; 1716 } 1717 1718 PMD_DRV_LOG(INFO, "%s vlan strip succeed, device: %s, port_id: %d", 1719 on ? "Enable" : "Disable", 1720 nic_dev->proc_dev_name, dev->data->port_id); 1721 } 1722 1723 return 0; 1724 } 1725 1726 static void hinic_remove_all_vlanid(struct rte_eth_dev *eth_dev) 1727 { 1728 struct hinic_nic_dev *nic_dev = 1729 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); 1730 u16 func_id; 1731 int i; 1732 1733 func_id = hinic_global_func_id(nic_dev->hwdev); 1734 for (i = 0; i <= RTE_ETHER_MAX_VLAN_ID; i++) { 1735 /* If can't find it, continue */ 1736 if (!hinic_find_vlan_filter(nic_dev, i)) 1737 continue; 1738 1739 (void)hinic_add_remove_vlan(nic_dev->hwdev, i, func_id, FALSE); 1740 hinic_store_vlan_filter(nic_dev, i, false); 1741 } 1742 } 1743 1744 static int hinic_set_dev_allmulticast(struct hinic_nic_dev *nic_dev, 1745 bool enable) 1746 { 1747 u32 rx_mode_ctrl; 1748 int err; 1749 1750 err = hinic_mutex_lock(&nic_dev->rx_mode_mutex); 1751 if (err) 1752 return err; 1753 1754 rx_mode_ctrl = nic_dev->rx_mode_status; 1755 1756 if (enable) 1757 rx_mode_ctrl |= HINIC_RX_MODE_MC_ALL; 1758 else 1759 rx_mode_ctrl &= (~HINIC_RX_MODE_MC_ALL); 1760 1761 err = hinic_config_rx_mode(nic_dev, rx_mode_ctrl); 1762 1763 (void)hinic_mutex_unlock(&nic_dev->rx_mode_mutex); 1764 1765 return err; 1766 } 1767 1768 /** 1769 * DPDK callback to enable allmulticast mode. 1770 * 1771 * @param dev 1772 * Pointer to Ethernet device structure. 1773 * 1774 * @return 1775 * 0 on success, 1776 * negative error value otherwise. 1777 */ 1778 static int hinic_dev_allmulticast_enable(struct rte_eth_dev *dev) 1779 { 1780 int ret = HINIC_OK; 1781 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1782 1783 ret = hinic_set_dev_allmulticast(nic_dev, true); 1784 if (ret) { 1785 PMD_DRV_LOG(ERR, "Enable allmulticast failed, error: %d", ret); 1786 return ret; 1787 } 1788 1789 PMD_DRV_LOG(INFO, "Enable allmulticast succeed, nic_dev: %s, port_id: %d", 1790 nic_dev->proc_dev_name, dev->data->port_id); 1791 return 0; 1792 } 1793 1794 /** 1795 * DPDK callback to disable allmulticast mode. 1796 * 1797 * @param dev 1798 * Pointer to Ethernet device structure. 1799 * 1800 * @return 1801 * 0 on success, 1802 * negative error value otherwise. 1803 */ 1804 static int hinic_dev_allmulticast_disable(struct rte_eth_dev *dev) 1805 { 1806 int ret = HINIC_OK; 1807 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1808 1809 ret = hinic_set_dev_allmulticast(nic_dev, false); 1810 if (ret) { 1811 PMD_DRV_LOG(ERR, "Disable allmulticast failed, error: %d", ret); 1812 return ret; 1813 } 1814 1815 PMD_DRV_LOG(INFO, "Disable allmulticast succeed, nic_dev: %s, port_id: %d", 1816 nic_dev->proc_dev_name, dev->data->port_id); 1817 return 0; 1818 } 1819 1820 /** 1821 * DPDK callback to enable promiscuous mode. 1822 * 1823 * @param dev 1824 * Pointer to Ethernet device structure. 1825 * 1826 * @return 1827 * 0 on success, 1828 * negative error value otherwise. 1829 */ 1830 static int hinic_dev_promiscuous_enable(struct rte_eth_dev *dev) 1831 { 1832 int rc = HINIC_OK; 1833 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1834 1835 PMD_DRV_LOG(INFO, "Enable promiscuous, nic_dev: %s, port_id: %d, promisc: %d", 1836 nic_dev->proc_dev_name, dev->data->port_id, 1837 dev->data->promiscuous); 1838 1839 rc = hinic_set_dev_promiscuous(nic_dev, true); 1840 if (rc) 1841 PMD_DRV_LOG(ERR, "Enable promiscuous failed"); 1842 1843 return rc; 1844 } 1845 1846 /** 1847 * DPDK callback to disable promiscuous mode. 1848 * 1849 * @param dev 1850 * Pointer to Ethernet device structure. 1851 * 1852 * @return 1853 * 0 on success, 1854 * negative error value otherwise. 1855 */ 1856 static int hinic_dev_promiscuous_disable(struct rte_eth_dev *dev) 1857 { 1858 int rc = HINIC_OK; 1859 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1860 1861 PMD_DRV_LOG(INFO, "Disable promiscuous, nic_dev: %s, port_id: %d, promisc: %d", 1862 nic_dev->proc_dev_name, dev->data->port_id, 1863 dev->data->promiscuous); 1864 1865 rc = hinic_set_dev_promiscuous(nic_dev, false); 1866 if (rc) 1867 PMD_DRV_LOG(ERR, "Disable promiscuous failed"); 1868 1869 return rc; 1870 } 1871 1872 static int hinic_flow_ctrl_get(struct rte_eth_dev *dev, 1873 struct rte_eth_fc_conf *fc_conf) 1874 { 1875 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1876 struct nic_pause_config nic_pause; 1877 int err; 1878 1879 memset(&nic_pause, 0, sizeof(nic_pause)); 1880 1881 err = hinic_get_pause_info(nic_dev->hwdev, &nic_pause); 1882 if (err) 1883 return err; 1884 1885 if (nic_dev->pause_set || !nic_pause.auto_neg) { 1886 nic_pause.rx_pause = nic_dev->nic_pause.rx_pause; 1887 nic_pause.tx_pause = nic_dev->nic_pause.tx_pause; 1888 } 1889 1890 fc_conf->autoneg = nic_pause.auto_neg; 1891 1892 if (nic_pause.tx_pause && nic_pause.rx_pause) 1893 fc_conf->mode = RTE_FC_FULL; 1894 else if (nic_pause.tx_pause) 1895 fc_conf->mode = RTE_FC_TX_PAUSE; 1896 else if (nic_pause.rx_pause) 1897 fc_conf->mode = RTE_FC_RX_PAUSE; 1898 else 1899 fc_conf->mode = RTE_FC_NONE; 1900 1901 return 0; 1902 } 1903 1904 static int hinic_flow_ctrl_set(struct rte_eth_dev *dev, 1905 struct rte_eth_fc_conf *fc_conf) 1906 { 1907 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1908 struct nic_pause_config nic_pause; 1909 int err; 1910 1911 nic_pause.auto_neg = fc_conf->autoneg; 1912 1913 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 1914 (fc_conf->mode & RTE_FC_TX_PAUSE)) 1915 nic_pause.tx_pause = true; 1916 else 1917 nic_pause.tx_pause = false; 1918 1919 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 1920 (fc_conf->mode & RTE_FC_RX_PAUSE)) 1921 nic_pause.rx_pause = true; 1922 else 1923 nic_pause.rx_pause = false; 1924 1925 err = hinic_set_pause_config(nic_dev->hwdev, nic_pause); 1926 if (err) 1927 return err; 1928 1929 nic_dev->pause_set = true; 1930 nic_dev->nic_pause.auto_neg = nic_pause.auto_neg; 1931 nic_dev->nic_pause.rx_pause = nic_pause.rx_pause; 1932 nic_dev->nic_pause.tx_pause = nic_pause.tx_pause; 1933 1934 PMD_DRV_LOG(INFO, "Set pause options, tx: %s, rx: %s, auto: %s\n", 1935 nic_pause.tx_pause ? "on" : "off", 1936 nic_pause.rx_pause ? "on" : "off", 1937 nic_pause.auto_neg ? "on" : "off"); 1938 1939 return 0; 1940 } 1941 1942 /** 1943 * DPDK callback to update the RSS hash key and RSS hash type. 1944 * 1945 * @param dev 1946 * Pointer to Ethernet device structure. 1947 * @param rss_conf 1948 * RSS configuration data. 1949 * 1950 * @return 1951 * 0 on success, negative error value otherwise. 1952 */ 1953 static int hinic_rss_hash_update(struct rte_eth_dev *dev, 1954 struct rte_eth_rss_conf *rss_conf) 1955 { 1956 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 1957 u8 tmpl_idx = nic_dev->rss_tmpl_idx; 1958 u8 hashkey[HINIC_RSS_KEY_SIZE] = {0}; 1959 u8 prio_tc[HINIC_DCB_UP_MAX] = {0}; 1960 u64 rss_hf = rss_conf->rss_hf; 1961 struct nic_rss_type rss_type = {0}; 1962 int err = 0; 1963 1964 if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) { 1965 PMD_DRV_LOG(WARNING, "RSS is not enabled"); 1966 return HINIC_OK; 1967 } 1968 1969 if (rss_conf->rss_key_len > HINIC_RSS_KEY_SIZE) { 1970 PMD_DRV_LOG(ERR, "Invalid rss key, rss_key_len: %d", 1971 rss_conf->rss_key_len); 1972 return HINIC_ERROR; 1973 } 1974 1975 if (rss_conf->rss_key) { 1976 memcpy(hashkey, rss_conf->rss_key, rss_conf->rss_key_len); 1977 err = hinic_rss_set_template_tbl(nic_dev->hwdev, tmpl_idx, 1978 hashkey); 1979 if (err) { 1980 PMD_DRV_LOG(ERR, "Set rss template table failed"); 1981 goto disable_rss; 1982 } 1983 } 1984 1985 rss_type.ipv4 = (rss_hf & (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4)) ? 1 : 0; 1986 rss_type.tcp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) ? 1 : 0; 1987 rss_type.ipv6 = (rss_hf & (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6)) ? 1 : 0; 1988 rss_type.ipv6_ext = (rss_hf & ETH_RSS_IPV6_EX) ? 1 : 0; 1989 rss_type.tcp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) ? 1 : 0; 1990 rss_type.tcp_ipv6_ext = (rss_hf & ETH_RSS_IPV6_TCP_EX) ? 1 : 0; 1991 rss_type.udp_ipv4 = (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) ? 1 : 0; 1992 rss_type.udp_ipv6 = (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) ? 1 : 0; 1993 1994 err = hinic_set_rss_type(nic_dev->hwdev, tmpl_idx, rss_type); 1995 if (err) { 1996 PMD_DRV_LOG(ERR, "Set rss type table failed"); 1997 goto disable_rss; 1998 } 1999 2000 return 0; 2001 2002 disable_rss: 2003 memset(prio_tc, 0, sizeof(prio_tc)); 2004 (void)hinic_rss_cfg(nic_dev->hwdev, 0, tmpl_idx, 0, prio_tc); 2005 return err; 2006 } 2007 2008 /** 2009 * DPDK callback to get the RSS hash configuration. 2010 * 2011 * @param dev 2012 * Pointer to Ethernet device structure. 2013 * @param rss_conf 2014 * RSS configuration data. 2015 * 2016 * @return 2017 * 0 on success, negative error value otherwise. 2018 */ 2019 static int hinic_rss_conf_get(struct rte_eth_dev *dev, 2020 struct rte_eth_rss_conf *rss_conf) 2021 { 2022 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2023 u8 tmpl_idx = nic_dev->rss_tmpl_idx; 2024 u8 hashkey[HINIC_RSS_KEY_SIZE] = {0}; 2025 struct nic_rss_type rss_type = {0}; 2026 int err; 2027 2028 if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) { 2029 PMD_DRV_LOG(WARNING, "RSS is not enabled"); 2030 return HINIC_ERROR; 2031 } 2032 2033 err = hinic_rss_get_template_tbl(nic_dev->hwdev, tmpl_idx, hashkey); 2034 if (err) 2035 return err; 2036 2037 if (rss_conf->rss_key && 2038 rss_conf->rss_key_len >= HINIC_RSS_KEY_SIZE) { 2039 memcpy(rss_conf->rss_key, hashkey, sizeof(hashkey)); 2040 rss_conf->rss_key_len = sizeof(hashkey); 2041 } 2042 2043 err = hinic_get_rss_type(nic_dev->hwdev, tmpl_idx, &rss_type); 2044 if (err) 2045 return err; 2046 2047 rss_conf->rss_hf = 0; 2048 rss_conf->rss_hf |= rss_type.ipv4 ? 2049 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4) : 0; 2050 rss_conf->rss_hf |= rss_type.tcp_ipv4 ? ETH_RSS_NONFRAG_IPV4_TCP : 0; 2051 rss_conf->rss_hf |= rss_type.ipv6 ? 2052 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6) : 0; 2053 rss_conf->rss_hf |= rss_type.ipv6_ext ? ETH_RSS_IPV6_EX : 0; 2054 rss_conf->rss_hf |= rss_type.tcp_ipv6 ? ETH_RSS_NONFRAG_IPV6_TCP : 0; 2055 rss_conf->rss_hf |= rss_type.tcp_ipv6_ext ? ETH_RSS_IPV6_TCP_EX : 0; 2056 rss_conf->rss_hf |= rss_type.udp_ipv4 ? ETH_RSS_NONFRAG_IPV4_UDP : 0; 2057 rss_conf->rss_hf |= rss_type.udp_ipv6 ? ETH_RSS_NONFRAG_IPV6_UDP : 0; 2058 2059 return HINIC_OK; 2060 } 2061 2062 /** 2063 * DPDK callback to update the RSS redirection table. 2064 * 2065 * @param dev 2066 * Pointer to Ethernet device structure. 2067 * @param reta_conf 2068 * Pointer to RSS reta configuration data. 2069 * @param reta_size 2070 * Size of the RETA table. 2071 * 2072 * @return 2073 * 0 on success, negative error value otherwise. 2074 */ 2075 static int hinic_rss_indirtbl_update(struct rte_eth_dev *dev, 2076 struct rte_eth_rss_reta_entry64 *reta_conf, 2077 uint16_t reta_size) 2078 { 2079 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2080 u8 tmpl_idx = nic_dev->rss_tmpl_idx; 2081 u8 prio_tc[HINIC_DCB_UP_MAX] = {0}; 2082 u32 indirtbl[NIC_RSS_INDIR_SIZE] = {0}; 2083 int err = 0; 2084 u16 i = 0; 2085 u16 idx, shift; 2086 2087 if (!(nic_dev->flags & ETH_MQ_RX_RSS_FLAG)) 2088 return HINIC_OK; 2089 2090 if (reta_size != NIC_RSS_INDIR_SIZE) { 2091 PMD_DRV_LOG(ERR, "Invalid reta size, reta_size: %d", reta_size); 2092 return HINIC_ERROR; 2093 } 2094 2095 err = hinic_rss_get_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl); 2096 if (err) 2097 return err; 2098 2099 /* update rss indir_tbl */ 2100 for (i = 0; i < reta_size; i++) { 2101 idx = i / RTE_RETA_GROUP_SIZE; 2102 shift = i % RTE_RETA_GROUP_SIZE; 2103 2104 if (reta_conf[idx].reta[shift] >= nic_dev->num_rq) { 2105 PMD_DRV_LOG(ERR, "Invalid reta entry, indirtbl[%d]: %d " 2106 "exceeds the maximum rxq num: %d", i, 2107 reta_conf[idx].reta[shift], nic_dev->num_rq); 2108 return -EINVAL; 2109 } 2110 2111 if (reta_conf[idx].mask & (1ULL << shift)) 2112 indirtbl[i] = reta_conf[idx].reta[shift]; 2113 } 2114 2115 err = hinic_rss_set_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl); 2116 if (err) 2117 goto disable_rss; 2118 2119 nic_dev->rss_indir_flag = true; 2120 2121 return 0; 2122 2123 disable_rss: 2124 memset(prio_tc, 0, sizeof(prio_tc)); 2125 (void)hinic_rss_cfg(nic_dev->hwdev, 0, tmpl_idx, 0, prio_tc); 2126 2127 return HINIC_ERROR; 2128 } 2129 2130 /** 2131 * DPDK callback to get the RSS indirection table. 2132 * 2133 * @param dev 2134 * Pointer to Ethernet device structure. 2135 * @param reta_conf 2136 * Pointer to RSS reta configuration data. 2137 * @param reta_size 2138 * Size of the RETA table. 2139 * 2140 * @return 2141 * 0 on success, negative error value otherwise. 2142 */ 2143 static int hinic_rss_indirtbl_query(struct rte_eth_dev *dev, 2144 struct rte_eth_rss_reta_entry64 *reta_conf, 2145 uint16_t reta_size) 2146 { 2147 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2148 u8 tmpl_idx = nic_dev->rss_tmpl_idx; 2149 int err = 0; 2150 u32 indirtbl[NIC_RSS_INDIR_SIZE] = {0}; 2151 u16 idx, shift; 2152 u16 i = 0; 2153 2154 if (reta_size != NIC_RSS_INDIR_SIZE) { 2155 PMD_DRV_LOG(ERR, "Invalid reta size, reta_size: %d", reta_size); 2156 return HINIC_ERROR; 2157 } 2158 2159 err = hinic_rss_get_indir_tbl(nic_dev->hwdev, tmpl_idx, indirtbl); 2160 if (err) { 2161 PMD_DRV_LOG(ERR, "Get rss indirect table failed, error: %d", 2162 err); 2163 return err; 2164 } 2165 2166 for (i = 0; i < reta_size; i++) { 2167 idx = i / RTE_RETA_GROUP_SIZE; 2168 shift = i % RTE_RETA_GROUP_SIZE; 2169 if (reta_conf[idx].mask & (1ULL << shift)) 2170 reta_conf[idx].reta[shift] = (uint16_t)indirtbl[i]; 2171 } 2172 2173 return HINIC_OK; 2174 } 2175 2176 /** 2177 * DPDK callback to get extended device statistics. 2178 * 2179 * @param dev 2180 * Pointer to Ethernet device. 2181 * @param xstats 2182 * Pointer to rte extended stats table. 2183 * @param n 2184 * The size of the stats table. 2185 * 2186 * @return 2187 * Number of extended stats on success and stats is filled, 2188 * negative error value otherwise. 2189 */ 2190 static int hinic_dev_xstats_get(struct rte_eth_dev *dev, 2191 struct rte_eth_xstat *xstats, 2192 unsigned int n) 2193 { 2194 u16 qid = 0; 2195 u32 i; 2196 int err, count; 2197 struct hinic_nic_dev *nic_dev; 2198 struct hinic_phy_port_stats port_stats; 2199 struct hinic_vport_stats vport_stats; 2200 struct hinic_rxq *rxq = NULL; 2201 struct hinic_rxq_stats rxq_stats; 2202 struct hinic_txq *txq = NULL; 2203 struct hinic_txq_stats txq_stats; 2204 2205 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2206 count = hinic_xstats_calc_num(nic_dev); 2207 if ((int)n < count) 2208 return count; 2209 2210 count = 0; 2211 2212 /* Get stats from hinic_rxq_stats */ 2213 for (qid = 0; qid < nic_dev->num_rq; qid++) { 2214 rxq = nic_dev->rxqs[qid]; 2215 hinic_rxq_get_stats(rxq, &rxq_stats); 2216 2217 for (i = 0; i < HINIC_RXQ_XSTATS_NUM; i++) { 2218 xstats[count].value = 2219 *(uint64_t *)(((char *)&rxq_stats) + 2220 hinic_rxq_stats_strings[i].offset); 2221 xstats[count].id = count; 2222 count++; 2223 } 2224 } 2225 2226 /* Get stats from hinic_txq_stats */ 2227 for (qid = 0; qid < nic_dev->num_sq; qid++) { 2228 txq = nic_dev->txqs[qid]; 2229 hinic_txq_get_stats(txq, &txq_stats); 2230 2231 for (i = 0; i < HINIC_TXQ_XSTATS_NUM; i++) { 2232 xstats[count].value = 2233 *(uint64_t *)(((char *)&txq_stats) + 2234 hinic_txq_stats_strings[i].offset); 2235 xstats[count].id = count; 2236 count++; 2237 } 2238 } 2239 2240 /* Get stats from hinic_vport_stats */ 2241 err = hinic_get_vport_stats(nic_dev->hwdev, &vport_stats); 2242 if (err) 2243 return err; 2244 2245 for (i = 0; i < HINIC_VPORT_XSTATS_NUM; i++) { 2246 xstats[count].value = 2247 *(uint64_t *)(((char *)&vport_stats) + 2248 hinic_vport_stats_strings[i].offset); 2249 xstats[count].id = count; 2250 count++; 2251 } 2252 2253 if (HINIC_IS_VF(nic_dev->hwdev)) 2254 return count; 2255 2256 /* Get stats from hinic_phy_port_stats */ 2257 err = hinic_get_phy_port_stats(nic_dev->hwdev, &port_stats); 2258 if (err) 2259 return err; 2260 2261 for (i = 0; i < HINIC_PHYPORT_XSTATS_NUM; i++) { 2262 xstats[count].value = *(uint64_t *)(((char *)&port_stats) + 2263 hinic_phyport_stats_strings[i].offset); 2264 xstats[count].id = count; 2265 count++; 2266 } 2267 2268 return count; 2269 } 2270 2271 static void hinic_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2272 struct rte_eth_rxq_info *qinfo) 2273 { 2274 struct hinic_rxq *rxq = dev->data->rx_queues[queue_id]; 2275 2276 qinfo->mp = rxq->mb_pool; 2277 qinfo->nb_desc = rxq->q_depth; 2278 } 2279 2280 static void hinic_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2281 struct rte_eth_txq_info *qinfo) 2282 { 2283 struct hinic_txq *txq = dev->data->tx_queues[queue_id]; 2284 2285 qinfo->nb_desc = txq->q_depth; 2286 } 2287 2288 /** 2289 * DPDK callback to retrieve names of extended device statistics 2290 * 2291 * @param dev 2292 * Pointer to Ethernet device structure. 2293 * @param xstats_names 2294 * Buffer to insert names into. 2295 * 2296 * @return 2297 * Number of xstats names. 2298 */ 2299 static int hinic_dev_xstats_get_names(struct rte_eth_dev *dev, 2300 struct rte_eth_xstat_name *xstats_names, 2301 __rte_unused unsigned int limit) 2302 { 2303 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2304 int count = 0; 2305 u16 i = 0, q_num; 2306 2307 if (xstats_names == NULL) 2308 return hinic_xstats_calc_num(nic_dev); 2309 2310 /* get pmd rxq stats */ 2311 for (q_num = 0; q_num < nic_dev->num_rq; q_num++) { 2312 for (i = 0; i < HINIC_RXQ_XSTATS_NUM; i++) { 2313 snprintf(xstats_names[count].name, 2314 sizeof(xstats_names[count].name), 2315 "rxq%d_%s_pmd", 2316 q_num, hinic_rxq_stats_strings[i].name); 2317 count++; 2318 } 2319 } 2320 2321 /* get pmd txq stats */ 2322 for (q_num = 0; q_num < nic_dev->num_sq; q_num++) { 2323 for (i = 0; i < HINIC_TXQ_XSTATS_NUM; i++) { 2324 snprintf(xstats_names[count].name, 2325 sizeof(xstats_names[count].name), 2326 "txq%d_%s_pmd", 2327 q_num, hinic_txq_stats_strings[i].name); 2328 count++; 2329 } 2330 } 2331 2332 /* get vport stats */ 2333 for (i = 0; i < HINIC_VPORT_XSTATS_NUM; i++) { 2334 snprintf(xstats_names[count].name, 2335 sizeof(xstats_names[count].name), 2336 "%s", hinic_vport_stats_strings[i].name); 2337 count++; 2338 } 2339 2340 if (HINIC_IS_VF(nic_dev->hwdev)) 2341 return count; 2342 2343 /* get phy port stats */ 2344 for (i = 0; i < HINIC_PHYPORT_XSTATS_NUM; i++) { 2345 snprintf(xstats_names[count].name, 2346 sizeof(xstats_names[count].name), 2347 "%s", hinic_phyport_stats_strings[i].name); 2348 count++; 2349 } 2350 2351 return count; 2352 } 2353 2354 /** 2355 * DPDK callback to set mac address 2356 * 2357 * @param dev 2358 * Pointer to Ethernet device structure. 2359 * @param addr 2360 * Pointer to mac address 2361 * @return 2362 * 0 on success, negative error value otherwise. 2363 */ 2364 static int hinic_set_mac_addr(struct rte_eth_dev *dev, 2365 struct rte_ether_addr *addr) 2366 { 2367 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2368 u16 func_id; 2369 int err; 2370 2371 func_id = hinic_global_func_id(nic_dev->hwdev); 2372 err = hinic_update_mac(nic_dev->hwdev, nic_dev->default_addr.addr_bytes, 2373 addr->addr_bytes, 0, func_id); 2374 if (err) 2375 return err; 2376 2377 rte_ether_addr_copy(addr, &nic_dev->default_addr); 2378 2379 PMD_DRV_LOG(INFO, "Set new mac address %02x:%02x:%02x:%02x:%02x:%02x", 2380 addr->addr_bytes[0], addr->addr_bytes[1], 2381 addr->addr_bytes[2], addr->addr_bytes[3], 2382 addr->addr_bytes[4], addr->addr_bytes[5]); 2383 2384 return 0; 2385 } 2386 2387 /** 2388 * DPDK callback to remove a MAC address. 2389 * 2390 * @param dev 2391 * Pointer to Ethernet device structure. 2392 * @param index 2393 * MAC address index, should less than 128. 2394 */ 2395 static void hinic_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 2396 { 2397 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2398 u16 func_id; 2399 int ret; 2400 2401 if (index >= HINIC_MAX_UC_MAC_ADDRS) { 2402 PMD_DRV_LOG(INFO, "Remove mac index(%u) is out of range", 2403 index); 2404 return; 2405 } 2406 2407 func_id = hinic_global_func_id(nic_dev->hwdev); 2408 ret = hinic_del_mac(nic_dev->hwdev, 2409 dev->data->mac_addrs[index].addr_bytes, 0, func_id); 2410 if (ret) 2411 return; 2412 2413 memset(&dev->data->mac_addrs[index], 0, sizeof(struct rte_ether_addr)); 2414 } 2415 2416 /** 2417 * DPDK callback to add a MAC address. 2418 * 2419 * @param dev 2420 * Pointer to Ethernet device structure. 2421 * @param mac_addr 2422 * Pointer to MAC address 2423 * @param index 2424 * MAC address index, should less than 128. 2425 * @param vmdq 2426 * VMDq pool index(not used). 2427 * 2428 * @return 2429 * 0 on success, negative error value otherwise. 2430 */ 2431 static int hinic_mac_addr_add(struct rte_eth_dev *dev, 2432 struct rte_ether_addr *mac_addr, uint32_t index, 2433 __rte_unused uint32_t vmdq) 2434 { 2435 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2436 unsigned int i; 2437 u16 func_id; 2438 int ret; 2439 2440 if (index >= HINIC_MAX_UC_MAC_ADDRS) { 2441 PMD_DRV_LOG(INFO, "Add mac index(%u) is out of range", index); 2442 return -EINVAL; 2443 } 2444 2445 /* First, make sure this address isn't already configured. */ 2446 for (i = 0; (i != HINIC_MAX_UC_MAC_ADDRS); ++i) { 2447 /* Skip this index, it's going to be reconfigured. */ 2448 if (i == index) 2449 continue; 2450 2451 if (memcmp(&dev->data->mac_addrs[i], 2452 mac_addr, sizeof(*mac_addr))) 2453 continue; 2454 2455 PMD_DRV_LOG(INFO, "MAC address already configured"); 2456 return -EADDRINUSE; 2457 } 2458 2459 func_id = hinic_global_func_id(nic_dev->hwdev); 2460 ret = hinic_set_mac(nic_dev->hwdev, mac_addr->addr_bytes, 0, func_id); 2461 if (ret) 2462 return ret; 2463 2464 dev->data->mac_addrs[index] = *mac_addr; 2465 return 0; 2466 } 2467 2468 /** 2469 * DPDK callback to set multicast mac address 2470 * 2471 * @param dev 2472 * Pointer to Ethernet device structure. 2473 * @param mc_addr_set 2474 * Pointer to multicast mac address 2475 * @param nb_mc_addr 2476 * mc addr count 2477 * @return 2478 * 0 on success, negative error value otherwise. 2479 */ 2480 static int hinic_set_mc_addr_list(struct rte_eth_dev *dev, 2481 struct rte_ether_addr *mc_addr_set, 2482 uint32_t nb_mc_addr) 2483 { 2484 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2485 u16 func_id; 2486 int ret; 2487 u32 i; 2488 2489 func_id = hinic_global_func_id(nic_dev->hwdev); 2490 2491 /* delete old multi_cast addrs firstly */ 2492 hinic_delete_mc_addr_list(nic_dev); 2493 2494 if (nb_mc_addr > HINIC_MAX_MC_MAC_ADDRS) 2495 goto allmulti; 2496 2497 for (i = 0; i < nb_mc_addr; i++) { 2498 ret = hinic_set_mac(nic_dev->hwdev, mc_addr_set[i].addr_bytes, 2499 0, func_id); 2500 /* if add mc addr failed, set all multi_cast */ 2501 if (ret) { 2502 hinic_delete_mc_addr_list(nic_dev); 2503 goto allmulti; 2504 } 2505 2506 rte_ether_addr_copy(&mc_addr_set[i], &nic_dev->mc_list[i]); 2507 } 2508 2509 return 0; 2510 2511 allmulti: 2512 hinic_dev_allmulticast_enable(dev); 2513 2514 return 0; 2515 } 2516 2517 /** 2518 * DPDK callback to manage filter control operations 2519 * 2520 * @param dev 2521 * Pointer to Ethernet device structure. 2522 * @param filter_type 2523 * Filter type, which just supports generic type. 2524 * @param filter_op 2525 * Filter operation to perform. 2526 * @param arg 2527 * Pointer to operation-specific structure. 2528 * 2529 * @return 2530 * 0 on success, negative error value otherwise. 2531 */ 2532 static int hinic_dev_filter_ctrl(struct rte_eth_dev *dev, 2533 enum rte_filter_type filter_type, 2534 enum rte_filter_op filter_op, 2535 void *arg) 2536 { 2537 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2538 int func_id = hinic_global_func_id(nic_dev->hwdev); 2539 2540 switch (filter_type) { 2541 case RTE_ETH_FILTER_GENERIC: 2542 if (filter_op != RTE_ETH_FILTER_GET) 2543 return -EINVAL; 2544 *(const void **)arg = &hinic_flow_ops; 2545 break; 2546 default: 2547 PMD_DRV_LOG(INFO, "Filter type (%d) not supported", 2548 filter_type); 2549 return -EINVAL; 2550 } 2551 2552 PMD_DRV_LOG(INFO, "Set filter_ctrl succeed, func_id: 0x%x, filter_type: 0x%x," 2553 "filter_op: 0x%x.", func_id, filter_type, filter_op); 2554 return 0; 2555 } 2556 2557 static int hinic_set_default_pause_feature(struct hinic_nic_dev *nic_dev) 2558 { 2559 struct nic_pause_config pause_config = {0}; 2560 int err; 2561 2562 pause_config.auto_neg = 0; 2563 pause_config.rx_pause = HINIC_DEFAUT_PAUSE_CONFIG; 2564 pause_config.tx_pause = HINIC_DEFAUT_PAUSE_CONFIG; 2565 2566 err = hinic_set_pause_config(nic_dev->hwdev, pause_config); 2567 if (err) 2568 return err; 2569 2570 nic_dev->pause_set = true; 2571 nic_dev->nic_pause.auto_neg = pause_config.auto_neg; 2572 nic_dev->nic_pause.rx_pause = pause_config.rx_pause; 2573 nic_dev->nic_pause.tx_pause = pause_config.tx_pause; 2574 2575 return 0; 2576 } 2577 2578 static int hinic_set_default_dcb_feature(struct hinic_nic_dev *nic_dev) 2579 { 2580 u8 up_tc[HINIC_DCB_UP_MAX] = {0}; 2581 u8 up_pgid[HINIC_DCB_UP_MAX] = {0}; 2582 u8 up_bw[HINIC_DCB_UP_MAX] = {0}; 2583 u8 pg_bw[HINIC_DCB_UP_MAX] = {0}; 2584 u8 up_strict[HINIC_DCB_UP_MAX] = {0}; 2585 int i = 0; 2586 2587 pg_bw[0] = 100; 2588 for (i = 0; i < HINIC_DCB_UP_MAX; i++) 2589 up_bw[i] = 100; 2590 2591 return hinic_dcb_set_ets(nic_dev->hwdev, up_tc, pg_bw, 2592 up_pgid, up_bw, up_strict); 2593 } 2594 2595 static int hinic_pf_get_default_cos(struct hinic_hwdev *hwdev, u8 *cos_id) 2596 { 2597 u8 default_cos = 0; 2598 u8 valid_cos_bitmap; 2599 u8 i; 2600 2601 valid_cos_bitmap = hwdev->cfg_mgmt->svc_cap.valid_cos_bitmap; 2602 if (!valid_cos_bitmap) { 2603 PMD_DRV_LOG(ERR, "PF has none cos to support\n"); 2604 return -EFAULT; 2605 } 2606 2607 for (i = 0; i < NR_MAX_COS; i++) { 2608 if (valid_cos_bitmap & BIT(i)) 2609 default_cos = i; /* Find max cos id as default cos */ 2610 } 2611 2612 *cos_id = default_cos; 2613 2614 return 0; 2615 } 2616 2617 static int hinic_init_default_cos(struct hinic_nic_dev *nic_dev) 2618 { 2619 u8 cos_id = 0; 2620 int err; 2621 2622 if (!HINIC_IS_VF(nic_dev->hwdev)) { 2623 err = hinic_pf_get_default_cos(nic_dev->hwdev, &cos_id); 2624 if (err) { 2625 PMD_DRV_LOG(ERR, "Get PF default cos failed, err: %d", 2626 err); 2627 return HINIC_ERROR; 2628 } 2629 } else { 2630 err = hinic_vf_get_default_cos(nic_dev->hwdev, &cos_id); 2631 if (err) { 2632 PMD_DRV_LOG(ERR, "Get VF default cos failed, err: %d", 2633 err); 2634 return HINIC_ERROR; 2635 } 2636 } 2637 2638 nic_dev->default_cos = cos_id; 2639 2640 PMD_DRV_LOG(INFO, "Default cos %d", nic_dev->default_cos); 2641 2642 return 0; 2643 } 2644 2645 static int hinic_set_default_hw_feature(struct hinic_nic_dev *nic_dev) 2646 { 2647 int err; 2648 2649 err = hinic_init_default_cos(nic_dev); 2650 if (err) 2651 return err; 2652 2653 if (hinic_func_type(nic_dev->hwdev) == TYPE_VF) 2654 return 0; 2655 2656 /* Restore DCB configure to default status */ 2657 err = hinic_set_default_dcb_feature(nic_dev); 2658 if (err) 2659 return err; 2660 2661 /* Set pause enable, and up will disable pfc. */ 2662 err = hinic_set_default_pause_feature(nic_dev); 2663 if (err) 2664 return err; 2665 2666 err = hinic_reset_port_link_cfg(nic_dev->hwdev); 2667 if (err) 2668 return err; 2669 2670 err = hinic_set_link_status_follow(nic_dev->hwdev, 2671 HINIC_LINK_FOLLOW_PORT); 2672 if (err == HINIC_MGMT_CMD_UNSUPPORTED) 2673 PMD_DRV_LOG(WARNING, "Don't support to set link status follow phy port status"); 2674 else if (err) 2675 return err; 2676 2677 return hinic_set_anti_attack(nic_dev->hwdev, true); 2678 } 2679 2680 static int32_t hinic_card_workmode_check(struct hinic_nic_dev *nic_dev) 2681 { 2682 struct hinic_board_info info = { 0 }; 2683 int rc; 2684 2685 if (hinic_func_type(nic_dev->hwdev) == TYPE_VF) 2686 return 0; 2687 2688 rc = hinic_get_board_info(nic_dev->hwdev, &info); 2689 if (rc) 2690 return rc; 2691 2692 return (info.service_mode == HINIC_SERVICE_MODE_NIC ? HINIC_OK : 2693 HINIC_ERROR); 2694 } 2695 2696 static int hinic_copy_mempool_init(struct hinic_nic_dev *nic_dev) 2697 { 2698 nic_dev->cpy_mpool = rte_mempool_lookup(nic_dev->proc_dev_name); 2699 if (nic_dev->cpy_mpool == NULL) { 2700 nic_dev->cpy_mpool = 2701 rte_pktmbuf_pool_create(nic_dev->proc_dev_name, 2702 HINIC_COPY_MEMPOOL_DEPTH, 2703 0, 0, 2704 HINIC_COPY_MBUF_SIZE, 2705 rte_socket_id()); 2706 if (!nic_dev->cpy_mpool) { 2707 PMD_DRV_LOG(ERR, "Create copy mempool failed, errno: %d, dev_name: %s", 2708 rte_errno, nic_dev->proc_dev_name); 2709 return -ENOMEM; 2710 } 2711 } 2712 2713 return 0; 2714 } 2715 2716 static void hinic_copy_mempool_uninit(struct hinic_nic_dev *nic_dev) 2717 { 2718 if (nic_dev->cpy_mpool != NULL) 2719 rte_mempool_free(nic_dev->cpy_mpool); 2720 } 2721 2722 static int hinic_init_sw_rxtxqs(struct hinic_nic_dev *nic_dev) 2723 { 2724 u32 txq_size; 2725 u32 rxq_size; 2726 2727 /* allocate software txq array */ 2728 txq_size = nic_dev->nic_cap.max_sqs * sizeof(*nic_dev->txqs); 2729 nic_dev->txqs = kzalloc_aligned(txq_size, GFP_KERNEL); 2730 if (!nic_dev->txqs) { 2731 PMD_DRV_LOG(ERR, "Allocate txqs failed"); 2732 return -ENOMEM; 2733 } 2734 2735 /* allocate software rxq array */ 2736 rxq_size = nic_dev->nic_cap.max_rqs * sizeof(*nic_dev->rxqs); 2737 nic_dev->rxqs = kzalloc_aligned(rxq_size, GFP_KERNEL); 2738 if (!nic_dev->rxqs) { 2739 /* free txqs */ 2740 kfree(nic_dev->txqs); 2741 nic_dev->txqs = NULL; 2742 2743 PMD_DRV_LOG(ERR, "Allocate rxqs failed"); 2744 return -ENOMEM; 2745 } 2746 2747 return HINIC_OK; 2748 } 2749 2750 static void hinic_deinit_sw_rxtxqs(struct hinic_nic_dev *nic_dev) 2751 { 2752 kfree(nic_dev->txqs); 2753 nic_dev->txqs = NULL; 2754 2755 kfree(nic_dev->rxqs); 2756 nic_dev->rxqs = NULL; 2757 } 2758 2759 static int hinic_nic_dev_create(struct rte_eth_dev *eth_dev) 2760 { 2761 struct hinic_nic_dev *nic_dev = 2762 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); 2763 int rc; 2764 2765 nic_dev->hwdev = rte_zmalloc("hinic_hwdev", sizeof(*nic_dev->hwdev), 2766 RTE_CACHE_LINE_SIZE); 2767 if (!nic_dev->hwdev) { 2768 PMD_DRV_LOG(ERR, "Allocate hinic hwdev memory failed, dev_name: %s", 2769 eth_dev->data->name); 2770 return -ENOMEM; 2771 } 2772 nic_dev->hwdev->pcidev_hdl = RTE_ETH_DEV_TO_PCI(eth_dev); 2773 2774 /* init osdep*/ 2775 rc = hinic_osdep_init(nic_dev->hwdev); 2776 if (rc) { 2777 PMD_DRV_LOG(ERR, "Initialize os_dep failed, dev_name: %s", 2778 eth_dev->data->name); 2779 goto init_osdep_fail; 2780 } 2781 2782 /* init_hwif */ 2783 rc = hinic_hwif_res_init(nic_dev->hwdev); 2784 if (rc) { 2785 PMD_DRV_LOG(ERR, "Initialize hwif failed, dev_name: %s", 2786 eth_dev->data->name); 2787 goto init_hwif_fail; 2788 } 2789 2790 /* init_cfg_mgmt */ 2791 rc = init_cfg_mgmt(nic_dev->hwdev); 2792 if (rc) { 2793 PMD_DRV_LOG(ERR, "Initialize cfg_mgmt failed, dev_name: %s", 2794 eth_dev->data->name); 2795 goto init_cfgmgnt_fail; 2796 } 2797 2798 /* init_aeqs */ 2799 rc = hinic_comm_aeqs_init(nic_dev->hwdev); 2800 if (rc) { 2801 PMD_DRV_LOG(ERR, "Initialize aeqs failed, dev_name: %s", 2802 eth_dev->data->name); 2803 goto init_aeqs_fail; 2804 } 2805 2806 /* init_pf_to_mgnt */ 2807 rc = hinic_comm_pf_to_mgmt_init(nic_dev->hwdev); 2808 if (rc) { 2809 PMD_DRV_LOG(ERR, "Initialize pf_to_mgmt failed, dev_name: %s", 2810 eth_dev->data->name); 2811 goto init_pf_to_mgmt_fail; 2812 } 2813 2814 /* init mailbox */ 2815 rc = hinic_comm_func_to_func_init(nic_dev->hwdev); 2816 if (rc) { 2817 PMD_DRV_LOG(ERR, "Initialize func_to_func failed, dev_name: %s", 2818 eth_dev->data->name); 2819 goto init_func_to_func_fail; 2820 } 2821 2822 rc = hinic_card_workmode_check(nic_dev); 2823 if (rc) { 2824 PMD_DRV_LOG(ERR, "Check card workmode failed, dev_name: %s", 2825 eth_dev->data->name); 2826 goto workmode_check_fail; 2827 } 2828 2829 /* do l2nic reset to make chip clear */ 2830 rc = hinic_l2nic_reset(nic_dev->hwdev); 2831 if (rc) { 2832 PMD_DRV_LOG(ERR, "Do l2nic reset failed, dev_name: %s", 2833 eth_dev->data->name); 2834 goto l2nic_reset_fail; 2835 } 2836 2837 /* init dma and aeq msix attribute table */ 2838 (void)hinic_init_attr_table(nic_dev->hwdev); 2839 2840 /* init_cmdqs */ 2841 rc = hinic_comm_cmdqs_init(nic_dev->hwdev); 2842 if (rc) { 2843 PMD_DRV_LOG(ERR, "Initialize cmdq failed, dev_name: %s", 2844 eth_dev->data->name); 2845 goto init_cmdq_fail; 2846 } 2847 2848 /* set hardware state active */ 2849 rc = hinic_activate_hwdev_state(nic_dev->hwdev); 2850 if (rc) { 2851 PMD_DRV_LOG(ERR, "Initialize resources state failed, dev_name: %s", 2852 eth_dev->data->name); 2853 goto init_resources_state_fail; 2854 } 2855 2856 /* init_capability */ 2857 rc = hinic_init_capability(nic_dev->hwdev); 2858 if (rc) { 2859 PMD_DRV_LOG(ERR, "Initialize capability failed, dev_name: %s", 2860 eth_dev->data->name); 2861 goto init_cap_fail; 2862 } 2863 2864 /* get nic capability */ 2865 if (!hinic_support_nic(nic_dev->hwdev, &nic_dev->nic_cap)) { 2866 PMD_DRV_LOG(ERR, "Hw doesn't support nic, dev_name: %s", 2867 eth_dev->data->name); 2868 rc = -EINVAL; 2869 goto nic_check_fail; 2870 } 2871 2872 /* init root cla and function table */ 2873 rc = hinic_init_nicio(nic_dev->hwdev); 2874 if (rc) { 2875 PMD_DRV_LOG(ERR, "Initialize nic_io failed, dev_name: %s", 2876 eth_dev->data->name); 2877 goto init_nicio_fail; 2878 } 2879 2880 /* init_software_txrxq */ 2881 rc = hinic_init_sw_rxtxqs(nic_dev); 2882 if (rc) { 2883 PMD_DRV_LOG(ERR, "Initialize sw_rxtxqs failed, dev_name: %s", 2884 eth_dev->data->name); 2885 goto init_sw_rxtxqs_fail; 2886 } 2887 2888 rc = hinic_copy_mempool_init(nic_dev); 2889 if (rc) { 2890 PMD_DRV_LOG(ERR, "Create copy mempool failed, dev_name: %s", 2891 eth_dev->data->name); 2892 goto init_mpool_fail; 2893 } 2894 2895 /* set hardware feature to default status */ 2896 rc = hinic_set_default_hw_feature(nic_dev); 2897 if (rc) { 2898 PMD_DRV_LOG(ERR, "Initialize hardware default features failed, dev_name: %s", 2899 eth_dev->data->name); 2900 goto set_default_hw_feature_fail; 2901 } 2902 2903 return 0; 2904 2905 set_default_hw_feature_fail: 2906 hinic_copy_mempool_uninit(nic_dev); 2907 2908 init_mpool_fail: 2909 hinic_deinit_sw_rxtxqs(nic_dev); 2910 2911 init_sw_rxtxqs_fail: 2912 hinic_deinit_nicio(nic_dev->hwdev); 2913 2914 nic_check_fail: 2915 init_nicio_fail: 2916 init_cap_fail: 2917 hinic_deactivate_hwdev_state(nic_dev->hwdev); 2918 2919 init_resources_state_fail: 2920 hinic_comm_cmdqs_free(nic_dev->hwdev); 2921 2922 init_cmdq_fail: 2923 l2nic_reset_fail: 2924 workmode_check_fail: 2925 hinic_comm_func_to_func_free(nic_dev->hwdev); 2926 2927 init_func_to_func_fail: 2928 hinic_comm_pf_to_mgmt_free(nic_dev->hwdev); 2929 2930 init_pf_to_mgmt_fail: 2931 hinic_comm_aeqs_free(nic_dev->hwdev); 2932 2933 init_aeqs_fail: 2934 free_cfg_mgmt(nic_dev->hwdev); 2935 2936 init_cfgmgnt_fail: 2937 hinic_hwif_res_free(nic_dev->hwdev); 2938 2939 init_hwif_fail: 2940 hinic_osdep_deinit(nic_dev->hwdev); 2941 2942 init_osdep_fail: 2943 rte_free(nic_dev->hwdev); 2944 nic_dev->hwdev = NULL; 2945 2946 return rc; 2947 } 2948 2949 static void hinic_nic_dev_destroy(struct rte_eth_dev *eth_dev) 2950 { 2951 struct hinic_nic_dev *nic_dev = 2952 HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); 2953 2954 (void)hinic_set_link_status_follow(nic_dev->hwdev, 2955 HINIC_LINK_FOLLOW_DEFAULT); 2956 hinic_copy_mempool_uninit(nic_dev); 2957 hinic_deinit_sw_rxtxqs(nic_dev); 2958 hinic_deinit_nicio(nic_dev->hwdev); 2959 hinic_deactivate_hwdev_state(nic_dev->hwdev); 2960 hinic_comm_cmdqs_free(nic_dev->hwdev); 2961 hinic_comm_func_to_func_free(nic_dev->hwdev); 2962 hinic_comm_pf_to_mgmt_free(nic_dev->hwdev); 2963 hinic_comm_aeqs_free(nic_dev->hwdev); 2964 free_cfg_mgmt(nic_dev->hwdev); 2965 hinic_hwif_res_free(nic_dev->hwdev); 2966 hinic_osdep_deinit(nic_dev->hwdev); 2967 rte_free(nic_dev->hwdev); 2968 nic_dev->hwdev = NULL; 2969 } 2970 2971 /** 2972 * DPDK callback to close the device. 2973 * 2974 * @param dev 2975 * Pointer to Ethernet device structure. 2976 */ 2977 static int hinic_dev_close(struct rte_eth_dev *dev) 2978 { 2979 struct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev); 2980 int ret; 2981 2982 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2983 return 0; 2984 2985 if (rte_bit_relaxed_test_and_set32(HINIC_DEV_CLOSE, 2986 &nic_dev->dev_status)) { 2987 PMD_DRV_LOG(WARNING, "Device %s already closed", 2988 dev->data->name); 2989 return 0; 2990 } 2991 2992 /* stop device first */ 2993 ret = hinic_dev_stop(dev); 2994 2995 /* rx_cqe, rx_info */ 2996 hinic_free_all_rx_resources(dev); 2997 2998 /* tx_info */ 2999 hinic_free_all_tx_resources(dev); 3000 3001 /* free wq, pi_dma_addr */ 3002 hinic_free_all_rq(nic_dev); 3003 3004 /* free wq, db_addr */ 3005 hinic_free_all_sq(nic_dev); 3006 3007 /* deinit mac vlan tbl */ 3008 hinic_deinit_mac_addr(dev); 3009 hinic_remove_all_vlanid(dev); 3010 3011 /* disable hardware and uio interrupt */ 3012 hinic_disable_interrupt(dev); 3013 3014 /* destroy rx mode mutex */ 3015 hinic_mutex_destroy(&nic_dev->rx_mode_mutex); 3016 3017 /* deinit nic hardware device */ 3018 hinic_nic_dev_destroy(dev); 3019 3020 return ret; 3021 } 3022 3023 static const struct eth_dev_ops hinic_pmd_ops = { 3024 .dev_configure = hinic_dev_configure, 3025 .dev_infos_get = hinic_dev_infos_get, 3026 .fw_version_get = hinic_fw_version_get, 3027 .rx_queue_setup = hinic_rx_queue_setup, 3028 .tx_queue_setup = hinic_tx_queue_setup, 3029 .dev_start = hinic_dev_start, 3030 .dev_set_link_up = hinic_dev_set_link_up, 3031 .dev_set_link_down = hinic_dev_set_link_down, 3032 .link_update = hinic_link_update, 3033 .rx_queue_release = hinic_rx_queue_release, 3034 .tx_queue_release = hinic_tx_queue_release, 3035 .dev_stop = hinic_dev_stop, 3036 .dev_close = hinic_dev_close, 3037 .mtu_set = hinic_dev_set_mtu, 3038 .vlan_filter_set = hinic_vlan_filter_set, 3039 .vlan_offload_set = hinic_vlan_offload_set, 3040 .allmulticast_enable = hinic_dev_allmulticast_enable, 3041 .allmulticast_disable = hinic_dev_allmulticast_disable, 3042 .promiscuous_enable = hinic_dev_promiscuous_enable, 3043 .promiscuous_disable = hinic_dev_promiscuous_disable, 3044 .flow_ctrl_get = hinic_flow_ctrl_get, 3045 .flow_ctrl_set = hinic_flow_ctrl_set, 3046 .rss_hash_update = hinic_rss_hash_update, 3047 .rss_hash_conf_get = hinic_rss_conf_get, 3048 .reta_update = hinic_rss_indirtbl_update, 3049 .reta_query = hinic_rss_indirtbl_query, 3050 .stats_get = hinic_dev_stats_get, 3051 .stats_reset = hinic_dev_stats_reset, 3052 .xstats_get = hinic_dev_xstats_get, 3053 .xstats_reset = hinic_dev_xstats_reset, 3054 .xstats_get_names = hinic_dev_xstats_get_names, 3055 .rxq_info_get = hinic_rxq_info_get, 3056 .txq_info_get = hinic_txq_info_get, 3057 .mac_addr_set = hinic_set_mac_addr, 3058 .mac_addr_remove = hinic_mac_addr_remove, 3059 .mac_addr_add = hinic_mac_addr_add, 3060 .set_mc_addr_list = hinic_set_mc_addr_list, 3061 .filter_ctrl = hinic_dev_filter_ctrl, 3062 }; 3063 3064 static const struct eth_dev_ops hinic_pmd_vf_ops = { 3065 .dev_configure = hinic_dev_configure, 3066 .dev_infos_get = hinic_dev_infos_get, 3067 .fw_version_get = hinic_fw_version_get, 3068 .rx_queue_setup = hinic_rx_queue_setup, 3069 .tx_queue_setup = hinic_tx_queue_setup, 3070 .dev_start = hinic_dev_start, 3071 .link_update = hinic_link_update, 3072 .rx_queue_release = hinic_rx_queue_release, 3073 .tx_queue_release = hinic_tx_queue_release, 3074 .dev_stop = hinic_dev_stop, 3075 .dev_close = hinic_dev_close, 3076 .mtu_set = hinic_dev_set_mtu, 3077 .vlan_filter_set = hinic_vlan_filter_set, 3078 .vlan_offload_set = hinic_vlan_offload_set, 3079 .allmulticast_enable = hinic_dev_allmulticast_enable, 3080 .allmulticast_disable = hinic_dev_allmulticast_disable, 3081 .rss_hash_update = hinic_rss_hash_update, 3082 .rss_hash_conf_get = hinic_rss_conf_get, 3083 .reta_update = hinic_rss_indirtbl_update, 3084 .reta_query = hinic_rss_indirtbl_query, 3085 .stats_get = hinic_dev_stats_get, 3086 .stats_reset = hinic_dev_stats_reset, 3087 .xstats_get = hinic_dev_xstats_get, 3088 .xstats_reset = hinic_dev_xstats_reset, 3089 .xstats_get_names = hinic_dev_xstats_get_names, 3090 .rxq_info_get = hinic_rxq_info_get, 3091 .txq_info_get = hinic_txq_info_get, 3092 .mac_addr_set = hinic_set_mac_addr, 3093 .mac_addr_remove = hinic_mac_addr_remove, 3094 .mac_addr_add = hinic_mac_addr_add, 3095 .set_mc_addr_list = hinic_set_mc_addr_list, 3096 .filter_ctrl = hinic_dev_filter_ctrl, 3097 }; 3098 3099 static int hinic_func_init(struct rte_eth_dev *eth_dev) 3100 { 3101 struct rte_pci_device *pci_dev; 3102 struct rte_ether_addr *eth_addr; 3103 struct hinic_nic_dev *nic_dev; 3104 struct hinic_filter_info *filter_info; 3105 struct hinic_tcam_info *tcam_info; 3106 u32 mac_size; 3107 int rc; 3108 3109 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3110 3111 /* EAL is SECONDARY and eth_dev is already created */ 3112 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 3113 PMD_DRV_LOG(INFO, "Initialize %s in secondary process", 3114 eth_dev->data->name); 3115 3116 return 0; 3117 } 3118 3119 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 3120 3121 nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev); 3122 memset(nic_dev, 0, sizeof(*nic_dev)); 3123 3124 snprintf(nic_dev->proc_dev_name, 3125 sizeof(nic_dev->proc_dev_name), 3126 "hinic-%.4x:%.2x:%.2x.%x", 3127 pci_dev->addr.domain, pci_dev->addr.bus, 3128 pci_dev->addr.devid, pci_dev->addr.function); 3129 3130 /* alloc mac_addrs */ 3131 mac_size = HINIC_MAX_UC_MAC_ADDRS * sizeof(struct rte_ether_addr); 3132 eth_addr = rte_zmalloc("hinic_mac", mac_size, 0); 3133 if (!eth_addr) { 3134 PMD_DRV_LOG(ERR, "Allocate ethernet addresses' memory failed, dev_name: %s", 3135 eth_dev->data->name); 3136 rc = -ENOMEM; 3137 goto eth_addr_fail; 3138 } 3139 eth_dev->data->mac_addrs = eth_addr; 3140 3141 mac_size = HINIC_MAX_MC_MAC_ADDRS * sizeof(struct rte_ether_addr); 3142 nic_dev->mc_list = rte_zmalloc("hinic_mc", mac_size, 0); 3143 if (!nic_dev->mc_list) { 3144 PMD_DRV_LOG(ERR, "Allocate mcast address' memory failed, dev_name: %s", 3145 eth_dev->data->name); 3146 rc = -ENOMEM; 3147 goto mc_addr_fail; 3148 } 3149 3150 /* create hardware nic_device */ 3151 rc = hinic_nic_dev_create(eth_dev); 3152 if (rc) { 3153 PMD_DRV_LOG(ERR, "Create nic device failed, dev_name: %s", 3154 eth_dev->data->name); 3155 goto create_nic_dev_fail; 3156 } 3157 3158 if (HINIC_IS_VF(nic_dev->hwdev)) 3159 eth_dev->dev_ops = &hinic_pmd_vf_ops; 3160 else 3161 eth_dev->dev_ops = &hinic_pmd_ops; 3162 3163 rc = hinic_init_mac_addr(eth_dev); 3164 if (rc) { 3165 PMD_DRV_LOG(ERR, "Initialize mac table failed, dev_name: %s", 3166 eth_dev->data->name); 3167 goto init_mac_fail; 3168 } 3169 3170 /* register callback func to eal lib */ 3171 rc = rte_intr_callback_register(&pci_dev->intr_handle, 3172 hinic_dev_interrupt_handler, 3173 (void *)eth_dev); 3174 if (rc) { 3175 PMD_DRV_LOG(ERR, "Register rte interrupt callback failed, dev_name: %s", 3176 eth_dev->data->name); 3177 goto reg_intr_cb_fail; 3178 } 3179 3180 /* enable uio/vfio intr/eventfd mapping */ 3181 rc = rte_intr_enable(&pci_dev->intr_handle); 3182 if (rc) { 3183 PMD_DRV_LOG(ERR, "Enable rte interrupt failed, dev_name: %s", 3184 eth_dev->data->name); 3185 goto enable_intr_fail; 3186 } 3187 rte_bit_relaxed_set32(HINIC_DEV_INTR_EN, &nic_dev->dev_status); 3188 3189 hinic_mutex_init(&nic_dev->rx_mode_mutex, NULL); 3190 3191 /* initialize filter info */ 3192 filter_info = &nic_dev->filter; 3193 tcam_info = &nic_dev->tcam; 3194 memset(filter_info, 0, sizeof(struct hinic_filter_info)); 3195 memset(tcam_info, 0, sizeof(struct hinic_tcam_info)); 3196 /* initialize 5tuple filter list */ 3197 TAILQ_INIT(&filter_info->fivetuple_list); 3198 TAILQ_INIT(&tcam_info->tcam_list); 3199 TAILQ_INIT(&nic_dev->filter_ntuple_list); 3200 TAILQ_INIT(&nic_dev->filter_ethertype_list); 3201 TAILQ_INIT(&nic_dev->filter_fdir_rule_list); 3202 TAILQ_INIT(&nic_dev->hinic_flow_list); 3203 3204 rte_bit_relaxed_set32(HINIC_DEV_INIT, &nic_dev->dev_status); 3205 PMD_DRV_LOG(INFO, "Initialize %s in primary successfully", 3206 eth_dev->data->name); 3207 3208 return 0; 3209 3210 enable_intr_fail: 3211 (void)rte_intr_callback_unregister(&pci_dev->intr_handle, 3212 hinic_dev_interrupt_handler, 3213 (void *)eth_dev); 3214 3215 reg_intr_cb_fail: 3216 hinic_deinit_mac_addr(eth_dev); 3217 3218 init_mac_fail: 3219 eth_dev->dev_ops = NULL; 3220 hinic_nic_dev_destroy(eth_dev); 3221 3222 create_nic_dev_fail: 3223 rte_free(nic_dev->mc_list); 3224 nic_dev->mc_list = NULL; 3225 3226 mc_addr_fail: 3227 rte_free(eth_addr); 3228 eth_dev->data->mac_addrs = NULL; 3229 3230 eth_addr_fail: 3231 PMD_DRV_LOG(ERR, "Initialize %s in primary failed", 3232 eth_dev->data->name); 3233 return rc; 3234 } 3235 3236 static int hinic_dev_init(struct rte_eth_dev *eth_dev) 3237 { 3238 struct rte_pci_device *pci_dev; 3239 3240 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3241 3242 PMD_DRV_LOG(INFO, "Initializing pf hinic-%.4x:%.2x:%.2x.%x in %s process", 3243 pci_dev->addr.domain, pci_dev->addr.bus, 3244 pci_dev->addr.devid, pci_dev->addr.function, 3245 (rte_eal_process_type() == RTE_PROC_PRIMARY) ? 3246 "primary" : "secondary"); 3247 3248 /* rte_eth_dev rx_burst and tx_burst */ 3249 eth_dev->rx_pkt_burst = hinic_recv_pkts; 3250 eth_dev->tx_pkt_burst = hinic_xmit_pkts; 3251 3252 return hinic_func_init(eth_dev); 3253 } 3254 3255 static int hinic_dev_uninit(struct rte_eth_dev *dev) 3256 { 3257 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3258 return 0; 3259 3260 hinic_dev_close(dev); 3261 3262 return HINIC_OK; 3263 } 3264 3265 static struct rte_pci_id pci_id_hinic_map[] = { 3266 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_PRD) }, 3267 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_25GE) }, 3268 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_MEZZ_100GE) }, 3269 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_VF) }, 3270 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_VF_HV) }, 3271 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_1822_DUAL_25GE) }, 3272 { RTE_PCI_DEVICE(HINIC_HUAWEI_VENDOR_ID, HINIC_DEV_ID_1822_100GE) }, 3273 {.vendor_id = 0}, 3274 }; 3275 3276 static int hinic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3277 struct rte_pci_device *pci_dev) 3278 { 3279 return rte_eth_dev_pci_generic_probe(pci_dev, 3280 sizeof(struct hinic_nic_dev), hinic_dev_init); 3281 } 3282 3283 static int hinic_pci_remove(struct rte_pci_device *pci_dev) 3284 { 3285 return rte_eth_dev_pci_generic_remove(pci_dev, hinic_dev_uninit); 3286 } 3287 3288 static struct rte_pci_driver rte_hinic_pmd = { 3289 .id_table = pci_id_hinic_map, 3290 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 3291 .probe = hinic_pci_probe, 3292 .remove = hinic_pci_remove, 3293 }; 3294 3295 RTE_PMD_REGISTER_PCI(net_hinic, rte_hinic_pmd); 3296 RTE_PMD_REGISTER_PCI_TABLE(net_hinic, pci_id_hinic_map); 3297 RTE_LOG_REGISTER(hinic_logtype, pmd.net.hinic, INFO); 3298