1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 */ 5 6 #include <stdio.h> 7 #include <stdint.h> 8 9 #include <rte_dev.h> 10 #include <rte_pci.h> 11 #include <rte_bus_pci.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_ethdev_pci.h> 14 #include <rte_kvargs.h> 15 #include <rte_string_fns.h> 16 17 #include "vnic_intr.h" 18 #include "vnic_cq.h" 19 #include "vnic_wq.h" 20 #include "vnic_rq.h" 21 #include "vnic_enet.h" 22 #include "enic.h" 23 24 /* 25 * The set of PCI devices this driver supports 26 */ 27 #define CISCO_PCI_VENDOR_ID 0x1137 28 static const struct rte_pci_id pci_id_enic_map[] = { 29 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)}, 30 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)}, 31 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)}, 32 {.vendor_id = 0, /* sentinel */}, 33 }; 34 35 /* Supported link speeds of production VIC models */ 36 static const struct vic_speed_capa { 37 uint16_t sub_devid; 38 uint32_t capa; 39 } vic_speed_capa_map[] = { 40 { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */ 41 { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */ 42 { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */ 43 { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */ 44 { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */ 45 { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */ 46 { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */ 47 { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */ 48 { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */ 49 { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */ 50 { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */ 51 { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */ 52 { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */ 53 { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */ 54 { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 55 ETH_LINK_SPEED_40G }, /* 1440 Mezz */ 56 { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 57 ETH_LINK_SPEED_40G }, /* 1480 MLOM */ 58 { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */ 59 { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */ 60 { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */ 61 { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */ 62 { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */ 63 { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */ 64 { 0, 0 }, /* End marker */ 65 }; 66 67 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay" 68 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx" 69 #define ENIC_DEVARG_GENEVE_OPT "geneve-opt" 70 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite" 71 72 RTE_LOG_REGISTER(enic_pmd_logtype, pmd.net.enic, INFO); 73 74 static int 75 enicpmd_fdir_ctrl_func(struct rte_eth_dev *eth_dev, 76 enum rte_filter_op filter_op, void *arg) 77 { 78 struct enic *enic = pmd_priv(eth_dev); 79 int ret = 0; 80 81 ENICPMD_FUNC_TRACE(); 82 if (filter_op == RTE_ETH_FILTER_NOP) 83 return 0; 84 85 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 86 return -EINVAL; 87 88 switch (filter_op) { 89 case RTE_ETH_FILTER_ADD: 90 case RTE_ETH_FILTER_UPDATE: 91 ret = enic_fdir_add_fltr(enic, 92 (struct rte_eth_fdir_filter *)arg); 93 break; 94 95 case RTE_ETH_FILTER_DELETE: 96 ret = enic_fdir_del_fltr(enic, 97 (struct rte_eth_fdir_filter *)arg); 98 break; 99 100 case RTE_ETH_FILTER_STATS: 101 enic_fdir_stats_get(enic, (struct rte_eth_fdir_stats *)arg); 102 break; 103 104 case RTE_ETH_FILTER_FLUSH: 105 dev_warning(enic, "unsupported operation %u", filter_op); 106 ret = -ENOTSUP; 107 break; 108 case RTE_ETH_FILTER_INFO: 109 enic_fdir_info_get(enic, (struct rte_eth_fdir_info *)arg); 110 break; 111 default: 112 dev_err(enic, "unknown operation %u", filter_op); 113 ret = -EINVAL; 114 break; 115 } 116 return ret; 117 } 118 119 static int 120 enicpmd_dev_filter_ctrl(struct rte_eth_dev *dev, 121 enum rte_filter_type filter_type, 122 enum rte_filter_op filter_op, 123 void *arg) 124 { 125 struct enic *enic = pmd_priv(dev); 126 int ret = 0; 127 128 ENICPMD_FUNC_TRACE(); 129 130 /* 131 * Currently, when Geneve with options offload is enabled, host 132 * cannot insert match-action rules. 133 */ 134 if (enic->geneve_opt_enabled) 135 return -ENOTSUP; 136 switch (filter_type) { 137 case RTE_ETH_FILTER_GENERIC: 138 if (filter_op != RTE_ETH_FILTER_GET) 139 return -EINVAL; 140 if (enic->flow_filter_mode == FILTER_FLOWMAN) 141 *(const void **)arg = &enic_fm_flow_ops; 142 else 143 *(const void **)arg = &enic_flow_ops; 144 break; 145 case RTE_ETH_FILTER_FDIR: 146 ret = enicpmd_fdir_ctrl_func(dev, filter_op, arg); 147 break; 148 default: 149 dev_warning(enic, "Filter type (%d) not supported", 150 filter_type); 151 ret = -EINVAL; 152 break; 153 } 154 155 return ret; 156 } 157 158 static void enicpmd_dev_tx_queue_release(void *txq) 159 { 160 ENICPMD_FUNC_TRACE(); 161 162 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 163 return; 164 165 enic_free_wq(txq); 166 } 167 168 static int enicpmd_dev_setup_intr(struct enic *enic) 169 { 170 int ret; 171 unsigned int index; 172 173 ENICPMD_FUNC_TRACE(); 174 175 /* Are we done with the init of all the queues? */ 176 for (index = 0; index < enic->cq_count; index++) { 177 if (!enic->cq[index].ctrl) 178 break; 179 } 180 if (enic->cq_count != index) 181 return 0; 182 for (index = 0; index < enic->wq_count; index++) { 183 if (!enic->wq[index].ctrl) 184 break; 185 } 186 if (enic->wq_count != index) 187 return 0; 188 /* check start of packet (SOP) RQs only in case scatter is disabled. */ 189 for (index = 0; index < enic->rq_count; index++) { 190 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl) 191 break; 192 } 193 if (enic->rq_count != index) 194 return 0; 195 196 ret = enic_alloc_intr_resources(enic); 197 if (ret) { 198 dev_err(enic, "alloc intr failed\n"); 199 return ret; 200 } 201 enic_init_vnic_resources(enic); 202 203 ret = enic_setup_finish(enic); 204 if (ret) 205 dev_err(enic, "setup could not be finished\n"); 206 207 return ret; 208 } 209 210 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 211 uint16_t queue_idx, 212 uint16_t nb_desc, 213 unsigned int socket_id, 214 const struct rte_eth_txconf *tx_conf) 215 { 216 int ret; 217 struct enic *enic = pmd_priv(eth_dev); 218 struct vnic_wq *wq; 219 220 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 221 return -E_RTE_SECONDARY; 222 223 ENICPMD_FUNC_TRACE(); 224 RTE_ASSERT(queue_idx < enic->conf_wq_count); 225 wq = &enic->wq[queue_idx]; 226 wq->offloads = tx_conf->offloads | 227 eth_dev->data->dev_conf.txmode.offloads; 228 eth_dev->data->tx_queues[queue_idx] = (void *)wq; 229 230 ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc); 231 if (ret) { 232 dev_err(enic, "error in allocating wq\n"); 233 return ret; 234 } 235 236 return enicpmd_dev_setup_intr(enic); 237 } 238 239 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 240 uint16_t queue_idx) 241 { 242 struct enic *enic = pmd_priv(eth_dev); 243 244 ENICPMD_FUNC_TRACE(); 245 246 enic_start_wq(enic, queue_idx); 247 248 return 0; 249 } 250 251 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, 252 uint16_t queue_idx) 253 { 254 int ret; 255 struct enic *enic = pmd_priv(eth_dev); 256 257 ENICPMD_FUNC_TRACE(); 258 259 ret = enic_stop_wq(enic, queue_idx); 260 if (ret) 261 dev_err(enic, "error in stopping wq %d\n", queue_idx); 262 263 return ret; 264 } 265 266 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 267 uint16_t queue_idx) 268 { 269 struct enic *enic = pmd_priv(eth_dev); 270 271 ENICPMD_FUNC_TRACE(); 272 273 enic_start_rq(enic, queue_idx); 274 275 return 0; 276 } 277 278 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, 279 uint16_t queue_idx) 280 { 281 int ret; 282 struct enic *enic = pmd_priv(eth_dev); 283 284 ENICPMD_FUNC_TRACE(); 285 286 ret = enic_stop_rq(enic, queue_idx); 287 if (ret) 288 dev_err(enic, "error in stopping rq %d\n", queue_idx); 289 290 return ret; 291 } 292 293 static void enicpmd_dev_rx_queue_release(void *rxq) 294 { 295 ENICPMD_FUNC_TRACE(); 296 297 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 298 return; 299 300 enic_free_rq(rxq); 301 } 302 303 static uint32_t enicpmd_dev_rx_queue_count(struct rte_eth_dev *dev, 304 uint16_t rx_queue_id) 305 { 306 struct enic *enic = pmd_priv(dev); 307 uint32_t queue_count = 0; 308 struct vnic_cq *cq; 309 uint32_t cq_tail; 310 uint16_t cq_idx; 311 int rq_num; 312 313 rq_num = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 314 cq = &enic->cq[enic_cq_rq(enic, rq_num)]; 315 cq_idx = cq->to_clean; 316 317 cq_tail = ioread32(&cq->ctrl->cq_tail); 318 319 if (cq_tail < cq_idx) 320 cq_tail += cq->ring.desc_count; 321 322 queue_count = cq_tail - cq_idx; 323 324 return queue_count; 325 } 326 327 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 328 uint16_t queue_idx, 329 uint16_t nb_desc, 330 unsigned int socket_id, 331 const struct rte_eth_rxconf *rx_conf, 332 struct rte_mempool *mp) 333 { 334 int ret; 335 struct enic *enic = pmd_priv(eth_dev); 336 337 ENICPMD_FUNC_TRACE(); 338 339 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 340 return -E_RTE_SECONDARY; 341 RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count); 342 eth_dev->data->rx_queues[queue_idx] = 343 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)]; 344 345 ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc, 346 rx_conf->rx_free_thresh); 347 if (ret) { 348 dev_err(enic, "error in allocating rq\n"); 349 return ret; 350 } 351 352 return enicpmd_dev_setup_intr(enic); 353 } 354 355 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 356 { 357 struct enic *enic = pmd_priv(eth_dev); 358 uint64_t offloads; 359 360 ENICPMD_FUNC_TRACE(); 361 362 offloads = eth_dev->data->dev_conf.rxmode.offloads; 363 if (mask & ETH_VLAN_STRIP_MASK) { 364 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 365 enic->ig_vlan_strip_en = 1; 366 else 367 enic->ig_vlan_strip_en = 0; 368 } 369 370 if ((mask & ETH_VLAN_FILTER_MASK) && 371 (offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 372 dev_warning(enic, 373 "Configuration of VLAN filter is not supported\n"); 374 } 375 376 if ((mask & ETH_VLAN_EXTEND_MASK) && 377 (offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)) { 378 dev_warning(enic, 379 "Configuration of extended VLAN is not supported\n"); 380 } 381 382 return enic_set_vlan_strip(enic); 383 } 384 385 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev) 386 { 387 int ret; 388 int mask; 389 struct enic *enic = pmd_priv(eth_dev); 390 391 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 392 return -E_RTE_SECONDARY; 393 394 ENICPMD_FUNC_TRACE(); 395 ret = enic_set_vnic_res(enic); 396 if (ret) { 397 dev_err(enic, "Set vNIC resource num failed, aborting\n"); 398 return ret; 399 } 400 401 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 402 eth_dev->data->dev_conf.rxmode.offloads |= 403 DEV_RX_OFFLOAD_RSS_HASH; 404 405 enic->mc_count = 0; 406 enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads & 407 DEV_RX_OFFLOAD_CHECKSUM); 408 /* All vlan offload masks to apply the current settings */ 409 mask = ETH_VLAN_STRIP_MASK | 410 ETH_VLAN_FILTER_MASK | 411 ETH_VLAN_EXTEND_MASK; 412 ret = enicpmd_vlan_offload_set(eth_dev, mask); 413 if (ret) { 414 dev_err(enic, "Failed to configure VLAN offloads\n"); 415 return ret; 416 } 417 /* 418 * Initialize RSS with the default reta and key. If the user key is 419 * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the 420 * default key. 421 */ 422 return enic_init_rss_nic_cfg(enic); 423 } 424 425 /* Start the device. 426 * It returns 0 on success. 427 */ 428 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev) 429 { 430 struct enic *enic = pmd_priv(eth_dev); 431 432 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 433 return -E_RTE_SECONDARY; 434 435 ENICPMD_FUNC_TRACE(); 436 return enic_enable(enic); 437 } 438 439 /* 440 * Stop device: disable rx and tx functions to allow for reconfiguring. 441 */ 442 static void enicpmd_dev_stop(struct rte_eth_dev *eth_dev) 443 { 444 struct rte_eth_link link; 445 struct enic *enic = pmd_priv(eth_dev); 446 447 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 448 return; 449 450 ENICPMD_FUNC_TRACE(); 451 enic_disable(enic); 452 453 memset(&link, 0, sizeof(link)); 454 rte_eth_linkstatus_set(eth_dev, &link); 455 } 456 457 /* 458 * Stop device. 459 */ 460 static void enicpmd_dev_close(struct rte_eth_dev *eth_dev) 461 { 462 struct enic *enic = pmd_priv(eth_dev); 463 464 ENICPMD_FUNC_TRACE(); 465 enic_remove(enic); 466 } 467 468 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev, 469 __rte_unused int wait_to_complete) 470 { 471 ENICPMD_FUNC_TRACE(); 472 return enic_link_update(eth_dev); 473 } 474 475 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev, 476 struct rte_eth_stats *stats) 477 { 478 struct enic *enic = pmd_priv(eth_dev); 479 480 ENICPMD_FUNC_TRACE(); 481 return enic_dev_stats_get(enic, stats); 482 } 483 484 static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev) 485 { 486 struct enic *enic = pmd_priv(eth_dev); 487 488 ENICPMD_FUNC_TRACE(); 489 return enic_dev_stats_clear(enic); 490 } 491 492 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev) 493 { 494 const struct vic_speed_capa *m; 495 struct rte_pci_device *pdev; 496 uint16_t id; 497 498 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 499 id = pdev->id.subsystem_device_id; 500 for (m = vic_speed_capa_map; m->sub_devid != 0; m++) { 501 if (m->sub_devid == id) 502 return m->capa; 503 } 504 /* 1300 and later models are at least 40G */ 505 if (id >= 0x0100) 506 return ETH_LINK_SPEED_40G; 507 /* VFs have subsystem id 0, check device id */ 508 if (id == 0) { 509 /* Newer VF implies at least 40G model */ 510 if (pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_SN) 511 return ETH_LINK_SPEED_40G; 512 } 513 return ETH_LINK_SPEED_10G; 514 } 515 516 static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, 517 struct rte_eth_dev_info *device_info) 518 { 519 struct enic *enic = pmd_priv(eth_dev); 520 521 ENICPMD_FUNC_TRACE(); 522 /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */ 523 device_info->max_rx_queues = enic->conf_rq_count / 2; 524 device_info->max_tx_queues = enic->conf_wq_count; 525 device_info->min_rx_bufsize = ENIC_MIN_MTU; 526 /* "Max" mtu is not a typo. HW receives packet sizes up to the 527 * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is 528 * a hint to the driver to size receive buffers accordingly so that 529 * larger-than-vnic-mtu packets get truncated.. For DPDK, we let 530 * the user decide the buffer size via rxmode.max_rx_pkt_len, basically 531 * ignoring vNIC mtu. 532 */ 533 device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu); 534 device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS; 535 device_info->min_mtu = ENIC_MIN_MTU; 536 device_info->max_mtu = enic->max_mtu; 537 device_info->rx_offload_capa = enic->rx_offload_capa; 538 device_info->tx_offload_capa = enic->tx_offload_capa; 539 device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa; 540 device_info->default_rxconf = (struct rte_eth_rxconf) { 541 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH 542 }; 543 device_info->reta_size = enic->reta_size; 544 device_info->hash_key_size = enic->hash_key_size; 545 device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads; 546 device_info->rx_desc_lim = (struct rte_eth_desc_lim) { 547 .nb_max = enic->config.rq_desc_count, 548 .nb_min = ENIC_MIN_RQ_DESCS, 549 .nb_align = ENIC_ALIGN_DESCS, 550 }; 551 device_info->tx_desc_lim = (struct rte_eth_desc_lim) { 552 .nb_max = enic->config.wq_desc_count, 553 .nb_min = ENIC_MIN_WQ_DESCS, 554 .nb_align = ENIC_ALIGN_DESCS, 555 .nb_seg_max = ENIC_TX_XMIT_MAX, 556 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC, 557 }; 558 device_info->default_rxportconf = (struct rte_eth_dev_portconf) { 559 .burst_size = ENIC_DEFAULT_RX_BURST, 560 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max, 561 ENIC_DEFAULT_RX_RING_SIZE), 562 .nb_queues = ENIC_DEFAULT_RX_RINGS, 563 }; 564 device_info->default_txportconf = (struct rte_eth_dev_portconf) { 565 .burst_size = ENIC_DEFAULT_TX_BURST, 566 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max, 567 ENIC_DEFAULT_TX_RING_SIZE), 568 .nb_queues = ENIC_DEFAULT_TX_RINGS, 569 }; 570 device_info->speed_capa = speed_capa_from_pci_id(eth_dev); 571 572 return 0; 573 } 574 575 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev) 576 { 577 static const uint32_t ptypes[] = { 578 RTE_PTYPE_L2_ETHER, 579 RTE_PTYPE_L2_ETHER_VLAN, 580 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 581 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 582 RTE_PTYPE_L4_TCP, 583 RTE_PTYPE_L4_UDP, 584 RTE_PTYPE_L4_FRAG, 585 RTE_PTYPE_L4_NONFRAG, 586 RTE_PTYPE_UNKNOWN 587 }; 588 static const uint32_t ptypes_overlay[] = { 589 RTE_PTYPE_L2_ETHER, 590 RTE_PTYPE_L2_ETHER_VLAN, 591 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 592 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 593 RTE_PTYPE_L4_TCP, 594 RTE_PTYPE_L4_UDP, 595 RTE_PTYPE_L4_FRAG, 596 RTE_PTYPE_L4_NONFRAG, 597 RTE_PTYPE_TUNNEL_GRENAT, 598 RTE_PTYPE_INNER_L2_ETHER, 599 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 600 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 601 RTE_PTYPE_INNER_L4_TCP, 602 RTE_PTYPE_INNER_L4_UDP, 603 RTE_PTYPE_INNER_L4_FRAG, 604 RTE_PTYPE_INNER_L4_NONFRAG, 605 RTE_PTYPE_UNKNOWN 606 }; 607 608 if (dev->rx_pkt_burst != enic_dummy_recv_pkts && 609 dev->rx_pkt_burst != NULL) { 610 struct enic *enic = pmd_priv(dev); 611 if (enic->overlay_offload) 612 return ptypes_overlay; 613 else 614 return ptypes; 615 } 616 return NULL; 617 } 618 619 static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 620 { 621 struct enic *enic = pmd_priv(eth_dev); 622 int ret; 623 624 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 625 return -E_RTE_SECONDARY; 626 627 ENICPMD_FUNC_TRACE(); 628 629 enic->promisc = 1; 630 ret = enic_add_packet_filter(enic); 631 if (ret != 0) 632 enic->promisc = 0; 633 634 return ret; 635 } 636 637 static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 638 { 639 struct enic *enic = pmd_priv(eth_dev); 640 int ret; 641 642 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 643 return -E_RTE_SECONDARY; 644 645 ENICPMD_FUNC_TRACE(); 646 enic->promisc = 0; 647 ret = enic_add_packet_filter(enic); 648 if (ret != 0) 649 enic->promisc = 1; 650 651 return ret; 652 } 653 654 static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 655 { 656 struct enic *enic = pmd_priv(eth_dev); 657 int ret; 658 659 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 660 return -E_RTE_SECONDARY; 661 662 ENICPMD_FUNC_TRACE(); 663 enic->allmulti = 1; 664 ret = enic_add_packet_filter(enic); 665 if (ret != 0) 666 enic->allmulti = 0; 667 668 return ret; 669 } 670 671 static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 672 { 673 struct enic *enic = pmd_priv(eth_dev); 674 int ret; 675 676 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 677 return -E_RTE_SECONDARY; 678 679 ENICPMD_FUNC_TRACE(); 680 enic->allmulti = 0; 681 ret = enic_add_packet_filter(enic); 682 if (ret != 0) 683 enic->allmulti = 1; 684 685 return ret; 686 } 687 688 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev, 689 struct rte_ether_addr *mac_addr, 690 __rte_unused uint32_t index, __rte_unused uint32_t pool) 691 { 692 struct enic *enic = pmd_priv(eth_dev); 693 694 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 695 return -E_RTE_SECONDARY; 696 697 ENICPMD_FUNC_TRACE(); 698 return enic_set_mac_address(enic, mac_addr->addr_bytes); 699 } 700 701 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index) 702 { 703 struct enic *enic = pmd_priv(eth_dev); 704 705 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 706 return; 707 708 ENICPMD_FUNC_TRACE(); 709 if (enic_del_mac_address(enic, index)) 710 dev_err(enic, "del mac addr failed\n"); 711 } 712 713 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev, 714 struct rte_ether_addr *addr) 715 { 716 struct enic *enic = pmd_priv(eth_dev); 717 int ret; 718 719 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 720 return -E_RTE_SECONDARY; 721 722 ENICPMD_FUNC_TRACE(); 723 ret = enic_del_mac_address(enic, 0); 724 if (ret) 725 return ret; 726 return enic_set_mac_address(enic, addr->addr_bytes); 727 } 728 729 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add) 730 { 731 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 732 733 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr); 734 ENICPMD_LOG(DEBUG, " %s address %s\n", 735 add ? "add" : "remove", mac_str); 736 } 737 738 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev, 739 struct rte_ether_addr *mc_addr_set, 740 uint32_t nb_mc_addr) 741 { 742 struct enic *enic = pmd_priv(eth_dev); 743 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 744 struct rte_ether_addr *addr; 745 uint32_t i, j; 746 int ret; 747 748 ENICPMD_FUNC_TRACE(); 749 750 /* Validate the given addresses first */ 751 for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) { 752 addr = &mc_addr_set[i]; 753 if (!rte_is_multicast_ether_addr(addr) || 754 rte_is_broadcast_ether_addr(addr)) { 755 rte_ether_format_addr(mac_str, 756 RTE_ETHER_ADDR_FMT_SIZE, addr); 757 ENICPMD_LOG(ERR, " invalid multicast address %s\n", 758 mac_str); 759 return -EINVAL; 760 } 761 } 762 763 /* Flush all if requested */ 764 if (nb_mc_addr == 0 || mc_addr_set == NULL) { 765 ENICPMD_LOG(DEBUG, " flush multicast addresses\n"); 766 for (i = 0; i < enic->mc_count; i++) { 767 addr = &enic->mc_addrs[i]; 768 debug_log_add_del_addr(addr, false); 769 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 770 if (ret) 771 return ret; 772 } 773 enic->mc_count = 0; 774 return 0; 775 } 776 777 if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) { 778 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n", 779 ENIC_MULTICAST_PERFECT_FILTERS); 780 return -ENOSPC; 781 } 782 /* 783 * devcmd is slow, so apply the difference instead of flushing and 784 * adding everything. 785 * 1. Delete addresses on the NIC but not on the host 786 */ 787 for (i = 0; i < enic->mc_count; i++) { 788 addr = &enic->mc_addrs[i]; 789 for (j = 0; j < nb_mc_addr; j++) { 790 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) 791 break; 792 } 793 if (j < nb_mc_addr) 794 continue; 795 debug_log_add_del_addr(addr, false); 796 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 797 if (ret) 798 return ret; 799 } 800 /* 2. Add addresses on the host but not on the NIC */ 801 for (i = 0; i < nb_mc_addr; i++) { 802 addr = &mc_addr_set[i]; 803 for (j = 0; j < enic->mc_count; j++) { 804 if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j])) 805 break; 806 } 807 if (j < enic->mc_count) 808 continue; 809 debug_log_add_del_addr(addr, true); 810 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes); 811 if (ret) 812 return ret; 813 } 814 /* Keep a copy so we can flush/apply later on.. */ 815 memcpy(enic->mc_addrs, mc_addr_set, 816 nb_mc_addr * sizeof(struct rte_ether_addr)); 817 enic->mc_count = nb_mc_addr; 818 return 0; 819 } 820 821 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 822 { 823 struct enic *enic = pmd_priv(eth_dev); 824 825 ENICPMD_FUNC_TRACE(); 826 return enic_set_mtu(enic, mtu); 827 } 828 829 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev, 830 struct rte_eth_rss_reta_entry64 831 *reta_conf, 832 uint16_t reta_size) 833 { 834 struct enic *enic = pmd_priv(dev); 835 uint16_t i, idx, shift; 836 837 ENICPMD_FUNC_TRACE(); 838 if (reta_size != ENIC_RSS_RETA_SIZE) { 839 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n", 840 reta_size, ENIC_RSS_RETA_SIZE); 841 return -EINVAL; 842 } 843 844 for (i = 0; i < reta_size; i++) { 845 idx = i / RTE_RETA_GROUP_SIZE; 846 shift = i % RTE_RETA_GROUP_SIZE; 847 if (reta_conf[idx].mask & (1ULL << shift)) 848 reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx( 849 enic->rss_cpu.cpu[i / 4].b[i % 4]); 850 } 851 852 return 0; 853 } 854 855 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev, 856 struct rte_eth_rss_reta_entry64 857 *reta_conf, 858 uint16_t reta_size) 859 { 860 struct enic *enic = pmd_priv(dev); 861 union vnic_rss_cpu rss_cpu; 862 uint16_t i, idx, shift; 863 864 ENICPMD_FUNC_TRACE(); 865 if (reta_size != ENIC_RSS_RETA_SIZE) { 866 dev_err(enic, "reta_update: wrong reta_size. given=%u" 867 " expected=%u\n", 868 reta_size, ENIC_RSS_RETA_SIZE); 869 return -EINVAL; 870 } 871 /* 872 * Start with the current reta and modify it per reta_conf, as we 873 * need to push the entire reta even if we only modify one entry. 874 */ 875 rss_cpu = enic->rss_cpu; 876 for (i = 0; i < reta_size; i++) { 877 idx = i / RTE_RETA_GROUP_SIZE; 878 shift = i % RTE_RETA_GROUP_SIZE; 879 if (reta_conf[idx].mask & (1ULL << shift)) 880 rss_cpu.cpu[i / 4].b[i % 4] = 881 enic_rte_rq_idx_to_sop_idx( 882 reta_conf[idx].reta[shift]); 883 } 884 return enic_set_rss_reta(enic, &rss_cpu); 885 } 886 887 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev, 888 struct rte_eth_rss_conf *rss_conf) 889 { 890 struct enic *enic = pmd_priv(dev); 891 892 ENICPMD_FUNC_TRACE(); 893 return enic_set_rss_conf(enic, rss_conf); 894 } 895 896 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 897 struct rte_eth_rss_conf *rss_conf) 898 { 899 struct enic *enic = pmd_priv(dev); 900 901 ENICPMD_FUNC_TRACE(); 902 if (rss_conf == NULL) 903 return -EINVAL; 904 if (rss_conf->rss_key != NULL && 905 rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) { 906 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u" 907 " expected=%u+\n", 908 rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE); 909 return -EINVAL; 910 } 911 rss_conf->rss_hf = enic->rss_hf; 912 if (rss_conf->rss_key != NULL) { 913 int i; 914 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) { 915 rss_conf->rss_key[i] = 916 enic->rss_key.key[i / 10].b[i % 10]; 917 } 918 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE; 919 } 920 return 0; 921 } 922 923 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev, 924 uint16_t rx_queue_id, 925 struct rte_eth_rxq_info *qinfo) 926 { 927 struct enic *enic = pmd_priv(dev); 928 struct vnic_rq *rq_sop; 929 struct vnic_rq *rq_data; 930 struct rte_eth_rxconf *conf; 931 uint16_t sop_queue_idx; 932 uint16_t data_queue_idx; 933 934 ENICPMD_FUNC_TRACE(); 935 sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 936 data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id, enic); 937 rq_sop = &enic->rq[sop_queue_idx]; 938 rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */ 939 qinfo->mp = rq_sop->mp; 940 qinfo->scattered_rx = rq_sop->data_queue_enable; 941 qinfo->nb_desc = rq_sop->ring.desc_count; 942 if (qinfo->scattered_rx) 943 qinfo->nb_desc += rq_data->ring.desc_count; 944 conf = &qinfo->conf; 945 memset(conf, 0, sizeof(*conf)); 946 conf->rx_free_thresh = rq_sop->rx_free_thresh; 947 conf->rx_drop_en = 1; 948 /* 949 * Except VLAN stripping (port setting), all the checksum offloads 950 * are always enabled. 951 */ 952 conf->offloads = enic->rx_offload_capa; 953 if (!enic->ig_vlan_strip_en) 954 conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 955 /* rx_thresh and other fields are not applicable for enic */ 956 } 957 958 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev, 959 uint16_t tx_queue_id, 960 struct rte_eth_txq_info *qinfo) 961 { 962 struct enic *enic = pmd_priv(dev); 963 struct vnic_wq *wq = &enic->wq[tx_queue_id]; 964 965 ENICPMD_FUNC_TRACE(); 966 qinfo->nb_desc = wq->ring.desc_count; 967 memset(&qinfo->conf, 0, sizeof(qinfo->conf)); 968 qinfo->conf.offloads = wq->offloads; 969 /* tx_thresh, and all the other fields are not applicable for enic */ 970 } 971 972 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 973 uint16_t rx_queue_id) 974 { 975 struct enic *enic = pmd_priv(eth_dev); 976 977 ENICPMD_FUNC_TRACE(); 978 vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 979 return 0; 980 } 981 982 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 983 uint16_t rx_queue_id) 984 { 985 struct enic *enic = pmd_priv(eth_dev); 986 987 ENICPMD_FUNC_TRACE(); 988 vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 989 return 0; 990 } 991 992 static int udp_tunnel_common_check(struct enic *enic, 993 struct rte_eth_udp_tunnel *tnl) 994 { 995 if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN) 996 return -ENOTSUP; 997 if (!enic->overlay_offload) { 998 ENICPMD_LOG(DEBUG, " vxlan (overlay offload) is not " 999 "supported\n"); 1000 return -ENOTSUP; 1001 } 1002 return 0; 1003 } 1004 1005 static int update_vxlan_port(struct enic *enic, uint16_t port) 1006 { 1007 if (vnic_dev_overlay_offload_cfg(enic->vdev, 1008 OVERLAY_CFG_VXLAN_PORT_UPDATE, 1009 port)) { 1010 ENICPMD_LOG(DEBUG, " failed to update vxlan port\n"); 1011 return -EINVAL; 1012 } 1013 ENICPMD_LOG(DEBUG, " updated vxlan port to %u\n", port); 1014 enic->vxlan_port = port; 1015 return 0; 1016 } 1017 1018 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev, 1019 struct rte_eth_udp_tunnel *tnl) 1020 { 1021 struct enic *enic = pmd_priv(eth_dev); 1022 int ret; 1023 1024 ENICPMD_FUNC_TRACE(); 1025 ret = udp_tunnel_common_check(enic, tnl); 1026 if (ret) 1027 return ret; 1028 /* 1029 * The NIC has 1 configurable VXLAN port number. "Adding" a new port 1030 * number replaces it. 1031 */ 1032 if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) { 1033 ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n", 1034 tnl->udp_port); 1035 return -EINVAL; 1036 } 1037 return update_vxlan_port(enic, tnl->udp_port); 1038 } 1039 1040 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev, 1041 struct rte_eth_udp_tunnel *tnl) 1042 { 1043 struct enic *enic = pmd_priv(eth_dev); 1044 int ret; 1045 1046 ENICPMD_FUNC_TRACE(); 1047 ret = udp_tunnel_common_check(enic, tnl); 1048 if (ret) 1049 return ret; 1050 /* 1051 * Clear the previously set port number and restore the 1052 * hardware default port number. Some drivers disable VXLAN 1053 * offloads when there are no configured port numbers. But 1054 * enic does not do that as VXLAN is part of overlay offload, 1055 * which is tied to inner RSS and TSO. 1056 */ 1057 if (tnl->udp_port != enic->vxlan_port) { 1058 ENICPMD_LOG(DEBUG, " %u is not a configured vxlan port\n", 1059 tnl->udp_port); 1060 return -EINVAL; 1061 } 1062 return update_vxlan_port(enic, RTE_VXLAN_DEFAULT_PORT); 1063 } 1064 1065 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev, 1066 char *fw_version, size_t fw_size) 1067 { 1068 struct vnic_devcmd_fw_info *info; 1069 struct enic *enic; 1070 int ret; 1071 1072 ENICPMD_FUNC_TRACE(); 1073 if (fw_version == NULL || fw_size <= 0) 1074 return -EINVAL; 1075 enic = pmd_priv(eth_dev); 1076 ret = vnic_dev_fw_info(enic->vdev, &info); 1077 if (ret) 1078 return ret; 1079 snprintf(fw_version, fw_size, "%s %s", 1080 info->fw_version, info->fw_build); 1081 fw_version[fw_size - 1] = '\0'; 1082 return 0; 1083 } 1084 1085 static const struct eth_dev_ops enicpmd_eth_dev_ops = { 1086 .dev_configure = enicpmd_dev_configure, 1087 .dev_start = enicpmd_dev_start, 1088 .dev_stop = enicpmd_dev_stop, 1089 .dev_set_link_up = NULL, 1090 .dev_set_link_down = NULL, 1091 .dev_close = enicpmd_dev_close, 1092 .promiscuous_enable = enicpmd_dev_promiscuous_enable, 1093 .promiscuous_disable = enicpmd_dev_promiscuous_disable, 1094 .allmulticast_enable = enicpmd_dev_allmulticast_enable, 1095 .allmulticast_disable = enicpmd_dev_allmulticast_disable, 1096 .link_update = enicpmd_dev_link_update, 1097 .stats_get = enicpmd_dev_stats_get, 1098 .stats_reset = enicpmd_dev_stats_reset, 1099 .queue_stats_mapping_set = NULL, 1100 .dev_infos_get = enicpmd_dev_info_get, 1101 .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get, 1102 .mtu_set = enicpmd_mtu_set, 1103 .vlan_filter_set = NULL, 1104 .vlan_tpid_set = NULL, 1105 .vlan_offload_set = enicpmd_vlan_offload_set, 1106 .vlan_strip_queue_set = NULL, 1107 .rx_queue_start = enicpmd_dev_rx_queue_start, 1108 .rx_queue_stop = enicpmd_dev_rx_queue_stop, 1109 .tx_queue_start = enicpmd_dev_tx_queue_start, 1110 .tx_queue_stop = enicpmd_dev_tx_queue_stop, 1111 .rx_queue_setup = enicpmd_dev_rx_queue_setup, 1112 .rx_queue_release = enicpmd_dev_rx_queue_release, 1113 .rx_queue_count = enicpmd_dev_rx_queue_count, 1114 .rx_descriptor_done = NULL, 1115 .tx_queue_setup = enicpmd_dev_tx_queue_setup, 1116 .tx_queue_release = enicpmd_dev_tx_queue_release, 1117 .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable, 1118 .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable, 1119 .rxq_info_get = enicpmd_dev_rxq_info_get, 1120 .txq_info_get = enicpmd_dev_txq_info_get, 1121 .dev_led_on = NULL, 1122 .dev_led_off = NULL, 1123 .flow_ctrl_get = NULL, 1124 .flow_ctrl_set = NULL, 1125 .priority_flow_ctrl_set = NULL, 1126 .mac_addr_add = enicpmd_add_mac_addr, 1127 .mac_addr_remove = enicpmd_remove_mac_addr, 1128 .mac_addr_set = enicpmd_set_mac_addr, 1129 .set_mc_addr_list = enicpmd_set_mc_addr_list, 1130 .filter_ctrl = enicpmd_dev_filter_ctrl, 1131 .reta_query = enicpmd_dev_rss_reta_query, 1132 .reta_update = enicpmd_dev_rss_reta_update, 1133 .rss_hash_conf_get = enicpmd_dev_rss_hash_conf_get, 1134 .rss_hash_update = enicpmd_dev_rss_hash_update, 1135 .udp_tunnel_port_add = enicpmd_dev_udp_tunnel_port_add, 1136 .udp_tunnel_port_del = enicpmd_dev_udp_tunnel_port_del, 1137 .fw_version_get = enicpmd_dev_fw_version_get, 1138 }; 1139 1140 static int enic_parse_zero_one(const char *key, 1141 const char *value, 1142 void *opaque) 1143 { 1144 struct enic *enic; 1145 bool b; 1146 1147 enic = (struct enic *)opaque; 1148 if (strcmp(value, "0") == 0) { 1149 b = false; 1150 } else if (strcmp(value, "1") == 0) { 1151 b = true; 1152 } else { 1153 dev_err(enic, "Invalid value for %s" 1154 ": expected=0|1 given=%s\n", key, value); 1155 return -EINVAL; 1156 } 1157 if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0) 1158 enic->disable_overlay = b; 1159 if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0) 1160 enic->enable_avx2_rx = b; 1161 if (strcmp(key, ENIC_DEVARG_GENEVE_OPT) == 0) 1162 enic->geneve_opt_request = b; 1163 return 0; 1164 } 1165 1166 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key, 1167 const char *value, 1168 void *opaque) 1169 { 1170 struct enic *enic; 1171 1172 enic = (struct enic *)opaque; 1173 if (strcmp(value, "trunk") == 0) { 1174 /* Trunk mode: always tag */ 1175 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK; 1176 } else if (strcmp(value, "untag") == 0) { 1177 /* Untag default VLAN mode: untag if VLAN = default VLAN */ 1178 enic->ig_vlan_rewrite_mode = 1179 IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN; 1180 } else if (strcmp(value, "priority") == 0) { 1181 /* 1182 * Priority-tag default VLAN mode: priority tag (VLAN header 1183 * with ID=0) if VLAN = default 1184 */ 1185 enic->ig_vlan_rewrite_mode = 1186 IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN; 1187 } else if (strcmp(value, "pass") == 0) { 1188 /* Pass through mode: do not touch tags */ 1189 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1190 } else { 1191 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE 1192 ": expected=trunk|untag|priority|pass given=%s\n", 1193 value); 1194 return -EINVAL; 1195 } 1196 return 0; 1197 } 1198 1199 static int enic_check_devargs(struct rte_eth_dev *dev) 1200 { 1201 static const char *const valid_keys[] = { 1202 ENIC_DEVARG_DISABLE_OVERLAY, 1203 ENIC_DEVARG_ENABLE_AVX2_RX, 1204 ENIC_DEVARG_GENEVE_OPT, 1205 ENIC_DEVARG_IG_VLAN_REWRITE, 1206 NULL}; 1207 struct enic *enic = pmd_priv(dev); 1208 struct rte_kvargs *kvlist; 1209 1210 ENICPMD_FUNC_TRACE(); 1211 1212 enic->disable_overlay = false; 1213 enic->enable_avx2_rx = false; 1214 enic->geneve_opt_request = false; 1215 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1216 if (!dev->device->devargs) 1217 return 0; 1218 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1219 if (!kvlist) 1220 return -EINVAL; 1221 if (rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY, 1222 enic_parse_zero_one, enic) < 0 || 1223 rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX, 1224 enic_parse_zero_one, enic) < 0 || 1225 rte_kvargs_process(kvlist, ENIC_DEVARG_GENEVE_OPT, 1226 enic_parse_zero_one, enic) < 0 || 1227 rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE, 1228 enic_parse_ig_vlan_rewrite, enic) < 0) { 1229 rte_kvargs_free(kvlist); 1230 return -EINVAL; 1231 } 1232 rte_kvargs_free(kvlist); 1233 return 0; 1234 } 1235 1236 /* Initialize the driver 1237 * It returns 0 on success. 1238 */ 1239 static int eth_enicpmd_dev_init(struct rte_eth_dev *eth_dev) 1240 { 1241 struct rte_pci_device *pdev; 1242 struct rte_pci_addr *addr; 1243 struct enic *enic = pmd_priv(eth_dev); 1244 int err; 1245 1246 ENICPMD_FUNC_TRACE(); 1247 1248 eth_dev->dev_ops = &enicpmd_eth_dev_ops; 1249 eth_dev->rx_pkt_burst = &enic_recv_pkts; 1250 eth_dev->tx_pkt_burst = &enic_xmit_pkts; 1251 eth_dev->tx_pkt_prepare = &enic_prep_pkts; 1252 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1253 enic_pick_tx_handler(eth_dev); 1254 enic_pick_rx_handler(eth_dev); 1255 return 0; 1256 } 1257 /* Only the primary sets up adapter and other data in shared memory */ 1258 enic->port_id = eth_dev->data->port_id; 1259 enic->rte_dev = eth_dev; 1260 enic->dev_data = eth_dev->data; 1261 /* Let rte_eth_dev_close() release the port resources */ 1262 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1263 1264 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 1265 rte_eth_copy_pci_info(eth_dev, pdev); 1266 enic->pdev = pdev; 1267 addr = &pdev->addr; 1268 1269 snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x", 1270 addr->domain, addr->bus, addr->devid, addr->function); 1271 1272 err = enic_check_devargs(eth_dev); 1273 if (err) 1274 return err; 1275 return enic_probe(enic); 1276 } 1277 1278 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1279 struct rte_pci_device *pci_dev) 1280 { 1281 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct enic), 1282 eth_enicpmd_dev_init); 1283 } 1284 1285 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev) 1286 { 1287 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 1288 } 1289 1290 static struct rte_pci_driver rte_enic_pmd = { 1291 .id_table = pci_id_enic_map, 1292 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1293 .probe = eth_enic_pci_probe, 1294 .remove = eth_enic_pci_remove, 1295 }; 1296 1297 int dev_is_enic(struct rte_eth_dev *dev) 1298 { 1299 return dev->device->driver == &rte_enic_pmd.driver; 1300 } 1301 1302 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd); 1303 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map); 1304 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci"); 1305 RTE_PMD_REGISTER_PARAM_STRING(net_enic, 1306 ENIC_DEVARG_DISABLE_OVERLAY "=0|1 " 1307 ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 " 1308 ENIC_DEVARG_GENEVE_OPT "=0|1 " 1309 ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass"); 1310