1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 */ 5 6 #include <stdio.h> 7 #include <stdint.h> 8 9 #include <rte_dev.h> 10 #include <rte_pci.h> 11 #include <rte_bus_pci.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_ethdev_pci.h> 14 #include <rte_kvargs.h> 15 #include <rte_string_fns.h> 16 17 #include "vnic_intr.h" 18 #include "vnic_cq.h" 19 #include "vnic_wq.h" 20 #include "vnic_rq.h" 21 #include "vnic_enet.h" 22 #include "enic.h" 23 24 int enic_pmd_logtype; 25 26 /* 27 * The set of PCI devices this driver supports 28 */ 29 #define CISCO_PCI_VENDOR_ID 0x1137 30 static const struct rte_pci_id pci_id_enic_map[] = { 31 { RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET) }, 32 { RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) }, 33 {.vendor_id = 0, /* sentinel */}, 34 }; 35 36 /* Supported link speeds of production VIC models */ 37 static const struct vic_speed_capa { 38 uint16_t sub_devid; 39 uint32_t capa; 40 } vic_speed_capa_map[] = { 41 { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */ 42 { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */ 43 { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */ 44 { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */ 45 { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */ 46 { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */ 47 { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */ 48 { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */ 49 { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */ 50 { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */ 51 { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */ 52 { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */ 53 { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */ 54 { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */ 55 { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 56 ETH_LINK_SPEED_40G }, /* 1440 Mezz */ 57 { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 58 ETH_LINK_SPEED_40G }, /* 1480 MLOM */ 59 { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */ 60 { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */ 61 { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */ 62 { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */ 63 { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */ 64 { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */ 65 { 0, 0 }, /* End marker */ 66 }; 67 68 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay" 69 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx" 70 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite" 71 72 RTE_INIT(enicpmd_init_log) 73 { 74 enic_pmd_logtype = rte_log_register("pmd.net.enic"); 75 if (enic_pmd_logtype >= 0) 76 rte_log_set_level(enic_pmd_logtype, RTE_LOG_INFO); 77 } 78 79 static int 80 enicpmd_fdir_ctrl_func(struct rte_eth_dev *eth_dev, 81 enum rte_filter_op filter_op, void *arg) 82 { 83 struct enic *enic = pmd_priv(eth_dev); 84 int ret = 0; 85 86 ENICPMD_FUNC_TRACE(); 87 if (filter_op == RTE_ETH_FILTER_NOP) 88 return 0; 89 90 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 91 return -EINVAL; 92 93 switch (filter_op) { 94 case RTE_ETH_FILTER_ADD: 95 case RTE_ETH_FILTER_UPDATE: 96 ret = enic_fdir_add_fltr(enic, 97 (struct rte_eth_fdir_filter *)arg); 98 break; 99 100 case RTE_ETH_FILTER_DELETE: 101 ret = enic_fdir_del_fltr(enic, 102 (struct rte_eth_fdir_filter *)arg); 103 break; 104 105 case RTE_ETH_FILTER_STATS: 106 enic_fdir_stats_get(enic, (struct rte_eth_fdir_stats *)arg); 107 break; 108 109 case RTE_ETH_FILTER_FLUSH: 110 dev_warning(enic, "unsupported operation %u", filter_op); 111 ret = -ENOTSUP; 112 break; 113 case RTE_ETH_FILTER_INFO: 114 enic_fdir_info_get(enic, (struct rte_eth_fdir_info *)arg); 115 break; 116 default: 117 dev_err(enic, "unknown operation %u", filter_op); 118 ret = -EINVAL; 119 break; 120 } 121 return ret; 122 } 123 124 static int 125 enicpmd_dev_filter_ctrl(struct rte_eth_dev *dev, 126 enum rte_filter_type filter_type, 127 enum rte_filter_op filter_op, 128 void *arg) 129 { 130 int ret = 0; 131 132 ENICPMD_FUNC_TRACE(); 133 134 switch (filter_type) { 135 case RTE_ETH_FILTER_GENERIC: 136 if (filter_op != RTE_ETH_FILTER_GET) 137 return -EINVAL; 138 *(const void **)arg = &enic_flow_ops; 139 break; 140 case RTE_ETH_FILTER_FDIR: 141 ret = enicpmd_fdir_ctrl_func(dev, filter_op, arg); 142 break; 143 default: 144 dev_warning(enic, "Filter type (%d) not supported", 145 filter_type); 146 ret = -EINVAL; 147 break; 148 } 149 150 return ret; 151 } 152 153 static void enicpmd_dev_tx_queue_release(void *txq) 154 { 155 ENICPMD_FUNC_TRACE(); 156 157 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 158 return; 159 160 enic_free_wq(txq); 161 } 162 163 static int enicpmd_dev_setup_intr(struct enic *enic) 164 { 165 int ret; 166 unsigned int index; 167 168 ENICPMD_FUNC_TRACE(); 169 170 /* Are we done with the init of all the queues? */ 171 for (index = 0; index < enic->cq_count; index++) { 172 if (!enic->cq[index].ctrl) 173 break; 174 } 175 if (enic->cq_count != index) 176 return 0; 177 for (index = 0; index < enic->wq_count; index++) { 178 if (!enic->wq[index].ctrl) 179 break; 180 } 181 if (enic->wq_count != index) 182 return 0; 183 /* check start of packet (SOP) RQs only in case scatter is disabled. */ 184 for (index = 0; index < enic->rq_count; index++) { 185 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl) 186 break; 187 } 188 if (enic->rq_count != index) 189 return 0; 190 191 ret = enic_alloc_intr_resources(enic); 192 if (ret) { 193 dev_err(enic, "alloc intr failed\n"); 194 return ret; 195 } 196 enic_init_vnic_resources(enic); 197 198 ret = enic_setup_finish(enic); 199 if (ret) 200 dev_err(enic, "setup could not be finished\n"); 201 202 return ret; 203 } 204 205 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 206 uint16_t queue_idx, 207 uint16_t nb_desc, 208 unsigned int socket_id, 209 const struct rte_eth_txconf *tx_conf) 210 { 211 int ret; 212 struct enic *enic = pmd_priv(eth_dev); 213 struct vnic_wq *wq; 214 215 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 216 return -E_RTE_SECONDARY; 217 218 ENICPMD_FUNC_TRACE(); 219 RTE_ASSERT(queue_idx < enic->conf_wq_count); 220 wq = &enic->wq[queue_idx]; 221 wq->offloads = tx_conf->offloads | 222 eth_dev->data->dev_conf.txmode.offloads; 223 eth_dev->data->tx_queues[queue_idx] = (void *)wq; 224 225 ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc); 226 if (ret) { 227 dev_err(enic, "error in allocating wq\n"); 228 return ret; 229 } 230 231 return enicpmd_dev_setup_intr(enic); 232 } 233 234 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 235 uint16_t queue_idx) 236 { 237 struct enic *enic = pmd_priv(eth_dev); 238 239 ENICPMD_FUNC_TRACE(); 240 241 enic_start_wq(enic, queue_idx); 242 243 return 0; 244 } 245 246 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, 247 uint16_t queue_idx) 248 { 249 int ret; 250 struct enic *enic = pmd_priv(eth_dev); 251 252 ENICPMD_FUNC_TRACE(); 253 254 ret = enic_stop_wq(enic, queue_idx); 255 if (ret) 256 dev_err(enic, "error in stopping wq %d\n", queue_idx); 257 258 return ret; 259 } 260 261 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 262 uint16_t queue_idx) 263 { 264 struct enic *enic = pmd_priv(eth_dev); 265 266 ENICPMD_FUNC_TRACE(); 267 268 enic_start_rq(enic, queue_idx); 269 270 return 0; 271 } 272 273 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, 274 uint16_t queue_idx) 275 { 276 int ret; 277 struct enic *enic = pmd_priv(eth_dev); 278 279 ENICPMD_FUNC_TRACE(); 280 281 ret = enic_stop_rq(enic, queue_idx); 282 if (ret) 283 dev_err(enic, "error in stopping rq %d\n", queue_idx); 284 285 return ret; 286 } 287 288 static void enicpmd_dev_rx_queue_release(void *rxq) 289 { 290 ENICPMD_FUNC_TRACE(); 291 292 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 293 return; 294 295 enic_free_rq(rxq); 296 } 297 298 static uint32_t enicpmd_dev_rx_queue_count(struct rte_eth_dev *dev, 299 uint16_t rx_queue_id) 300 { 301 struct enic *enic = pmd_priv(dev); 302 uint32_t queue_count = 0; 303 struct vnic_cq *cq; 304 uint32_t cq_tail; 305 uint16_t cq_idx; 306 int rq_num; 307 308 rq_num = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 309 cq = &enic->cq[enic_cq_rq(enic, rq_num)]; 310 cq_idx = cq->to_clean; 311 312 cq_tail = ioread32(&cq->ctrl->cq_tail); 313 314 if (cq_tail < cq_idx) 315 cq_tail += cq->ring.desc_count; 316 317 queue_count = cq_tail - cq_idx; 318 319 return queue_count; 320 } 321 322 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 323 uint16_t queue_idx, 324 uint16_t nb_desc, 325 unsigned int socket_id, 326 const struct rte_eth_rxconf *rx_conf, 327 struct rte_mempool *mp) 328 { 329 int ret; 330 struct enic *enic = pmd_priv(eth_dev); 331 332 ENICPMD_FUNC_TRACE(); 333 334 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 335 return -E_RTE_SECONDARY; 336 RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count); 337 eth_dev->data->rx_queues[queue_idx] = 338 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)]; 339 340 ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc, 341 rx_conf->rx_free_thresh); 342 if (ret) { 343 dev_err(enic, "error in allocating rq\n"); 344 return ret; 345 } 346 347 return enicpmd_dev_setup_intr(enic); 348 } 349 350 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 351 { 352 struct enic *enic = pmd_priv(eth_dev); 353 uint64_t offloads; 354 355 ENICPMD_FUNC_TRACE(); 356 357 offloads = eth_dev->data->dev_conf.rxmode.offloads; 358 if (mask & ETH_VLAN_STRIP_MASK) { 359 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 360 enic->ig_vlan_strip_en = 1; 361 else 362 enic->ig_vlan_strip_en = 0; 363 } 364 365 if ((mask & ETH_VLAN_FILTER_MASK) && 366 (offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 367 dev_warning(enic, 368 "Configuration of VLAN filter is not supported\n"); 369 } 370 371 if ((mask & ETH_VLAN_EXTEND_MASK) && 372 (offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)) { 373 dev_warning(enic, 374 "Configuration of extended VLAN is not supported\n"); 375 } 376 377 return enic_set_vlan_strip(enic); 378 } 379 380 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev) 381 { 382 int ret; 383 int mask; 384 struct enic *enic = pmd_priv(eth_dev); 385 386 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 387 return -E_RTE_SECONDARY; 388 389 ENICPMD_FUNC_TRACE(); 390 ret = enic_set_vnic_res(enic); 391 if (ret) { 392 dev_err(enic, "Set vNIC resource num failed, aborting\n"); 393 return ret; 394 } 395 396 enic->mc_count = 0; 397 enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads & 398 DEV_RX_OFFLOAD_CHECKSUM); 399 /* All vlan offload masks to apply the current settings */ 400 mask = ETH_VLAN_STRIP_MASK | 401 ETH_VLAN_FILTER_MASK | 402 ETH_VLAN_EXTEND_MASK; 403 ret = enicpmd_vlan_offload_set(eth_dev, mask); 404 if (ret) { 405 dev_err(enic, "Failed to configure VLAN offloads\n"); 406 return ret; 407 } 408 /* 409 * Initialize RSS with the default reta and key. If the user key is 410 * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the 411 * default key. 412 */ 413 return enic_init_rss_nic_cfg(enic); 414 } 415 416 /* Start the device. 417 * It returns 0 on success. 418 */ 419 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev) 420 { 421 struct enic *enic = pmd_priv(eth_dev); 422 423 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 424 return -E_RTE_SECONDARY; 425 426 ENICPMD_FUNC_TRACE(); 427 return enic_enable(enic); 428 } 429 430 /* 431 * Stop device: disable rx and tx functions to allow for reconfiguring. 432 */ 433 static void enicpmd_dev_stop(struct rte_eth_dev *eth_dev) 434 { 435 struct rte_eth_link link; 436 struct enic *enic = pmd_priv(eth_dev); 437 438 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 439 return; 440 441 ENICPMD_FUNC_TRACE(); 442 enic_disable(enic); 443 444 memset(&link, 0, sizeof(link)); 445 rte_eth_linkstatus_set(eth_dev, &link); 446 } 447 448 /* 449 * Stop device. 450 */ 451 static void enicpmd_dev_close(struct rte_eth_dev *eth_dev) 452 { 453 struct enic *enic = pmd_priv(eth_dev); 454 455 ENICPMD_FUNC_TRACE(); 456 enic_remove(enic); 457 } 458 459 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev, 460 __rte_unused int wait_to_complete) 461 { 462 struct enic *enic = pmd_priv(eth_dev); 463 464 ENICPMD_FUNC_TRACE(); 465 return enic_link_update(enic); 466 } 467 468 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev, 469 struct rte_eth_stats *stats) 470 { 471 struct enic *enic = pmd_priv(eth_dev); 472 473 ENICPMD_FUNC_TRACE(); 474 return enic_dev_stats_get(enic, stats); 475 } 476 477 static void enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev) 478 { 479 struct enic *enic = pmd_priv(eth_dev); 480 481 ENICPMD_FUNC_TRACE(); 482 enic_dev_stats_clear(enic); 483 } 484 485 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev) 486 { 487 const struct vic_speed_capa *m; 488 struct rte_pci_device *pdev; 489 uint16_t id; 490 491 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 492 id = pdev->id.subsystem_device_id; 493 for (m = vic_speed_capa_map; m->sub_devid != 0; m++) { 494 if (m->sub_devid == id) 495 return m->capa; 496 } 497 /* 1300 and later models are at least 40G */ 498 if (id >= 0x0100) 499 return ETH_LINK_SPEED_40G; 500 return ETH_LINK_SPEED_10G; 501 } 502 503 static void enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, 504 struct rte_eth_dev_info *device_info) 505 { 506 struct enic *enic = pmd_priv(eth_dev); 507 508 ENICPMD_FUNC_TRACE(); 509 /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */ 510 device_info->max_rx_queues = enic->conf_rq_count / 2; 511 device_info->max_tx_queues = enic->conf_wq_count; 512 device_info->min_rx_bufsize = ENIC_MIN_MTU; 513 /* "Max" mtu is not a typo. HW receives packet sizes up to the 514 * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is 515 * a hint to the driver to size receive buffers accordingly so that 516 * larger-than-vnic-mtu packets get truncated.. For DPDK, we let 517 * the user decide the buffer size via rxmode.max_rx_pkt_len, basically 518 * ignoring vNIC mtu. 519 */ 520 device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu); 521 device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS; 522 device_info->min_mtu = ENIC_MIN_MTU; 523 device_info->max_mtu = enic->max_mtu; 524 device_info->rx_offload_capa = enic->rx_offload_capa; 525 device_info->tx_offload_capa = enic->tx_offload_capa; 526 device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa; 527 device_info->default_rxconf = (struct rte_eth_rxconf) { 528 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH 529 }; 530 device_info->reta_size = enic->reta_size; 531 device_info->hash_key_size = enic->hash_key_size; 532 device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads; 533 device_info->rx_desc_lim = (struct rte_eth_desc_lim) { 534 .nb_max = enic->config.rq_desc_count, 535 .nb_min = ENIC_MIN_RQ_DESCS, 536 .nb_align = ENIC_ALIGN_DESCS, 537 }; 538 device_info->tx_desc_lim = (struct rte_eth_desc_lim) { 539 .nb_max = enic->config.wq_desc_count, 540 .nb_min = ENIC_MIN_WQ_DESCS, 541 .nb_align = ENIC_ALIGN_DESCS, 542 .nb_seg_max = ENIC_TX_XMIT_MAX, 543 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC, 544 }; 545 device_info->default_rxportconf = (struct rte_eth_dev_portconf) { 546 .burst_size = ENIC_DEFAULT_RX_BURST, 547 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max, 548 ENIC_DEFAULT_RX_RING_SIZE), 549 .nb_queues = ENIC_DEFAULT_RX_RINGS, 550 }; 551 device_info->default_txportconf = (struct rte_eth_dev_portconf) { 552 .burst_size = ENIC_DEFAULT_TX_BURST, 553 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max, 554 ENIC_DEFAULT_TX_RING_SIZE), 555 .nb_queues = ENIC_DEFAULT_TX_RINGS, 556 }; 557 device_info->speed_capa = speed_capa_from_pci_id(eth_dev); 558 } 559 560 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev) 561 { 562 static const uint32_t ptypes[] = { 563 RTE_PTYPE_L2_ETHER, 564 RTE_PTYPE_L2_ETHER_VLAN, 565 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 566 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 567 RTE_PTYPE_L4_TCP, 568 RTE_PTYPE_L4_UDP, 569 RTE_PTYPE_L4_FRAG, 570 RTE_PTYPE_L4_NONFRAG, 571 RTE_PTYPE_UNKNOWN 572 }; 573 static const uint32_t ptypes_overlay[] = { 574 RTE_PTYPE_L2_ETHER, 575 RTE_PTYPE_L2_ETHER_VLAN, 576 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 577 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 578 RTE_PTYPE_L4_TCP, 579 RTE_PTYPE_L4_UDP, 580 RTE_PTYPE_L4_FRAG, 581 RTE_PTYPE_L4_NONFRAG, 582 RTE_PTYPE_TUNNEL_GRENAT, 583 RTE_PTYPE_INNER_L2_ETHER, 584 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 585 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 586 RTE_PTYPE_INNER_L4_TCP, 587 RTE_PTYPE_INNER_L4_UDP, 588 RTE_PTYPE_INNER_L4_FRAG, 589 RTE_PTYPE_INNER_L4_NONFRAG, 590 RTE_PTYPE_UNKNOWN 591 }; 592 593 if (dev->rx_pkt_burst != enic_dummy_recv_pkts && 594 dev->rx_pkt_burst != NULL) { 595 struct enic *enic = pmd_priv(dev); 596 if (enic->overlay_offload) 597 return ptypes_overlay; 598 else 599 return ptypes; 600 } 601 return NULL; 602 } 603 604 static void enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 605 { 606 struct enic *enic = pmd_priv(eth_dev); 607 608 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 609 return; 610 611 ENICPMD_FUNC_TRACE(); 612 613 enic->promisc = 1; 614 enic_add_packet_filter(enic); 615 } 616 617 static void enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 618 { 619 struct enic *enic = pmd_priv(eth_dev); 620 621 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 622 return; 623 624 ENICPMD_FUNC_TRACE(); 625 enic->promisc = 0; 626 enic_add_packet_filter(enic); 627 } 628 629 static void enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 630 { 631 struct enic *enic = pmd_priv(eth_dev); 632 633 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 634 return; 635 636 ENICPMD_FUNC_TRACE(); 637 enic->allmulti = 1; 638 enic_add_packet_filter(enic); 639 } 640 641 static void enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 642 { 643 struct enic *enic = pmd_priv(eth_dev); 644 645 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 646 return; 647 648 ENICPMD_FUNC_TRACE(); 649 enic->allmulti = 0; 650 enic_add_packet_filter(enic); 651 } 652 653 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev, 654 struct rte_ether_addr *mac_addr, 655 __rte_unused uint32_t index, __rte_unused uint32_t pool) 656 { 657 struct enic *enic = pmd_priv(eth_dev); 658 659 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 660 return -E_RTE_SECONDARY; 661 662 ENICPMD_FUNC_TRACE(); 663 return enic_set_mac_address(enic, mac_addr->addr_bytes); 664 } 665 666 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index) 667 { 668 struct enic *enic = pmd_priv(eth_dev); 669 670 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 671 return; 672 673 ENICPMD_FUNC_TRACE(); 674 if (enic_del_mac_address(enic, index)) 675 dev_err(enic, "del mac addr failed\n"); 676 } 677 678 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev, 679 struct rte_ether_addr *addr) 680 { 681 struct enic *enic = pmd_priv(eth_dev); 682 int ret; 683 684 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 685 return -E_RTE_SECONDARY; 686 687 ENICPMD_FUNC_TRACE(); 688 ret = enic_del_mac_address(enic, 0); 689 if (ret) 690 return ret; 691 return enic_set_mac_address(enic, addr->addr_bytes); 692 } 693 694 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add) 695 { 696 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 697 698 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr); 699 ENICPMD_LOG(DEBUG, " %s address %s\n", 700 add ? "add" : "remove", mac_str); 701 } 702 703 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev, 704 struct rte_ether_addr *mc_addr_set, 705 uint32_t nb_mc_addr) 706 { 707 struct enic *enic = pmd_priv(eth_dev); 708 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 709 struct rte_ether_addr *addr; 710 uint32_t i, j; 711 int ret; 712 713 ENICPMD_FUNC_TRACE(); 714 715 /* Validate the given addresses first */ 716 for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) { 717 addr = &mc_addr_set[i]; 718 if (!rte_is_multicast_ether_addr(addr) || 719 rte_is_broadcast_ether_addr(addr)) { 720 rte_ether_format_addr(mac_str, 721 RTE_ETHER_ADDR_FMT_SIZE, addr); 722 ENICPMD_LOG(ERR, " invalid multicast address %s\n", 723 mac_str); 724 return -EINVAL; 725 } 726 } 727 728 /* Flush all if requested */ 729 if (nb_mc_addr == 0 || mc_addr_set == NULL) { 730 ENICPMD_LOG(DEBUG, " flush multicast addresses\n"); 731 for (i = 0; i < enic->mc_count; i++) { 732 addr = &enic->mc_addrs[i]; 733 debug_log_add_del_addr(addr, false); 734 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 735 if (ret) 736 return ret; 737 } 738 enic->mc_count = 0; 739 return 0; 740 } 741 742 if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) { 743 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n", 744 ENIC_MULTICAST_PERFECT_FILTERS); 745 return -ENOSPC; 746 } 747 /* 748 * devcmd is slow, so apply the difference instead of flushing and 749 * adding everything. 750 * 1. Delete addresses on the NIC but not on the host 751 */ 752 for (i = 0; i < enic->mc_count; i++) { 753 addr = &enic->mc_addrs[i]; 754 for (j = 0; j < nb_mc_addr; j++) { 755 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) 756 break; 757 } 758 if (j < nb_mc_addr) 759 continue; 760 debug_log_add_del_addr(addr, false); 761 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 762 if (ret) 763 return ret; 764 } 765 /* 2. Add addresses on the host but not on the NIC */ 766 for (i = 0; i < nb_mc_addr; i++) { 767 addr = &mc_addr_set[i]; 768 for (j = 0; j < enic->mc_count; j++) { 769 if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j])) 770 break; 771 } 772 if (j < enic->mc_count) 773 continue; 774 debug_log_add_del_addr(addr, true); 775 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes); 776 if (ret) 777 return ret; 778 } 779 /* Keep a copy so we can flush/apply later on.. */ 780 memcpy(enic->mc_addrs, mc_addr_set, 781 nb_mc_addr * sizeof(struct rte_ether_addr)); 782 enic->mc_count = nb_mc_addr; 783 return 0; 784 } 785 786 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 787 { 788 struct enic *enic = pmd_priv(eth_dev); 789 790 ENICPMD_FUNC_TRACE(); 791 return enic_set_mtu(enic, mtu); 792 } 793 794 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev, 795 struct rte_eth_rss_reta_entry64 796 *reta_conf, 797 uint16_t reta_size) 798 { 799 struct enic *enic = pmd_priv(dev); 800 uint16_t i, idx, shift; 801 802 ENICPMD_FUNC_TRACE(); 803 if (reta_size != ENIC_RSS_RETA_SIZE) { 804 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n", 805 reta_size, ENIC_RSS_RETA_SIZE); 806 return -EINVAL; 807 } 808 809 for (i = 0; i < reta_size; i++) { 810 idx = i / RTE_RETA_GROUP_SIZE; 811 shift = i % RTE_RETA_GROUP_SIZE; 812 if (reta_conf[idx].mask & (1ULL << shift)) 813 reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx( 814 enic->rss_cpu.cpu[i / 4].b[i % 4]); 815 } 816 817 return 0; 818 } 819 820 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev, 821 struct rte_eth_rss_reta_entry64 822 *reta_conf, 823 uint16_t reta_size) 824 { 825 struct enic *enic = pmd_priv(dev); 826 union vnic_rss_cpu rss_cpu; 827 uint16_t i, idx, shift; 828 829 ENICPMD_FUNC_TRACE(); 830 if (reta_size != ENIC_RSS_RETA_SIZE) { 831 dev_err(enic, "reta_update: wrong reta_size. given=%u" 832 " expected=%u\n", 833 reta_size, ENIC_RSS_RETA_SIZE); 834 return -EINVAL; 835 } 836 /* 837 * Start with the current reta and modify it per reta_conf, as we 838 * need to push the entire reta even if we only modify one entry. 839 */ 840 rss_cpu = enic->rss_cpu; 841 for (i = 0; i < reta_size; i++) { 842 idx = i / RTE_RETA_GROUP_SIZE; 843 shift = i % RTE_RETA_GROUP_SIZE; 844 if (reta_conf[idx].mask & (1ULL << shift)) 845 rss_cpu.cpu[i / 4].b[i % 4] = 846 enic_rte_rq_idx_to_sop_idx( 847 reta_conf[idx].reta[shift]); 848 } 849 return enic_set_rss_reta(enic, &rss_cpu); 850 } 851 852 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev, 853 struct rte_eth_rss_conf *rss_conf) 854 { 855 struct enic *enic = pmd_priv(dev); 856 857 ENICPMD_FUNC_TRACE(); 858 return enic_set_rss_conf(enic, rss_conf); 859 } 860 861 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 862 struct rte_eth_rss_conf *rss_conf) 863 { 864 struct enic *enic = pmd_priv(dev); 865 866 ENICPMD_FUNC_TRACE(); 867 if (rss_conf == NULL) 868 return -EINVAL; 869 if (rss_conf->rss_key != NULL && 870 rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) { 871 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u" 872 " expected=%u+\n", 873 rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE); 874 return -EINVAL; 875 } 876 rss_conf->rss_hf = enic->rss_hf; 877 if (rss_conf->rss_key != NULL) { 878 int i; 879 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) { 880 rss_conf->rss_key[i] = 881 enic->rss_key.key[i / 10].b[i % 10]; 882 } 883 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE; 884 } 885 return 0; 886 } 887 888 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev, 889 uint16_t rx_queue_id, 890 struct rte_eth_rxq_info *qinfo) 891 { 892 struct enic *enic = pmd_priv(dev); 893 struct vnic_rq *rq_sop; 894 struct vnic_rq *rq_data; 895 struct rte_eth_rxconf *conf; 896 uint16_t sop_queue_idx; 897 uint16_t data_queue_idx; 898 899 ENICPMD_FUNC_TRACE(); 900 sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 901 data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id); 902 rq_sop = &enic->rq[sop_queue_idx]; 903 rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */ 904 qinfo->mp = rq_sop->mp; 905 qinfo->scattered_rx = rq_sop->data_queue_enable; 906 qinfo->nb_desc = rq_sop->ring.desc_count; 907 if (qinfo->scattered_rx) 908 qinfo->nb_desc += rq_data->ring.desc_count; 909 conf = &qinfo->conf; 910 memset(conf, 0, sizeof(*conf)); 911 conf->rx_free_thresh = rq_sop->rx_free_thresh; 912 conf->rx_drop_en = 1; 913 /* 914 * Except VLAN stripping (port setting), all the checksum offloads 915 * are always enabled. 916 */ 917 conf->offloads = enic->rx_offload_capa; 918 if (!enic->ig_vlan_strip_en) 919 conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 920 /* rx_thresh and other fields are not applicable for enic */ 921 } 922 923 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev, 924 uint16_t tx_queue_id, 925 struct rte_eth_txq_info *qinfo) 926 { 927 struct enic *enic = pmd_priv(dev); 928 struct vnic_wq *wq = &enic->wq[tx_queue_id]; 929 930 ENICPMD_FUNC_TRACE(); 931 qinfo->nb_desc = wq->ring.desc_count; 932 memset(&qinfo->conf, 0, sizeof(qinfo->conf)); 933 qinfo->conf.offloads = wq->offloads; 934 /* tx_thresh, and all the other fields are not applicable for enic */ 935 } 936 937 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 938 uint16_t rx_queue_id) 939 { 940 struct enic *enic = pmd_priv(eth_dev); 941 942 ENICPMD_FUNC_TRACE(); 943 vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 944 return 0; 945 } 946 947 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 948 uint16_t rx_queue_id) 949 { 950 struct enic *enic = pmd_priv(eth_dev); 951 952 ENICPMD_FUNC_TRACE(); 953 vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 954 return 0; 955 } 956 957 static int udp_tunnel_common_check(struct enic *enic, 958 struct rte_eth_udp_tunnel *tnl) 959 { 960 if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN) 961 return -ENOTSUP; 962 if (!enic->overlay_offload) { 963 ENICPMD_LOG(DEBUG, " vxlan (overlay offload) is not " 964 "supported\n"); 965 return -ENOTSUP; 966 } 967 return 0; 968 } 969 970 static int update_vxlan_port(struct enic *enic, uint16_t port) 971 { 972 if (vnic_dev_overlay_offload_cfg(enic->vdev, 973 OVERLAY_CFG_VXLAN_PORT_UPDATE, 974 port)) { 975 ENICPMD_LOG(DEBUG, " failed to update vxlan port\n"); 976 return -EINVAL; 977 } 978 ENICPMD_LOG(DEBUG, " updated vxlan port to %u\n", port); 979 enic->vxlan_port = port; 980 return 0; 981 } 982 983 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev, 984 struct rte_eth_udp_tunnel *tnl) 985 { 986 struct enic *enic = pmd_priv(eth_dev); 987 int ret; 988 989 ENICPMD_FUNC_TRACE(); 990 ret = udp_tunnel_common_check(enic, tnl); 991 if (ret) 992 return ret; 993 /* 994 * The NIC has 1 configurable VXLAN port number. "Adding" a new port 995 * number replaces it. 996 */ 997 if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) { 998 ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n", 999 tnl->udp_port); 1000 return -EINVAL; 1001 } 1002 return update_vxlan_port(enic, tnl->udp_port); 1003 } 1004 1005 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev, 1006 struct rte_eth_udp_tunnel *tnl) 1007 { 1008 struct enic *enic = pmd_priv(eth_dev); 1009 int ret; 1010 1011 ENICPMD_FUNC_TRACE(); 1012 ret = udp_tunnel_common_check(enic, tnl); 1013 if (ret) 1014 return ret; 1015 /* 1016 * Clear the previously set port number and restore the 1017 * hardware default port number. Some drivers disable VXLAN 1018 * offloads when there are no configured port numbers. But 1019 * enic does not do that as VXLAN is part of overlay offload, 1020 * which is tied to inner RSS and TSO. 1021 */ 1022 if (tnl->udp_port != enic->vxlan_port) { 1023 ENICPMD_LOG(DEBUG, " %u is not a configured vxlan port\n", 1024 tnl->udp_port); 1025 return -EINVAL; 1026 } 1027 return update_vxlan_port(enic, ENIC_DEFAULT_VXLAN_PORT); 1028 } 1029 1030 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev, 1031 char *fw_version, size_t fw_size) 1032 { 1033 struct vnic_devcmd_fw_info *info; 1034 struct enic *enic; 1035 int ret; 1036 1037 ENICPMD_FUNC_TRACE(); 1038 if (fw_version == NULL || fw_size <= 0) 1039 return -EINVAL; 1040 enic = pmd_priv(eth_dev); 1041 ret = vnic_dev_fw_info(enic->vdev, &info); 1042 if (ret) 1043 return ret; 1044 snprintf(fw_version, fw_size, "%s %s", 1045 info->fw_version, info->fw_build); 1046 fw_version[fw_size - 1] = '\0'; 1047 return 0; 1048 } 1049 1050 static const struct eth_dev_ops enicpmd_eth_dev_ops = { 1051 .dev_configure = enicpmd_dev_configure, 1052 .dev_start = enicpmd_dev_start, 1053 .dev_stop = enicpmd_dev_stop, 1054 .dev_set_link_up = NULL, 1055 .dev_set_link_down = NULL, 1056 .dev_close = enicpmd_dev_close, 1057 .promiscuous_enable = enicpmd_dev_promiscuous_enable, 1058 .promiscuous_disable = enicpmd_dev_promiscuous_disable, 1059 .allmulticast_enable = enicpmd_dev_allmulticast_enable, 1060 .allmulticast_disable = enicpmd_dev_allmulticast_disable, 1061 .link_update = enicpmd_dev_link_update, 1062 .stats_get = enicpmd_dev_stats_get, 1063 .stats_reset = enicpmd_dev_stats_reset, 1064 .queue_stats_mapping_set = NULL, 1065 .dev_infos_get = enicpmd_dev_info_get, 1066 .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get, 1067 .mtu_set = enicpmd_mtu_set, 1068 .vlan_filter_set = NULL, 1069 .vlan_tpid_set = NULL, 1070 .vlan_offload_set = enicpmd_vlan_offload_set, 1071 .vlan_strip_queue_set = NULL, 1072 .rx_queue_start = enicpmd_dev_rx_queue_start, 1073 .rx_queue_stop = enicpmd_dev_rx_queue_stop, 1074 .tx_queue_start = enicpmd_dev_tx_queue_start, 1075 .tx_queue_stop = enicpmd_dev_tx_queue_stop, 1076 .rx_queue_setup = enicpmd_dev_rx_queue_setup, 1077 .rx_queue_release = enicpmd_dev_rx_queue_release, 1078 .rx_queue_count = enicpmd_dev_rx_queue_count, 1079 .rx_descriptor_done = NULL, 1080 .tx_queue_setup = enicpmd_dev_tx_queue_setup, 1081 .tx_queue_release = enicpmd_dev_tx_queue_release, 1082 .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable, 1083 .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable, 1084 .rxq_info_get = enicpmd_dev_rxq_info_get, 1085 .txq_info_get = enicpmd_dev_txq_info_get, 1086 .dev_led_on = NULL, 1087 .dev_led_off = NULL, 1088 .flow_ctrl_get = NULL, 1089 .flow_ctrl_set = NULL, 1090 .priority_flow_ctrl_set = NULL, 1091 .mac_addr_add = enicpmd_add_mac_addr, 1092 .mac_addr_remove = enicpmd_remove_mac_addr, 1093 .mac_addr_set = enicpmd_set_mac_addr, 1094 .set_mc_addr_list = enicpmd_set_mc_addr_list, 1095 .filter_ctrl = enicpmd_dev_filter_ctrl, 1096 .reta_query = enicpmd_dev_rss_reta_query, 1097 .reta_update = enicpmd_dev_rss_reta_update, 1098 .rss_hash_conf_get = enicpmd_dev_rss_hash_conf_get, 1099 .rss_hash_update = enicpmd_dev_rss_hash_update, 1100 .udp_tunnel_port_add = enicpmd_dev_udp_tunnel_port_add, 1101 .udp_tunnel_port_del = enicpmd_dev_udp_tunnel_port_del, 1102 .fw_version_get = enicpmd_dev_fw_version_get, 1103 }; 1104 1105 static int enic_parse_zero_one(const char *key, 1106 const char *value, 1107 void *opaque) 1108 { 1109 struct enic *enic; 1110 bool b; 1111 1112 enic = (struct enic *)opaque; 1113 if (strcmp(value, "0") == 0) { 1114 b = false; 1115 } else if (strcmp(value, "1") == 0) { 1116 b = true; 1117 } else { 1118 dev_err(enic, "Invalid value for %s" 1119 ": expected=0|1 given=%s\n", key, value); 1120 return -EINVAL; 1121 } 1122 if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0) 1123 enic->disable_overlay = b; 1124 if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0) 1125 enic->enable_avx2_rx = b; 1126 return 0; 1127 } 1128 1129 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key, 1130 const char *value, 1131 void *opaque) 1132 { 1133 struct enic *enic; 1134 1135 enic = (struct enic *)opaque; 1136 if (strcmp(value, "trunk") == 0) { 1137 /* Trunk mode: always tag */ 1138 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK; 1139 } else if (strcmp(value, "untag") == 0) { 1140 /* Untag default VLAN mode: untag if VLAN = default VLAN */ 1141 enic->ig_vlan_rewrite_mode = 1142 IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN; 1143 } else if (strcmp(value, "priority") == 0) { 1144 /* 1145 * Priority-tag default VLAN mode: priority tag (VLAN header 1146 * with ID=0) if VLAN = default 1147 */ 1148 enic->ig_vlan_rewrite_mode = 1149 IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN; 1150 } else if (strcmp(value, "pass") == 0) { 1151 /* Pass through mode: do not touch tags */ 1152 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1153 } else { 1154 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE 1155 ": expected=trunk|untag|priority|pass given=%s\n", 1156 value); 1157 return -EINVAL; 1158 } 1159 return 0; 1160 } 1161 1162 static int enic_check_devargs(struct rte_eth_dev *dev) 1163 { 1164 static const char *const valid_keys[] = { 1165 ENIC_DEVARG_DISABLE_OVERLAY, 1166 ENIC_DEVARG_ENABLE_AVX2_RX, 1167 ENIC_DEVARG_IG_VLAN_REWRITE, 1168 NULL}; 1169 struct enic *enic = pmd_priv(dev); 1170 struct rte_kvargs *kvlist; 1171 1172 ENICPMD_FUNC_TRACE(); 1173 1174 enic->disable_overlay = false; 1175 enic->enable_avx2_rx = false; 1176 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1177 if (!dev->device->devargs) 1178 return 0; 1179 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1180 if (!kvlist) 1181 return -EINVAL; 1182 if (rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY, 1183 enic_parse_zero_one, enic) < 0 || 1184 rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX, 1185 enic_parse_zero_one, enic) < 0 || 1186 rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE, 1187 enic_parse_ig_vlan_rewrite, enic) < 0) { 1188 rte_kvargs_free(kvlist); 1189 return -EINVAL; 1190 } 1191 rte_kvargs_free(kvlist); 1192 return 0; 1193 } 1194 1195 /* Initialize the driver 1196 * It returns 0 on success. 1197 */ 1198 static int eth_enicpmd_dev_init(struct rte_eth_dev *eth_dev) 1199 { 1200 struct rte_pci_device *pdev; 1201 struct rte_pci_addr *addr; 1202 struct enic *enic = pmd_priv(eth_dev); 1203 int err; 1204 1205 ENICPMD_FUNC_TRACE(); 1206 1207 enic->port_id = eth_dev->data->port_id; 1208 enic->rte_dev = eth_dev; 1209 eth_dev->dev_ops = &enicpmd_eth_dev_ops; 1210 eth_dev->rx_pkt_burst = &enic_recv_pkts; 1211 eth_dev->tx_pkt_burst = &enic_xmit_pkts; 1212 eth_dev->tx_pkt_prepare = &enic_prep_pkts; 1213 /* Let rte_eth_dev_close() release the port resources */ 1214 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1215 1216 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 1217 rte_eth_copy_pci_info(eth_dev, pdev); 1218 enic->pdev = pdev; 1219 addr = &pdev->addr; 1220 1221 snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x", 1222 addr->domain, addr->bus, addr->devid, addr->function); 1223 1224 err = enic_check_devargs(eth_dev); 1225 if (err) 1226 return err; 1227 return enic_probe(enic); 1228 } 1229 1230 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1231 struct rte_pci_device *pci_dev) 1232 { 1233 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct enic), 1234 eth_enicpmd_dev_init); 1235 } 1236 1237 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev) 1238 { 1239 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 1240 } 1241 1242 static struct rte_pci_driver rte_enic_pmd = { 1243 .id_table = pci_id_enic_map, 1244 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1245 .probe = eth_enic_pci_probe, 1246 .remove = eth_enic_pci_remove, 1247 }; 1248 1249 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd); 1250 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map); 1251 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci"); 1252 RTE_PMD_REGISTER_PARAM_STRING(net_enic, 1253 ENIC_DEVARG_DISABLE_OVERLAY "=0|1 " 1254 ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 " 1255 ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass"); 1256