1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3 * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4 */ 5 6 #include <stdio.h> 7 #include <stdint.h> 8 9 #include <rte_dev.h> 10 #include <rte_pci.h> 11 #include <rte_bus_pci.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_ethdev_pci.h> 14 #include <rte_kvargs.h> 15 #include <rte_string_fns.h> 16 17 #include "vnic_intr.h" 18 #include "vnic_cq.h" 19 #include "vnic_wq.h" 20 #include "vnic_rq.h" 21 #include "vnic_enet.h" 22 #include "enic.h" 23 24 /* 25 * The set of PCI devices this driver supports 26 */ 27 #define CISCO_PCI_VENDOR_ID 0x1137 28 static const struct rte_pci_id pci_id_enic_map[] = { 29 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET)}, 30 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)}, 31 {RTE_PCI_DEVICE(CISCO_PCI_VENDOR_ID, PCI_DEVICE_ID_CISCO_VIC_ENET_SN)}, 32 {.vendor_id = 0, /* sentinel */}, 33 }; 34 35 /* Supported link speeds of production VIC models */ 36 static const struct vic_speed_capa { 37 uint16_t sub_devid; 38 uint32_t capa; 39 } vic_speed_capa_map[] = { 40 { 0x0043, ETH_LINK_SPEED_10G }, /* VIC */ 41 { 0x0047, ETH_LINK_SPEED_10G }, /* P81E PCIe */ 42 { 0x0048, ETH_LINK_SPEED_10G }, /* M81KR Mezz */ 43 { 0x004f, ETH_LINK_SPEED_10G }, /* 1280 Mezz */ 44 { 0x0084, ETH_LINK_SPEED_10G }, /* 1240 MLOM */ 45 { 0x0085, ETH_LINK_SPEED_10G }, /* 1225 PCIe */ 46 { 0x00cd, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1285 PCIe */ 47 { 0x00ce, ETH_LINK_SPEED_10G }, /* 1225T PCIe */ 48 { 0x012a, ETH_LINK_SPEED_40G }, /* M4308 */ 49 { 0x012c, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1340 MLOM */ 50 { 0x012e, ETH_LINK_SPEED_10G }, /* 1227 PCIe */ 51 { 0x0137, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1380 Mezz */ 52 { 0x014d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1385 PCIe */ 53 { 0x015d, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G }, /* 1387 MLOM */ 54 { 0x0215, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 55 ETH_LINK_SPEED_40G }, /* 1440 Mezz */ 56 { 0x0216, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G | 57 ETH_LINK_SPEED_40G }, /* 1480 MLOM */ 58 { 0x0217, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1455 PCIe */ 59 { 0x0218, ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G }, /* 1457 MLOM */ 60 { 0x0219, ETH_LINK_SPEED_40G }, /* 1485 PCIe */ 61 { 0x021a, ETH_LINK_SPEED_40G }, /* 1487 MLOM */ 62 { 0x024a, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1495 PCIe */ 63 { 0x024b, ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G }, /* 1497 MLOM */ 64 { 0, 0 }, /* End marker */ 65 }; 66 67 #define ENIC_DEVARG_DISABLE_OVERLAY "disable-overlay" 68 #define ENIC_DEVARG_ENABLE_AVX2_RX "enable-avx2-rx" 69 #define ENIC_DEVARG_GENEVE_OPT "geneve-opt" 70 #define ENIC_DEVARG_IG_VLAN_REWRITE "ig-vlan-rewrite" 71 #define ENIC_DEVARG_REPRESENTOR "representor" 72 73 RTE_LOG_REGISTER(enic_pmd_logtype, pmd.net.enic, INFO); 74 75 static int 76 enicpmd_fdir_ctrl_func(struct rte_eth_dev *eth_dev, 77 enum rte_filter_op filter_op, void *arg) 78 { 79 struct enic *enic = pmd_priv(eth_dev); 80 int ret = 0; 81 82 ENICPMD_FUNC_TRACE(); 83 if (filter_op == RTE_ETH_FILTER_NOP) 84 return 0; 85 86 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 87 return -EINVAL; 88 89 switch (filter_op) { 90 case RTE_ETH_FILTER_ADD: 91 case RTE_ETH_FILTER_UPDATE: 92 ret = enic_fdir_add_fltr(enic, 93 (struct rte_eth_fdir_filter *)arg); 94 break; 95 96 case RTE_ETH_FILTER_DELETE: 97 ret = enic_fdir_del_fltr(enic, 98 (struct rte_eth_fdir_filter *)arg); 99 break; 100 101 case RTE_ETH_FILTER_STATS: 102 enic_fdir_stats_get(enic, (struct rte_eth_fdir_stats *)arg); 103 break; 104 105 case RTE_ETH_FILTER_FLUSH: 106 dev_warning(enic, "unsupported operation %u", filter_op); 107 ret = -ENOTSUP; 108 break; 109 case RTE_ETH_FILTER_INFO: 110 enic_fdir_info_get(enic, (struct rte_eth_fdir_info *)arg); 111 break; 112 default: 113 dev_err(enic, "unknown operation %u", filter_op); 114 ret = -EINVAL; 115 break; 116 } 117 return ret; 118 } 119 120 static int 121 enicpmd_dev_filter_ctrl(struct rte_eth_dev *dev, 122 enum rte_filter_type filter_type, 123 enum rte_filter_op filter_op, 124 void *arg) 125 { 126 struct enic *enic = pmd_priv(dev); 127 int ret = 0; 128 129 ENICPMD_FUNC_TRACE(); 130 131 /* 132 * Currently, when Geneve with options offload is enabled, host 133 * cannot insert match-action rules. 134 */ 135 if (enic->geneve_opt_enabled) 136 return -ENOTSUP; 137 switch (filter_type) { 138 case RTE_ETH_FILTER_GENERIC: 139 if (filter_op != RTE_ETH_FILTER_GET) 140 return -EINVAL; 141 if (enic->flow_filter_mode == FILTER_FLOWMAN) 142 *(const void **)arg = &enic_fm_flow_ops; 143 else 144 *(const void **)arg = &enic_flow_ops; 145 break; 146 case RTE_ETH_FILTER_FDIR: 147 ret = enicpmd_fdir_ctrl_func(dev, filter_op, arg); 148 break; 149 default: 150 dev_warning(enic, "Filter type (%d) not supported", 151 filter_type); 152 ret = -EINVAL; 153 break; 154 } 155 156 return ret; 157 } 158 159 static void enicpmd_dev_tx_queue_release(void *txq) 160 { 161 ENICPMD_FUNC_TRACE(); 162 163 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 164 return; 165 166 enic_free_wq(txq); 167 } 168 169 static int enicpmd_dev_setup_intr(struct enic *enic) 170 { 171 int ret; 172 unsigned int index; 173 174 ENICPMD_FUNC_TRACE(); 175 176 /* Are we done with the init of all the queues? */ 177 for (index = 0; index < enic->cq_count; index++) { 178 if (!enic->cq[index].ctrl) 179 break; 180 } 181 if (enic->cq_count != index) 182 return 0; 183 for (index = 0; index < enic->wq_count; index++) { 184 if (!enic->wq[index].ctrl) 185 break; 186 } 187 if (enic->wq_count != index) 188 return 0; 189 /* check start of packet (SOP) RQs only in case scatter is disabled. */ 190 for (index = 0; index < enic->rq_count; index++) { 191 if (!enic->rq[enic_rte_rq_idx_to_sop_idx(index)].ctrl) 192 break; 193 } 194 if (enic->rq_count != index) 195 return 0; 196 197 ret = enic_alloc_intr_resources(enic); 198 if (ret) { 199 dev_err(enic, "alloc intr failed\n"); 200 return ret; 201 } 202 enic_init_vnic_resources(enic); 203 204 ret = enic_setup_finish(enic); 205 if (ret) 206 dev_err(enic, "setup could not be finished\n"); 207 208 return ret; 209 } 210 211 static int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 212 uint16_t queue_idx, 213 uint16_t nb_desc, 214 unsigned int socket_id, 215 const struct rte_eth_txconf *tx_conf) 216 { 217 int ret; 218 struct enic *enic = pmd_priv(eth_dev); 219 struct vnic_wq *wq; 220 221 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 222 return -E_RTE_SECONDARY; 223 224 ENICPMD_FUNC_TRACE(); 225 RTE_ASSERT(queue_idx < enic->conf_wq_count); 226 wq = &enic->wq[queue_idx]; 227 wq->offloads = tx_conf->offloads | 228 eth_dev->data->dev_conf.txmode.offloads; 229 eth_dev->data->tx_queues[queue_idx] = (void *)wq; 230 231 ret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc); 232 if (ret) { 233 dev_err(enic, "error in allocating wq\n"); 234 return ret; 235 } 236 237 return enicpmd_dev_setup_intr(enic); 238 } 239 240 static int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 241 uint16_t queue_idx) 242 { 243 struct enic *enic = pmd_priv(eth_dev); 244 245 ENICPMD_FUNC_TRACE(); 246 247 enic_start_wq(enic, queue_idx); 248 249 return 0; 250 } 251 252 static int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, 253 uint16_t queue_idx) 254 { 255 int ret; 256 struct enic *enic = pmd_priv(eth_dev); 257 258 ENICPMD_FUNC_TRACE(); 259 260 ret = enic_stop_wq(enic, queue_idx); 261 if (ret) 262 dev_err(enic, "error in stopping wq %d\n", queue_idx); 263 264 return ret; 265 } 266 267 static int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 268 uint16_t queue_idx) 269 { 270 struct enic *enic = pmd_priv(eth_dev); 271 272 ENICPMD_FUNC_TRACE(); 273 274 enic_start_rq(enic, queue_idx); 275 276 return 0; 277 } 278 279 static int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, 280 uint16_t queue_idx) 281 { 282 int ret; 283 struct enic *enic = pmd_priv(eth_dev); 284 285 ENICPMD_FUNC_TRACE(); 286 287 ret = enic_stop_rq(enic, queue_idx); 288 if (ret) 289 dev_err(enic, "error in stopping rq %d\n", queue_idx); 290 291 return ret; 292 } 293 294 static void enicpmd_dev_rx_queue_release(void *rxq) 295 { 296 ENICPMD_FUNC_TRACE(); 297 298 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 299 return; 300 301 enic_free_rq(rxq); 302 } 303 304 static uint32_t enicpmd_dev_rx_queue_count(struct rte_eth_dev *dev, 305 uint16_t rx_queue_id) 306 { 307 struct enic *enic = pmd_priv(dev); 308 uint32_t queue_count = 0; 309 struct vnic_cq *cq; 310 uint32_t cq_tail; 311 uint16_t cq_idx; 312 int rq_num; 313 314 rq_num = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 315 cq = &enic->cq[enic_cq_rq(enic, rq_num)]; 316 cq_idx = cq->to_clean; 317 318 cq_tail = ioread32(&cq->ctrl->cq_tail); 319 320 if (cq_tail < cq_idx) 321 cq_tail += cq->ring.desc_count; 322 323 queue_count = cq_tail - cq_idx; 324 325 return queue_count; 326 } 327 328 static int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 329 uint16_t queue_idx, 330 uint16_t nb_desc, 331 unsigned int socket_id, 332 const struct rte_eth_rxconf *rx_conf, 333 struct rte_mempool *mp) 334 { 335 int ret; 336 struct enic *enic = pmd_priv(eth_dev); 337 338 ENICPMD_FUNC_TRACE(); 339 340 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 341 return -E_RTE_SECONDARY; 342 RTE_ASSERT(enic_rte_rq_idx_to_sop_idx(queue_idx) < enic->conf_rq_count); 343 eth_dev->data->rx_queues[queue_idx] = 344 (void *)&enic->rq[enic_rte_rq_idx_to_sop_idx(queue_idx)]; 345 346 ret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc, 347 rx_conf->rx_free_thresh); 348 if (ret) { 349 dev_err(enic, "error in allocating rq\n"); 350 return ret; 351 } 352 353 return enicpmd_dev_setup_intr(enic); 354 } 355 356 static int enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 357 { 358 struct enic *enic = pmd_priv(eth_dev); 359 uint64_t offloads; 360 361 ENICPMD_FUNC_TRACE(); 362 363 offloads = eth_dev->data->dev_conf.rxmode.offloads; 364 if (mask & ETH_VLAN_STRIP_MASK) { 365 if (offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 366 enic->ig_vlan_strip_en = 1; 367 else 368 enic->ig_vlan_strip_en = 0; 369 } 370 371 return enic_set_vlan_strip(enic); 372 } 373 374 static int enicpmd_dev_configure(struct rte_eth_dev *eth_dev) 375 { 376 int ret; 377 int mask; 378 struct enic *enic = pmd_priv(eth_dev); 379 380 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 381 return -E_RTE_SECONDARY; 382 383 ENICPMD_FUNC_TRACE(); 384 ret = enic_set_vnic_res(enic); 385 if (ret) { 386 dev_err(enic, "Set vNIC resource num failed, aborting\n"); 387 return ret; 388 } 389 390 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 391 eth_dev->data->dev_conf.rxmode.offloads |= 392 DEV_RX_OFFLOAD_RSS_HASH; 393 394 enic->mc_count = 0; 395 enic->hw_ip_checksum = !!(eth_dev->data->dev_conf.rxmode.offloads & 396 DEV_RX_OFFLOAD_CHECKSUM); 397 /* All vlan offload masks to apply the current settings */ 398 mask = ETH_VLAN_STRIP_MASK | 399 ETH_VLAN_FILTER_MASK | 400 ETH_VLAN_EXTEND_MASK; 401 ret = enicpmd_vlan_offload_set(eth_dev, mask); 402 if (ret) { 403 dev_err(enic, "Failed to configure VLAN offloads\n"); 404 return ret; 405 } 406 /* 407 * Initialize RSS with the default reta and key. If the user key is 408 * given (rx_adv_conf.rss_conf.rss_key), will use that instead of the 409 * default key. 410 */ 411 return enic_init_rss_nic_cfg(enic); 412 } 413 414 /* Start the device. 415 * It returns 0 on success. 416 */ 417 static int enicpmd_dev_start(struct rte_eth_dev *eth_dev) 418 { 419 struct enic *enic = pmd_priv(eth_dev); 420 421 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 422 return -E_RTE_SECONDARY; 423 424 ENICPMD_FUNC_TRACE(); 425 return enic_enable(enic); 426 } 427 428 /* 429 * Stop device: disable rx and tx functions to allow for reconfiguring. 430 */ 431 static int enicpmd_dev_stop(struct rte_eth_dev *eth_dev) 432 { 433 struct rte_eth_link link; 434 struct enic *enic = pmd_priv(eth_dev); 435 436 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 437 return 0; 438 439 ENICPMD_FUNC_TRACE(); 440 enic_disable(enic); 441 442 memset(&link, 0, sizeof(link)); 443 rte_eth_linkstatus_set(eth_dev, &link); 444 445 return 0; 446 } 447 448 /* 449 * Stop device. 450 */ 451 static int enicpmd_dev_close(struct rte_eth_dev *eth_dev) 452 { 453 struct enic *enic = pmd_priv(eth_dev); 454 455 ENICPMD_FUNC_TRACE(); 456 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 457 return 0; 458 459 enic_remove(enic); 460 461 return 0; 462 } 463 464 static int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev, 465 __rte_unused int wait_to_complete) 466 { 467 ENICPMD_FUNC_TRACE(); 468 return enic_link_update(eth_dev); 469 } 470 471 static int enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev, 472 struct rte_eth_stats *stats) 473 { 474 struct enic *enic = pmd_priv(eth_dev); 475 476 ENICPMD_FUNC_TRACE(); 477 return enic_dev_stats_get(enic, stats); 478 } 479 480 static int enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev) 481 { 482 struct enic *enic = pmd_priv(eth_dev); 483 484 ENICPMD_FUNC_TRACE(); 485 return enic_dev_stats_clear(enic); 486 } 487 488 static uint32_t speed_capa_from_pci_id(struct rte_eth_dev *eth_dev) 489 { 490 const struct vic_speed_capa *m; 491 struct rte_pci_device *pdev; 492 uint16_t id; 493 494 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 495 id = pdev->id.subsystem_device_id; 496 for (m = vic_speed_capa_map; m->sub_devid != 0; m++) { 497 if (m->sub_devid == id) 498 return m->capa; 499 } 500 /* 1300 and later models are at least 40G */ 501 if (id >= 0x0100) 502 return ETH_LINK_SPEED_40G; 503 /* VFs have subsystem id 0, check device id */ 504 if (id == 0) { 505 /* Newer VF implies at least 40G model */ 506 if (pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_SN) 507 return ETH_LINK_SPEED_40G; 508 } 509 return ETH_LINK_SPEED_10G; 510 } 511 512 static int enicpmd_dev_info_get(struct rte_eth_dev *eth_dev, 513 struct rte_eth_dev_info *device_info) 514 { 515 struct enic *enic = pmd_priv(eth_dev); 516 517 ENICPMD_FUNC_TRACE(); 518 /* Scattered Rx uses two receive queues per rx queue exposed to dpdk */ 519 device_info->max_rx_queues = enic->conf_rq_count / 2; 520 device_info->max_tx_queues = enic->conf_wq_count; 521 device_info->min_rx_bufsize = ENIC_MIN_MTU; 522 /* "Max" mtu is not a typo. HW receives packet sizes up to the 523 * max mtu regardless of the current mtu (vNIC's mtu). vNIC mtu is 524 * a hint to the driver to size receive buffers accordingly so that 525 * larger-than-vnic-mtu packets get truncated.. For DPDK, we let 526 * the user decide the buffer size via rxmode.max_rx_pkt_len, basically 527 * ignoring vNIC mtu. 528 */ 529 device_info->max_rx_pktlen = enic_mtu_to_max_rx_pktlen(enic->max_mtu); 530 device_info->max_mac_addrs = ENIC_UNICAST_PERFECT_FILTERS; 531 device_info->min_mtu = ENIC_MIN_MTU; 532 device_info->max_mtu = enic->max_mtu; 533 device_info->rx_offload_capa = enic->rx_offload_capa; 534 device_info->tx_offload_capa = enic->tx_offload_capa; 535 device_info->tx_queue_offload_capa = enic->tx_queue_offload_capa; 536 device_info->default_rxconf = (struct rte_eth_rxconf) { 537 .rx_free_thresh = ENIC_DEFAULT_RX_FREE_THRESH 538 }; 539 device_info->reta_size = enic->reta_size; 540 device_info->hash_key_size = enic->hash_key_size; 541 device_info->flow_type_rss_offloads = enic->flow_type_rss_offloads; 542 device_info->rx_desc_lim = (struct rte_eth_desc_lim) { 543 .nb_max = enic->config.rq_desc_count, 544 .nb_min = ENIC_MIN_RQ_DESCS, 545 .nb_align = ENIC_ALIGN_DESCS, 546 }; 547 device_info->tx_desc_lim = (struct rte_eth_desc_lim) { 548 .nb_max = enic->config.wq_desc_count, 549 .nb_min = ENIC_MIN_WQ_DESCS, 550 .nb_align = ENIC_ALIGN_DESCS, 551 .nb_seg_max = ENIC_TX_XMIT_MAX, 552 .nb_mtu_seg_max = ENIC_NON_TSO_MAX_DESC, 553 }; 554 device_info->default_rxportconf = (struct rte_eth_dev_portconf) { 555 .burst_size = ENIC_DEFAULT_RX_BURST, 556 .ring_size = RTE_MIN(device_info->rx_desc_lim.nb_max, 557 ENIC_DEFAULT_RX_RING_SIZE), 558 .nb_queues = ENIC_DEFAULT_RX_RINGS, 559 }; 560 device_info->default_txportconf = (struct rte_eth_dev_portconf) { 561 .burst_size = ENIC_DEFAULT_TX_BURST, 562 .ring_size = RTE_MIN(device_info->tx_desc_lim.nb_max, 563 ENIC_DEFAULT_TX_RING_SIZE), 564 .nb_queues = ENIC_DEFAULT_TX_RINGS, 565 }; 566 device_info->speed_capa = speed_capa_from_pci_id(eth_dev); 567 568 return 0; 569 } 570 571 static const uint32_t *enicpmd_dev_supported_ptypes_get(struct rte_eth_dev *dev) 572 { 573 static const uint32_t ptypes[] = { 574 RTE_PTYPE_L2_ETHER, 575 RTE_PTYPE_L2_ETHER_VLAN, 576 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 577 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 578 RTE_PTYPE_L4_TCP, 579 RTE_PTYPE_L4_UDP, 580 RTE_PTYPE_L4_FRAG, 581 RTE_PTYPE_L4_NONFRAG, 582 RTE_PTYPE_UNKNOWN 583 }; 584 static const uint32_t ptypes_overlay[] = { 585 RTE_PTYPE_L2_ETHER, 586 RTE_PTYPE_L2_ETHER_VLAN, 587 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 588 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 589 RTE_PTYPE_L4_TCP, 590 RTE_PTYPE_L4_UDP, 591 RTE_PTYPE_L4_FRAG, 592 RTE_PTYPE_L4_NONFRAG, 593 RTE_PTYPE_TUNNEL_GRENAT, 594 RTE_PTYPE_INNER_L2_ETHER, 595 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 596 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 597 RTE_PTYPE_INNER_L4_TCP, 598 RTE_PTYPE_INNER_L4_UDP, 599 RTE_PTYPE_INNER_L4_FRAG, 600 RTE_PTYPE_INNER_L4_NONFRAG, 601 RTE_PTYPE_UNKNOWN 602 }; 603 604 if (dev->rx_pkt_burst != enic_dummy_recv_pkts && 605 dev->rx_pkt_burst != NULL) { 606 struct enic *enic = pmd_priv(dev); 607 if (enic->overlay_offload) 608 return ptypes_overlay; 609 else 610 return ptypes; 611 } 612 return NULL; 613 } 614 615 static int enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 616 { 617 struct enic *enic = pmd_priv(eth_dev); 618 int ret; 619 620 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 621 return -E_RTE_SECONDARY; 622 623 ENICPMD_FUNC_TRACE(); 624 625 enic->promisc = 1; 626 ret = enic_add_packet_filter(enic); 627 if (ret != 0) 628 enic->promisc = 0; 629 630 return ret; 631 } 632 633 static int enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 634 { 635 struct enic *enic = pmd_priv(eth_dev); 636 int ret; 637 638 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 639 return -E_RTE_SECONDARY; 640 641 ENICPMD_FUNC_TRACE(); 642 enic->promisc = 0; 643 ret = enic_add_packet_filter(enic); 644 if (ret != 0) 645 enic->promisc = 1; 646 647 return ret; 648 } 649 650 static int enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 651 { 652 struct enic *enic = pmd_priv(eth_dev); 653 int ret; 654 655 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 656 return -E_RTE_SECONDARY; 657 658 ENICPMD_FUNC_TRACE(); 659 enic->allmulti = 1; 660 ret = enic_add_packet_filter(enic); 661 if (ret != 0) 662 enic->allmulti = 0; 663 664 return ret; 665 } 666 667 static int enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 668 { 669 struct enic *enic = pmd_priv(eth_dev); 670 int ret; 671 672 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 673 return -E_RTE_SECONDARY; 674 675 ENICPMD_FUNC_TRACE(); 676 enic->allmulti = 0; 677 ret = enic_add_packet_filter(enic); 678 if (ret != 0) 679 enic->allmulti = 1; 680 681 return ret; 682 } 683 684 static int enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev, 685 struct rte_ether_addr *mac_addr, 686 __rte_unused uint32_t index, __rte_unused uint32_t pool) 687 { 688 struct enic *enic = pmd_priv(eth_dev); 689 690 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 691 return -E_RTE_SECONDARY; 692 693 ENICPMD_FUNC_TRACE(); 694 return enic_set_mac_address(enic, mac_addr->addr_bytes); 695 } 696 697 static void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, uint32_t index) 698 { 699 struct enic *enic = pmd_priv(eth_dev); 700 701 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 702 return; 703 704 ENICPMD_FUNC_TRACE(); 705 if (enic_del_mac_address(enic, index)) 706 dev_err(enic, "del mac addr failed\n"); 707 } 708 709 static int enicpmd_set_mac_addr(struct rte_eth_dev *eth_dev, 710 struct rte_ether_addr *addr) 711 { 712 struct enic *enic = pmd_priv(eth_dev); 713 int ret; 714 715 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 716 return -E_RTE_SECONDARY; 717 718 ENICPMD_FUNC_TRACE(); 719 ret = enic_del_mac_address(enic, 0); 720 if (ret) 721 return ret; 722 return enic_set_mac_address(enic, addr->addr_bytes); 723 } 724 725 static void debug_log_add_del_addr(struct rte_ether_addr *addr, bool add) 726 { 727 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 728 729 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr); 730 ENICPMD_LOG(DEBUG, " %s address %s\n", 731 add ? "add" : "remove", mac_str); 732 } 733 734 static int enicpmd_set_mc_addr_list(struct rte_eth_dev *eth_dev, 735 struct rte_ether_addr *mc_addr_set, 736 uint32_t nb_mc_addr) 737 { 738 struct enic *enic = pmd_priv(eth_dev); 739 char mac_str[RTE_ETHER_ADDR_FMT_SIZE]; 740 struct rte_ether_addr *addr; 741 uint32_t i, j; 742 int ret; 743 744 ENICPMD_FUNC_TRACE(); 745 746 /* Validate the given addresses first */ 747 for (i = 0; i < nb_mc_addr && mc_addr_set != NULL; i++) { 748 addr = &mc_addr_set[i]; 749 if (!rte_is_multicast_ether_addr(addr) || 750 rte_is_broadcast_ether_addr(addr)) { 751 rte_ether_format_addr(mac_str, 752 RTE_ETHER_ADDR_FMT_SIZE, addr); 753 ENICPMD_LOG(ERR, " invalid multicast address %s\n", 754 mac_str); 755 return -EINVAL; 756 } 757 } 758 759 /* Flush all if requested */ 760 if (nb_mc_addr == 0 || mc_addr_set == NULL) { 761 ENICPMD_LOG(DEBUG, " flush multicast addresses\n"); 762 for (i = 0; i < enic->mc_count; i++) { 763 addr = &enic->mc_addrs[i]; 764 debug_log_add_del_addr(addr, false); 765 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 766 if (ret) 767 return ret; 768 } 769 enic->mc_count = 0; 770 return 0; 771 } 772 773 if (nb_mc_addr > ENIC_MULTICAST_PERFECT_FILTERS) { 774 ENICPMD_LOG(ERR, " too many multicast addresses: max=%d\n", 775 ENIC_MULTICAST_PERFECT_FILTERS); 776 return -ENOSPC; 777 } 778 /* 779 * devcmd is slow, so apply the difference instead of flushing and 780 * adding everything. 781 * 1. Delete addresses on the NIC but not on the host 782 */ 783 for (i = 0; i < enic->mc_count; i++) { 784 addr = &enic->mc_addrs[i]; 785 for (j = 0; j < nb_mc_addr; j++) { 786 if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) 787 break; 788 } 789 if (j < nb_mc_addr) 790 continue; 791 debug_log_add_del_addr(addr, false); 792 ret = vnic_dev_del_addr(enic->vdev, addr->addr_bytes); 793 if (ret) 794 return ret; 795 } 796 /* 2. Add addresses on the host but not on the NIC */ 797 for (i = 0; i < nb_mc_addr; i++) { 798 addr = &mc_addr_set[i]; 799 for (j = 0; j < enic->mc_count; j++) { 800 if (rte_is_same_ether_addr(addr, &enic->mc_addrs[j])) 801 break; 802 } 803 if (j < enic->mc_count) 804 continue; 805 debug_log_add_del_addr(addr, true); 806 ret = vnic_dev_add_addr(enic->vdev, addr->addr_bytes); 807 if (ret) 808 return ret; 809 } 810 /* Keep a copy so we can flush/apply later on.. */ 811 memcpy(enic->mc_addrs, mc_addr_set, 812 nb_mc_addr * sizeof(struct rte_ether_addr)); 813 enic->mc_count = nb_mc_addr; 814 return 0; 815 } 816 817 static int enicpmd_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 818 { 819 struct enic *enic = pmd_priv(eth_dev); 820 821 ENICPMD_FUNC_TRACE(); 822 return enic_set_mtu(enic, mtu); 823 } 824 825 static int enicpmd_dev_rss_reta_query(struct rte_eth_dev *dev, 826 struct rte_eth_rss_reta_entry64 827 *reta_conf, 828 uint16_t reta_size) 829 { 830 struct enic *enic = pmd_priv(dev); 831 uint16_t i, idx, shift; 832 833 ENICPMD_FUNC_TRACE(); 834 if (reta_size != ENIC_RSS_RETA_SIZE) { 835 dev_err(enic, "reta_query: wrong reta_size. given=%u expected=%u\n", 836 reta_size, ENIC_RSS_RETA_SIZE); 837 return -EINVAL; 838 } 839 840 for (i = 0; i < reta_size; i++) { 841 idx = i / RTE_RETA_GROUP_SIZE; 842 shift = i % RTE_RETA_GROUP_SIZE; 843 if (reta_conf[idx].mask & (1ULL << shift)) 844 reta_conf[idx].reta[shift] = enic_sop_rq_idx_to_rte_idx( 845 enic->rss_cpu.cpu[i / 4].b[i % 4]); 846 } 847 848 return 0; 849 } 850 851 static int enicpmd_dev_rss_reta_update(struct rte_eth_dev *dev, 852 struct rte_eth_rss_reta_entry64 853 *reta_conf, 854 uint16_t reta_size) 855 { 856 struct enic *enic = pmd_priv(dev); 857 union vnic_rss_cpu rss_cpu; 858 uint16_t i, idx, shift; 859 860 ENICPMD_FUNC_TRACE(); 861 if (reta_size != ENIC_RSS_RETA_SIZE) { 862 dev_err(enic, "reta_update: wrong reta_size. given=%u" 863 " expected=%u\n", 864 reta_size, ENIC_RSS_RETA_SIZE); 865 return -EINVAL; 866 } 867 /* 868 * Start with the current reta and modify it per reta_conf, as we 869 * need to push the entire reta even if we only modify one entry. 870 */ 871 rss_cpu = enic->rss_cpu; 872 for (i = 0; i < reta_size; i++) { 873 idx = i / RTE_RETA_GROUP_SIZE; 874 shift = i % RTE_RETA_GROUP_SIZE; 875 if (reta_conf[idx].mask & (1ULL << shift)) 876 rss_cpu.cpu[i / 4].b[i % 4] = 877 enic_rte_rq_idx_to_sop_idx( 878 reta_conf[idx].reta[shift]); 879 } 880 return enic_set_rss_reta(enic, &rss_cpu); 881 } 882 883 static int enicpmd_dev_rss_hash_update(struct rte_eth_dev *dev, 884 struct rte_eth_rss_conf *rss_conf) 885 { 886 struct enic *enic = pmd_priv(dev); 887 888 ENICPMD_FUNC_TRACE(); 889 return enic_set_rss_conf(enic, rss_conf); 890 } 891 892 static int enicpmd_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 893 struct rte_eth_rss_conf *rss_conf) 894 { 895 struct enic *enic = pmd_priv(dev); 896 897 ENICPMD_FUNC_TRACE(); 898 if (rss_conf == NULL) 899 return -EINVAL; 900 if (rss_conf->rss_key != NULL && 901 rss_conf->rss_key_len < ENIC_RSS_HASH_KEY_SIZE) { 902 dev_err(enic, "rss_hash_conf_get: wrong rss_key_len. given=%u" 903 " expected=%u+\n", 904 rss_conf->rss_key_len, ENIC_RSS_HASH_KEY_SIZE); 905 return -EINVAL; 906 } 907 rss_conf->rss_hf = enic->rss_hf; 908 if (rss_conf->rss_key != NULL) { 909 int i; 910 for (i = 0; i < ENIC_RSS_HASH_KEY_SIZE; i++) { 911 rss_conf->rss_key[i] = 912 enic->rss_key.key[i / 10].b[i % 10]; 913 } 914 rss_conf->rss_key_len = ENIC_RSS_HASH_KEY_SIZE; 915 } 916 return 0; 917 } 918 919 static void enicpmd_dev_rxq_info_get(struct rte_eth_dev *dev, 920 uint16_t rx_queue_id, 921 struct rte_eth_rxq_info *qinfo) 922 { 923 struct enic *enic = pmd_priv(dev); 924 struct vnic_rq *rq_sop; 925 struct vnic_rq *rq_data; 926 struct rte_eth_rxconf *conf; 927 uint16_t sop_queue_idx; 928 uint16_t data_queue_idx; 929 930 ENICPMD_FUNC_TRACE(); 931 sop_queue_idx = enic_rte_rq_idx_to_sop_idx(rx_queue_id); 932 data_queue_idx = enic_rte_rq_idx_to_data_idx(rx_queue_id, enic); 933 rq_sop = &enic->rq[sop_queue_idx]; 934 rq_data = &enic->rq[data_queue_idx]; /* valid if data_queue_enable */ 935 qinfo->mp = rq_sop->mp; 936 qinfo->scattered_rx = rq_sop->data_queue_enable; 937 qinfo->nb_desc = rq_sop->ring.desc_count; 938 if (qinfo->scattered_rx) 939 qinfo->nb_desc += rq_data->ring.desc_count; 940 conf = &qinfo->conf; 941 memset(conf, 0, sizeof(*conf)); 942 conf->rx_free_thresh = rq_sop->rx_free_thresh; 943 conf->rx_drop_en = 1; 944 /* 945 * Except VLAN stripping (port setting), all the checksum offloads 946 * are always enabled. 947 */ 948 conf->offloads = enic->rx_offload_capa; 949 if (!enic->ig_vlan_strip_en) 950 conf->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 951 /* rx_thresh and other fields are not applicable for enic */ 952 } 953 954 static void enicpmd_dev_txq_info_get(struct rte_eth_dev *dev, 955 uint16_t tx_queue_id, 956 struct rte_eth_txq_info *qinfo) 957 { 958 struct enic *enic = pmd_priv(dev); 959 struct vnic_wq *wq = &enic->wq[tx_queue_id]; 960 961 ENICPMD_FUNC_TRACE(); 962 qinfo->nb_desc = wq->ring.desc_count; 963 memset(&qinfo->conf, 0, sizeof(qinfo->conf)); 964 qinfo->conf.offloads = wq->offloads; 965 /* tx_thresh, and all the other fields are not applicable for enic */ 966 } 967 968 static int enicpmd_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 969 __rte_unused uint16_t queue_id, 970 struct rte_eth_burst_mode *mode) 971 { 972 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 973 struct enic *enic = pmd_priv(dev); 974 const char *info_str = NULL; 975 int ret = -EINVAL; 976 977 ENICPMD_FUNC_TRACE(); 978 if (enic->use_noscatter_vec_rx_handler) 979 info_str = "Vector AVX2 No Scatter"; 980 else if (pkt_burst == enic_noscatter_recv_pkts) 981 info_str = "Scalar No Scatter"; 982 else if (pkt_burst == enic_recv_pkts) 983 info_str = "Scalar"; 984 if (info_str) { 985 strlcpy(mode->info, info_str, sizeof(mode->info)); 986 ret = 0; 987 } 988 return ret; 989 } 990 991 static int enicpmd_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 992 __rte_unused uint16_t queue_id, 993 struct rte_eth_burst_mode *mode) 994 { 995 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 996 const char *info_str = NULL; 997 int ret = -EINVAL; 998 999 ENICPMD_FUNC_TRACE(); 1000 if (pkt_burst == enic_simple_xmit_pkts) 1001 info_str = "Scalar Simplified"; 1002 else if (pkt_burst == enic_xmit_pkts) 1003 info_str = "Scalar"; 1004 if (info_str) { 1005 strlcpy(mode->info, info_str, sizeof(mode->info)); 1006 ret = 0; 1007 } 1008 return ret; 1009 } 1010 1011 static int enicpmd_dev_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 1012 uint16_t rx_queue_id) 1013 { 1014 struct enic *enic = pmd_priv(eth_dev); 1015 1016 ENICPMD_FUNC_TRACE(); 1017 vnic_intr_unmask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 1018 return 0; 1019 } 1020 1021 static int enicpmd_dev_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 1022 uint16_t rx_queue_id) 1023 { 1024 struct enic *enic = pmd_priv(eth_dev); 1025 1026 ENICPMD_FUNC_TRACE(); 1027 vnic_intr_mask(&enic->intr[rx_queue_id + ENICPMD_RXQ_INTR_OFFSET]); 1028 return 0; 1029 } 1030 1031 static int udp_tunnel_common_check(struct enic *enic, 1032 struct rte_eth_udp_tunnel *tnl) 1033 { 1034 if (tnl->prot_type != RTE_TUNNEL_TYPE_VXLAN) 1035 return -ENOTSUP; 1036 if (!enic->overlay_offload) { 1037 ENICPMD_LOG(DEBUG, " vxlan (overlay offload) is not " 1038 "supported\n"); 1039 return -ENOTSUP; 1040 } 1041 return 0; 1042 } 1043 1044 static int update_vxlan_port(struct enic *enic, uint16_t port) 1045 { 1046 if (vnic_dev_overlay_offload_cfg(enic->vdev, 1047 OVERLAY_CFG_VXLAN_PORT_UPDATE, 1048 port)) { 1049 ENICPMD_LOG(DEBUG, " failed to update vxlan port\n"); 1050 return -EINVAL; 1051 } 1052 ENICPMD_LOG(DEBUG, " updated vxlan port to %u\n", port); 1053 enic->vxlan_port = port; 1054 return 0; 1055 } 1056 1057 static int enicpmd_dev_udp_tunnel_port_add(struct rte_eth_dev *eth_dev, 1058 struct rte_eth_udp_tunnel *tnl) 1059 { 1060 struct enic *enic = pmd_priv(eth_dev); 1061 int ret; 1062 1063 ENICPMD_FUNC_TRACE(); 1064 ret = udp_tunnel_common_check(enic, tnl); 1065 if (ret) 1066 return ret; 1067 /* 1068 * The NIC has 1 configurable VXLAN port number. "Adding" a new port 1069 * number replaces it. 1070 */ 1071 if (tnl->udp_port == enic->vxlan_port || tnl->udp_port == 0) { 1072 ENICPMD_LOG(DEBUG, " %u is already configured or invalid\n", 1073 tnl->udp_port); 1074 return -EINVAL; 1075 } 1076 return update_vxlan_port(enic, tnl->udp_port); 1077 } 1078 1079 static int enicpmd_dev_udp_tunnel_port_del(struct rte_eth_dev *eth_dev, 1080 struct rte_eth_udp_tunnel *tnl) 1081 { 1082 struct enic *enic = pmd_priv(eth_dev); 1083 int ret; 1084 1085 ENICPMD_FUNC_TRACE(); 1086 ret = udp_tunnel_common_check(enic, tnl); 1087 if (ret) 1088 return ret; 1089 /* 1090 * Clear the previously set port number and restore the 1091 * hardware default port number. Some drivers disable VXLAN 1092 * offloads when there are no configured port numbers. But 1093 * enic does not do that as VXLAN is part of overlay offload, 1094 * which is tied to inner RSS and TSO. 1095 */ 1096 if (tnl->udp_port != enic->vxlan_port) { 1097 ENICPMD_LOG(DEBUG, " %u is not a configured vxlan port\n", 1098 tnl->udp_port); 1099 return -EINVAL; 1100 } 1101 return update_vxlan_port(enic, RTE_VXLAN_DEFAULT_PORT); 1102 } 1103 1104 static int enicpmd_dev_fw_version_get(struct rte_eth_dev *eth_dev, 1105 char *fw_version, size_t fw_size) 1106 { 1107 struct vnic_devcmd_fw_info *info; 1108 struct enic *enic; 1109 int ret; 1110 1111 ENICPMD_FUNC_TRACE(); 1112 if (fw_version == NULL || fw_size <= 0) 1113 return -EINVAL; 1114 enic = pmd_priv(eth_dev); 1115 ret = vnic_dev_fw_info(enic->vdev, &info); 1116 if (ret) 1117 return ret; 1118 snprintf(fw_version, fw_size, "%s %s", 1119 info->fw_version, info->fw_build); 1120 fw_version[fw_size - 1] = '\0'; 1121 return 0; 1122 } 1123 1124 static const struct eth_dev_ops enicpmd_eth_dev_ops = { 1125 .dev_configure = enicpmd_dev_configure, 1126 .dev_start = enicpmd_dev_start, 1127 .dev_stop = enicpmd_dev_stop, 1128 .dev_set_link_up = NULL, 1129 .dev_set_link_down = NULL, 1130 .dev_close = enicpmd_dev_close, 1131 .promiscuous_enable = enicpmd_dev_promiscuous_enable, 1132 .promiscuous_disable = enicpmd_dev_promiscuous_disable, 1133 .allmulticast_enable = enicpmd_dev_allmulticast_enable, 1134 .allmulticast_disable = enicpmd_dev_allmulticast_disable, 1135 .link_update = enicpmd_dev_link_update, 1136 .stats_get = enicpmd_dev_stats_get, 1137 .stats_reset = enicpmd_dev_stats_reset, 1138 .queue_stats_mapping_set = NULL, 1139 .dev_infos_get = enicpmd_dev_info_get, 1140 .dev_supported_ptypes_get = enicpmd_dev_supported_ptypes_get, 1141 .mtu_set = enicpmd_mtu_set, 1142 .vlan_filter_set = NULL, 1143 .vlan_tpid_set = NULL, 1144 .vlan_offload_set = enicpmd_vlan_offload_set, 1145 .vlan_strip_queue_set = NULL, 1146 .rx_queue_start = enicpmd_dev_rx_queue_start, 1147 .rx_queue_stop = enicpmd_dev_rx_queue_stop, 1148 .tx_queue_start = enicpmd_dev_tx_queue_start, 1149 .tx_queue_stop = enicpmd_dev_tx_queue_stop, 1150 .rx_queue_setup = enicpmd_dev_rx_queue_setup, 1151 .rx_queue_release = enicpmd_dev_rx_queue_release, 1152 .tx_queue_setup = enicpmd_dev_tx_queue_setup, 1153 .tx_queue_release = enicpmd_dev_tx_queue_release, 1154 .rx_queue_intr_enable = enicpmd_dev_rx_queue_intr_enable, 1155 .rx_queue_intr_disable = enicpmd_dev_rx_queue_intr_disable, 1156 .rxq_info_get = enicpmd_dev_rxq_info_get, 1157 .txq_info_get = enicpmd_dev_txq_info_get, 1158 .rx_burst_mode_get = enicpmd_dev_rx_burst_mode_get, 1159 .tx_burst_mode_get = enicpmd_dev_tx_burst_mode_get, 1160 .dev_led_on = NULL, 1161 .dev_led_off = NULL, 1162 .flow_ctrl_get = NULL, 1163 .flow_ctrl_set = NULL, 1164 .priority_flow_ctrl_set = NULL, 1165 .mac_addr_add = enicpmd_add_mac_addr, 1166 .mac_addr_remove = enicpmd_remove_mac_addr, 1167 .mac_addr_set = enicpmd_set_mac_addr, 1168 .set_mc_addr_list = enicpmd_set_mc_addr_list, 1169 .filter_ctrl = enicpmd_dev_filter_ctrl, 1170 .reta_query = enicpmd_dev_rss_reta_query, 1171 .reta_update = enicpmd_dev_rss_reta_update, 1172 .rss_hash_conf_get = enicpmd_dev_rss_hash_conf_get, 1173 .rss_hash_update = enicpmd_dev_rss_hash_update, 1174 .udp_tunnel_port_add = enicpmd_dev_udp_tunnel_port_add, 1175 .udp_tunnel_port_del = enicpmd_dev_udp_tunnel_port_del, 1176 .fw_version_get = enicpmd_dev_fw_version_get, 1177 }; 1178 1179 static int enic_parse_zero_one(const char *key, 1180 const char *value, 1181 void *opaque) 1182 { 1183 struct enic *enic; 1184 bool b; 1185 1186 enic = (struct enic *)opaque; 1187 if (strcmp(value, "0") == 0) { 1188 b = false; 1189 } else if (strcmp(value, "1") == 0) { 1190 b = true; 1191 } else { 1192 dev_err(enic, "Invalid value for %s" 1193 ": expected=0|1 given=%s\n", key, value); 1194 return -EINVAL; 1195 } 1196 if (strcmp(key, ENIC_DEVARG_DISABLE_OVERLAY) == 0) 1197 enic->disable_overlay = b; 1198 if (strcmp(key, ENIC_DEVARG_ENABLE_AVX2_RX) == 0) 1199 enic->enable_avx2_rx = b; 1200 if (strcmp(key, ENIC_DEVARG_GENEVE_OPT) == 0) 1201 enic->geneve_opt_request = b; 1202 return 0; 1203 } 1204 1205 static int enic_parse_ig_vlan_rewrite(__rte_unused const char *key, 1206 const char *value, 1207 void *opaque) 1208 { 1209 struct enic *enic; 1210 1211 enic = (struct enic *)opaque; 1212 if (strcmp(value, "trunk") == 0) { 1213 /* Trunk mode: always tag */ 1214 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK; 1215 } else if (strcmp(value, "untag") == 0) { 1216 /* Untag default VLAN mode: untag if VLAN = default VLAN */ 1217 enic->ig_vlan_rewrite_mode = 1218 IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN; 1219 } else if (strcmp(value, "priority") == 0) { 1220 /* 1221 * Priority-tag default VLAN mode: priority tag (VLAN header 1222 * with ID=0) if VLAN = default 1223 */ 1224 enic->ig_vlan_rewrite_mode = 1225 IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN; 1226 } else if (strcmp(value, "pass") == 0) { 1227 /* Pass through mode: do not touch tags */ 1228 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1229 } else { 1230 dev_err(enic, "Invalid value for " ENIC_DEVARG_IG_VLAN_REWRITE 1231 ": expected=trunk|untag|priority|pass given=%s\n", 1232 value); 1233 return -EINVAL; 1234 } 1235 return 0; 1236 } 1237 1238 static int enic_check_devargs(struct rte_eth_dev *dev) 1239 { 1240 static const char *const valid_keys[] = { 1241 ENIC_DEVARG_DISABLE_OVERLAY, 1242 ENIC_DEVARG_ENABLE_AVX2_RX, 1243 ENIC_DEVARG_GENEVE_OPT, 1244 ENIC_DEVARG_IG_VLAN_REWRITE, 1245 ENIC_DEVARG_REPRESENTOR, 1246 NULL}; 1247 struct enic *enic = pmd_priv(dev); 1248 struct rte_kvargs *kvlist; 1249 1250 ENICPMD_FUNC_TRACE(); 1251 1252 enic->disable_overlay = false; 1253 enic->enable_avx2_rx = false; 1254 enic->geneve_opt_request = false; 1255 enic->ig_vlan_rewrite_mode = IG_VLAN_REWRITE_MODE_PASS_THRU; 1256 if (!dev->device->devargs) 1257 return 0; 1258 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys); 1259 if (!kvlist) 1260 return -EINVAL; 1261 if (rte_kvargs_process(kvlist, ENIC_DEVARG_DISABLE_OVERLAY, 1262 enic_parse_zero_one, enic) < 0 || 1263 rte_kvargs_process(kvlist, ENIC_DEVARG_ENABLE_AVX2_RX, 1264 enic_parse_zero_one, enic) < 0 || 1265 rte_kvargs_process(kvlist, ENIC_DEVARG_GENEVE_OPT, 1266 enic_parse_zero_one, enic) < 0 || 1267 rte_kvargs_process(kvlist, ENIC_DEVARG_IG_VLAN_REWRITE, 1268 enic_parse_ig_vlan_rewrite, enic) < 0) { 1269 rte_kvargs_free(kvlist); 1270 return -EINVAL; 1271 } 1272 rte_kvargs_free(kvlist); 1273 return 0; 1274 } 1275 1276 /* Initialize the driver for PF */ 1277 static int eth_enic_dev_init(struct rte_eth_dev *eth_dev, 1278 void *init_params __rte_unused) 1279 { 1280 struct rte_pci_device *pdev; 1281 struct rte_pci_addr *addr; 1282 struct enic *enic = pmd_priv(eth_dev); 1283 int err; 1284 1285 ENICPMD_FUNC_TRACE(); 1286 eth_dev->dev_ops = &enicpmd_eth_dev_ops; 1287 eth_dev->rx_queue_count = enicpmd_dev_rx_queue_count; 1288 eth_dev->rx_pkt_burst = &enic_recv_pkts; 1289 eth_dev->tx_pkt_burst = &enic_xmit_pkts; 1290 eth_dev->tx_pkt_prepare = &enic_prep_pkts; 1291 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1292 enic_pick_tx_handler(eth_dev); 1293 enic_pick_rx_handler(eth_dev); 1294 return 0; 1295 } 1296 /* Only the primary sets up adapter and other data in shared memory */ 1297 enic->port_id = eth_dev->data->port_id; 1298 enic->rte_dev = eth_dev; 1299 enic->dev_data = eth_dev->data; 1300 1301 pdev = RTE_ETH_DEV_TO_PCI(eth_dev); 1302 rte_eth_copy_pci_info(eth_dev, pdev); 1303 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1304 enic->pdev = pdev; 1305 addr = &pdev->addr; 1306 1307 snprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, "%04x:%02x:%02x.%x", 1308 addr->domain, addr->bus, addr->devid, addr->function); 1309 1310 err = enic_check_devargs(eth_dev); 1311 if (err) 1312 return err; 1313 err = enic_probe(enic); 1314 if (!err && enic->fm) { 1315 err = enic_fm_allocate_switch_domain(enic); 1316 if (err) 1317 ENICPMD_LOG(ERR, "failed to allocate switch domain id"); 1318 } 1319 return err; 1320 } 1321 1322 static int eth_enic_dev_uninit(struct rte_eth_dev *eth_dev) 1323 { 1324 struct enic *enic = pmd_priv(eth_dev); 1325 int err; 1326 1327 ENICPMD_FUNC_TRACE(); 1328 eth_dev->device = NULL; 1329 eth_dev->intr_handle = NULL; 1330 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1331 return 0; 1332 err = rte_eth_switch_domain_free(enic->switch_domain_id); 1333 if (err) 1334 ENICPMD_LOG(WARNING, "failed to free switch domain: %d", err); 1335 return 0; 1336 } 1337 1338 static int eth_enic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1339 struct rte_pci_device *pci_dev) 1340 { 1341 char name[RTE_ETH_NAME_MAX_LEN]; 1342 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 1343 struct rte_eth_dev *pf_ethdev; 1344 struct enic *pf_enic; 1345 int i, retval; 1346 1347 ENICPMD_FUNC_TRACE(); 1348 if (pci_dev->device.devargs) { 1349 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1350 ð_da); 1351 if (retval) 1352 return retval; 1353 } 1354 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1355 sizeof(struct enic), 1356 eth_dev_pci_specific_init, pci_dev, 1357 eth_enic_dev_init, NULL); 1358 if (retval || eth_da.nb_representor_ports < 1) 1359 return retval; 1360 1361 /* Probe VF representor */ 1362 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1363 if (pf_ethdev == NULL) 1364 return -ENODEV; 1365 /* Representors require flowman */ 1366 pf_enic = pmd_priv(pf_ethdev); 1367 if (pf_enic->fm == NULL) { 1368 ENICPMD_LOG(ERR, "VF representors require flowman"); 1369 return -ENOTSUP; 1370 } 1371 /* 1372 * For now representors imply switchdev, as firmware does not support 1373 * legacy mode SR-IOV 1374 */ 1375 pf_enic->switchdev_mode = 1; 1376 /* Calculate max VF ID before initializing representor*/ 1377 pf_enic->max_vf_id = 0; 1378 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1379 pf_enic->max_vf_id = RTE_MAX(pf_enic->max_vf_id, 1380 eth_da.representor_ports[i]); 1381 } 1382 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1383 struct enic_vf_representor representor; 1384 1385 representor.vf_id = eth_da.representor_ports[i]; 1386 representor.switch_domain_id = 1387 pmd_priv(pf_ethdev)->switch_domain_id; 1388 representor.pf = pmd_priv(pf_ethdev); 1389 snprintf(name, sizeof(name), "net_%s_representor_%d", 1390 pci_dev->device.name, eth_da.representor_ports[i]); 1391 retval = rte_eth_dev_create(&pci_dev->device, name, 1392 sizeof(struct enic_vf_representor), NULL, NULL, 1393 enic_vf_representor_init, &representor); 1394 if (retval) { 1395 ENICPMD_LOG(ERR, "failed to create enic vf representor %s", 1396 name); 1397 return retval; 1398 } 1399 } 1400 return 0; 1401 } 1402 1403 static int eth_enic_pci_remove(struct rte_pci_device *pci_dev) 1404 { 1405 struct rte_eth_dev *ethdev; 1406 1407 ENICPMD_FUNC_TRACE(); 1408 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1409 if (!ethdev) 1410 return -ENODEV; 1411 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1412 return rte_eth_dev_destroy(ethdev, enic_vf_representor_uninit); 1413 else 1414 return rte_eth_dev_destroy(ethdev, eth_enic_dev_uninit); 1415 } 1416 1417 static struct rte_pci_driver rte_enic_pmd = { 1418 .id_table = pci_id_enic_map, 1419 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1420 .probe = eth_enic_pci_probe, 1421 .remove = eth_enic_pci_remove, 1422 }; 1423 1424 int dev_is_enic(struct rte_eth_dev *dev) 1425 { 1426 return dev->device->driver == &rte_enic_pmd.driver; 1427 } 1428 1429 RTE_PMD_REGISTER_PCI(net_enic, rte_enic_pmd); 1430 RTE_PMD_REGISTER_PCI_TABLE(net_enic, pci_id_enic_map); 1431 RTE_PMD_REGISTER_KMOD_DEP(net_enic, "* igb_uio | uio_pci_generic | vfio-pci"); 1432 RTE_PMD_REGISTER_PARAM_STRING(net_enic, 1433 ENIC_DEVARG_DISABLE_OVERLAY "=0|1 " 1434 ENIC_DEVARG_ENABLE_AVX2_RX "=0|1 " 1435 ENIC_DEVARG_GENEVE_OPT "=0|1 " 1436 ENIC_DEVARG_IG_VLAN_REWRITE "=trunk|untag|priority|pass"); 1437