1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020-2021 NXP 3 */ 4 5 #ifndef __ENETFEC_ETHDEV_H__ 6 #define __ENETFEC_ETHDEV_H__ 7 8 #include <rte_ethdev.h> 9 10 #define BD_LEN 49152 11 #define ENETFEC_TX_FR_SIZE 2048 12 #define ETH_HLEN RTE_ETHER_HDR_LEN 13 #define VLAN_HLEN 4 14 15 /* full duplex */ 16 #define FULL_DUPLEX 0x00 17 18 #define MAX_TX_BD_RING_SIZE 512 /* It should be power of 2 */ 19 #define MAX_RX_BD_RING_SIZE 512 20 #define PKT_MAX_BUF_SIZE 1984 21 #define OPT_FRAME_SIZE (PKT_MAX_BUF_SIZE << 16) 22 #define ENETFEC_MAX_RX_PKT_LEN 3000 23 24 #define __iomem 25 #if defined(RTE_ARCH_ARM) 26 #if defined(RTE_ARCH_64) 27 #define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); } 28 #define dcbf_64(p) dcbf(p) 29 30 #else /* RTE_ARCH_32 */ 31 #define dcbf(p) RTE_SET_USED(p) 32 #define dcbf_64(p) dcbf(p) 33 #endif 34 35 #else 36 #define dcbf(p) RTE_SET_USED(p) 37 #define dcbf_64(p) dcbf(p) 38 #endif 39 40 /* 41 * ENETFEC can support 1 rx and tx queue.. 42 */ 43 44 #define ENETFEC_MAX_Q 1 45 46 #define writel(v, p) ({*(volatile unsigned int *)(p) = (v); }) 47 #define readl(p) rte_read32(p) 48 49 struct bufdesc { 50 uint16_t bd_datlen; /* buffer data length */ 51 uint16_t bd_sc; /* buffer control & status */ 52 uint32_t bd_bufaddr; /* buffer address */ 53 }; 54 55 struct bufdesc_ex { 56 struct bufdesc desc; 57 uint32_t bd_esc; 58 uint32_t bd_prot; 59 uint32_t bd_bdu; 60 uint32_t ts; 61 uint16_t res0[4]; 62 }; 63 64 struct bufdesc_prop { 65 int queue_id; 66 /* Addresses of Tx and Rx buffers */ 67 struct bufdesc *base; 68 struct bufdesc *last; 69 struct bufdesc *cur; 70 void __iomem *active_reg_desc; 71 uint64_t descr_baseaddr_p; 72 unsigned short ring_size; 73 unsigned char d_size; 74 unsigned char d_size_log2; 75 }; 76 77 struct enetfec_priv_tx_q { 78 struct bufdesc_prop bd; 79 struct rte_mbuf *tx_mbuf[MAX_TX_BD_RING_SIZE]; 80 struct bufdesc *dirty_tx; 81 struct rte_mempool *pool; 82 struct enetfec_private *fep; 83 }; 84 85 struct enetfec_priv_rx_q { 86 struct bufdesc_prop bd; 87 struct rte_mbuf *rx_mbuf[MAX_RX_BD_RING_SIZE]; 88 struct rte_mempool *pool; 89 struct enetfec_private *fep; 90 }; 91 92 struct enetfec_private { 93 struct rte_eth_dev *dev; 94 struct rte_eth_stats stats; 95 int full_duplex; 96 int flag_pause; 97 int flag_csum; 98 uint32_t quirks; 99 uint32_t cbus_size; 100 uint32_t enetfec_e_cntl; 101 uint16_t max_rx_queues; 102 uint16_t max_tx_queues; 103 unsigned int total_tx_ring_size; 104 unsigned int total_rx_ring_size; 105 unsigned int reg_size; 106 unsigned int bd_size; 107 bool bufdesc_ex; 108 bool rgmii_txc_delay; 109 bool rgmii_rxc_delay; 110 void *hw_baseaddr_v; 111 void *bd_addr_v; 112 uint32_t hw_baseaddr_p; 113 uint32_t bd_addr_p; 114 uint32_t bd_addr_p_r[ENETFEC_MAX_Q]; 115 uint32_t bd_addr_p_t[ENETFEC_MAX_Q]; 116 void *dma_baseaddr_r[ENETFEC_MAX_Q]; 117 void *dma_baseaddr_t[ENETFEC_MAX_Q]; 118 struct enetfec_priv_rx_q *rx_queues[ENETFEC_MAX_Q]; 119 struct enetfec_priv_tx_q *tx_queues[ENETFEC_MAX_Q]; 120 }; 121 122 static inline struct 123 bufdesc *enet_get_nextdesc(struct bufdesc *bdp, struct bufdesc_prop *bd) 124 { 125 return (bdp >= bd->last) ? bd->base 126 : (struct bufdesc *)(((uintptr_t)bdp) + bd->d_size); 127 } 128 129 static inline int 130 fls64(unsigned long word) 131 { 132 return (64 - __builtin_clzl(word)) - 1; 133 } 134 135 static inline struct 136 bufdesc *enet_get_prevdesc(struct bufdesc *bdp, struct bufdesc_prop *bd) 137 { 138 return (bdp <= bd->base) ? bd->last 139 : (struct bufdesc *)(((uintptr_t)bdp) - bd->d_size); 140 } 141 142 static inline int 143 enet_get_bd_index(struct bufdesc *bdp, struct bufdesc_prop *bd) 144 { 145 return ((const char *)bdp - (const char *)bd->base) >> bd->d_size_log2; 146 } 147 148 uint16_t enetfec_recv_pkts(void *rxq1, struct rte_mbuf **rx_pkts, 149 uint16_t nb_pkts); 150 uint16_t enetfec_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 151 uint16_t nb_pkts); 152 153 #endif /*__ENETFEC_ETHDEV_H__*/ 154