1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _ENA_ETHDEV_H_ 35 #define _ENA_ETHDEV_H_ 36 37 #include <rte_pci.h> 38 39 #include "ena_com.h" 40 41 #define ENA_REGS_BAR 0 42 #define ENA_MEM_BAR 2 43 44 #define ENA_MAX_NUM_QUEUES 128 45 46 #define ENA_DEFAULT_TX_SW_DESCS (1024) 47 #define ENA_DEFAULT_TX_HW_DESCS (1024) 48 #define ENA_DEFAULT_RING_SIZE (1024) 49 50 #define ENA_MIN_FRAME_LEN 64 51 52 #define ENA_NAME_MAX_LEN 20 53 #define ENA_IRQNAME_SIZE 40 54 55 #define ENA_PKT_MAX_BUFS 17 56 57 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 58 59 #define ENA_CIRC_COUNT(head, tail, size) \ 60 (((uint16_t)((uint16_t)(head) - (uint16_t)(tail))) & ((size) - 1)) 61 62 #define ENA_CIRC_INC(index, step, size) \ 63 ((uint16_t)(index) + (uint16_t)(step)) 64 #define ENA_CIRC_INC_WRAP(index, step, size) \ 65 (((uint16_t)(index) + (uint16_t)(step)) & ((size) - 1)) 66 67 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) \ 68 ENA_CIRC_INC_WRAP(idx, 1, ring_size) 69 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) \ 70 ENA_CIRC_INC_WRAP(idx, 1, ring_size) 71 72 struct ena_adapter; 73 74 enum ena_ring_type { 75 ENA_RING_TYPE_RX = 1, 76 ENA_RING_TYPE_TX = 2, 77 }; 78 79 struct ena_tx_buffer { 80 struct rte_mbuf *mbuf; 81 unsigned int tx_descs; 82 unsigned int num_of_bufs; 83 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 84 }; 85 86 struct ena_ring { 87 u16 next_to_use; 88 u16 next_to_clean; 89 90 enum ena_ring_type type; 91 enum ena_admin_placement_policy_type tx_mem_queue_type; 92 /* Holds the empty requests for TX OOO completions */ 93 uint16_t *empty_tx_reqs; 94 union { 95 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */ 96 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */ 97 }; 98 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */ 99 100 struct ena_com_io_cq *ena_com_io_cq; 101 struct ena_com_io_sq *ena_com_io_sq; 102 103 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS] 104 __rte_cache_aligned; 105 106 struct rte_mempool *mb_pool; 107 unsigned int port_id; 108 unsigned int id; 109 /* Max length PMD can push to device for LLQ */ 110 uint8_t tx_max_header_size; 111 int configured; 112 struct ena_adapter *adapter; 113 } __rte_cache_aligned; 114 115 enum ena_adapter_state { 116 ENA_ADAPTER_STATE_FREE = 0, 117 ENA_ADAPTER_STATE_INIT = 1, 118 ENA_ADAPTER_STATE_RUNNING = 2, 119 ENA_ADAPTER_STATE_STOPPED = 3, 120 ENA_ADAPTER_STATE_CONFIG = 4, 121 }; 122 123 struct ena_driver_stats { 124 rte_atomic64_t ierrors; 125 rte_atomic64_t oerrors; 126 rte_atomic64_t rx_nombuf; 127 }; 128 129 struct ena_stats_dev { 130 u64 tx_timeout; 131 u64 io_suspend; 132 u64 io_resume; 133 u64 wd_expired; 134 u64 interface_up; 135 u64 interface_down; 136 u64 admin_q_pause; 137 }; 138 139 struct ena_stats_tx { 140 u64 cnt; 141 u64 bytes; 142 u64 queue_stop; 143 u64 prepare_ctx_err; 144 u64 queue_wakeup; 145 u64 dma_mapping_err; 146 u64 linearize; 147 u64 linearize_failed; 148 u64 tx_poll; 149 u64 doorbells; 150 u64 missing_tx_comp; 151 u64 bad_req_id; 152 }; 153 154 struct ena_stats_rx { 155 u64 cnt; 156 u64 bytes; 157 u64 refil_partial; 158 u64 bad_csum; 159 u64 page_alloc_fail; 160 u64 skb_alloc_fail; 161 u64 dma_mapping_err; 162 u64 bad_desc_num; 163 u64 small_copy_len_pkt; 164 }; 165 166 /* board specific private data structure */ 167 struct ena_adapter { 168 /* OS defined structs */ 169 struct rte_pci_device *pdev; 170 struct rte_eth_dev_data *rte_eth_dev_data; 171 struct rte_eth_dev *rte_dev; 172 173 struct ena_com_dev ena_dev __rte_cache_aligned; 174 175 /* TX */ 176 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; 177 int tx_ring_size; 178 179 /* RX */ 180 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; 181 int rx_ring_size; 182 183 u16 num_queues; 184 u16 max_mtu; 185 186 int id_number; 187 char name[ENA_NAME_MAX_LEN]; 188 u8 mac_addr[ETHER_ADDR_LEN]; 189 190 void *regs; 191 void *dev_mem_base; 192 193 struct ena_driver_stats *drv_stats; 194 enum ena_adapter_state state; 195 196 }; 197 198 #endif /* _ENA_ETHDEV_H_ */ 199