1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _ENA_ETHDEV_H_ 35 #define _ENA_ETHDEV_H_ 36 37 #include <rte_cycles.h> 38 #include <rte_pci.h> 39 #include <rte_bus_pci.h> 40 #include <rte_timer.h> 41 42 #include "ena_com.h" 43 44 #define ENA_REGS_BAR 0 45 #define ENA_MEM_BAR 2 46 47 #define ENA_MAX_NUM_QUEUES 128 48 #define ENA_DEFAULT_RING_SIZE (1024) 49 #define ENA_MIN_FRAME_LEN 64 50 #define ENA_NAME_MAX_LEN 20 51 #define ENA_PKT_MAX_BUFS 17 52 53 #define ENA_MIN_MTU 128 54 55 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 56 57 #define ENA_WD_TIMEOUT_SEC 3 58 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz()) 59 60 struct ena_adapter; 61 62 enum ena_ring_type { 63 ENA_RING_TYPE_RX = 1, 64 ENA_RING_TYPE_TX = 2, 65 }; 66 67 struct ena_tx_buffer { 68 struct rte_mbuf *mbuf; 69 unsigned int tx_descs; 70 unsigned int num_of_bufs; 71 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 72 }; 73 74 struct ena_ring { 75 u16 next_to_use; 76 u16 next_to_clean; 77 78 enum ena_ring_type type; 79 enum ena_admin_placement_policy_type tx_mem_queue_type; 80 /* Holds the empty requests for TX/RX OOO completions */ 81 union { 82 uint16_t *empty_tx_reqs; 83 uint16_t *empty_rx_reqs; 84 }; 85 86 union { 87 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */ 88 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */ 89 }; 90 struct rte_mbuf **rx_refill_buffer; 91 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */ 92 93 struct ena_com_io_cq *ena_com_io_cq; 94 struct ena_com_io_sq *ena_com_io_sq; 95 96 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS] 97 __rte_cache_aligned; 98 99 struct rte_mempool *mb_pool; 100 unsigned int port_id; 101 unsigned int id; 102 /* Max length PMD can push to device for LLQ */ 103 uint8_t tx_max_header_size; 104 int configured; 105 struct ena_adapter *adapter; 106 uint64_t offloads; 107 u16 sgl_size; 108 } __rte_cache_aligned; 109 110 enum ena_adapter_state { 111 ENA_ADAPTER_STATE_FREE = 0, 112 ENA_ADAPTER_STATE_INIT = 1, 113 ENA_ADAPTER_STATE_RUNNING = 2, 114 ENA_ADAPTER_STATE_STOPPED = 3, 115 ENA_ADAPTER_STATE_CONFIG = 4, 116 ENA_ADAPTER_STATE_CLOSED = 5, 117 }; 118 119 struct ena_driver_stats { 120 rte_atomic64_t ierrors; 121 rte_atomic64_t oerrors; 122 rte_atomic64_t rx_nombuf; 123 }; 124 125 struct ena_stats_dev { 126 u64 tx_timeout; 127 u64 io_suspend; 128 u64 io_resume; 129 u64 wd_expired; 130 u64 interface_up; 131 u64 interface_down; 132 u64 admin_q_pause; 133 }; 134 135 struct ena_stats_tx { 136 u64 cnt; 137 u64 bytes; 138 u64 queue_stop; 139 u64 prepare_ctx_err; 140 u64 queue_wakeup; 141 u64 dma_mapping_err; 142 u64 linearize; 143 u64 linearize_failed; 144 u64 tx_poll; 145 u64 doorbells; 146 u64 missing_tx_comp; 147 u64 bad_req_id; 148 }; 149 150 struct ena_stats_rx { 151 u64 cnt; 152 u64 bytes; 153 u64 refil_partial; 154 u64 bad_csum; 155 u64 page_alloc_fail; 156 u64 skb_alloc_fail; 157 u64 dma_mapping_err; 158 u64 bad_desc_num; 159 u64 small_copy_len_pkt; 160 }; 161 162 /* board specific private data structure */ 163 struct ena_adapter { 164 /* OS defined structs */ 165 struct rte_pci_device *pdev; 166 struct rte_eth_dev_data *rte_eth_dev_data; 167 struct rte_eth_dev *rte_dev; 168 169 struct ena_com_dev ena_dev __rte_cache_aligned; 170 171 /* TX */ 172 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; 173 int tx_ring_size; 174 u16 max_tx_sgl_size; 175 176 /* RX */ 177 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; 178 int rx_ring_size; 179 180 u16 num_queues; 181 u16 max_mtu; 182 u8 tso4_supported; 183 184 int id_number; 185 char name[ENA_NAME_MAX_LEN]; 186 u8 mac_addr[ETHER_ADDR_LEN]; 187 188 void *regs; 189 void *dev_mem_base; 190 191 struct ena_driver_stats *drv_stats; 192 enum ena_adapter_state state; 193 194 uint64_t tx_supported_offloads; 195 uint64_t tx_selected_offloads; 196 uint64_t rx_supported_offloads; 197 uint64_t rx_selected_offloads; 198 199 bool link_status; 200 201 enum ena_regs_reset_reason_types reset_reason; 202 203 struct rte_timer timer_wd; 204 uint64_t timestamp_wd; 205 uint64_t keep_alive_timeout; 206 207 bool trigger_reset; 208 209 bool wd_state; 210 }; 211 212 #endif /* _ENA_ETHDEV_H_ */ 213