1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #include "ena_com.h" 7 8 /*****************************************************************************/ 9 /*****************************************************************************/ 10 11 /* Timeout in micro-sec */ 12 #define ADMIN_CMD_TIMEOUT_US (3000000) 13 14 #define ENA_ASYNC_QUEUE_DEPTH 16 15 #define ENA_ADMIN_QUEUE_DEPTH 32 16 17 #define ENA_CTRL_MAJOR 0 18 #define ENA_CTRL_MINOR 0 19 #define ENA_CTRL_SUB_MINOR 1 20 21 #define MIN_ENA_CTRL_VER \ 22 (((ENA_CTRL_MAJOR) << \ 23 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \ 24 ((ENA_CTRL_MINOR) << \ 25 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \ 26 (ENA_CTRL_SUB_MINOR)) 27 28 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x))) 29 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32)) 30 31 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF 32 33 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4 34 35 #define ENA_REGS_ADMIN_INTR_MASK 1 36 37 #define ENA_MIN_ADMIN_POLL_US 100 38 39 #define ENA_MAX_ADMIN_POLL_US 5000 40 41 /*****************************************************************************/ 42 /*****************************************************************************/ 43 /*****************************************************************************/ 44 45 enum ena_cmd_status { 46 ENA_CMD_SUBMITTED, 47 ENA_CMD_COMPLETED, 48 /* Abort - canceled by the driver */ 49 ENA_CMD_ABORTED, 50 }; 51 52 struct ena_comp_ctx { 53 ena_wait_event_t wait_event; 54 struct ena_admin_acq_entry *user_cqe; 55 u32 comp_size; 56 enum ena_cmd_status status; 57 /* status from the device */ 58 u8 comp_status; 59 u8 cmd_opcode; 60 bool occupied; 61 }; 62 63 struct ena_com_stats_ctx { 64 struct ena_admin_aq_get_stats_cmd get_cmd; 65 struct ena_admin_acq_get_stats_resp get_resp; 66 }; 67 68 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, 69 struct ena_common_mem_addr *ena_addr, 70 dma_addr_t addr) 71 { 72 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { 73 ena_trc_err("dma address has more bits that the device supports\n"); 74 return ENA_COM_INVAL; 75 } 76 77 ena_addr->mem_addr_low = lower_32_bits(addr); 78 ena_addr->mem_addr_high = (u16)upper_32_bits(addr); 79 80 return 0; 81 } 82 83 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue) 84 { 85 struct ena_com_admin_sq *sq = &queue->sq; 86 u16 size = ADMIN_SQ_SIZE(queue->q_depth); 87 88 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr, 89 sq->mem_handle); 90 91 if (!sq->entries) { 92 ena_trc_err("memory allocation failed\n"); 93 return ENA_COM_NO_MEM; 94 } 95 96 sq->head = 0; 97 sq->tail = 0; 98 sq->phase = 1; 99 100 sq->db_addr = NULL; 101 102 return 0; 103 } 104 105 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue) 106 { 107 struct ena_com_admin_cq *cq = &queue->cq; 108 u16 size = ADMIN_CQ_SIZE(queue->q_depth); 109 110 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr, 111 cq->mem_handle); 112 113 if (!cq->entries) { 114 ena_trc_err("memory allocation failed\n"); 115 return ENA_COM_NO_MEM; 116 } 117 118 cq->head = 0; 119 cq->phase = 1; 120 121 return 0; 122 } 123 124 static int ena_com_admin_init_aenq(struct ena_com_dev *dev, 125 struct ena_aenq_handlers *aenq_handlers) 126 { 127 struct ena_com_aenq *aenq = &dev->aenq; 128 u32 addr_low, addr_high, aenq_caps; 129 u16 size; 130 131 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; 132 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH); 133 ENA_MEM_ALLOC_COHERENT(dev->dmadev, size, 134 aenq->entries, 135 aenq->dma_addr, 136 aenq->mem_handle); 137 138 if (!aenq->entries) { 139 ena_trc_err("memory allocation failed\n"); 140 return ENA_COM_NO_MEM; 141 } 142 143 aenq->head = aenq->q_depth; 144 aenq->phase = 1; 145 146 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); 147 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); 148 149 ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF); 150 ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); 151 152 aenq_caps = 0; 153 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; 154 aenq_caps |= (sizeof(struct ena_admin_aenq_entry) << 155 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) & 156 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK; 157 ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); 158 159 if (unlikely(!aenq_handlers)) { 160 ena_trc_err("aenq handlers pointer is NULL\n"); 161 return ENA_COM_INVAL; 162 } 163 164 aenq->aenq_handlers = aenq_handlers; 165 166 return 0; 167 } 168 169 static void comp_ctxt_release(struct ena_com_admin_queue *queue, 170 struct ena_comp_ctx *comp_ctx) 171 { 172 comp_ctx->occupied = false; 173 ATOMIC32_DEC(&queue->outstanding_cmds); 174 } 175 176 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue, 177 u16 command_id, bool capture) 178 { 179 if (unlikely(command_id >= queue->q_depth)) { 180 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n", 181 command_id, queue->q_depth); 182 return NULL; 183 } 184 185 if (unlikely(!queue->comp_ctx)) { 186 ena_trc_err("Completion context is NULL\n"); 187 return NULL; 188 } 189 190 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) { 191 ena_trc_err("Completion context is occupied\n"); 192 return NULL; 193 } 194 195 if (capture) { 196 ATOMIC32_INC(&queue->outstanding_cmds); 197 queue->comp_ctx[command_id].occupied = true; 198 } 199 200 return &queue->comp_ctx[command_id]; 201 } 202 203 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 204 struct ena_admin_aq_entry *cmd, 205 size_t cmd_size_in_bytes, 206 struct ena_admin_acq_entry *comp, 207 size_t comp_size_in_bytes) 208 { 209 struct ena_comp_ctx *comp_ctx; 210 u16 tail_masked, cmd_id; 211 u16 queue_size_mask; 212 u16 cnt; 213 214 queue_size_mask = admin_queue->q_depth - 1; 215 216 tail_masked = admin_queue->sq.tail & queue_size_mask; 217 218 /* In case of queue FULL */ 219 cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds); 220 if (cnt >= admin_queue->q_depth) { 221 ena_trc_dbg("admin queue is full.\n"); 222 admin_queue->stats.out_of_space++; 223 return ERR_PTR(ENA_COM_NO_SPACE); 224 } 225 226 cmd_id = admin_queue->curr_cmd_id; 227 228 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase & 229 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 230 231 cmd->aq_common_descriptor.command_id |= cmd_id & 232 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 233 234 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true); 235 if (unlikely(!comp_ctx)) 236 return ERR_PTR(ENA_COM_INVAL); 237 238 comp_ctx->status = ENA_CMD_SUBMITTED; 239 comp_ctx->comp_size = (u32)comp_size_in_bytes; 240 comp_ctx->user_cqe = comp; 241 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode; 242 243 ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event); 244 245 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes); 246 247 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) & 248 queue_size_mask; 249 250 admin_queue->sq.tail++; 251 admin_queue->stats.submitted_cmd++; 252 253 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0)) 254 admin_queue->sq.phase = !admin_queue->sq.phase; 255 256 ENA_DB_SYNC(&admin_queue->sq.mem_handle); 257 ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail, 258 admin_queue->sq.db_addr); 259 260 return comp_ctx; 261 } 262 263 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue) 264 { 265 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx); 266 struct ena_comp_ctx *comp_ctx; 267 u16 i; 268 269 queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size); 270 if (unlikely(!queue->comp_ctx)) { 271 ena_trc_err("memory allocation failed\n"); 272 return ENA_COM_NO_MEM; 273 } 274 275 for (i = 0; i < queue->q_depth; i++) { 276 comp_ctx = get_comp_ctxt(queue, i, false); 277 if (comp_ctx) 278 ENA_WAIT_EVENT_INIT(comp_ctx->wait_event); 279 } 280 281 return 0; 282 } 283 284 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 285 struct ena_admin_aq_entry *cmd, 286 size_t cmd_size_in_bytes, 287 struct ena_admin_acq_entry *comp, 288 size_t comp_size_in_bytes) 289 { 290 unsigned long flags = 0; 291 struct ena_comp_ctx *comp_ctx; 292 293 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 294 if (unlikely(!admin_queue->running_state)) { 295 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 296 return ERR_PTR(ENA_COM_NO_DEVICE); 297 } 298 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd, 299 cmd_size_in_bytes, 300 comp, 301 comp_size_in_bytes); 302 if (IS_ERR(comp_ctx)) 303 admin_queue->running_state = false; 304 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 305 306 return comp_ctx; 307 } 308 309 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, 310 struct ena_com_create_io_ctx *ctx, 311 struct ena_com_io_sq *io_sq) 312 { 313 size_t size; 314 int dev_node = 0; 315 316 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr)); 317 318 io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits; 319 io_sq->desc_entry_size = 320 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 321 sizeof(struct ena_eth_io_tx_desc) : 322 sizeof(struct ena_eth_io_rx_desc); 323 324 size = io_sq->desc_entry_size * io_sq->q_depth; 325 io_sq->bus = ena_dev->bus; 326 327 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 328 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev, 329 size, 330 io_sq->desc_addr.virt_addr, 331 io_sq->desc_addr.phys_addr, 332 io_sq->desc_addr.mem_handle, 333 ctx->numa_node, 334 dev_node); 335 if (!io_sq->desc_addr.virt_addr) { 336 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 337 size, 338 io_sq->desc_addr.virt_addr, 339 io_sq->desc_addr.phys_addr, 340 io_sq->desc_addr.mem_handle); 341 } 342 343 if (!io_sq->desc_addr.virt_addr) { 344 ena_trc_err("memory allocation failed\n"); 345 return ENA_COM_NO_MEM; 346 } 347 } 348 349 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 350 /* Allocate bounce buffers */ 351 io_sq->bounce_buf_ctrl.buffer_size = 352 ena_dev->llq_info.desc_list_entry_size; 353 io_sq->bounce_buf_ctrl.buffers_num = 354 ENA_COM_BOUNCE_BUFFER_CNTRL_CNT; 355 io_sq->bounce_buf_ctrl.next_to_use = 0; 356 357 size = io_sq->bounce_buf_ctrl.buffer_size * 358 io_sq->bounce_buf_ctrl.buffers_num; 359 360 ENA_MEM_ALLOC_NODE(ena_dev->dmadev, 361 size, 362 io_sq->bounce_buf_ctrl.base_buffer, 363 ctx->numa_node, 364 dev_node); 365 if (!io_sq->bounce_buf_ctrl.base_buffer) 366 io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size); 367 368 if (!io_sq->bounce_buf_ctrl.base_buffer) { 369 ena_trc_err("bounce buffer memory allocation failed\n"); 370 return ENA_COM_NO_MEM; 371 } 372 373 memcpy(&io_sq->llq_info, &ena_dev->llq_info, 374 sizeof(io_sq->llq_info)); 375 376 /* Initiate the first bounce buffer */ 377 io_sq->llq_buf_ctrl.curr_bounce_buf = 378 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl); 379 memset(io_sq->llq_buf_ctrl.curr_bounce_buf, 380 0x0, io_sq->llq_info.desc_list_entry_size); 381 io_sq->llq_buf_ctrl.descs_left_in_line = 382 io_sq->llq_info.descs_num_before_header; 383 io_sq->disable_meta_caching = 384 io_sq->llq_info.disable_meta_caching; 385 386 if (io_sq->llq_info.max_entries_in_tx_burst > 0) 387 io_sq->entries_in_tx_burst_left = 388 io_sq->llq_info.max_entries_in_tx_burst; 389 } 390 391 io_sq->tail = 0; 392 io_sq->next_to_comp = 0; 393 io_sq->phase = 1; 394 395 return 0; 396 } 397 398 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, 399 struct ena_com_create_io_ctx *ctx, 400 struct ena_com_io_cq *io_cq) 401 { 402 size_t size; 403 int prev_node = 0; 404 405 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr)); 406 407 /* Use the basic completion descriptor for Rx */ 408 io_cq->cdesc_entry_size_in_bytes = 409 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 410 sizeof(struct ena_eth_io_tx_cdesc) : 411 sizeof(struct ena_eth_io_rx_cdesc_base); 412 413 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 414 io_cq->bus = ena_dev->bus; 415 416 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev, 417 size, 418 io_cq->cdesc_addr.virt_addr, 419 io_cq->cdesc_addr.phys_addr, 420 io_cq->cdesc_addr.mem_handle, 421 ctx->numa_node, 422 prev_node); 423 if (!io_cq->cdesc_addr.virt_addr) { 424 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 425 size, 426 io_cq->cdesc_addr.virt_addr, 427 io_cq->cdesc_addr.phys_addr, 428 io_cq->cdesc_addr.mem_handle); 429 } 430 431 if (!io_cq->cdesc_addr.virt_addr) { 432 ena_trc_err("memory allocation failed\n"); 433 return ENA_COM_NO_MEM; 434 } 435 436 io_cq->phase = 1; 437 io_cq->head = 0; 438 439 return 0; 440 } 441 442 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue, 443 struct ena_admin_acq_entry *cqe) 444 { 445 struct ena_comp_ctx *comp_ctx; 446 u16 cmd_id; 447 448 cmd_id = cqe->acq_common_descriptor.command & 449 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 450 451 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false); 452 if (unlikely(!comp_ctx)) { 453 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n"); 454 admin_queue->running_state = false; 455 return; 456 } 457 458 comp_ctx->status = ENA_CMD_COMPLETED; 459 comp_ctx->comp_status = cqe->acq_common_descriptor.status; 460 461 if (comp_ctx->user_cqe) 462 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size); 463 464 if (!admin_queue->polling) 465 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event); 466 } 467 468 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue) 469 { 470 struct ena_admin_acq_entry *cqe = NULL; 471 u16 comp_num = 0; 472 u16 head_masked; 473 u8 phase; 474 475 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1); 476 phase = admin_queue->cq.phase; 477 478 cqe = &admin_queue->cq.entries[head_masked]; 479 480 /* Go over all the completions */ 481 while ((READ_ONCE8(cqe->acq_common_descriptor.flags) & 482 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) { 483 /* Do not read the rest of the completion entry before the 484 * phase bit was validated 485 */ 486 dma_rmb(); 487 ena_com_handle_single_admin_completion(admin_queue, cqe); 488 489 head_masked++; 490 comp_num++; 491 if (unlikely(head_masked == admin_queue->q_depth)) { 492 head_masked = 0; 493 phase = !phase; 494 } 495 496 cqe = &admin_queue->cq.entries[head_masked]; 497 } 498 499 admin_queue->cq.head += comp_num; 500 admin_queue->cq.phase = phase; 501 admin_queue->sq.head += comp_num; 502 admin_queue->stats.completed_cmd += comp_num; 503 } 504 505 static int ena_com_comp_status_to_errno(u8 comp_status) 506 { 507 if (unlikely(comp_status != 0)) 508 ena_trc_err("admin command failed[%u]\n", comp_status); 509 510 switch (comp_status) { 511 case ENA_ADMIN_SUCCESS: 512 return ENA_COM_OK; 513 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE: 514 return ENA_COM_NO_MEM; 515 case ENA_ADMIN_UNSUPPORTED_OPCODE: 516 return ENA_COM_UNSUPPORTED; 517 case ENA_ADMIN_BAD_OPCODE: 518 case ENA_ADMIN_MALFORMED_REQUEST: 519 case ENA_ADMIN_ILLEGAL_PARAMETER: 520 case ENA_ADMIN_UNKNOWN_ERROR: 521 return ENA_COM_INVAL; 522 case ENA_ADMIN_RESOURCE_BUSY: 523 return ENA_COM_TRY_AGAIN; 524 } 525 526 return ENA_COM_INVAL; 527 } 528 529 static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us) 530 { 531 delay_us = ENA_MAX32(ENA_MIN_ADMIN_POLL_US, delay_us); 532 delay_us = ENA_MIN32(delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US); 533 ENA_USLEEP(delay_us); 534 } 535 536 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx, 537 struct ena_com_admin_queue *admin_queue) 538 { 539 unsigned long flags = 0; 540 ena_time_t timeout; 541 int ret; 542 u32 exp = 0; 543 544 timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout); 545 546 while (1) { 547 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 548 ena_com_handle_admin_completion(admin_queue); 549 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 550 551 if (comp_ctx->status != ENA_CMD_SUBMITTED) 552 break; 553 554 if (ENA_TIME_EXPIRE(timeout)) { 555 ena_trc_err("Wait for completion (polling) timeout\n"); 556 /* ENA didn't have any completion */ 557 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 558 admin_queue->stats.no_completion++; 559 admin_queue->running_state = false; 560 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 561 562 ret = ENA_COM_TIMER_EXPIRED; 563 goto err; 564 } 565 566 ena_delay_exponential_backoff_us(exp++, 567 admin_queue->ena_dev->ena_min_poll_delay_us); 568 } 569 570 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) { 571 ena_trc_err("Command was aborted\n"); 572 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 573 admin_queue->stats.aborted_cmd++; 574 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 575 ret = ENA_COM_NO_DEVICE; 576 goto err; 577 } 578 579 ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED, 580 "Invalid comp status %d\n", comp_ctx->status); 581 582 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); 583 err: 584 comp_ctxt_release(admin_queue, comp_ctx); 585 return ret; 586 } 587 588 /** 589 * Set the LLQ configurations of the firmware 590 * 591 * The driver provides only the enabled feature values to the device, 592 * which in turn, checks if they are supported. 593 */ 594 static int ena_com_set_llq(struct ena_com_dev *ena_dev) 595 { 596 struct ena_com_admin_queue *admin_queue; 597 struct ena_admin_set_feat_cmd cmd; 598 struct ena_admin_set_feat_resp resp; 599 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; 600 int ret; 601 602 memset(&cmd, 0x0, sizeof(cmd)); 603 admin_queue = &ena_dev->admin_queue; 604 605 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 606 cmd.feat_common.feature_id = ENA_ADMIN_LLQ; 607 608 cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl; 609 cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl; 610 cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header; 611 cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl; 612 613 cmd.u.llq.accel_mode.u.set.enabled_flags = 614 BIT(ENA_ADMIN_DISABLE_META_CACHING) | 615 BIT(ENA_ADMIN_LIMIT_TX_BURST); 616 617 ret = ena_com_execute_admin_command(admin_queue, 618 (struct ena_admin_aq_entry *)&cmd, 619 sizeof(cmd), 620 (struct ena_admin_acq_entry *)&resp, 621 sizeof(resp)); 622 623 if (unlikely(ret)) 624 ena_trc_err("Failed to set LLQ configurations: %d\n", ret); 625 626 return ret; 627 } 628 629 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, 630 struct ena_admin_feature_llq_desc *llq_features, 631 struct ena_llq_configurations *llq_default_cfg) 632 { 633 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; 634 struct ena_admin_accel_mode_get llq_accel_mode_get; 635 u16 supported_feat; 636 int rc; 637 638 memset(llq_info, 0, sizeof(*llq_info)); 639 640 supported_feat = llq_features->header_location_ctrl_supported; 641 642 if (likely(supported_feat & llq_default_cfg->llq_header_location)) { 643 llq_info->header_location_ctrl = 644 llq_default_cfg->llq_header_location; 645 } else { 646 ena_trc_err("Invalid header location control, supported: 0x%x\n", 647 supported_feat); 648 return -EINVAL; 649 } 650 651 if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) { 652 supported_feat = llq_features->descriptors_stride_ctrl_supported; 653 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) { 654 llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl; 655 } else { 656 if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) { 657 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 658 } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) { 659 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY; 660 } else { 661 ena_trc_err("Invalid desc_stride_ctrl, supported: 0x%x\n", 662 supported_feat); 663 return -EINVAL; 664 } 665 666 ena_trc_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", 667 llq_default_cfg->llq_stride_ctrl, 668 supported_feat, 669 llq_info->desc_stride_ctrl); 670 } 671 } else { 672 llq_info->desc_stride_ctrl = 0; 673 } 674 675 supported_feat = llq_features->entry_size_ctrl_supported; 676 if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) { 677 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size; 678 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value; 679 } else { 680 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) { 681 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B; 682 llq_info->desc_list_entry_size = 128; 683 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) { 684 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B; 685 llq_info->desc_list_entry_size = 192; 686 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) { 687 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B; 688 llq_info->desc_list_entry_size = 256; 689 } else { 690 ena_trc_err("Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat); 691 return -EINVAL; 692 } 693 694 ena_trc_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", 695 llq_default_cfg->llq_ring_entry_size, 696 supported_feat, 697 llq_info->desc_list_entry_size); 698 } 699 if (unlikely(llq_info->desc_list_entry_size & 0x7)) { 700 /* The desc list entry size should be whole multiply of 8 701 * This requirement comes from __iowrite64_copy() 702 */ 703 ena_trc_err("illegal entry size %d\n", 704 llq_info->desc_list_entry_size); 705 return -EINVAL; 706 } 707 708 if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) 709 llq_info->descs_per_entry = llq_info->desc_list_entry_size / 710 sizeof(struct ena_eth_io_tx_desc); 711 else 712 llq_info->descs_per_entry = 1; 713 714 supported_feat = llq_features->desc_num_before_header_supported; 715 if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) { 716 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header; 717 } else { 718 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) { 719 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 720 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) { 721 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1; 722 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) { 723 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4; 724 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) { 725 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8; 726 } else { 727 ena_trc_err("Invalid descs_num_before_header, supported: 0x%x\n", 728 supported_feat); 729 return -EINVAL; 730 } 731 732 ena_trc_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", 733 llq_default_cfg->llq_num_decs_before_header, 734 supported_feat, 735 llq_info->descs_num_before_header); 736 } 737 /* Check for accelerated queue supported */ 738 llq_accel_mode_get = llq_features->accel_mode.u.get; 739 740 llq_info->disable_meta_caching = 741 !!(llq_accel_mode_get.supported_flags & 742 BIT(ENA_ADMIN_DISABLE_META_CACHING)); 743 744 if (llq_accel_mode_get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST)) 745 llq_info->max_entries_in_tx_burst = 746 llq_accel_mode_get.max_tx_burst_size / 747 llq_default_cfg->llq_ring_entry_size_value; 748 749 rc = ena_com_set_llq(ena_dev); 750 if (rc) 751 ena_trc_err("Cannot set LLQ configuration: %d\n", rc); 752 753 return rc; 754 } 755 756 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx, 757 struct ena_com_admin_queue *admin_queue) 758 { 759 unsigned long flags = 0; 760 int ret; 761 762 ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event, 763 admin_queue->completion_timeout); 764 765 /* In case the command wasn't completed find out the root cause. 766 * There might be 2 kinds of errors 767 * 1) No completion (timeout reached) 768 * 2) There is completion but the device didn't get any msi-x interrupt. 769 */ 770 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) { 771 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 772 ena_com_handle_admin_completion(admin_queue); 773 admin_queue->stats.no_completion++; 774 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 775 776 if (comp_ctx->status == ENA_CMD_COMPLETED) { 777 ena_trc_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n", 778 comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF"); 779 /* Check if fallback to polling is enabled */ 780 if (admin_queue->auto_polling) 781 admin_queue->polling = true; 782 } else { 783 ena_trc_err("The ena device didn't send a completion for the admin cmd %d status %d\n", 784 comp_ctx->cmd_opcode, comp_ctx->status); 785 } 786 /* Check if shifted to polling mode. 787 * This will happen if there is a completion without an interrupt 788 * and autopolling mode is enabled. Continuing normal execution in such case 789 */ 790 if (!admin_queue->polling) { 791 admin_queue->running_state = false; 792 ret = ENA_COM_TIMER_EXPIRED; 793 goto err; 794 } 795 } 796 797 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); 798 err: 799 comp_ctxt_release(admin_queue, comp_ctx); 800 return ret; 801 } 802 803 /* This method read the hardware device register through posting writes 804 * and waiting for response 805 * On timeout the function will return ENA_MMIO_READ_TIMEOUT 806 */ 807 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) 808 { 809 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 810 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp = 811 mmio_read->read_resp; 812 u32 mmio_read_reg, ret, i; 813 unsigned long flags = 0; 814 u32 timeout = mmio_read->reg_read_to; 815 816 ENA_MIGHT_SLEEP(); 817 818 if (timeout == 0) 819 timeout = ENA_REG_READ_TIMEOUT; 820 821 /* If readless is disabled, perform regular read */ 822 if (!mmio_read->readless_supported) 823 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset); 824 825 ENA_SPINLOCK_LOCK(mmio_read->lock, flags); 826 mmio_read->seq_num++; 827 828 read_resp->req_id = mmio_read->seq_num + 0xDEAD; 829 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) & 830 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK; 831 mmio_read_reg |= mmio_read->seq_num & 832 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK; 833 834 ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg, 835 ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF); 836 837 for (i = 0; i < timeout; i++) { 838 if (READ_ONCE16(read_resp->req_id) == mmio_read->seq_num) 839 break; 840 841 ENA_UDELAY(1); 842 } 843 844 if (unlikely(i == timeout)) { 845 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n", 846 mmio_read->seq_num, 847 offset, 848 read_resp->req_id, 849 read_resp->reg_off); 850 ret = ENA_MMIO_READ_TIMEOUT; 851 goto err; 852 } 853 854 if (read_resp->reg_off != offset) { 855 ena_trc_err("Read failure: wrong offset provided\n"); 856 ret = ENA_MMIO_READ_TIMEOUT; 857 } else { 858 ret = read_resp->reg_val; 859 } 860 err: 861 ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags); 862 863 return ret; 864 } 865 866 /* There are two types to wait for completion. 867 * Polling mode - wait until the completion is available. 868 * Async mode - wait on wait queue until the completion is ready 869 * (or the timeout expired). 870 * It is expected that the IRQ called ena_com_handle_admin_completion 871 * to mark the completions. 872 */ 873 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx, 874 struct ena_com_admin_queue *admin_queue) 875 { 876 if (admin_queue->polling) 877 return ena_com_wait_and_process_admin_cq_polling(comp_ctx, 878 admin_queue); 879 880 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx, 881 admin_queue); 882 } 883 884 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, 885 struct ena_com_io_sq *io_sq) 886 { 887 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 888 struct ena_admin_aq_destroy_sq_cmd destroy_cmd; 889 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp; 890 u8 direction; 891 int ret; 892 893 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 894 895 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 896 direction = ENA_ADMIN_SQ_DIRECTION_TX; 897 else 898 direction = ENA_ADMIN_SQ_DIRECTION_RX; 899 900 destroy_cmd.sq.sq_identity |= (direction << 901 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & 902 ENA_ADMIN_SQ_SQ_DIRECTION_MASK; 903 904 destroy_cmd.sq.sq_idx = io_sq->idx; 905 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ; 906 907 ret = ena_com_execute_admin_command(admin_queue, 908 (struct ena_admin_aq_entry *)&destroy_cmd, 909 sizeof(destroy_cmd), 910 (struct ena_admin_acq_entry *)&destroy_resp, 911 sizeof(destroy_resp)); 912 913 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE))) 914 ena_trc_err("failed to destroy io sq error: %d\n", ret); 915 916 return ret; 917 } 918 919 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev, 920 struct ena_com_io_sq *io_sq, 921 struct ena_com_io_cq *io_cq) 922 { 923 size_t size; 924 925 if (io_cq->cdesc_addr.virt_addr) { 926 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 927 928 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 929 size, 930 io_cq->cdesc_addr.virt_addr, 931 io_cq->cdesc_addr.phys_addr, 932 io_cq->cdesc_addr.mem_handle); 933 934 io_cq->cdesc_addr.virt_addr = NULL; 935 } 936 937 if (io_sq->desc_addr.virt_addr) { 938 size = io_sq->desc_entry_size * io_sq->q_depth; 939 940 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 941 size, 942 io_sq->desc_addr.virt_addr, 943 io_sq->desc_addr.phys_addr, 944 io_sq->desc_addr.mem_handle); 945 946 io_sq->desc_addr.virt_addr = NULL; 947 } 948 949 if (io_sq->bounce_buf_ctrl.base_buffer) { 950 ENA_MEM_FREE(ena_dev->dmadev, 951 io_sq->bounce_buf_ctrl.base_buffer, 952 (io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT)); 953 io_sq->bounce_buf_ctrl.base_buffer = NULL; 954 } 955 } 956 957 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, 958 u16 exp_state) 959 { 960 u32 val, exp = 0; 961 ena_time_t timeout_stamp; 962 963 /* Convert timeout from resolution of 100ms to us resolution. */ 964 timeout_stamp = ENA_GET_SYSTEM_TIMEOUT(100 * 1000 * timeout); 965 966 while (1) { 967 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 968 969 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) { 970 ena_trc_err("Reg read timeout occurred\n"); 971 return ENA_COM_TIMER_EXPIRED; 972 } 973 974 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) == 975 exp_state) 976 return 0; 977 978 if (ENA_TIME_EXPIRE(timeout_stamp)) 979 return ENA_COM_TIMER_EXPIRED; 980 981 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us); 982 } 983 } 984 985 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev, 986 enum ena_admin_aq_feature_id feature_id) 987 { 988 u32 feature_mask = 1 << feature_id; 989 990 /* Device attributes is always supported */ 991 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) && 992 !(ena_dev->supported_features & feature_mask)) 993 return false; 994 995 return true; 996 } 997 998 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, 999 struct ena_admin_get_feat_resp *get_resp, 1000 enum ena_admin_aq_feature_id feature_id, 1001 dma_addr_t control_buf_dma_addr, 1002 u32 control_buff_size, 1003 u8 feature_ver) 1004 { 1005 struct ena_com_admin_queue *admin_queue; 1006 struct ena_admin_get_feat_cmd get_cmd; 1007 int ret; 1008 1009 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) { 1010 ena_trc_dbg("Feature %d isn't supported\n", feature_id); 1011 return ENA_COM_UNSUPPORTED; 1012 } 1013 1014 memset(&get_cmd, 0x0, sizeof(get_cmd)); 1015 admin_queue = &ena_dev->admin_queue; 1016 1017 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE; 1018 1019 if (control_buff_size) 1020 get_cmd.aq_common_descriptor.flags = 1021 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 1022 else 1023 get_cmd.aq_common_descriptor.flags = 0; 1024 1025 ret = ena_com_mem_addr_set(ena_dev, 1026 &get_cmd.control_buffer.address, 1027 control_buf_dma_addr); 1028 if (unlikely(ret)) { 1029 ena_trc_err("memory address set failed\n"); 1030 return ret; 1031 } 1032 1033 get_cmd.control_buffer.length = control_buff_size; 1034 get_cmd.feat_common.feature_version = feature_ver; 1035 get_cmd.feat_common.feature_id = feature_id; 1036 1037 ret = ena_com_execute_admin_command(admin_queue, 1038 (struct ena_admin_aq_entry *) 1039 &get_cmd, 1040 sizeof(get_cmd), 1041 (struct ena_admin_acq_entry *) 1042 get_resp, 1043 sizeof(*get_resp)); 1044 1045 if (unlikely(ret)) 1046 ena_trc_err("Failed to submit get_feature command %d error: %d\n", 1047 feature_id, ret); 1048 1049 return ret; 1050 } 1051 1052 static int ena_com_get_feature(struct ena_com_dev *ena_dev, 1053 struct ena_admin_get_feat_resp *get_resp, 1054 enum ena_admin_aq_feature_id feature_id, 1055 u8 feature_ver) 1056 { 1057 return ena_com_get_feature_ex(ena_dev, 1058 get_resp, 1059 feature_id, 1060 0, 1061 0, 1062 feature_ver); 1063 } 1064 1065 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev) 1066 { 1067 struct ena_admin_feature_rss_flow_hash_control *hash_key = 1068 (ena_dev->rss).hash_key; 1069 1070 ENA_RSS_FILL_KEY(&hash_key->key, sizeof(hash_key->key)); 1071 /* The key is stored in the device in uint32_t array 1072 * as well as the API requires the key to be passed in this 1073 * format. Thus the size of our array should be divided by 4 1074 */ 1075 hash_key->keys_num = sizeof(hash_key->key) / sizeof(uint32_t); 1076 } 1077 1078 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) 1079 { 1080 struct ena_rss *rss = &ena_dev->rss; 1081 1082 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 1083 sizeof(*rss->hash_key), 1084 rss->hash_key, 1085 rss->hash_key_dma_addr, 1086 rss->hash_key_mem_handle); 1087 1088 if (unlikely(!rss->hash_key)) 1089 return ENA_COM_NO_MEM; 1090 1091 return 0; 1092 } 1093 1094 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev) 1095 { 1096 struct ena_rss *rss = &ena_dev->rss; 1097 1098 if (rss->hash_key) 1099 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 1100 sizeof(*rss->hash_key), 1101 rss->hash_key, 1102 rss->hash_key_dma_addr, 1103 rss->hash_key_mem_handle); 1104 rss->hash_key = NULL; 1105 } 1106 1107 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev) 1108 { 1109 struct ena_rss *rss = &ena_dev->rss; 1110 1111 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 1112 sizeof(*rss->hash_ctrl), 1113 rss->hash_ctrl, 1114 rss->hash_ctrl_dma_addr, 1115 rss->hash_ctrl_mem_handle); 1116 1117 if (unlikely(!rss->hash_ctrl)) 1118 return ENA_COM_NO_MEM; 1119 1120 return 0; 1121 } 1122 1123 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev) 1124 { 1125 struct ena_rss *rss = &ena_dev->rss; 1126 1127 if (rss->hash_ctrl) 1128 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 1129 sizeof(*rss->hash_ctrl), 1130 rss->hash_ctrl, 1131 rss->hash_ctrl_dma_addr, 1132 rss->hash_ctrl_mem_handle); 1133 rss->hash_ctrl = NULL; 1134 } 1135 1136 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, 1137 u16 log_size) 1138 { 1139 struct ena_rss *rss = &ena_dev->rss; 1140 struct ena_admin_get_feat_resp get_resp; 1141 size_t tbl_size; 1142 int ret; 1143 1144 ret = ena_com_get_feature(ena_dev, &get_resp, 1145 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0); 1146 if (unlikely(ret)) 1147 return ret; 1148 1149 if ((get_resp.u.ind_table.min_size > log_size) || 1150 (get_resp.u.ind_table.max_size < log_size)) { 1151 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n", 1152 1 << log_size, 1153 1 << get_resp.u.ind_table.min_size, 1154 1 << get_resp.u.ind_table.max_size); 1155 return ENA_COM_INVAL; 1156 } 1157 1158 tbl_size = (1ULL << log_size) * 1159 sizeof(struct ena_admin_rss_ind_table_entry); 1160 1161 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 1162 tbl_size, 1163 rss->rss_ind_tbl, 1164 rss->rss_ind_tbl_dma_addr, 1165 rss->rss_ind_tbl_mem_handle); 1166 if (unlikely(!rss->rss_ind_tbl)) 1167 goto mem_err1; 1168 1169 tbl_size = (1ULL << log_size) * sizeof(u16); 1170 rss->host_rss_ind_tbl = 1171 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size); 1172 if (unlikely(!rss->host_rss_ind_tbl)) 1173 goto mem_err2; 1174 1175 rss->tbl_log_size = log_size; 1176 1177 return 0; 1178 1179 mem_err2: 1180 tbl_size = (1ULL << log_size) * 1181 sizeof(struct ena_admin_rss_ind_table_entry); 1182 1183 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 1184 tbl_size, 1185 rss->rss_ind_tbl, 1186 rss->rss_ind_tbl_dma_addr, 1187 rss->rss_ind_tbl_mem_handle); 1188 rss->rss_ind_tbl = NULL; 1189 mem_err1: 1190 rss->tbl_log_size = 0; 1191 return ENA_COM_NO_MEM; 1192 } 1193 1194 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev) 1195 { 1196 struct ena_rss *rss = &ena_dev->rss; 1197 size_t tbl_size = (1ULL << rss->tbl_log_size) * 1198 sizeof(struct ena_admin_rss_ind_table_entry); 1199 1200 if (rss->rss_ind_tbl) 1201 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 1202 tbl_size, 1203 rss->rss_ind_tbl, 1204 rss->rss_ind_tbl_dma_addr, 1205 rss->rss_ind_tbl_mem_handle); 1206 rss->rss_ind_tbl = NULL; 1207 1208 if (rss->host_rss_ind_tbl) 1209 ENA_MEM_FREE(ena_dev->dmadev, 1210 rss->host_rss_ind_tbl, 1211 ((1ULL << rss->tbl_log_size) * sizeof(u16))); 1212 rss->host_rss_ind_tbl = NULL; 1213 } 1214 1215 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, 1216 struct ena_com_io_sq *io_sq, u16 cq_idx) 1217 { 1218 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1219 struct ena_admin_aq_create_sq_cmd create_cmd; 1220 struct ena_admin_acq_create_sq_resp_desc cmd_completion; 1221 u8 direction; 1222 int ret; 1223 1224 memset(&create_cmd, 0x0, sizeof(create_cmd)); 1225 1226 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ; 1227 1228 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 1229 direction = ENA_ADMIN_SQ_DIRECTION_TX; 1230 else 1231 direction = ENA_ADMIN_SQ_DIRECTION_RX; 1232 1233 create_cmd.sq_identity |= (direction << 1234 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & 1235 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; 1236 1237 create_cmd.sq_caps_2 |= io_sq->mem_queue_type & 1238 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1239 1240 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC << 1241 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & 1242 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; 1243 1244 create_cmd.sq_caps_3 |= 1245 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1246 1247 create_cmd.cq_idx = cq_idx; 1248 create_cmd.sq_depth = io_sq->q_depth; 1249 1250 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 1251 ret = ena_com_mem_addr_set(ena_dev, 1252 &create_cmd.sq_ba, 1253 io_sq->desc_addr.phys_addr); 1254 if (unlikely(ret)) { 1255 ena_trc_err("memory address set failed\n"); 1256 return ret; 1257 } 1258 } 1259 1260 ret = ena_com_execute_admin_command(admin_queue, 1261 (struct ena_admin_aq_entry *)&create_cmd, 1262 sizeof(create_cmd), 1263 (struct ena_admin_acq_entry *)&cmd_completion, 1264 sizeof(cmd_completion)); 1265 if (unlikely(ret)) { 1266 ena_trc_err("Failed to create IO SQ. error: %d\n", ret); 1267 return ret; 1268 } 1269 1270 io_sq->idx = cmd_completion.sq_idx; 1271 1272 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1273 (uintptr_t)cmd_completion.sq_doorbell_offset); 1274 1275 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1276 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar 1277 + cmd_completion.llq_headers_offset); 1278 1279 io_sq->desc_addr.pbuf_dev_addr = 1280 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar + 1281 cmd_completion.llq_descriptors_offset); 1282 } 1283 1284 ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth); 1285 1286 return ret; 1287 } 1288 1289 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev) 1290 { 1291 struct ena_rss *rss = &ena_dev->rss; 1292 struct ena_com_io_sq *io_sq; 1293 u16 qid; 1294 int i; 1295 1296 for (i = 0; i < 1 << rss->tbl_log_size; i++) { 1297 qid = rss->host_rss_ind_tbl[i]; 1298 if (qid >= ENA_TOTAL_NUM_QUEUES) 1299 return ENA_COM_INVAL; 1300 1301 io_sq = &ena_dev->io_sq_queues[qid]; 1302 1303 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX) 1304 return ENA_COM_INVAL; 1305 1306 rss->rss_ind_tbl[i].cq_idx = io_sq->idx; 1307 } 1308 1309 return 0; 1310 } 1311 1312 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, 1313 u16 intr_delay_resolution) 1314 { 1315 u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution; 1316 1317 if (unlikely(!intr_delay_resolution)) { 1318 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); 1319 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION; 1320 } 1321 1322 /* update Rx */ 1323 ena_dev->intr_moder_rx_interval = 1324 ena_dev->intr_moder_rx_interval * 1325 prev_intr_delay_resolution / 1326 intr_delay_resolution; 1327 1328 /* update Tx */ 1329 ena_dev->intr_moder_tx_interval = 1330 ena_dev->intr_moder_tx_interval * 1331 prev_intr_delay_resolution / 1332 intr_delay_resolution; 1333 1334 ena_dev->intr_delay_resolution = intr_delay_resolution; 1335 } 1336 1337 /*****************************************************************************/ 1338 /******************************* API ******************************/ 1339 /*****************************************************************************/ 1340 1341 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, 1342 struct ena_admin_aq_entry *cmd, 1343 size_t cmd_size, 1344 struct ena_admin_acq_entry *comp, 1345 size_t comp_size) 1346 { 1347 struct ena_comp_ctx *comp_ctx; 1348 int ret; 1349 1350 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size, 1351 comp, comp_size); 1352 if (IS_ERR(comp_ctx)) { 1353 if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE)) 1354 ena_trc_dbg("Failed to submit command [%ld]\n", 1355 PTR_ERR(comp_ctx)); 1356 else 1357 ena_trc_err("Failed to submit command [%ld]\n", 1358 PTR_ERR(comp_ctx)); 1359 1360 return PTR_ERR(comp_ctx); 1361 } 1362 1363 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue); 1364 if (unlikely(ret)) { 1365 if (admin_queue->running_state) 1366 ena_trc_err("Failed to process command. ret = %d\n", 1367 ret); 1368 else 1369 ena_trc_dbg("Failed to process command. ret = %d\n", 1370 ret); 1371 } 1372 return ret; 1373 } 1374 1375 int ena_com_create_io_cq(struct ena_com_dev *ena_dev, 1376 struct ena_com_io_cq *io_cq) 1377 { 1378 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1379 struct ena_admin_aq_create_cq_cmd create_cmd; 1380 struct ena_admin_acq_create_cq_resp_desc cmd_completion; 1381 int ret; 1382 1383 memset(&create_cmd, 0x0, sizeof(create_cmd)); 1384 1385 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ; 1386 1387 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) & 1388 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1389 create_cmd.cq_caps_1 |= 1390 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK; 1391 1392 create_cmd.msix_vector = io_cq->msix_vector; 1393 create_cmd.cq_depth = io_cq->q_depth; 1394 1395 ret = ena_com_mem_addr_set(ena_dev, 1396 &create_cmd.cq_ba, 1397 io_cq->cdesc_addr.phys_addr); 1398 if (unlikely(ret)) { 1399 ena_trc_err("memory address set failed\n"); 1400 return ret; 1401 } 1402 1403 ret = ena_com_execute_admin_command(admin_queue, 1404 (struct ena_admin_aq_entry *)&create_cmd, 1405 sizeof(create_cmd), 1406 (struct ena_admin_acq_entry *)&cmd_completion, 1407 sizeof(cmd_completion)); 1408 if (unlikely(ret)) { 1409 ena_trc_err("Failed to create IO CQ. error: %d\n", ret); 1410 return ret; 1411 } 1412 1413 io_cq->idx = cmd_completion.cq_idx; 1414 1415 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1416 cmd_completion.cq_interrupt_unmask_register_offset); 1417 1418 if (cmd_completion.cq_head_db_register_offset) 1419 io_cq->cq_head_db_reg = 1420 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1421 cmd_completion.cq_head_db_register_offset); 1422 1423 if (cmd_completion.numa_node_register_offset) 1424 io_cq->numa_node_cfg_reg = 1425 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1426 cmd_completion.numa_node_register_offset); 1427 1428 ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth); 1429 1430 return ret; 1431 } 1432 1433 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, 1434 struct ena_com_io_sq **io_sq, 1435 struct ena_com_io_cq **io_cq) 1436 { 1437 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1438 ena_trc_err("Invalid queue number %d but the max is %d\n", 1439 qid, ENA_TOTAL_NUM_QUEUES); 1440 return ENA_COM_INVAL; 1441 } 1442 1443 *io_sq = &ena_dev->io_sq_queues[qid]; 1444 *io_cq = &ena_dev->io_cq_queues[qid]; 1445 1446 return 0; 1447 } 1448 1449 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev) 1450 { 1451 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1452 struct ena_comp_ctx *comp_ctx; 1453 u16 i; 1454 1455 if (!admin_queue->comp_ctx) 1456 return; 1457 1458 for (i = 0; i < admin_queue->q_depth; i++) { 1459 comp_ctx = get_comp_ctxt(admin_queue, i, false); 1460 if (unlikely(!comp_ctx)) 1461 break; 1462 1463 comp_ctx->status = ENA_CMD_ABORTED; 1464 1465 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event); 1466 } 1467 } 1468 1469 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev) 1470 { 1471 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1472 unsigned long flags = 0; 1473 u32 exp = 0; 1474 1475 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 1476 while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) { 1477 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 1478 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us); 1479 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 1480 } 1481 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 1482 } 1483 1484 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, 1485 struct ena_com_io_cq *io_cq) 1486 { 1487 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1488 struct ena_admin_aq_destroy_cq_cmd destroy_cmd; 1489 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp; 1490 int ret; 1491 1492 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 1493 1494 destroy_cmd.cq_idx = io_cq->idx; 1495 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ; 1496 1497 ret = ena_com_execute_admin_command(admin_queue, 1498 (struct ena_admin_aq_entry *)&destroy_cmd, 1499 sizeof(destroy_cmd), 1500 (struct ena_admin_acq_entry *)&destroy_resp, 1501 sizeof(destroy_resp)); 1502 1503 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE))) 1504 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret); 1505 1506 return ret; 1507 } 1508 1509 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev) 1510 { 1511 return ena_dev->admin_queue.running_state; 1512 } 1513 1514 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state) 1515 { 1516 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1517 unsigned long flags = 0; 1518 1519 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags); 1520 ena_dev->admin_queue.running_state = state; 1521 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags); 1522 } 1523 1524 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev) 1525 { 1526 u16 depth = ena_dev->aenq.q_depth; 1527 1528 ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); 1529 1530 /* Init head_db to mark that all entries in the queue 1531 * are initially available 1532 */ 1533 ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 1534 } 1535 1536 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) 1537 { 1538 struct ena_com_admin_queue *admin_queue; 1539 struct ena_admin_set_feat_cmd cmd; 1540 struct ena_admin_set_feat_resp resp; 1541 struct ena_admin_get_feat_resp get_resp; 1542 int ret; 1543 1544 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0); 1545 if (ret) { 1546 ena_trc_info("Can't get aenq configuration\n"); 1547 return ret; 1548 } 1549 1550 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) { 1551 ena_trc_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n", 1552 get_resp.u.aenq.supported_groups, 1553 groups_flag); 1554 return ENA_COM_UNSUPPORTED; 1555 } 1556 1557 memset(&cmd, 0x0, sizeof(cmd)); 1558 admin_queue = &ena_dev->admin_queue; 1559 1560 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1561 cmd.aq_common_descriptor.flags = 0; 1562 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG; 1563 cmd.u.aenq.enabled_groups = groups_flag; 1564 1565 ret = ena_com_execute_admin_command(admin_queue, 1566 (struct ena_admin_aq_entry *)&cmd, 1567 sizeof(cmd), 1568 (struct ena_admin_acq_entry *)&resp, 1569 sizeof(resp)); 1570 1571 if (unlikely(ret)) 1572 ena_trc_err("Failed to config AENQ ret: %d\n", ret); 1573 1574 return ret; 1575 } 1576 1577 int ena_com_get_dma_width(struct ena_com_dev *ena_dev) 1578 { 1579 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 1580 int width; 1581 1582 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { 1583 ena_trc_err("Reg read timeout occurred\n"); 1584 return ENA_COM_TIMER_EXPIRED; 1585 } 1586 1587 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> 1588 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT; 1589 1590 ena_trc_dbg("ENA dma width: %d\n", width); 1591 1592 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { 1593 ena_trc_err("DMA width illegal value: %d\n", width); 1594 return ENA_COM_INVAL; 1595 } 1596 1597 ena_dev->dma_addr_bits = width; 1598 1599 return width; 1600 } 1601 1602 int ena_com_validate_version(struct ena_com_dev *ena_dev) 1603 { 1604 u32 ver; 1605 u32 ctrl_ver; 1606 u32 ctrl_ver_masked; 1607 1608 /* Make sure the ENA version and the controller version are at least 1609 * as the driver expects 1610 */ 1611 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF); 1612 ctrl_ver = ena_com_reg_bar_read32(ena_dev, 1613 ENA_REGS_CONTROLLER_VERSION_OFF); 1614 1615 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || 1616 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) { 1617 ena_trc_err("Reg read timeout occurred\n"); 1618 return ENA_COM_TIMER_EXPIRED; 1619 } 1620 1621 ena_trc_info("ena device version: %d.%d\n", 1622 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> 1623 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT, 1624 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK); 1625 1626 ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n", 1627 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) 1628 >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT, 1629 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) 1630 >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT, 1631 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK), 1632 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >> 1633 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT); 1634 1635 ctrl_ver_masked = 1636 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) | 1637 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) | 1638 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK); 1639 1640 /* Validate the ctrl version without the implementation ID */ 1641 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) { 1642 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n"); 1643 return -1; 1644 } 1645 1646 return 0; 1647 } 1648 1649 void ena_com_admin_destroy(struct ena_com_dev *ena_dev) 1650 { 1651 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1652 struct ena_com_admin_cq *cq = &admin_queue->cq; 1653 struct ena_com_admin_sq *sq = &admin_queue->sq; 1654 struct ena_com_aenq *aenq = &ena_dev->aenq; 1655 u16 size; 1656 1657 if (admin_queue->comp_ctx) { 1658 ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event); 1659 ENA_MEM_FREE(ena_dev->dmadev, 1660 admin_queue->comp_ctx, 1661 (admin_queue->q_depth * sizeof(struct ena_comp_ctx))); 1662 } 1663 1664 admin_queue->comp_ctx = NULL; 1665 size = ADMIN_SQ_SIZE(admin_queue->q_depth); 1666 if (sq->entries) 1667 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries, 1668 sq->dma_addr, sq->mem_handle); 1669 sq->entries = NULL; 1670 1671 size = ADMIN_CQ_SIZE(admin_queue->q_depth); 1672 if (cq->entries) 1673 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries, 1674 cq->dma_addr, cq->mem_handle); 1675 cq->entries = NULL; 1676 1677 size = ADMIN_AENQ_SIZE(aenq->q_depth); 1678 if (ena_dev->aenq.entries) 1679 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries, 1680 aenq->dma_addr, aenq->mem_handle); 1681 aenq->entries = NULL; 1682 ENA_SPINLOCK_DESTROY(admin_queue->q_lock); 1683 } 1684 1685 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling) 1686 { 1687 u32 mask_value = 0; 1688 1689 if (polling) 1690 mask_value = ENA_REGS_ADMIN_INTR_MASK; 1691 1692 ENA_REG_WRITE32(ena_dev->bus, mask_value, 1693 ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF); 1694 ena_dev->admin_queue.polling = polling; 1695 } 1696 1697 bool ena_com_get_admin_polling_mode(struct ena_com_dev * ena_dev) 1698 { 1699 return ena_dev->admin_queue.polling; 1700 } 1701 1702 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev, 1703 bool polling) 1704 { 1705 ena_dev->admin_queue.auto_polling = polling; 1706 } 1707 1708 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev) 1709 { 1710 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1711 1712 ENA_SPINLOCK_INIT(mmio_read->lock); 1713 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 1714 sizeof(*mmio_read->read_resp), 1715 mmio_read->read_resp, 1716 mmio_read->read_resp_dma_addr, 1717 mmio_read->read_resp_mem_handle); 1718 if (unlikely(!mmio_read->read_resp)) 1719 goto err; 1720 1721 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 1722 1723 mmio_read->read_resp->req_id = 0x0; 1724 mmio_read->seq_num = 0x0; 1725 mmio_read->readless_supported = true; 1726 1727 return 0; 1728 1729 err: 1730 ENA_SPINLOCK_DESTROY(mmio_read->lock); 1731 return ENA_COM_NO_MEM; 1732 } 1733 1734 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported) 1735 { 1736 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1737 1738 mmio_read->readless_supported = readless_supported; 1739 } 1740 1741 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev) 1742 { 1743 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1744 1745 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1746 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1747 1748 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 1749 sizeof(*mmio_read->read_resp), 1750 mmio_read->read_resp, 1751 mmio_read->read_resp_dma_addr, 1752 mmio_read->read_resp_mem_handle); 1753 1754 mmio_read->read_resp = NULL; 1755 ENA_SPINLOCK_DESTROY(mmio_read->lock); 1756 } 1757 1758 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev) 1759 { 1760 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1761 u32 addr_low, addr_high; 1762 1763 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr); 1764 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr); 1765 1766 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1767 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1768 } 1769 1770 int ena_com_admin_init(struct ena_com_dev *ena_dev, 1771 struct ena_aenq_handlers *aenq_handlers) 1772 { 1773 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1774 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high; 1775 int ret; 1776 1777 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 1778 1779 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) { 1780 ena_trc_err("Reg read timeout occurred\n"); 1781 return ENA_COM_TIMER_EXPIRED; 1782 } 1783 1784 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) { 1785 ena_trc_err("Device isn't ready, abort com init\n"); 1786 return ENA_COM_NO_DEVICE; 1787 } 1788 1789 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH; 1790 1791 admin_queue->bus = ena_dev->bus; 1792 admin_queue->q_dmadev = ena_dev->dmadev; 1793 admin_queue->polling = false; 1794 admin_queue->curr_cmd_id = 0; 1795 1796 ATOMIC32_SET(&admin_queue->outstanding_cmds, 0); 1797 1798 ENA_SPINLOCK_INIT(admin_queue->q_lock); 1799 1800 ret = ena_com_init_comp_ctxt(admin_queue); 1801 if (ret) 1802 goto error; 1803 1804 ret = ena_com_admin_init_sq(admin_queue); 1805 if (ret) 1806 goto error; 1807 1808 ret = ena_com_admin_init_cq(admin_queue); 1809 if (ret) 1810 goto error; 1811 1812 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1813 ENA_REGS_AQ_DB_OFF); 1814 1815 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr); 1816 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr); 1817 1818 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF); 1819 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF); 1820 1821 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr); 1822 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr); 1823 1824 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF); 1825 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF); 1826 1827 aq_caps = 0; 1828 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK; 1829 aq_caps |= (sizeof(struct ena_admin_aq_entry) << 1830 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) & 1831 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK; 1832 1833 acq_caps = 0; 1834 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK; 1835 acq_caps |= (sizeof(struct ena_admin_acq_entry) << 1836 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) & 1837 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK; 1838 1839 ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF); 1840 ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF); 1841 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers); 1842 if (ret) 1843 goto error; 1844 1845 admin_queue->ena_dev = ena_dev; 1846 admin_queue->running_state = true; 1847 1848 return 0; 1849 error: 1850 ena_com_admin_destroy(ena_dev); 1851 1852 return ret; 1853 } 1854 1855 int ena_com_create_io_queue(struct ena_com_dev *ena_dev, 1856 struct ena_com_create_io_ctx *ctx) 1857 { 1858 struct ena_com_io_sq *io_sq; 1859 struct ena_com_io_cq *io_cq; 1860 int ret; 1861 1862 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) { 1863 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n", 1864 ctx->qid, ENA_TOTAL_NUM_QUEUES); 1865 return ENA_COM_INVAL; 1866 } 1867 1868 io_sq = &ena_dev->io_sq_queues[ctx->qid]; 1869 io_cq = &ena_dev->io_cq_queues[ctx->qid]; 1870 1871 memset(io_sq, 0x0, sizeof(*io_sq)); 1872 memset(io_cq, 0x0, sizeof(*io_cq)); 1873 1874 /* Init CQ */ 1875 io_cq->q_depth = ctx->queue_size; 1876 io_cq->direction = ctx->direction; 1877 io_cq->qid = ctx->qid; 1878 1879 io_cq->msix_vector = ctx->msix_vector; 1880 1881 io_sq->q_depth = ctx->queue_size; 1882 io_sq->direction = ctx->direction; 1883 io_sq->qid = ctx->qid; 1884 1885 io_sq->mem_queue_type = ctx->mem_queue_type; 1886 1887 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 1888 /* header length is limited to 8 bits */ 1889 io_sq->tx_max_header_size = 1890 ENA_MIN32(ena_dev->tx_max_header_size, SZ_256); 1891 1892 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq); 1893 if (ret) 1894 goto error; 1895 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq); 1896 if (ret) 1897 goto error; 1898 1899 ret = ena_com_create_io_cq(ena_dev, io_cq); 1900 if (ret) 1901 goto error; 1902 1903 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx); 1904 if (ret) 1905 goto destroy_io_cq; 1906 1907 return 0; 1908 1909 destroy_io_cq: 1910 ena_com_destroy_io_cq(ena_dev, io_cq); 1911 error: 1912 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1913 return ret; 1914 } 1915 1916 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) 1917 { 1918 struct ena_com_io_sq *io_sq; 1919 struct ena_com_io_cq *io_cq; 1920 1921 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1922 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n", 1923 qid, ENA_TOTAL_NUM_QUEUES); 1924 return; 1925 } 1926 1927 io_sq = &ena_dev->io_sq_queues[qid]; 1928 io_cq = &ena_dev->io_cq_queues[qid]; 1929 1930 ena_com_destroy_io_sq(ena_dev, io_sq); 1931 ena_com_destroy_io_cq(ena_dev, io_cq); 1932 1933 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1934 } 1935 1936 int ena_com_get_link_params(struct ena_com_dev *ena_dev, 1937 struct ena_admin_get_feat_resp *resp) 1938 { 1939 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0); 1940 } 1941 1942 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, 1943 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1944 { 1945 struct ena_admin_get_feat_resp get_resp; 1946 int rc; 1947 1948 rc = ena_com_get_feature(ena_dev, &get_resp, 1949 ENA_ADMIN_DEVICE_ATTRIBUTES, 0); 1950 if (rc) 1951 return rc; 1952 1953 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr, 1954 sizeof(get_resp.u.dev_attr)); 1955 ena_dev->supported_features = get_resp.u.dev_attr.supported_features; 1956 1957 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1958 rc = ena_com_get_feature(ena_dev, &get_resp, 1959 ENA_ADMIN_MAX_QUEUES_EXT, 1960 ENA_FEATURE_MAX_QUEUE_EXT_VER); 1961 if (rc) 1962 return rc; 1963 1964 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER) 1965 return -EINVAL; 1966 1967 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext, 1968 sizeof(get_resp.u.max_queue_ext)); 1969 ena_dev->tx_max_header_size = 1970 get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size; 1971 } else { 1972 rc = ena_com_get_feature(ena_dev, &get_resp, 1973 ENA_ADMIN_MAX_QUEUES_NUM, 0); 1974 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue, 1975 sizeof(get_resp.u.max_queue)); 1976 ena_dev->tx_max_header_size = 1977 get_resp.u.max_queue.max_header_size; 1978 1979 if (rc) 1980 return rc; 1981 } 1982 1983 rc = ena_com_get_feature(ena_dev, &get_resp, 1984 ENA_ADMIN_AENQ_CONFIG, 0); 1985 if (rc) 1986 return rc; 1987 1988 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq, 1989 sizeof(get_resp.u.aenq)); 1990 1991 rc = ena_com_get_feature(ena_dev, &get_resp, 1992 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0); 1993 if (rc) 1994 return rc; 1995 1996 memcpy(&get_feat_ctx->offload, &get_resp.u.offload, 1997 sizeof(get_resp.u.offload)); 1998 1999 /* Driver hints isn't mandatory admin command. So in case the 2000 * command isn't supported set driver hints to 0 2001 */ 2002 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0); 2003 2004 if (!rc) 2005 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints, 2006 sizeof(get_resp.u.hw_hints)); 2007 else if (rc == ENA_COM_UNSUPPORTED) 2008 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints)); 2009 else 2010 return rc; 2011 2012 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0); 2013 if (!rc) 2014 memcpy(&get_feat_ctx->llq, &get_resp.u.llq, 2015 sizeof(get_resp.u.llq)); 2016 else if (rc == ENA_COM_UNSUPPORTED) 2017 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq)); 2018 else 2019 return rc; 2020 2021 rc = ena_com_get_feature(ena_dev, &get_resp, 2022 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0); 2023 if (!rc) 2024 memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table, 2025 sizeof(get_resp.u.ind_table)); 2026 else if (rc == ENA_COM_UNSUPPORTED) 2027 memset(&get_feat_ctx->ind_table, 0x0, 2028 sizeof(get_feat_ctx->ind_table)); 2029 else 2030 return rc; 2031 2032 return 0; 2033 } 2034 2035 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev) 2036 { 2037 ena_com_handle_admin_completion(&ena_dev->admin_queue); 2038 } 2039 2040 /* ena_handle_specific_aenq_event: 2041 * return the handler that is relevant to the specific event group 2042 */ 2043 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev, 2044 u16 group) 2045 { 2046 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers; 2047 2048 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group]) 2049 return aenq_handlers->handlers[group]; 2050 2051 return aenq_handlers->unimplemented_handler; 2052 } 2053 2054 /* ena_aenq_intr_handler: 2055 * handles the aenq incoming events. 2056 * pop events from the queue and apply the specific handler 2057 */ 2058 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) 2059 { 2060 struct ena_admin_aenq_entry *aenq_e; 2061 struct ena_admin_aenq_common_desc *aenq_common; 2062 struct ena_com_aenq *aenq = &dev->aenq; 2063 u64 timestamp; 2064 ena_aenq_handler handler_cb; 2065 u16 masked_head, processed = 0; 2066 u8 phase; 2067 2068 masked_head = aenq->head & (aenq->q_depth - 1); 2069 phase = aenq->phase; 2070 aenq_e = &aenq->entries[masked_head]; /* Get first entry */ 2071 aenq_common = &aenq_e->aenq_common_desc; 2072 2073 /* Go over all the events */ 2074 while ((READ_ONCE8(aenq_common->flags) & 2075 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) { 2076 /* Make sure the phase bit (ownership) is as expected before 2077 * reading the rest of the descriptor. 2078 */ 2079 dma_rmb(); 2080 2081 timestamp = (u64)aenq_common->timestamp_low | 2082 ((u64)aenq_common->timestamp_high << 32); 2083 ENA_TOUCH(timestamp); /* In case debug is disabled */ 2084 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n", 2085 aenq_common->group, 2086 aenq_common->syndrom, 2087 timestamp); 2088 2089 /* Handle specific event*/ 2090 handler_cb = ena_com_get_specific_aenq_cb(dev, 2091 aenq_common->group); 2092 handler_cb(data, aenq_e); /* call the actual event handler*/ 2093 2094 /* Get next event entry */ 2095 masked_head++; 2096 processed++; 2097 2098 if (unlikely(masked_head == aenq->q_depth)) { 2099 masked_head = 0; 2100 phase = !phase; 2101 } 2102 aenq_e = &aenq->entries[masked_head]; 2103 aenq_common = &aenq_e->aenq_common_desc; 2104 } 2105 2106 aenq->head += processed; 2107 aenq->phase = phase; 2108 2109 /* Don't update aenq doorbell if there weren't any processed events */ 2110 if (!processed) 2111 return; 2112 2113 /* write the aenq doorbell after all AENQ descriptors were read */ 2114 mb(); 2115 ENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head, 2116 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 2117 mmiowb(); 2118 } 2119 2120 int ena_com_dev_reset(struct ena_com_dev *ena_dev, 2121 enum ena_regs_reset_reason_types reset_reason) 2122 { 2123 u32 stat, timeout, cap, reset_val; 2124 int rc; 2125 2126 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 2127 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 2128 2129 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || 2130 (cap == ENA_MMIO_READ_TIMEOUT))) { 2131 ena_trc_err("Reg read32 timeout occurred\n"); 2132 return ENA_COM_TIMER_EXPIRED; 2133 } 2134 2135 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) { 2136 ena_trc_err("Device isn't ready, can't reset device\n"); 2137 return ENA_COM_INVAL; 2138 } 2139 2140 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >> 2141 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT; 2142 if (timeout == 0) { 2143 ena_trc_err("Invalid timeout value\n"); 2144 return ENA_COM_INVAL; 2145 } 2146 2147 /* start reset */ 2148 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; 2149 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) & 2150 ENA_REGS_DEV_CTL_RESET_REASON_MASK; 2151 ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 2152 2153 /* Write again the MMIO read request address */ 2154 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 2155 2156 rc = wait_for_reset_state(ena_dev, timeout, 2157 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK); 2158 if (rc != 0) { 2159 ena_trc_err("Reset indication didn't turn on\n"); 2160 return rc; 2161 } 2162 2163 /* reset done */ 2164 ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 2165 rc = wait_for_reset_state(ena_dev, timeout, 0); 2166 if (rc != 0) { 2167 ena_trc_err("Reset indication didn't turn off\n"); 2168 return rc; 2169 } 2170 2171 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >> 2172 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT; 2173 if (timeout) 2174 /* the resolution of timeout reg is 100ms */ 2175 ena_dev->admin_queue.completion_timeout = timeout * 100000; 2176 else 2177 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US; 2178 2179 return 0; 2180 } 2181 2182 static int ena_get_dev_stats(struct ena_com_dev *ena_dev, 2183 struct ena_com_stats_ctx *ctx, 2184 enum ena_admin_get_stats_type type) 2185 { 2186 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd; 2187 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp; 2188 struct ena_com_admin_queue *admin_queue; 2189 int ret; 2190 2191 admin_queue = &ena_dev->admin_queue; 2192 2193 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS; 2194 get_cmd->aq_common_descriptor.flags = 0; 2195 get_cmd->type = type; 2196 2197 ret = ena_com_execute_admin_command(admin_queue, 2198 (struct ena_admin_aq_entry *)get_cmd, 2199 sizeof(*get_cmd), 2200 (struct ena_admin_acq_entry *)get_resp, 2201 sizeof(*get_resp)); 2202 2203 if (unlikely(ret)) 2204 ena_trc_err("Failed to get stats. error: %d\n", ret); 2205 2206 return ret; 2207 } 2208 2209 int ena_com_get_eni_stats(struct ena_com_dev *ena_dev, 2210 struct ena_admin_eni_stats *stats) 2211 { 2212 struct ena_com_stats_ctx ctx; 2213 int ret; 2214 2215 memset(&ctx, 0x0, sizeof(ctx)); 2216 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI); 2217 if (likely(ret == 0)) 2218 memcpy(stats, &ctx.get_resp.u.eni_stats, 2219 sizeof(ctx.get_resp.u.eni_stats)); 2220 2221 return ret; 2222 } 2223 2224 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, 2225 struct ena_admin_basic_stats *stats) 2226 { 2227 struct ena_com_stats_ctx ctx; 2228 int ret; 2229 2230 memset(&ctx, 0x0, sizeof(ctx)); 2231 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC); 2232 if (likely(ret == 0)) 2233 memcpy(stats, &ctx.get_resp.u.basic_stats, 2234 sizeof(ctx.get_resp.u.basic_stats)); 2235 2236 return ret; 2237 } 2238 2239 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) 2240 { 2241 struct ena_com_admin_queue *admin_queue; 2242 struct ena_admin_set_feat_cmd cmd; 2243 struct ena_admin_set_feat_resp resp; 2244 int ret; 2245 2246 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) { 2247 ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU); 2248 return ENA_COM_UNSUPPORTED; 2249 } 2250 2251 memset(&cmd, 0x0, sizeof(cmd)); 2252 admin_queue = &ena_dev->admin_queue; 2253 2254 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2255 cmd.aq_common_descriptor.flags = 0; 2256 cmd.feat_common.feature_id = ENA_ADMIN_MTU; 2257 cmd.u.mtu.mtu = mtu; 2258 2259 ret = ena_com_execute_admin_command(admin_queue, 2260 (struct ena_admin_aq_entry *)&cmd, 2261 sizeof(cmd), 2262 (struct ena_admin_acq_entry *)&resp, 2263 sizeof(resp)); 2264 2265 if (unlikely(ret)) 2266 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret); 2267 2268 return ret; 2269 } 2270 2271 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, 2272 struct ena_admin_feature_offload_desc *offload) 2273 { 2274 int ret; 2275 struct ena_admin_get_feat_resp resp; 2276 2277 ret = ena_com_get_feature(ena_dev, &resp, 2278 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0); 2279 if (unlikely(ret)) { 2280 ena_trc_err("Failed to get offload capabilities %d\n", ret); 2281 return ret; 2282 } 2283 2284 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload)); 2285 2286 return 0; 2287 } 2288 2289 int ena_com_set_hash_function(struct ena_com_dev *ena_dev) 2290 { 2291 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2292 struct ena_rss *rss = &ena_dev->rss; 2293 struct ena_admin_set_feat_cmd cmd; 2294 struct ena_admin_set_feat_resp resp; 2295 struct ena_admin_get_feat_resp get_resp; 2296 int ret; 2297 2298 if (!ena_com_check_supported_feature_id(ena_dev, 2299 ENA_ADMIN_RSS_HASH_FUNCTION)) { 2300 ena_trc_dbg("Feature %d isn't supported\n", 2301 ENA_ADMIN_RSS_HASH_FUNCTION); 2302 return ENA_COM_UNSUPPORTED; 2303 } 2304 2305 /* Validate hash function is supported */ 2306 ret = ena_com_get_feature(ena_dev, &get_resp, 2307 ENA_ADMIN_RSS_HASH_FUNCTION, 0); 2308 if (unlikely(ret)) 2309 return ret; 2310 2311 if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) { 2312 ena_trc_err("Func hash %d isn't supported by device, abort\n", 2313 rss->hash_func); 2314 return ENA_COM_UNSUPPORTED; 2315 } 2316 2317 memset(&cmd, 0x0, sizeof(cmd)); 2318 2319 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2320 cmd.aq_common_descriptor.flags = 2321 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2322 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION; 2323 cmd.u.flow_hash_func.init_val = rss->hash_init_val; 2324 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func; 2325 2326 ret = ena_com_mem_addr_set(ena_dev, 2327 &cmd.control_buffer.address, 2328 rss->hash_key_dma_addr); 2329 if (unlikely(ret)) { 2330 ena_trc_err("memory address set failed\n"); 2331 return ret; 2332 } 2333 2334 cmd.control_buffer.length = sizeof(*rss->hash_key); 2335 2336 ret = ena_com_execute_admin_command(admin_queue, 2337 (struct ena_admin_aq_entry *)&cmd, 2338 sizeof(cmd), 2339 (struct ena_admin_acq_entry *)&resp, 2340 sizeof(resp)); 2341 if (unlikely(ret)) { 2342 ena_trc_err("Failed to set hash function %d. error: %d\n", 2343 rss->hash_func, ret); 2344 return ENA_COM_INVAL; 2345 } 2346 2347 return 0; 2348 } 2349 2350 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, 2351 enum ena_admin_hash_functions func, 2352 const u8 *key, u16 key_len, u32 init_val) 2353 { 2354 struct ena_admin_feature_rss_flow_hash_control *hash_key; 2355 struct ena_admin_get_feat_resp get_resp; 2356 enum ena_admin_hash_functions old_func; 2357 struct ena_rss *rss = &ena_dev->rss; 2358 int rc; 2359 2360 hash_key = rss->hash_key; 2361 2362 /* Make sure size is a mult of DWs */ 2363 if (unlikely(key_len & 0x3)) 2364 return ENA_COM_INVAL; 2365 2366 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2367 ENA_ADMIN_RSS_HASH_FUNCTION, 2368 rss->hash_key_dma_addr, 2369 sizeof(*rss->hash_key), 0); 2370 if (unlikely(rc)) 2371 return rc; 2372 2373 if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) { 2374 ena_trc_err("Flow hash function %d isn't supported\n", func); 2375 return ENA_COM_UNSUPPORTED; 2376 } 2377 2378 switch (func) { 2379 case ENA_ADMIN_TOEPLITZ: 2380 if (key) { 2381 if (key_len != sizeof(hash_key->key)) { 2382 ena_trc_err("key len (%hu) doesn't equal the supported size (%zu)\n", 2383 key_len, sizeof(hash_key->key)); 2384 return ENA_COM_INVAL; 2385 } 2386 memcpy(hash_key->key, key, key_len); 2387 rss->hash_init_val = init_val; 2388 hash_key->keys_num = key_len / sizeof(u32); 2389 } 2390 break; 2391 case ENA_ADMIN_CRC32: 2392 rss->hash_init_val = init_val; 2393 break; 2394 default: 2395 ena_trc_err("Invalid hash function (%d)\n", func); 2396 return ENA_COM_INVAL; 2397 } 2398 2399 old_func = rss->hash_func; 2400 rss->hash_func = func; 2401 rc = ena_com_set_hash_function(ena_dev); 2402 2403 /* Restore the old function */ 2404 if (unlikely(rc)) 2405 rss->hash_func = old_func; 2406 2407 return rc; 2408 } 2409 2410 int ena_com_get_hash_function(struct ena_com_dev *ena_dev, 2411 enum ena_admin_hash_functions *func, 2412 u8 *key) 2413 { 2414 struct ena_rss *rss = &ena_dev->rss; 2415 struct ena_admin_get_feat_resp get_resp; 2416 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2417 rss->hash_key; 2418 int rc; 2419 2420 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2421 ENA_ADMIN_RSS_HASH_FUNCTION, 2422 rss->hash_key_dma_addr, 2423 sizeof(*rss->hash_key), 0); 2424 if (unlikely(rc)) 2425 return rc; 2426 2427 /* ENA_FFS returns 1 in case the lsb is set */ 2428 rss->hash_func = ENA_FFS(get_resp.u.flow_hash_func.selected_func); 2429 if (rss->hash_func) 2430 rss->hash_func--; 2431 2432 if (func) 2433 *func = rss->hash_func; 2434 2435 if (key) 2436 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2); 2437 2438 return 0; 2439 } 2440 2441 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, 2442 enum ena_admin_flow_hash_proto proto, 2443 u16 *fields) 2444 { 2445 struct ena_rss *rss = &ena_dev->rss; 2446 struct ena_admin_get_feat_resp get_resp; 2447 int rc; 2448 2449 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2450 ENA_ADMIN_RSS_HASH_INPUT, 2451 rss->hash_ctrl_dma_addr, 2452 sizeof(*rss->hash_ctrl), 0); 2453 if (unlikely(rc)) 2454 return rc; 2455 2456 if (fields) 2457 *fields = rss->hash_ctrl->selected_fields[proto].fields; 2458 2459 return 0; 2460 } 2461 2462 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) 2463 { 2464 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2465 struct ena_rss *rss = &ena_dev->rss; 2466 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2467 struct ena_admin_set_feat_cmd cmd; 2468 struct ena_admin_set_feat_resp resp; 2469 int ret; 2470 2471 if (!ena_com_check_supported_feature_id(ena_dev, 2472 ENA_ADMIN_RSS_HASH_INPUT)) { 2473 ena_trc_dbg("Feature %d isn't supported\n", 2474 ENA_ADMIN_RSS_HASH_INPUT); 2475 return ENA_COM_UNSUPPORTED; 2476 } 2477 2478 memset(&cmd, 0x0, sizeof(cmd)); 2479 2480 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2481 cmd.aq_common_descriptor.flags = 2482 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2483 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT; 2484 cmd.u.flow_hash_input.enabled_input_sort = 2485 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK | 2486 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; 2487 2488 ret = ena_com_mem_addr_set(ena_dev, 2489 &cmd.control_buffer.address, 2490 rss->hash_ctrl_dma_addr); 2491 if (unlikely(ret)) { 2492 ena_trc_err("memory address set failed\n"); 2493 return ret; 2494 } 2495 cmd.control_buffer.length = sizeof(*hash_ctrl); 2496 2497 ret = ena_com_execute_admin_command(admin_queue, 2498 (struct ena_admin_aq_entry *)&cmd, 2499 sizeof(cmd), 2500 (struct ena_admin_acq_entry *)&resp, 2501 sizeof(resp)); 2502 if (unlikely(ret)) 2503 ena_trc_err("Failed to set hash input. error: %d\n", ret); 2504 2505 return ret; 2506 } 2507 2508 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) 2509 { 2510 struct ena_rss *rss = &ena_dev->rss; 2511 struct ena_admin_feature_rss_hash_control *hash_ctrl = 2512 rss->hash_ctrl; 2513 u16 available_fields = 0; 2514 int rc, i; 2515 2516 /* Get the supported hash input */ 2517 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2518 if (unlikely(rc)) 2519 return rc; 2520 2521 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields = 2522 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2523 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2524 2525 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields = 2526 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2527 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2528 2529 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields = 2530 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2531 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2532 2533 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields = 2534 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2535 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2536 2537 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields = 2538 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2539 2540 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields = 2541 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2542 2543 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields = 2544 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2545 2546 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields = 2547 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA; 2548 2549 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) { 2550 available_fields = hash_ctrl->selected_fields[i].fields & 2551 hash_ctrl->supported_fields[i].fields; 2552 if (available_fields != hash_ctrl->selected_fields[i].fields) { 2553 ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n", 2554 i, hash_ctrl->supported_fields[i].fields, 2555 hash_ctrl->selected_fields[i].fields); 2556 return ENA_COM_UNSUPPORTED; 2557 } 2558 } 2559 2560 rc = ena_com_set_hash_ctrl(ena_dev); 2561 2562 /* In case of failure, restore the old hash ctrl */ 2563 if (unlikely(rc)) 2564 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2565 2566 return rc; 2567 } 2568 2569 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, 2570 enum ena_admin_flow_hash_proto proto, 2571 u16 hash_fields) 2572 { 2573 struct ena_rss *rss = &ena_dev->rss; 2574 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2575 u16 supported_fields; 2576 int rc; 2577 2578 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) { 2579 ena_trc_err("Invalid proto num (%u)\n", proto); 2580 return ENA_COM_INVAL; 2581 } 2582 2583 /* Get the ctrl table */ 2584 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL); 2585 if (unlikely(rc)) 2586 return rc; 2587 2588 /* Make sure all the fields are supported */ 2589 supported_fields = hash_ctrl->supported_fields[proto].fields; 2590 if ((hash_fields & supported_fields) != hash_fields) { 2591 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n", 2592 proto, hash_fields, supported_fields); 2593 } 2594 2595 hash_ctrl->selected_fields[proto].fields = hash_fields; 2596 2597 rc = ena_com_set_hash_ctrl(ena_dev); 2598 2599 /* In case of failure, restore the old hash ctrl */ 2600 if (unlikely(rc)) 2601 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2602 2603 return 0; 2604 } 2605 2606 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, 2607 u16 entry_idx, u16 entry_value) 2608 { 2609 struct ena_rss *rss = &ena_dev->rss; 2610 2611 if (unlikely(entry_idx >= (1 << rss->tbl_log_size))) 2612 return ENA_COM_INVAL; 2613 2614 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES))) 2615 return ENA_COM_INVAL; 2616 2617 rss->host_rss_ind_tbl[entry_idx] = entry_value; 2618 2619 return 0; 2620 } 2621 2622 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) 2623 { 2624 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2625 struct ena_rss *rss = &ena_dev->rss; 2626 struct ena_admin_set_feat_cmd cmd; 2627 struct ena_admin_set_feat_resp resp; 2628 int ret; 2629 2630 if (!ena_com_check_supported_feature_id(ena_dev, 2631 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) { 2632 ena_trc_dbg("Feature %d isn't supported\n", 2633 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); 2634 return ENA_COM_UNSUPPORTED; 2635 } 2636 2637 ret = ena_com_ind_tbl_convert_to_device(ena_dev); 2638 if (ret) { 2639 ena_trc_err("Failed to convert host indirection table to device table\n"); 2640 return ret; 2641 } 2642 2643 memset(&cmd, 0x0, sizeof(cmd)); 2644 2645 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2646 cmd.aq_common_descriptor.flags = 2647 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2648 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG; 2649 cmd.u.ind_table.size = rss->tbl_log_size; 2650 cmd.u.ind_table.inline_index = 0xFFFFFFFF; 2651 2652 ret = ena_com_mem_addr_set(ena_dev, 2653 &cmd.control_buffer.address, 2654 rss->rss_ind_tbl_dma_addr); 2655 if (unlikely(ret)) { 2656 ena_trc_err("memory address set failed\n"); 2657 return ret; 2658 } 2659 2660 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) * 2661 sizeof(struct ena_admin_rss_ind_table_entry); 2662 2663 ret = ena_com_execute_admin_command(admin_queue, 2664 (struct ena_admin_aq_entry *)&cmd, 2665 sizeof(cmd), 2666 (struct ena_admin_acq_entry *)&resp, 2667 sizeof(resp)); 2668 2669 if (unlikely(ret)) 2670 ena_trc_err("Failed to set indirect table. error: %d\n", ret); 2671 2672 return ret; 2673 } 2674 2675 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) 2676 { 2677 struct ena_rss *rss = &ena_dev->rss; 2678 struct ena_admin_get_feat_resp get_resp; 2679 u32 tbl_size; 2680 int i, rc; 2681 2682 tbl_size = (1ULL << rss->tbl_log_size) * 2683 sizeof(struct ena_admin_rss_ind_table_entry); 2684 2685 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2686 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 2687 rss->rss_ind_tbl_dma_addr, 2688 tbl_size, 0); 2689 if (unlikely(rc)) 2690 return rc; 2691 2692 if (!ind_tbl) 2693 return 0; 2694 2695 for (i = 0; i < (1 << rss->tbl_log_size); i++) 2696 ind_tbl[i] = rss->host_rss_ind_tbl[i]; 2697 2698 return 0; 2699 } 2700 2701 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size) 2702 { 2703 int rc; 2704 2705 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2706 2707 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size); 2708 if (unlikely(rc)) 2709 goto err_indr_tbl; 2710 2711 rc = ena_com_hash_key_allocate(ena_dev); 2712 if (unlikely(rc)) 2713 goto err_hash_key; 2714 2715 ena_com_hash_key_fill_default_key(ena_dev); 2716 2717 rc = ena_com_hash_ctrl_init(ena_dev); 2718 if (unlikely(rc)) 2719 goto err_hash_ctrl; 2720 2721 return 0; 2722 2723 err_hash_ctrl: 2724 ena_com_hash_key_destroy(ena_dev); 2725 err_hash_key: 2726 ena_com_indirect_table_destroy(ena_dev); 2727 err_indr_tbl: 2728 2729 return rc; 2730 } 2731 2732 void ena_com_rss_destroy(struct ena_com_dev *ena_dev) 2733 { 2734 ena_com_indirect_table_destroy(ena_dev); 2735 ena_com_hash_key_destroy(ena_dev); 2736 ena_com_hash_ctrl_destroy(ena_dev); 2737 2738 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2739 } 2740 2741 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev) 2742 { 2743 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2744 2745 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 2746 SZ_4K, 2747 host_attr->host_info, 2748 host_attr->host_info_dma_addr, 2749 host_attr->host_info_dma_handle); 2750 if (unlikely(!host_attr->host_info)) 2751 return ENA_COM_NO_MEM; 2752 2753 host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR << 2754 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) | 2755 (ENA_COMMON_SPEC_VERSION_MINOR)); 2756 2757 return 0; 2758 } 2759 2760 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, 2761 u32 debug_area_size) 2762 { 2763 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2764 2765 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, 2766 debug_area_size, 2767 host_attr->debug_area_virt_addr, 2768 host_attr->debug_area_dma_addr, 2769 host_attr->debug_area_dma_handle); 2770 if (unlikely(!host_attr->debug_area_virt_addr)) { 2771 host_attr->debug_area_size = 0; 2772 return ENA_COM_NO_MEM; 2773 } 2774 2775 host_attr->debug_area_size = debug_area_size; 2776 2777 return 0; 2778 } 2779 2780 void ena_com_delete_host_info(struct ena_com_dev *ena_dev) 2781 { 2782 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2783 2784 if (host_attr->host_info) { 2785 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 2786 SZ_4K, 2787 host_attr->host_info, 2788 host_attr->host_info_dma_addr, 2789 host_attr->host_info_dma_handle); 2790 host_attr->host_info = NULL; 2791 } 2792 } 2793 2794 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev) 2795 { 2796 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2797 2798 if (host_attr->debug_area_virt_addr) { 2799 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, 2800 host_attr->debug_area_size, 2801 host_attr->debug_area_virt_addr, 2802 host_attr->debug_area_dma_addr, 2803 host_attr->debug_area_dma_handle); 2804 host_attr->debug_area_virt_addr = NULL; 2805 } 2806 } 2807 2808 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) 2809 { 2810 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2811 struct ena_com_admin_queue *admin_queue; 2812 struct ena_admin_set_feat_cmd cmd; 2813 struct ena_admin_set_feat_resp resp; 2814 2815 int ret; 2816 2817 /* Host attribute config is called before ena_com_get_dev_attr_feat 2818 * so ena_com can't check if the feature is supported. 2819 */ 2820 2821 memset(&cmd, 0x0, sizeof(cmd)); 2822 admin_queue = &ena_dev->admin_queue; 2823 2824 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2825 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG; 2826 2827 ret = ena_com_mem_addr_set(ena_dev, 2828 &cmd.u.host_attr.debug_ba, 2829 host_attr->debug_area_dma_addr); 2830 if (unlikely(ret)) { 2831 ena_trc_err("memory address set failed\n"); 2832 return ret; 2833 } 2834 2835 ret = ena_com_mem_addr_set(ena_dev, 2836 &cmd.u.host_attr.os_info_ba, 2837 host_attr->host_info_dma_addr); 2838 if (unlikely(ret)) { 2839 ena_trc_err("memory address set failed\n"); 2840 return ret; 2841 } 2842 2843 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size; 2844 2845 ret = ena_com_execute_admin_command(admin_queue, 2846 (struct ena_admin_aq_entry *)&cmd, 2847 sizeof(cmd), 2848 (struct ena_admin_acq_entry *)&resp, 2849 sizeof(resp)); 2850 2851 if (unlikely(ret)) 2852 ena_trc_err("Failed to set host attributes: %d\n", ret); 2853 2854 return ret; 2855 } 2856 2857 /* Interrupt moderation */ 2858 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) 2859 { 2860 return ena_com_check_supported_feature_id(ena_dev, 2861 ENA_ADMIN_INTERRUPT_MODERATION); 2862 } 2863 2864 static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs, 2865 u32 intr_delay_resolution, 2866 u32 *intr_moder_interval) 2867 { 2868 if (!intr_delay_resolution) { 2869 ena_trc_err("Illegal interrupt delay granularity value\n"); 2870 return ENA_COM_FAULT; 2871 } 2872 2873 *intr_moder_interval = coalesce_usecs / intr_delay_resolution; 2874 2875 return 0; 2876 } 2877 2878 2879 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, 2880 u32 tx_coalesce_usecs) 2881 { 2882 return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs, 2883 ena_dev->intr_delay_resolution, 2884 &ena_dev->intr_moder_tx_interval); 2885 } 2886 2887 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, 2888 u32 rx_coalesce_usecs) 2889 { 2890 return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs, 2891 ena_dev->intr_delay_resolution, 2892 &ena_dev->intr_moder_rx_interval); 2893 } 2894 2895 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) 2896 { 2897 struct ena_admin_get_feat_resp get_resp; 2898 u16 delay_resolution; 2899 int rc; 2900 2901 rc = ena_com_get_feature(ena_dev, &get_resp, 2902 ENA_ADMIN_INTERRUPT_MODERATION, 0); 2903 2904 if (rc) { 2905 if (rc == ENA_COM_UNSUPPORTED) { 2906 ena_trc_dbg("Feature %d isn't supported\n", 2907 ENA_ADMIN_INTERRUPT_MODERATION); 2908 rc = 0; 2909 } else { 2910 ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n", 2911 rc); 2912 } 2913 2914 /* no moderation supported, disable adaptive support */ 2915 ena_com_disable_adaptive_moderation(ena_dev); 2916 return rc; 2917 } 2918 2919 /* if moderation is supported by device we set adaptive moderation */ 2920 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution; 2921 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution); 2922 2923 /* Disable adaptive moderation by default - can be enabled later */ 2924 ena_com_disable_adaptive_moderation(ena_dev); 2925 2926 return 0; 2927 } 2928 2929 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev) 2930 { 2931 return ena_dev->intr_moder_tx_interval; 2932 } 2933 2934 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev) 2935 { 2936 return ena_dev->intr_moder_rx_interval; 2937 } 2938 2939 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, 2940 struct ena_admin_feature_llq_desc *llq_features, 2941 struct ena_llq_configurations *llq_default_cfg) 2942 { 2943 int rc; 2944 struct ena_com_llq_info *llq_info = &(ena_dev->llq_info);; 2945 2946 if (!llq_features->max_llq_num) { 2947 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 2948 return 0; 2949 } 2950 2951 rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg); 2952 if (rc) 2953 return rc; 2954 2955 ena_dev->tx_max_header_size = llq_info->desc_list_entry_size - 2956 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc)); 2957 2958 if (ena_dev->tx_max_header_size == 0) { 2959 ena_trc_err("the size of the LLQ entry is smaller than needed\n"); 2960 return -EINVAL; 2961 } 2962 2963 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV; 2964 2965 return 0; 2966 } 2967