1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2016 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <stdarg.h> 10 11 #include <rte_common.h> 12 #include <rte_interrupts.h> 13 #include <rte_byteorder.h> 14 #include <rte_debug.h> 15 #include <rte_pci.h> 16 #include <rte_bus_pci.h> 17 #include <rte_ether.h> 18 #include <ethdev_driver.h> 19 #include <ethdev_pci.h> 20 #include <rte_memory.h> 21 #include <rte_eal.h> 22 #include <rte_malloc.h> 23 #include <rte_dev.h> 24 25 #include "e1000_logs.h" 26 #include "base/e1000_api.h" 27 #include "e1000_ethdev.h" 28 29 #define EM_EIAC 0x000DC 30 31 #define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y)) 32 33 34 static int eth_em_configure(struct rte_eth_dev *dev); 35 static int eth_em_start(struct rte_eth_dev *dev); 36 static int eth_em_stop(struct rte_eth_dev *dev); 37 static int eth_em_close(struct rte_eth_dev *dev); 38 static int eth_em_promiscuous_enable(struct rte_eth_dev *dev); 39 static int eth_em_promiscuous_disable(struct rte_eth_dev *dev); 40 static int eth_em_allmulticast_enable(struct rte_eth_dev *dev); 41 static int eth_em_allmulticast_disable(struct rte_eth_dev *dev); 42 static int eth_em_link_update(struct rte_eth_dev *dev, 43 int wait_to_complete); 44 static int eth_em_stats_get(struct rte_eth_dev *dev, 45 struct rte_eth_stats *rte_stats); 46 static int eth_em_stats_reset(struct rte_eth_dev *dev); 47 static int eth_em_infos_get(struct rte_eth_dev *dev, 48 struct rte_eth_dev_info *dev_info); 49 static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev, 50 struct rte_eth_fc_conf *fc_conf); 51 static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev, 52 struct rte_eth_fc_conf *fc_conf); 53 static int eth_em_interrupt_setup(struct rte_eth_dev *dev); 54 static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev); 55 static int eth_em_interrupt_get_status(struct rte_eth_dev *dev); 56 static int eth_em_interrupt_action(struct rte_eth_dev *dev, 57 struct rte_intr_handle *handle); 58 static void eth_em_interrupt_handler(void *param); 59 60 static int em_hw_init(struct e1000_hw *hw); 61 static int em_hardware_init(struct e1000_hw *hw); 62 static void em_hw_control_acquire(struct e1000_hw *hw); 63 static void em_hw_control_release(struct e1000_hw *hw); 64 static void em_init_manageability(struct e1000_hw *hw); 65 static void em_release_manageability(struct e1000_hw *hw); 66 67 static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 68 69 static int eth_em_vlan_filter_set(struct rte_eth_dev *dev, 70 uint16_t vlan_id, int on); 71 static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask); 72 static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev); 73 static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev); 74 static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev); 75 static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev); 76 77 /* 78 static void eth_em_vlan_filter_set(struct rte_eth_dev *dev, 79 uint16_t vlan_id, int on); 80 */ 81 82 static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id); 83 static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id); 84 static void em_lsc_intr_disable(struct e1000_hw *hw); 85 static void em_rxq_intr_enable(struct e1000_hw *hw); 86 static void em_rxq_intr_disable(struct e1000_hw *hw); 87 88 static int eth_em_led_on(struct rte_eth_dev *dev); 89 static int eth_em_led_off(struct rte_eth_dev *dev); 90 91 static int em_get_rx_buffer_size(struct e1000_hw *hw); 92 static int eth_em_rar_set(struct rte_eth_dev *dev, 93 struct rte_ether_addr *mac_addr, 94 uint32_t index, uint32_t pool); 95 static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index); 96 static int eth_em_default_mac_addr_set(struct rte_eth_dev *dev, 97 struct rte_ether_addr *addr); 98 99 static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev, 100 struct rte_ether_addr *mc_addr_set, 101 uint32_t nb_mc_addr); 102 103 #define EM_FC_PAUSE_TIME 0x0680 104 #define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */ 105 #define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */ 106 107 static enum e1000_fc_mode em_fc_setting = e1000_fc_full; 108 109 /* 110 * The set of PCI devices this driver supports 111 */ 112 static const struct rte_pci_id pci_id_em_map[] = { 113 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) }, 114 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) }, 115 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) }, 116 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) }, 117 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) }, 118 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) }, 119 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) }, 120 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) }, 121 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) }, 122 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) }, 123 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) }, 124 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) }, 125 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) }, 126 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) }, 127 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) }, 128 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) }, 129 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) }, 130 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) }, 131 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) }, 132 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) }, 133 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) }, 134 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) }, 135 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) }, 136 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) }, 137 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) }, 138 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) }, 139 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) }, 140 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) }, 141 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) }, 142 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) }, 143 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) }, 144 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) }, 145 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) }, 146 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) }, 147 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) }, 148 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) }, 149 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) }, 150 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) }, 151 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) }, 152 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) }, 153 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) }, 154 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) }, 155 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) }, 156 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) }, 157 { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) }, 158 { .vendor_id = 0, /* sentinel */ }, 159 }; 160 161 static const struct eth_dev_ops eth_em_ops = { 162 .dev_configure = eth_em_configure, 163 .dev_start = eth_em_start, 164 .dev_stop = eth_em_stop, 165 .dev_close = eth_em_close, 166 .promiscuous_enable = eth_em_promiscuous_enable, 167 .promiscuous_disable = eth_em_promiscuous_disable, 168 .allmulticast_enable = eth_em_allmulticast_enable, 169 .allmulticast_disable = eth_em_allmulticast_disable, 170 .link_update = eth_em_link_update, 171 .stats_get = eth_em_stats_get, 172 .stats_reset = eth_em_stats_reset, 173 .dev_infos_get = eth_em_infos_get, 174 .mtu_set = eth_em_mtu_set, 175 .vlan_filter_set = eth_em_vlan_filter_set, 176 .vlan_offload_set = eth_em_vlan_offload_set, 177 .rx_queue_setup = eth_em_rx_queue_setup, 178 .rx_queue_release = eth_em_rx_queue_release, 179 .tx_queue_setup = eth_em_tx_queue_setup, 180 .tx_queue_release = eth_em_tx_queue_release, 181 .rx_queue_intr_enable = eth_em_rx_queue_intr_enable, 182 .rx_queue_intr_disable = eth_em_rx_queue_intr_disable, 183 .dev_led_on = eth_em_led_on, 184 .dev_led_off = eth_em_led_off, 185 .flow_ctrl_get = eth_em_flow_ctrl_get, 186 .flow_ctrl_set = eth_em_flow_ctrl_set, 187 .mac_addr_set = eth_em_default_mac_addr_set, 188 .mac_addr_add = eth_em_rar_set, 189 .mac_addr_remove = eth_em_rar_clear, 190 .set_mc_addr_list = eth_em_set_mc_addr_list, 191 .rxq_info_get = em_rxq_info_get, 192 .txq_info_get = em_txq_info_get, 193 }; 194 195 196 /** 197 * eth_em_dev_is_ich8 - Check for ICH8 device 198 * @hw: pointer to the HW structure 199 * 200 * return TRUE for ICH8, otherwise FALSE 201 **/ 202 static bool 203 eth_em_dev_is_ich8(struct e1000_hw *hw) 204 { 205 DEBUGFUNC("eth_em_dev_is_ich8"); 206 207 switch (hw->device_id) { 208 case E1000_DEV_ID_PCH2_LV_LM: 209 case E1000_DEV_ID_PCH_LPT_I217_LM: 210 case E1000_DEV_ID_PCH_LPT_I217_V: 211 case E1000_DEV_ID_PCH_LPTLP_I218_LM: 212 case E1000_DEV_ID_PCH_LPTLP_I218_V: 213 case E1000_DEV_ID_PCH_I218_V2: 214 case E1000_DEV_ID_PCH_I218_LM2: 215 case E1000_DEV_ID_PCH_I218_V3: 216 case E1000_DEV_ID_PCH_I218_LM3: 217 case E1000_DEV_ID_PCH_SPT_I219_LM: 218 case E1000_DEV_ID_PCH_SPT_I219_V: 219 case E1000_DEV_ID_PCH_SPT_I219_LM2: 220 case E1000_DEV_ID_PCH_SPT_I219_V2: 221 case E1000_DEV_ID_PCH_LBG_I219_LM3: 222 case E1000_DEV_ID_PCH_SPT_I219_LM4: 223 case E1000_DEV_ID_PCH_SPT_I219_V4: 224 case E1000_DEV_ID_PCH_SPT_I219_LM5: 225 case E1000_DEV_ID_PCH_SPT_I219_V5: 226 case E1000_DEV_ID_PCH_CNP_I219_LM6: 227 case E1000_DEV_ID_PCH_CNP_I219_V6: 228 case E1000_DEV_ID_PCH_CNP_I219_LM7: 229 case E1000_DEV_ID_PCH_CNP_I219_V7: 230 return 1; 231 default: 232 return 0; 233 } 234 } 235 236 static int 237 eth_em_dev_init(struct rte_eth_dev *eth_dev) 238 { 239 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 240 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 241 struct e1000_adapter *adapter = 242 E1000_DEV_PRIVATE(eth_dev->data->dev_private); 243 struct e1000_hw *hw = 244 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 245 struct e1000_vfta * shadow_vfta = 246 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 247 248 eth_dev->dev_ops = ð_em_ops; 249 eth_dev->rx_queue_count = eth_em_rx_queue_count; 250 eth_dev->rx_descriptor_status = eth_em_rx_descriptor_status; 251 eth_dev->tx_descriptor_status = eth_em_tx_descriptor_status; 252 eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts; 253 eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts; 254 eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts; 255 256 /* for secondary processes, we don't initialise any further as primary 257 * has already done this work. Only check we don't need a different 258 * RX function */ 259 if (rte_eal_process_type() != RTE_PROC_PRIMARY){ 260 if (eth_dev->data->scattered_rx) 261 eth_dev->rx_pkt_burst = 262 (eth_rx_burst_t)ð_em_recv_scattered_pkts; 263 return 0; 264 } 265 266 rte_eth_copy_pci_info(eth_dev, pci_dev); 267 268 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 269 hw->device_id = pci_dev->id.device_id; 270 adapter->stopped = 0; 271 272 /* For ICH8 support we'll need to map the flash memory BAR */ 273 if (eth_em_dev_is_ich8(hw)) 274 hw->flash_address = (void *)pci_dev->mem_resource[1].addr; 275 276 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS || 277 em_hw_init(hw) != 0) { 278 PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: " 279 "failed to init HW", 280 eth_dev->data->port_id, pci_dev->id.vendor_id, 281 pci_dev->id.device_id); 282 return -ENODEV; 283 } 284 285 /* Allocate memory for storing MAC addresses */ 286 eth_dev->data->mac_addrs = rte_zmalloc("e1000", RTE_ETHER_ADDR_LEN * 287 hw->mac.rar_entry_count, 0); 288 if (eth_dev->data->mac_addrs == NULL) { 289 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to " 290 "store MAC addresses", 291 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count); 292 return -ENOMEM; 293 } 294 295 /* Copy the permanent MAC address */ 296 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr, 297 eth_dev->data->mac_addrs); 298 299 /* initialize the vfta */ 300 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 301 302 PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x", 303 eth_dev->data->port_id, pci_dev->id.vendor_id, 304 pci_dev->id.device_id); 305 306 rte_intr_callback_register(intr_handle, 307 eth_em_interrupt_handler, eth_dev); 308 309 return 0; 310 } 311 312 static int 313 eth_em_dev_uninit(struct rte_eth_dev *eth_dev) 314 { 315 PMD_INIT_FUNC_TRACE(); 316 317 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 318 return 0; 319 320 eth_em_close(eth_dev); 321 322 return 0; 323 } 324 325 static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 326 struct rte_pci_device *pci_dev) 327 { 328 return rte_eth_dev_pci_generic_probe(pci_dev, 329 sizeof(struct e1000_adapter), eth_em_dev_init); 330 } 331 332 static int eth_em_pci_remove(struct rte_pci_device *pci_dev) 333 { 334 return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit); 335 } 336 337 static struct rte_pci_driver rte_em_pmd = { 338 .id_table = pci_id_em_map, 339 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 340 .probe = eth_em_pci_probe, 341 .remove = eth_em_pci_remove, 342 }; 343 344 static int 345 em_hw_init(struct e1000_hw *hw) 346 { 347 int diag; 348 349 diag = hw->mac.ops.init_params(hw); 350 if (diag != 0) { 351 PMD_INIT_LOG(ERR, "MAC Initialization Error"); 352 return diag; 353 } 354 diag = hw->nvm.ops.init_params(hw); 355 if (diag != 0) { 356 PMD_INIT_LOG(ERR, "NVM Initialization Error"); 357 return diag; 358 } 359 diag = hw->phy.ops.init_params(hw); 360 if (diag != 0) { 361 PMD_INIT_LOG(ERR, "PHY Initialization Error"); 362 return diag; 363 } 364 (void) e1000_get_bus_info(hw); 365 366 hw->mac.autoneg = 1; 367 hw->phy.autoneg_wait_to_complete = 0; 368 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX; 369 370 e1000_init_script_state_82541(hw, TRUE); 371 e1000_set_tbi_compatibility_82543(hw, TRUE); 372 373 /* Copper options */ 374 if (hw->phy.media_type == e1000_media_type_copper) { 375 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 376 hw->phy.disable_polarity_correction = 0; 377 hw->phy.ms_type = e1000_ms_hw_default; 378 } 379 380 /* 381 * Start from a known state, this is important in reading the nvm 382 * and mac from that. 383 */ 384 e1000_reset_hw(hw); 385 386 /* Make sure we have a good EEPROM before we read from it */ 387 if (e1000_validate_nvm_checksum(hw) < 0) { 388 /* 389 * Some PCI-E parts fail the first check due to 390 * the link being in sleep state, call it again, 391 * if it fails a second time its a real issue. 392 */ 393 diag = e1000_validate_nvm_checksum(hw); 394 if (diag < 0) { 395 PMD_INIT_LOG(ERR, "EEPROM checksum invalid"); 396 goto error; 397 } 398 } 399 400 /* Read the permanent MAC address out of the EEPROM */ 401 diag = e1000_read_mac_addr(hw); 402 if (diag != 0) { 403 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address"); 404 goto error; 405 } 406 407 /* Now initialize the hardware */ 408 diag = em_hardware_init(hw); 409 if (diag != 0) { 410 PMD_INIT_LOG(ERR, "Hardware initialization failed"); 411 goto error; 412 } 413 414 hw->mac.get_link_status = 1; 415 416 /* Indicate SOL/IDER usage */ 417 diag = e1000_check_reset_block(hw); 418 if (diag < 0) { 419 PMD_INIT_LOG(ERR, "PHY reset is blocked due to " 420 "SOL/IDER session"); 421 } 422 return 0; 423 424 error: 425 em_hw_control_release(hw); 426 return diag; 427 } 428 429 static int 430 eth_em_configure(struct rte_eth_dev *dev) 431 { 432 struct e1000_interrupt *intr = 433 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 434 435 PMD_INIT_FUNC_TRACE(); 436 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE; 437 438 PMD_INIT_FUNC_TRACE(); 439 440 return 0; 441 } 442 443 static void 444 em_set_pba(struct e1000_hw *hw) 445 { 446 uint32_t pba; 447 448 /* 449 * Packet Buffer Allocation (PBA) 450 * Writing PBA sets the receive portion of the buffer 451 * the remainder is used for the transmit buffer. 452 * Devices before the 82547 had a Packet Buffer of 64K. 453 * After the 82547 the buffer was reduced to 40K. 454 */ 455 switch (hw->mac.type) { 456 case e1000_82547: 457 case e1000_82547_rev_2: 458 /* 82547: Total Packet Buffer is 40K */ 459 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 460 break; 461 case e1000_82571: 462 case e1000_82572: 463 case e1000_80003es2lan: 464 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 465 break; 466 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 467 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 468 break; 469 case e1000_82574: 470 case e1000_82583: 471 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */ 472 break; 473 case e1000_ich8lan: 474 pba = E1000_PBA_8K; 475 break; 476 case e1000_ich9lan: 477 case e1000_ich10lan: 478 pba = E1000_PBA_10K; 479 break; 480 case e1000_pchlan: 481 case e1000_pch2lan: 482 case e1000_pch_lpt: 483 case e1000_pch_spt: 484 case e1000_pch_cnp: 485 pba = E1000_PBA_26K; 486 break; 487 default: 488 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 489 } 490 491 E1000_WRITE_REG(hw, E1000_PBA, pba); 492 } 493 494 static void 495 eth_em_rxtx_control(struct rte_eth_dev *dev, 496 bool enable) 497 { 498 struct e1000_hw *hw = 499 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 500 uint32_t tctl, rctl; 501 502 tctl = E1000_READ_REG(hw, E1000_TCTL); 503 rctl = E1000_READ_REG(hw, E1000_RCTL); 504 if (enable) { 505 /* enable Tx/Rx */ 506 tctl |= E1000_TCTL_EN; 507 rctl |= E1000_RCTL_EN; 508 } else { 509 /* disable Tx/Rx */ 510 tctl &= ~E1000_TCTL_EN; 511 rctl &= ~E1000_RCTL_EN; 512 } 513 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 514 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 515 E1000_WRITE_FLUSH(hw); 516 } 517 518 static int 519 eth_em_start(struct rte_eth_dev *dev) 520 { 521 struct e1000_adapter *adapter = 522 E1000_DEV_PRIVATE(dev->data->dev_private); 523 struct e1000_hw *hw = 524 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 525 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 526 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 527 int ret, mask; 528 uint32_t intr_vector = 0; 529 uint32_t *speeds; 530 int num_speeds; 531 bool autoneg; 532 533 PMD_INIT_FUNC_TRACE(); 534 535 ret = eth_em_stop(dev); 536 if (ret != 0) 537 return ret; 538 539 e1000_power_up_phy(hw); 540 541 /* Set default PBA value */ 542 em_set_pba(hw); 543 544 /* Put the address into the Receive Address Array */ 545 e1000_rar_set(hw, hw->mac.addr, 0); 546 547 /* 548 * With the 82571 adapter, RAR[0] may be overwritten 549 * when the other port is reset, we make a duplicate 550 * in RAR[14] for that eventuality, this assures 551 * the interface continues to function. 552 */ 553 if (hw->mac.type == e1000_82571) { 554 e1000_set_laa_state_82571(hw, TRUE); 555 e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1); 556 } 557 558 /* Initialize the hardware */ 559 if (em_hardware_init(hw)) { 560 PMD_INIT_LOG(ERR, "Unable to initialize the hardware"); 561 return -EIO; 562 } 563 564 E1000_WRITE_REG(hw, E1000_VET, RTE_ETHER_TYPE_VLAN); 565 566 /* Configure for OS presence */ 567 em_init_manageability(hw); 568 569 if (dev->data->dev_conf.intr_conf.rxq != 0) { 570 intr_vector = dev->data->nb_rx_queues; 571 if (rte_intr_efd_enable(intr_handle, intr_vector)) 572 return -1; 573 } 574 575 if (rte_intr_dp_is_en(intr_handle)) { 576 intr_handle->intr_vec = 577 rte_zmalloc("intr_vec", 578 dev->data->nb_rx_queues * sizeof(int), 0); 579 if (intr_handle->intr_vec == NULL) { 580 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 581 " intr_vec", dev->data->nb_rx_queues); 582 return -ENOMEM; 583 } 584 585 /* enable rx interrupt */ 586 em_rxq_intr_enable(hw); 587 } 588 589 eth_em_tx_init(dev); 590 591 ret = eth_em_rx_init(dev); 592 if (ret) { 593 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 594 em_dev_clear_queues(dev); 595 return ret; 596 } 597 598 e1000_clear_hw_cntrs_base_generic(hw); 599 600 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \ 601 ETH_VLAN_EXTEND_MASK; 602 ret = eth_em_vlan_offload_set(dev, mask); 603 if (ret) { 604 PMD_INIT_LOG(ERR, "Unable to update vlan offload"); 605 em_dev_clear_queues(dev); 606 return ret; 607 } 608 609 /* Set Interrupt Throttling Rate to maximum allowed value. */ 610 E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX); 611 612 /* Setup link speed and duplex */ 613 speeds = &dev->data->dev_conf.link_speeds; 614 if (*speeds == ETH_LINK_SPEED_AUTONEG) { 615 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX; 616 hw->mac.autoneg = 1; 617 } else { 618 num_speeds = 0; 619 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0; 620 621 /* Reset */ 622 hw->phy.autoneg_advertised = 0; 623 624 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M | 625 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M | 626 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) { 627 num_speeds = -1; 628 goto error_invalid_config; 629 } 630 if (*speeds & ETH_LINK_SPEED_10M_HD) { 631 hw->phy.autoneg_advertised |= ADVERTISE_10_HALF; 632 num_speeds++; 633 } 634 if (*speeds & ETH_LINK_SPEED_10M) { 635 hw->phy.autoneg_advertised |= ADVERTISE_10_FULL; 636 num_speeds++; 637 } 638 if (*speeds & ETH_LINK_SPEED_100M_HD) { 639 hw->phy.autoneg_advertised |= ADVERTISE_100_HALF; 640 num_speeds++; 641 } 642 if (*speeds & ETH_LINK_SPEED_100M) { 643 hw->phy.autoneg_advertised |= ADVERTISE_100_FULL; 644 num_speeds++; 645 } 646 if (*speeds & ETH_LINK_SPEED_1G) { 647 hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL; 648 num_speeds++; 649 } 650 if (num_speeds == 0 || (!autoneg && (num_speeds > 1))) 651 goto error_invalid_config; 652 653 /* Set/reset the mac.autoneg based on the link speed, 654 * fixed or not 655 */ 656 if (!autoneg) { 657 hw->mac.autoneg = 0; 658 hw->mac.forced_speed_duplex = 659 hw->phy.autoneg_advertised; 660 } else { 661 hw->mac.autoneg = 1; 662 } 663 } 664 665 e1000_setup_link(hw); 666 667 if (rte_intr_allow_others(intr_handle)) { 668 /* check if lsc interrupt is enabled */ 669 if (dev->data->dev_conf.intr_conf.lsc != 0) { 670 ret = eth_em_interrupt_setup(dev); 671 if (ret) { 672 PMD_INIT_LOG(ERR, "Unable to setup interrupts"); 673 em_dev_clear_queues(dev); 674 return ret; 675 } 676 } 677 } else { 678 rte_intr_callback_unregister(intr_handle, 679 eth_em_interrupt_handler, 680 (void *)dev); 681 if (dev->data->dev_conf.intr_conf.lsc != 0) 682 PMD_INIT_LOG(INFO, "lsc won't enable because of" 683 " no intr multiplexn"); 684 } 685 /* check if rxq interrupt is enabled */ 686 if (dev->data->dev_conf.intr_conf.rxq != 0) 687 eth_em_rxq_interrupt_setup(dev); 688 689 rte_intr_enable(intr_handle); 690 691 adapter->stopped = 0; 692 693 eth_em_rxtx_control(dev, true); 694 eth_em_link_update(dev, 0); 695 696 PMD_INIT_LOG(DEBUG, "<<"); 697 698 return 0; 699 700 error_invalid_config: 701 PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u", 702 dev->data->dev_conf.link_speeds, dev->data->port_id); 703 em_dev_clear_queues(dev); 704 return -EINVAL; 705 } 706 707 /********************************************************************* 708 * 709 * This routine disables all traffic on the adapter by issuing a 710 * global reset on the MAC. 711 * 712 **********************************************************************/ 713 static int 714 eth_em_stop(struct rte_eth_dev *dev) 715 { 716 struct rte_eth_link link; 717 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 718 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 719 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 720 721 dev->data->dev_started = 0; 722 723 eth_em_rxtx_control(dev, false); 724 em_rxq_intr_disable(hw); 725 em_lsc_intr_disable(hw); 726 727 e1000_reset_hw(hw); 728 729 /* Flush desc rings for i219 */ 730 if (hw->mac.type == e1000_pch_spt || hw->mac.type == e1000_pch_cnp) 731 em_flush_desc_rings(dev); 732 733 if (hw->mac.type >= e1000_82544) 734 E1000_WRITE_REG(hw, E1000_WUC, 0); 735 736 /* Power down the phy. Needed to make the link go down */ 737 e1000_power_down_phy(hw); 738 739 em_dev_clear_queues(dev); 740 741 /* clear the recorded link status */ 742 memset(&link, 0, sizeof(link)); 743 rte_eth_linkstatus_set(dev, &link); 744 745 if (!rte_intr_allow_others(intr_handle)) 746 /* resume to the default handler */ 747 rte_intr_callback_register(intr_handle, 748 eth_em_interrupt_handler, 749 (void *)dev); 750 751 /* Clean datapath event and queue/vec mapping */ 752 rte_intr_efd_disable(intr_handle); 753 if (intr_handle->intr_vec != NULL) { 754 rte_free(intr_handle->intr_vec); 755 intr_handle->intr_vec = NULL; 756 } 757 758 return 0; 759 } 760 761 static int 762 eth_em_close(struct rte_eth_dev *dev) 763 { 764 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 765 struct e1000_adapter *adapter = 766 E1000_DEV_PRIVATE(dev->data->dev_private); 767 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 768 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 769 int ret; 770 771 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 772 return 0; 773 774 ret = eth_em_stop(dev); 775 adapter->stopped = 1; 776 em_dev_free_queues(dev); 777 e1000_phy_hw_reset(hw); 778 em_release_manageability(hw); 779 em_hw_control_release(hw); 780 781 /* disable uio intr before callback unregister */ 782 rte_intr_disable(intr_handle); 783 rte_intr_callback_unregister(intr_handle, 784 eth_em_interrupt_handler, dev); 785 786 return ret; 787 } 788 789 static int 790 em_get_rx_buffer_size(struct e1000_hw *hw) 791 { 792 uint32_t rx_buf_size; 793 794 rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10); 795 return rx_buf_size; 796 } 797 798 /********************************************************************* 799 * 800 * Initialize the hardware 801 * 802 **********************************************************************/ 803 static int 804 em_hardware_init(struct e1000_hw *hw) 805 { 806 uint32_t rx_buf_size; 807 int diag; 808 809 /* Issue a global reset */ 810 e1000_reset_hw(hw); 811 812 /* Let the firmware know the OS is in control */ 813 em_hw_control_acquire(hw); 814 815 /* 816 * These parameters control the automatic generation (Tx) and 817 * response (Rx) to Ethernet PAUSE frames. 818 * - High water mark should allow for at least two standard size (1518) 819 * frames to be received after sending an XOFF. 820 * - Low water mark works best when it is very near the high water mark. 821 * This allows the receiver to restart by sending XON when it has 822 * drained a bit. Here we use an arbitrary value of 1500 which will 823 * restart after one full frame is pulled from the buffer. There 824 * could be several smaller frames in the buffer and if so they will 825 * not trigger the XON until their total number reduces the buffer 826 * by 1500. 827 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 828 */ 829 rx_buf_size = em_get_rx_buffer_size(hw); 830 831 hw->fc.high_water = rx_buf_size - 832 PMD_ROUNDUP(RTE_ETHER_MAX_LEN * 2, 1024); 833 hw->fc.low_water = hw->fc.high_water - 1500; 834 835 if (hw->mac.type == e1000_80003es2lan) 836 hw->fc.pause_time = UINT16_MAX; 837 else 838 hw->fc.pause_time = EM_FC_PAUSE_TIME; 839 840 hw->fc.send_xon = 1; 841 842 /* Set Flow control, use the tunable location if sane */ 843 if (em_fc_setting <= e1000_fc_full) 844 hw->fc.requested_mode = em_fc_setting; 845 else 846 hw->fc.requested_mode = e1000_fc_none; 847 848 /* Workaround: no TX flow ctrl for PCH */ 849 if (hw->mac.type == e1000_pchlan) 850 hw->fc.requested_mode = e1000_fc_rx_pause; 851 852 /* Override - settings for PCH2LAN, ya its magic :) */ 853 if (hw->mac.type == e1000_pch2lan) { 854 hw->fc.high_water = 0x5C20; 855 hw->fc.low_water = 0x5048; 856 hw->fc.pause_time = 0x0650; 857 hw->fc.refresh_time = 0x0400; 858 } else if (hw->mac.type == e1000_pch_lpt || 859 hw->mac.type == e1000_pch_spt || 860 hw->mac.type == e1000_pch_cnp) { 861 hw->fc.requested_mode = e1000_fc_full; 862 } 863 864 diag = e1000_init_hw(hw); 865 if (diag < 0) 866 return diag; 867 e1000_check_for_link(hw); 868 return 0; 869 } 870 871 /* This function is based on em_update_stats_counters() in e1000/if_em.c */ 872 static int 873 eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats) 874 { 875 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 876 struct e1000_hw_stats *stats = 877 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 878 int pause_frames; 879 880 if(hw->phy.media_type == e1000_media_type_copper || 881 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) { 882 stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS); 883 stats->sec += E1000_READ_REG(hw, E1000_SEC); 884 } 885 886 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS); 887 stats->mpc += E1000_READ_REG(hw, E1000_MPC); 888 stats->scc += E1000_READ_REG(hw, E1000_SCC); 889 stats->ecol += E1000_READ_REG(hw, E1000_ECOL); 890 891 stats->mcc += E1000_READ_REG(hw, E1000_MCC); 892 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL); 893 stats->colc += E1000_READ_REG(hw, E1000_COLC); 894 stats->dc += E1000_READ_REG(hw, E1000_DC); 895 stats->rlec += E1000_READ_REG(hw, E1000_RLEC); 896 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC); 897 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC); 898 899 /* 900 * For watchdog management we need to know if we have been 901 * paused during the last interval, so capture that here. 902 */ 903 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC); 904 stats->xoffrxc += pause_frames; 905 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC); 906 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC); 907 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64); 908 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127); 909 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255); 910 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511); 911 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023); 912 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522); 913 stats->gprc += E1000_READ_REG(hw, E1000_GPRC); 914 stats->bprc += E1000_READ_REG(hw, E1000_BPRC); 915 stats->mprc += E1000_READ_REG(hw, E1000_MPRC); 916 stats->gptc += E1000_READ_REG(hw, E1000_GPTC); 917 918 /* 919 * For the 64-bit byte counters the low dword must be read first. 920 * Both registers clear on the read of the high dword. 921 */ 922 923 stats->gorc += E1000_READ_REG(hw, E1000_GORCL); 924 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32); 925 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL); 926 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32); 927 928 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC); 929 stats->ruc += E1000_READ_REG(hw, E1000_RUC); 930 stats->rfc += E1000_READ_REG(hw, E1000_RFC); 931 stats->roc += E1000_READ_REG(hw, E1000_ROC); 932 stats->rjc += E1000_READ_REG(hw, E1000_RJC); 933 934 stats->tor += E1000_READ_REG(hw, E1000_TORH); 935 stats->tot += E1000_READ_REG(hw, E1000_TOTH); 936 937 stats->tpr += E1000_READ_REG(hw, E1000_TPR); 938 stats->tpt += E1000_READ_REG(hw, E1000_TPT); 939 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64); 940 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127); 941 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255); 942 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511); 943 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023); 944 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522); 945 stats->mptc += E1000_READ_REG(hw, E1000_MPTC); 946 stats->bptc += E1000_READ_REG(hw, E1000_BPTC); 947 948 /* Interrupt Counts */ 949 950 if (hw->mac.type >= e1000_82571) { 951 stats->iac += E1000_READ_REG(hw, E1000_IAC); 952 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC); 953 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC); 954 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC); 955 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC); 956 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC); 957 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC); 958 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC); 959 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC); 960 } 961 962 if (hw->mac.type >= e1000_82543) { 963 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC); 964 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC); 965 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS); 966 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR); 967 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC); 968 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC); 969 } 970 971 if (rte_stats == NULL) 972 return -EINVAL; 973 974 /* Rx Errors */ 975 rte_stats->imissed = stats->mpc; 976 rte_stats->ierrors = stats->crcerrs + stats->rlec + 977 stats->rxerrc + stats->algnerrc + stats->cexterr; 978 979 /* Tx Errors */ 980 rte_stats->oerrors = stats->ecol + stats->latecol; 981 982 rte_stats->ipackets = stats->gprc; 983 rte_stats->opackets = stats->gptc; 984 rte_stats->ibytes = stats->gorc; 985 rte_stats->obytes = stats->gotc; 986 return 0; 987 } 988 989 static int 990 eth_em_stats_reset(struct rte_eth_dev *dev) 991 { 992 struct e1000_hw_stats *hw_stats = 993 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 994 995 /* HW registers are cleared on read */ 996 eth_em_stats_get(dev, NULL); 997 998 /* Reset software totals */ 999 memset(hw_stats, 0, sizeof(*hw_stats)); 1000 1001 return 0; 1002 } 1003 1004 static int 1005 eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id) 1006 { 1007 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1008 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1009 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1010 1011 em_rxq_intr_enable(hw); 1012 rte_intr_ack(intr_handle); 1013 1014 return 0; 1015 } 1016 1017 static int 1018 eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id) 1019 { 1020 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1021 1022 em_rxq_intr_disable(hw); 1023 1024 return 0; 1025 } 1026 1027 uint32_t 1028 em_get_max_pktlen(struct rte_eth_dev *dev) 1029 { 1030 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1031 1032 switch (hw->mac.type) { 1033 case e1000_82571: 1034 case e1000_82572: 1035 case e1000_ich9lan: 1036 case e1000_ich10lan: 1037 case e1000_pch2lan: 1038 case e1000_pch_lpt: 1039 case e1000_pch_spt: 1040 case e1000_pch_cnp: 1041 case e1000_82574: 1042 case e1000_80003es2lan: /* 9K Jumbo Frame size */ 1043 case e1000_82583: 1044 return 0x2412; 1045 case e1000_pchlan: 1046 return 0x1000; 1047 /* Adapters that do not support jumbo frames */ 1048 case e1000_ich8lan: 1049 return RTE_ETHER_MAX_LEN; 1050 default: 1051 return MAX_JUMBO_FRAME_SIZE; 1052 } 1053 } 1054 1055 static int 1056 eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1057 { 1058 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1059 1060 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */ 1061 dev_info->max_rx_pktlen = em_get_max_pktlen(dev); 1062 dev_info->max_mac_addrs = hw->mac.rar_entry_count; 1063 1064 /* 1065 * Starting with 631xESB hw supports 2 TX/RX queues per port. 1066 * Unfortunatelly, all these nics have just one TX context. 1067 * So we have few choises for TX: 1068 * - Use just one TX queue. 1069 * - Allow cksum offload only for one TX queue. 1070 * - Don't allow TX cksum offload at all. 1071 * For now, option #1 was chosen. 1072 * To use second RX queue we have to use extended RX descriptor 1073 * (Multiple Receive Queues are mutually exclusive with UDP 1074 * fragmentation and are not supported when a legacy receive 1075 * descriptor format is used). 1076 * Which means separate RX routinies - as legacy nics (82540, 82545) 1077 * don't support extended RXD. 1078 * To avoid it we support just one RX queue for now (no RSS). 1079 */ 1080 1081 dev_info->max_rx_queues = 1; 1082 dev_info->max_tx_queues = 1; 1083 1084 dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(); 1085 dev_info->rx_offload_capa = em_get_rx_port_offloads_capa() | 1086 dev_info->rx_queue_offload_capa; 1087 dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev); 1088 dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) | 1089 dev_info->tx_queue_offload_capa; 1090 1091 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 1092 .nb_max = E1000_MAX_RING_DESC, 1093 .nb_min = E1000_MIN_RING_DESC, 1094 .nb_align = EM_RXD_ALIGN, 1095 }; 1096 1097 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 1098 .nb_max = E1000_MAX_RING_DESC, 1099 .nb_min = E1000_MIN_RING_DESC, 1100 .nb_align = EM_TXD_ALIGN, 1101 .nb_seg_max = EM_TX_MAX_SEG, 1102 .nb_mtu_seg_max = EM_TX_MAX_MTU_SEG, 1103 }; 1104 1105 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M | 1106 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M | 1107 ETH_LINK_SPEED_1G; 1108 1109 /* Preferred queue parameters */ 1110 dev_info->default_rxportconf.nb_queues = 1; 1111 dev_info->default_txportconf.nb_queues = 1; 1112 dev_info->default_txportconf.ring_size = 256; 1113 dev_info->default_rxportconf.ring_size = 256; 1114 1115 return 0; 1116 } 1117 1118 /* return 0 means link status changed, -1 means not changed */ 1119 static int 1120 eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete) 1121 { 1122 struct e1000_hw *hw = 1123 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1124 struct rte_eth_link link; 1125 int link_up, count; 1126 1127 link_up = 0; 1128 hw->mac.get_link_status = 1; 1129 1130 /* possible wait-to-complete in up to 9 seconds */ 1131 for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) { 1132 /* Read the real link status */ 1133 switch (hw->phy.media_type) { 1134 case e1000_media_type_copper: 1135 /* Do the work to read phy */ 1136 e1000_check_for_link(hw); 1137 link_up = !hw->mac.get_link_status; 1138 break; 1139 1140 case e1000_media_type_fiber: 1141 e1000_check_for_link(hw); 1142 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1143 E1000_STATUS_LU); 1144 break; 1145 1146 case e1000_media_type_internal_serdes: 1147 e1000_check_for_link(hw); 1148 link_up = hw->mac.serdes_has_link; 1149 break; 1150 1151 default: 1152 break; 1153 } 1154 if (link_up || wait_to_complete == 0) 1155 break; 1156 rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL); 1157 } 1158 memset(&link, 0, sizeof(link)); 1159 1160 /* Now we check if a transition has happened */ 1161 if (link_up) { 1162 uint16_t duplex, speed; 1163 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1164 link.link_duplex = (duplex == FULL_DUPLEX) ? 1165 ETH_LINK_FULL_DUPLEX : 1166 ETH_LINK_HALF_DUPLEX; 1167 link.link_speed = speed; 1168 link.link_status = ETH_LINK_UP; 1169 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 1170 ETH_LINK_SPEED_FIXED); 1171 } else { 1172 link.link_speed = ETH_SPEED_NUM_NONE; 1173 link.link_duplex = ETH_LINK_HALF_DUPLEX; 1174 link.link_status = ETH_LINK_DOWN; 1175 link.link_autoneg = ETH_LINK_FIXED; 1176 } 1177 1178 return rte_eth_linkstatus_set(dev, &link); 1179 } 1180 1181 /* 1182 * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 1183 * For ASF and Pass Through versions of f/w this means 1184 * that the driver is loaded. For AMT version type f/w 1185 * this means that the network i/f is open. 1186 */ 1187 static void 1188 em_hw_control_acquire(struct e1000_hw *hw) 1189 { 1190 uint32_t ctrl_ext, swsm; 1191 1192 /* Let firmware know the driver has taken over */ 1193 if (hw->mac.type == e1000_82573) { 1194 swsm = E1000_READ_REG(hw, E1000_SWSM); 1195 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 1196 1197 } else { 1198 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1199 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 1200 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1201 } 1202 } 1203 1204 /* 1205 * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit. 1206 * For ASF and Pass Through versions of f/w this means that the 1207 * driver is no longer loaded. For AMT versions of the 1208 * f/w this means that the network i/f is closed. 1209 */ 1210 static void 1211 em_hw_control_release(struct e1000_hw *hw) 1212 { 1213 uint32_t ctrl_ext, swsm; 1214 1215 /* Let firmware taken over control of h/w */ 1216 if (hw->mac.type == e1000_82573) { 1217 swsm = E1000_READ_REG(hw, E1000_SWSM); 1218 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 1219 } else { 1220 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1221 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 1222 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1223 } 1224 } 1225 1226 /* 1227 * Bit of a misnomer, what this really means is 1228 * to enable OS management of the system... aka 1229 * to disable special hardware management features. 1230 */ 1231 static void 1232 em_init_manageability(struct e1000_hw *hw) 1233 { 1234 if (e1000_enable_mng_pass_thru(hw)) { 1235 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H); 1236 uint32_t manc = E1000_READ_REG(hw, E1000_MANC); 1237 1238 /* disable hardware interception of ARP */ 1239 manc &= ~(E1000_MANC_ARP_EN); 1240 1241 /* enable receiving management packets to the host */ 1242 manc |= E1000_MANC_EN_MNG2HOST; 1243 manc2h |= 1 << 5; /* Mng Port 623 */ 1244 manc2h |= 1 << 6; /* Mng Port 664 */ 1245 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h); 1246 E1000_WRITE_REG(hw, E1000_MANC, manc); 1247 } 1248 } 1249 1250 /* 1251 * Give control back to hardware management 1252 * controller if there is one. 1253 */ 1254 static void 1255 em_release_manageability(struct e1000_hw *hw) 1256 { 1257 uint32_t manc; 1258 1259 if (e1000_enable_mng_pass_thru(hw)) { 1260 manc = E1000_READ_REG(hw, E1000_MANC); 1261 1262 /* re-enable hardware interception of ARP */ 1263 manc |= E1000_MANC_ARP_EN; 1264 manc &= ~E1000_MANC_EN_MNG2HOST; 1265 1266 E1000_WRITE_REG(hw, E1000_MANC, manc); 1267 } 1268 } 1269 1270 static int 1271 eth_em_promiscuous_enable(struct rte_eth_dev *dev) 1272 { 1273 struct e1000_hw *hw = 1274 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1275 uint32_t rctl; 1276 1277 rctl = E1000_READ_REG(hw, E1000_RCTL); 1278 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1279 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1280 1281 return 0; 1282 } 1283 1284 static int 1285 eth_em_promiscuous_disable(struct rte_eth_dev *dev) 1286 { 1287 struct e1000_hw *hw = 1288 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1289 uint32_t rctl; 1290 1291 rctl = E1000_READ_REG(hw, E1000_RCTL); 1292 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP); 1293 if (dev->data->all_multicast == 1) 1294 rctl |= E1000_RCTL_MPE; 1295 else 1296 rctl &= (~E1000_RCTL_MPE); 1297 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1298 1299 return 0; 1300 } 1301 1302 static int 1303 eth_em_allmulticast_enable(struct rte_eth_dev *dev) 1304 { 1305 struct e1000_hw *hw = 1306 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1307 uint32_t rctl; 1308 1309 rctl = E1000_READ_REG(hw, E1000_RCTL); 1310 rctl |= E1000_RCTL_MPE; 1311 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1312 1313 return 0; 1314 } 1315 1316 static int 1317 eth_em_allmulticast_disable(struct rte_eth_dev *dev) 1318 { 1319 struct e1000_hw *hw = 1320 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1321 uint32_t rctl; 1322 1323 if (dev->data->promiscuous == 1) 1324 return 0; /* must remain in all_multicast mode */ 1325 rctl = E1000_READ_REG(hw, E1000_RCTL); 1326 rctl &= (~E1000_RCTL_MPE); 1327 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1328 1329 return 0; 1330 } 1331 1332 static int 1333 eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1334 { 1335 struct e1000_hw *hw = 1336 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1337 struct e1000_vfta * shadow_vfta = 1338 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1339 uint32_t vfta; 1340 uint32_t vid_idx; 1341 uint32_t vid_bit; 1342 1343 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) & 1344 E1000_VFTA_ENTRY_MASK); 1345 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK)); 1346 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx); 1347 if (on) 1348 vfta |= vid_bit; 1349 else 1350 vfta &= ~vid_bit; 1351 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta); 1352 1353 /* update local VFTA copy */ 1354 shadow_vfta->vfta[vid_idx] = vfta; 1355 1356 return 0; 1357 } 1358 1359 static void 1360 em_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1361 { 1362 struct e1000_hw *hw = 1363 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1364 uint32_t reg; 1365 1366 /* Filter Table Disable */ 1367 reg = E1000_READ_REG(hw, E1000_RCTL); 1368 reg &= ~E1000_RCTL_CFIEN; 1369 reg &= ~E1000_RCTL_VFE; 1370 E1000_WRITE_REG(hw, E1000_RCTL, reg); 1371 } 1372 1373 static void 1374 em_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1375 { 1376 struct e1000_hw *hw = 1377 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1378 struct e1000_vfta * shadow_vfta = 1379 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1380 uint32_t reg; 1381 int i; 1382 1383 /* Filter Table Enable, CFI not used for packet acceptance */ 1384 reg = E1000_READ_REG(hw, E1000_RCTL); 1385 reg &= ~E1000_RCTL_CFIEN; 1386 reg |= E1000_RCTL_VFE; 1387 E1000_WRITE_REG(hw, E1000_RCTL, reg); 1388 1389 /* restore vfta from local copy */ 1390 for (i = 0; i < IGB_VFTA_SIZE; i++) 1391 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]); 1392 } 1393 1394 static void 1395 em_vlan_hw_strip_disable(struct rte_eth_dev *dev) 1396 { 1397 struct e1000_hw *hw = 1398 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1399 uint32_t reg; 1400 1401 /* VLAN Mode Disable */ 1402 reg = E1000_READ_REG(hw, E1000_CTRL); 1403 reg &= ~E1000_CTRL_VME; 1404 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1405 1406 } 1407 1408 static void 1409 em_vlan_hw_strip_enable(struct rte_eth_dev *dev) 1410 { 1411 struct e1000_hw *hw = 1412 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1413 uint32_t reg; 1414 1415 /* VLAN Mode Enable */ 1416 reg = E1000_READ_REG(hw, E1000_CTRL); 1417 reg |= E1000_CTRL_VME; 1418 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1419 } 1420 1421 static int 1422 eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1423 { 1424 struct rte_eth_rxmode *rxmode; 1425 1426 rxmode = &dev->data->dev_conf.rxmode; 1427 if(mask & ETH_VLAN_STRIP_MASK){ 1428 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1429 em_vlan_hw_strip_enable(dev); 1430 else 1431 em_vlan_hw_strip_disable(dev); 1432 } 1433 1434 if(mask & ETH_VLAN_FILTER_MASK){ 1435 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1436 em_vlan_hw_filter_enable(dev); 1437 else 1438 em_vlan_hw_filter_disable(dev); 1439 } 1440 1441 return 0; 1442 } 1443 1444 /* 1445 * It enables the interrupt mask and then enable the interrupt. 1446 * 1447 * @param dev 1448 * Pointer to struct rte_eth_dev. 1449 * 1450 * @return 1451 * - On success, zero. 1452 * - On failure, a negative value. 1453 */ 1454 static int 1455 eth_em_interrupt_setup(struct rte_eth_dev *dev) 1456 { 1457 uint32_t regval; 1458 struct e1000_hw *hw = 1459 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1460 1461 /* clear interrupt */ 1462 E1000_READ_REG(hw, E1000_ICR); 1463 regval = E1000_READ_REG(hw, E1000_IMS); 1464 E1000_WRITE_REG(hw, E1000_IMS, 1465 regval | E1000_ICR_LSC | E1000_ICR_OTHER); 1466 return 0; 1467 } 1468 1469 /* 1470 * It clears the interrupt causes and enables the interrupt. 1471 * It will be called once only during nic initialized. 1472 * 1473 * @param dev 1474 * Pointer to struct rte_eth_dev. 1475 * 1476 * @return 1477 * - On success, zero. 1478 * - On failure, a negative value. 1479 */ 1480 static int 1481 eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev) 1482 { 1483 struct e1000_hw *hw = 1484 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1485 1486 E1000_READ_REG(hw, E1000_ICR); 1487 em_rxq_intr_enable(hw); 1488 return 0; 1489 } 1490 1491 /* 1492 * It enable receive packet interrupt. 1493 * @param hw 1494 * Pointer to struct e1000_hw 1495 * 1496 * @return 1497 */ 1498 static void 1499 em_rxq_intr_enable(struct e1000_hw *hw) 1500 { 1501 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0); 1502 E1000_WRITE_FLUSH(hw); 1503 } 1504 1505 /* 1506 * It disabled lsc interrupt. 1507 * @param hw 1508 * Pointer to struct e1000_hw 1509 * 1510 * @return 1511 */ 1512 static void 1513 em_lsc_intr_disable(struct e1000_hw *hw) 1514 { 1515 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC | E1000_IMS_OTHER); 1516 E1000_WRITE_FLUSH(hw); 1517 } 1518 1519 /* 1520 * It disabled receive packet interrupt. 1521 * @param hw 1522 * Pointer to struct e1000_hw 1523 * 1524 * @return 1525 */ 1526 static void 1527 em_rxq_intr_disable(struct e1000_hw *hw) 1528 { 1529 E1000_READ_REG(hw, E1000_ICR); 1530 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 1531 E1000_WRITE_FLUSH(hw); 1532 } 1533 1534 /* 1535 * It reads ICR and gets interrupt causes, check it and set a bit flag 1536 * to update link status. 1537 * 1538 * @param dev 1539 * Pointer to struct rte_eth_dev. 1540 * 1541 * @return 1542 * - On success, zero. 1543 * - On failure, a negative value. 1544 */ 1545 static int 1546 eth_em_interrupt_get_status(struct rte_eth_dev *dev) 1547 { 1548 uint32_t icr; 1549 struct e1000_hw *hw = 1550 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1551 struct e1000_interrupt *intr = 1552 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 1553 1554 /* read-on-clear nic registers here */ 1555 icr = E1000_READ_REG(hw, E1000_ICR); 1556 if (icr & E1000_ICR_LSC) { 1557 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE; 1558 } 1559 1560 return 0; 1561 } 1562 1563 /* 1564 * It executes link_update after knowing an interrupt is prsent. 1565 * 1566 * @param dev 1567 * Pointer to struct rte_eth_dev. 1568 * 1569 * @return 1570 * - On success, zero. 1571 * - On failure, a negative value. 1572 */ 1573 static int 1574 eth_em_interrupt_action(struct rte_eth_dev *dev, 1575 struct rte_intr_handle *intr_handle) 1576 { 1577 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 1578 struct e1000_hw *hw = 1579 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1580 struct e1000_interrupt *intr = 1581 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 1582 struct rte_eth_link link; 1583 int ret; 1584 1585 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE)) 1586 return -1; 1587 1588 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE; 1589 rte_intr_ack(intr_handle); 1590 1591 /* set get_link_status to check register later */ 1592 hw->mac.get_link_status = 1; 1593 ret = eth_em_link_update(dev, 0); 1594 1595 /* check if link has changed */ 1596 if (ret < 0) 1597 return 0; 1598 1599 rte_eth_linkstatus_get(dev, &link); 1600 1601 if (link.link_status) { 1602 PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s", 1603 dev->data->port_id, link.link_speed, 1604 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 1605 "full-duplex" : "half-duplex"); 1606 } else { 1607 PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id); 1608 } 1609 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 1610 pci_dev->addr.domain, pci_dev->addr.bus, 1611 pci_dev->addr.devid, pci_dev->addr.function); 1612 1613 return 0; 1614 } 1615 1616 /** 1617 * Interrupt handler which shall be registered at first. 1618 * 1619 * @param handle 1620 * Pointer to interrupt handle. 1621 * @param param 1622 * The address of parameter (struct rte_eth_dev *) regsitered before. 1623 * 1624 * @return 1625 * void 1626 */ 1627 static void 1628 eth_em_interrupt_handler(void *param) 1629 { 1630 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 1631 1632 eth_em_interrupt_get_status(dev); 1633 eth_em_interrupt_action(dev, dev->intr_handle); 1634 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1635 } 1636 1637 static int 1638 eth_em_led_on(struct rte_eth_dev *dev) 1639 { 1640 struct e1000_hw *hw; 1641 1642 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1643 return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP; 1644 } 1645 1646 static int 1647 eth_em_led_off(struct rte_eth_dev *dev) 1648 { 1649 struct e1000_hw *hw; 1650 1651 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1652 return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP; 1653 } 1654 1655 static int 1656 eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1657 { 1658 struct e1000_hw *hw; 1659 uint32_t ctrl; 1660 int tx_pause; 1661 int rx_pause; 1662 1663 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1664 fc_conf->pause_time = hw->fc.pause_time; 1665 fc_conf->high_water = hw->fc.high_water; 1666 fc_conf->low_water = hw->fc.low_water; 1667 fc_conf->send_xon = hw->fc.send_xon; 1668 fc_conf->autoneg = hw->mac.autoneg; 1669 1670 /* 1671 * Return rx_pause and tx_pause status according to actual setting of 1672 * the TFCE and RFCE bits in the CTRL register. 1673 */ 1674 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1675 if (ctrl & E1000_CTRL_TFCE) 1676 tx_pause = 1; 1677 else 1678 tx_pause = 0; 1679 1680 if (ctrl & E1000_CTRL_RFCE) 1681 rx_pause = 1; 1682 else 1683 rx_pause = 0; 1684 1685 if (rx_pause && tx_pause) 1686 fc_conf->mode = RTE_FC_FULL; 1687 else if (rx_pause) 1688 fc_conf->mode = RTE_FC_RX_PAUSE; 1689 else if (tx_pause) 1690 fc_conf->mode = RTE_FC_TX_PAUSE; 1691 else 1692 fc_conf->mode = RTE_FC_NONE; 1693 1694 return 0; 1695 } 1696 1697 static int 1698 eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1699 { 1700 struct e1000_hw *hw; 1701 int err; 1702 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = { 1703 e1000_fc_none, 1704 e1000_fc_rx_pause, 1705 e1000_fc_tx_pause, 1706 e1000_fc_full 1707 }; 1708 uint32_t rx_buf_size; 1709 uint32_t max_high_water; 1710 uint32_t rctl; 1711 1712 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1713 if (fc_conf->autoneg != hw->mac.autoneg) 1714 return -ENOTSUP; 1715 rx_buf_size = em_get_rx_buffer_size(hw); 1716 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 1717 1718 /* At least reserve one Ethernet frame for watermark */ 1719 max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN; 1720 if ((fc_conf->high_water > max_high_water) || 1721 (fc_conf->high_water < fc_conf->low_water)) { 1722 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value"); 1723 PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water); 1724 return -EINVAL; 1725 } 1726 1727 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode]; 1728 hw->fc.pause_time = fc_conf->pause_time; 1729 hw->fc.high_water = fc_conf->high_water; 1730 hw->fc.low_water = fc_conf->low_water; 1731 hw->fc.send_xon = fc_conf->send_xon; 1732 1733 err = e1000_setup_link_generic(hw); 1734 if (err == E1000_SUCCESS) { 1735 1736 /* check if we want to forward MAC frames - driver doesn't have native 1737 * capability to do that, so we'll write the registers ourselves */ 1738 1739 rctl = E1000_READ_REG(hw, E1000_RCTL); 1740 1741 /* set or clear MFLCN.PMCF bit depending on configuration */ 1742 if (fc_conf->mac_ctrl_frame_fwd != 0) 1743 rctl |= E1000_RCTL_PMCF; 1744 else 1745 rctl &= ~E1000_RCTL_PMCF; 1746 1747 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1748 E1000_WRITE_FLUSH(hw); 1749 1750 return 0; 1751 } 1752 1753 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err); 1754 return -EIO; 1755 } 1756 1757 static int 1758 eth_em_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 1759 uint32_t index, __rte_unused uint32_t pool) 1760 { 1761 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1762 1763 return e1000_rar_set(hw, mac_addr->addr_bytes, index); 1764 } 1765 1766 static void 1767 eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index) 1768 { 1769 uint8_t addr[RTE_ETHER_ADDR_LEN]; 1770 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1771 1772 memset(addr, 0, sizeof(addr)); 1773 1774 e1000_rar_set(hw, addr, index); 1775 } 1776 1777 static int 1778 eth_em_default_mac_addr_set(struct rte_eth_dev *dev, 1779 struct rte_ether_addr *addr) 1780 { 1781 eth_em_rar_clear(dev, 0); 1782 1783 return eth_em_rar_set(dev, (void *)addr, 0, 0); 1784 } 1785 1786 static int 1787 eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1788 { 1789 struct e1000_hw *hw; 1790 uint32_t frame_size; 1791 uint32_t rctl; 1792 1793 frame_size = mtu + E1000_ETH_OVERHEAD; 1794 1795 /* 1796 * If device is started, refuse mtu that requires the support of 1797 * scattered packets when this feature has not been enabled before. 1798 */ 1799 if (dev->data->dev_started && !dev->data->scattered_rx && 1800 frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { 1801 PMD_INIT_LOG(ERR, "Stop port first."); 1802 return -EINVAL; 1803 } 1804 1805 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1806 rctl = E1000_READ_REG(hw, E1000_RCTL); 1807 1808 /* switch to jumbo mode if needed */ 1809 if (mtu > RTE_ETHER_MTU) 1810 rctl |= E1000_RCTL_LPE; 1811 else 1812 rctl &= ~E1000_RCTL_LPE; 1813 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1814 1815 return 0; 1816 } 1817 1818 static int 1819 eth_em_set_mc_addr_list(struct rte_eth_dev *dev, 1820 struct rte_ether_addr *mc_addr_set, 1821 uint32_t nb_mc_addr) 1822 { 1823 struct e1000_hw *hw; 1824 1825 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1826 e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr); 1827 return 0; 1828 } 1829 1830 RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd); 1831 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map); 1832 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci"); 1833