1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #ifndef _E1000_ETHDEV_H_ 6 #define _E1000_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include <rte_flow.h> 11 #include <rte_time.h> 12 #include <rte_pci.h> 13 14 #define E1000_INTEL_VENDOR_ID 0x8086 15 16 /* need update link, bit flag */ 17 #define E1000_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) 18 #define E1000_FLAG_MAILBOX (uint32_t)(1 << 1) 19 20 /* 21 * Defines that were not part of e1000_hw.h as they are not used by the FreeBSD 22 * driver. 23 */ 24 #define E1000_ADVTXD_POPTS_TXSM 0x00000200 /* L4 Checksum offload request */ 25 #define E1000_ADVTXD_POPTS_IXSM 0x00000100 /* IP Checksum offload request */ 26 #define E1000_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE of Reserved */ 27 #define E1000_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */ 28 #define E1000_RXD_ERR_CKSUM_BIT 29 29 #define E1000_RXD_ERR_CKSUM_MSK 3 30 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */ 31 #define E1000_CTRL_EXT_EXTEND_VLAN (1<<26) /* EXTENDED VLAN */ 32 #define IGB_VFTA_SIZE 128 33 34 #define IGB_HKEY_MAX_INDEX 10 35 #define IGB_MAX_RX_QUEUE_NUM 8 36 #define IGB_MAX_RX_QUEUE_NUM_82576 16 37 38 #define E1000_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */ 39 #define E1000_SYN_FILTER_QUEUE 0x0000000E /* syn filter queue field */ 40 #define E1000_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field */ 41 #define E1000_RFCTL_SYNQFP 0x00080000 /* SYNQFP in RFCTL register */ 42 43 #define E1000_ETQF_ETHERTYPE 0x0000FFFF 44 #define E1000_ETQF_QUEUE 0x00070000 45 #define E1000_ETQF_QUEUE_SHIFT 16 46 #define E1000_MAX_ETQF_FILTERS 8 47 48 #define E1000_IMIR_DSTPORT 0x0000FFFF 49 #define E1000_IMIR_PRIORITY 0xE0000000 50 #define E1000_MAX_TTQF_FILTERS 8 51 #define E1000_2TUPLE_MAX_PRI 7 52 53 #define E1000_MAX_FLEX_FILTERS 8 54 #define E1000_MAX_FHFT 4 55 #define E1000_MAX_FHFT_EXT 4 56 #define E1000_FHFT_SIZE_IN_DWD 64 57 #define E1000_MAX_FLEX_FILTER_PRI 7 58 #define E1000_MAX_FLEX_FILTER_LEN 128 59 #define E1000_MAX_FLEX_FILTER_DWDS \ 60 (E1000_MAX_FLEX_FILTER_LEN / sizeof(uint32_t)) 61 #define E1000_FLEX_FILTERS_MASK_SIZE \ 62 (E1000_MAX_FLEX_FILTER_DWDS / 2) 63 #define E1000_FHFT_QUEUEING_LEN 0x0000007F 64 #define E1000_FHFT_QUEUEING_QUEUE 0x00000700 65 #define E1000_FHFT_QUEUEING_PRIO 0x00070000 66 #define E1000_FHFT_QUEUEING_OFFSET 0xFC 67 #define E1000_FHFT_QUEUEING_QUEUE_SHIFT 8 68 #define E1000_FHFT_QUEUEING_PRIO_SHIFT 16 69 #define E1000_WUFC_FLEX_HQ 0x00004000 70 71 #define E1000_SPQF_SRCPORT 0x0000FFFF 72 73 #define E1000_MAX_FTQF_FILTERS 8 74 #define E1000_FTQF_PROTOCOL_MASK 0x000000FF 75 #define E1000_FTQF_5TUPLE_MASK_SHIFT 28 76 #define E1000_FTQF_QUEUE_MASK 0x03ff0000 77 #define E1000_FTQF_QUEUE_SHIFT 16 78 #define E1000_FTQF_QUEUE_ENABLE 0x00000100 79 80 #define IGB_RSS_OFFLOAD_ALL ( \ 81 ETH_RSS_IPV4 | \ 82 ETH_RSS_NONFRAG_IPV4_TCP | \ 83 ETH_RSS_NONFRAG_IPV4_UDP | \ 84 ETH_RSS_IPV6 | \ 85 ETH_RSS_NONFRAG_IPV6_TCP | \ 86 ETH_RSS_NONFRAG_IPV6_UDP | \ 87 ETH_RSS_IPV6_EX | \ 88 ETH_RSS_IPV6_TCP_EX | \ 89 ETH_RSS_IPV6_UDP_EX) 90 91 /* 92 * The overhead from MTU to max frame size. 93 * Considering VLAN so a tag needs to be counted. 94 */ 95 #define E1000_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \ 96 VLAN_TAG_SIZE) 97 98 /* 99 * Maximum number of Ring Descriptors. 100 * 101 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring 102 * desscriptors should meet the following condition: 103 * (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0 104 */ 105 #define E1000_MIN_RING_DESC 32 106 #define E1000_MAX_RING_DESC 4096 107 108 /* 109 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 110 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. 111 * This will also optimize cache line size effect. 112 * H/W supports up to cache line size 128. 113 */ 114 #define E1000_ALIGN 128 115 116 #define IGB_RXD_ALIGN (E1000_ALIGN / sizeof(union e1000_adv_rx_desc)) 117 #define IGB_TXD_ALIGN (E1000_ALIGN / sizeof(union e1000_adv_tx_desc)) 118 119 #define EM_RXD_ALIGN (E1000_ALIGN / sizeof(struct e1000_rx_desc)) 120 #define EM_TXD_ALIGN (E1000_ALIGN / sizeof(struct e1000_data_desc)) 121 122 #define E1000_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 123 #define E1000_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 124 125 #define IGB_TX_MAX_SEG UINT8_MAX 126 #define IGB_TX_MAX_MTU_SEG UINT8_MAX 127 #define EM_TX_MAX_SEG UINT8_MAX 128 #define EM_TX_MAX_MTU_SEG UINT8_MAX 129 130 #define MAC_TYPE_FILTER_SUP(type) do {\ 131 if ((type) != e1000_82580 && (type) != e1000_i350 &&\ 132 (type) != e1000_82576 && (type) != e1000_i210 &&\ 133 (type) != e1000_i211)\ 134 return -ENOTSUP;\ 135 } while (0) 136 137 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\ 138 if ((type) != e1000_82580 && (type) != e1000_i350 &&\ 139 (type) != e1000_i210 && (type) != e1000_i211)\ 140 return -ENOTSUP; \ 141 } while (0) 142 143 /* structure for interrupt relative data */ 144 struct e1000_interrupt { 145 uint32_t flags; 146 uint32_t mask; 147 }; 148 149 /* local vfta copy */ 150 struct e1000_vfta { 151 uint32_t vfta[IGB_VFTA_SIZE]; 152 }; 153 154 /* 155 * VF data which used by PF host only 156 */ 157 #define E1000_MAX_VF_MC_ENTRIES 30 158 struct e1000_vf_info { 159 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN]; 160 uint16_t vf_mc_hashes[E1000_MAX_VF_MC_ENTRIES]; 161 uint16_t num_vf_mc_hashes; 162 uint16_t default_vf_vlan_id; 163 uint16_t vlans_enabled; 164 uint16_t pf_qos; 165 uint16_t vlan_count; 166 uint16_t tx_rate; 167 }; 168 169 TAILQ_HEAD(e1000_flex_filter_list, e1000_flex_filter); 170 171 struct e1000_flex_filter_info { 172 uint16_t len; 173 uint32_t dwords[E1000_MAX_FLEX_FILTER_DWDS]; /* flex bytes in dword. */ 174 /* if mask bit is 1b, do not compare corresponding byte in dwords. */ 175 uint8_t mask[E1000_FLEX_FILTERS_MASK_SIZE]; 176 uint8_t priority; 177 }; 178 179 /* Flex filter structure */ 180 struct e1000_flex_filter { 181 TAILQ_ENTRY(e1000_flex_filter) entries; 182 uint16_t index; /* index of flex filter */ 183 struct e1000_flex_filter_info filter_info; 184 uint16_t queue; /* rx queue assigned to */ 185 }; 186 187 TAILQ_HEAD(e1000_5tuple_filter_list, e1000_5tuple_filter); 188 TAILQ_HEAD(e1000_2tuple_filter_list, e1000_2tuple_filter); 189 190 struct e1000_5tuple_filter_info { 191 uint32_t dst_ip; 192 uint32_t src_ip; 193 uint16_t dst_port; 194 uint16_t src_port; 195 uint8_t proto; /* l4 protocol. */ 196 /* the packet matched above 5tuple and contain any set bit will hit this filter. */ 197 uint8_t tcp_flags; 198 uint8_t priority; /* seven levels (001b-111b), 111b is highest, 199 used when more than one filter matches. */ 200 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */ 201 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */ 202 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */ 203 src_port_mask:1, /* if mask is 1b, do not compare src port. */ 204 proto_mask:1; /* if mask is 1b, do not compare protocol. */ 205 }; 206 207 struct e1000_2tuple_filter_info { 208 uint16_t dst_port; 209 uint8_t proto; /* l4 protocol. */ 210 /* the packet matched above 2tuple and contain any set bit will hit this filter. */ 211 uint8_t tcp_flags; 212 uint8_t priority; /* seven levels (001b-111b), 111b is highest, 213 used when more than one filter matches. */ 214 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */ 215 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */ 216 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */ 217 src_port_mask:1, /* if mask is 1b, do not compare src port. */ 218 proto_mask:1; /* if mask is 1b, do not compare protocol. */ 219 }; 220 221 /* 5tuple filter structure */ 222 struct e1000_5tuple_filter { 223 TAILQ_ENTRY(e1000_5tuple_filter) entries; 224 uint16_t index; /* the index of 5tuple filter */ 225 struct e1000_5tuple_filter_info filter_info; 226 uint16_t queue; /* rx queue assigned to */ 227 }; 228 229 /* 2tuple filter structure */ 230 struct e1000_2tuple_filter { 231 TAILQ_ENTRY(e1000_2tuple_filter) entries; 232 uint16_t index; /* the index of 2tuple filter */ 233 struct e1000_2tuple_filter_info filter_info; 234 uint16_t queue; /* rx queue assigned to */ 235 }; 236 237 /* ethertype filter structure */ 238 struct igb_ethertype_filter { 239 uint16_t ethertype; 240 uint32_t etqf; 241 }; 242 243 struct igb_rte_flow_rss_conf { 244 struct rte_flow_action_rss conf; /**< RSS parameters. */ 245 uint8_t key[IGB_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */ 246 /* Queues indices to use. */ 247 uint16_t queue[IGB_MAX_RX_QUEUE_NUM_82576]; 248 }; 249 250 /* 251 * Structure to store filters'info. 252 */ 253 struct e1000_filter_info { 254 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */ 255 /* store used ethertype filters*/ 256 struct igb_ethertype_filter ethertype_filters[E1000_MAX_ETQF_FILTERS]; 257 uint8_t flex_mask; /* Bit mask for every used flex filter */ 258 struct e1000_flex_filter_list flex_list; 259 /* Bit mask for every used 5tuple filter */ 260 uint8_t fivetuple_mask; 261 struct e1000_5tuple_filter_list fivetuple_list; 262 /* Bit mask for every used 2tuple filter */ 263 uint8_t twotuple_mask; 264 struct e1000_2tuple_filter_list twotuple_list; 265 /* store the SYN filter info */ 266 uint32_t syn_info; 267 /* store the rss filter info */ 268 struct igb_rte_flow_rss_conf rss_info; 269 }; 270 271 /* 272 * Structure to store private data for each driver instance (for each port). 273 */ 274 struct e1000_adapter { 275 struct e1000_hw hw; 276 struct e1000_hw_stats stats; 277 struct e1000_interrupt intr; 278 struct e1000_vfta shadow_vfta; 279 struct e1000_vf_info *vfdata; 280 struct e1000_filter_info filter; 281 bool stopped; 282 struct rte_timecounter systime_tc; 283 struct rte_timecounter rx_tstamp_tc; 284 struct rte_timecounter tx_tstamp_tc; 285 }; 286 287 #define E1000_DEV_PRIVATE(adapter) \ 288 ((struct e1000_adapter *)adapter) 289 290 #define E1000_DEV_PRIVATE_TO_HW(adapter) \ 291 (&((struct e1000_adapter *)adapter)->hw) 292 293 #define E1000_DEV_PRIVATE_TO_STATS(adapter) \ 294 (&((struct e1000_adapter *)adapter)->stats) 295 296 #define E1000_DEV_PRIVATE_TO_INTR(adapter) \ 297 (&((struct e1000_adapter *)adapter)->intr) 298 299 #define E1000_DEV_PRIVATE_TO_VFTA(adapter) \ 300 (&((struct e1000_adapter *)adapter)->shadow_vfta) 301 302 #define E1000_DEV_PRIVATE_TO_P_VFDATA(adapter) \ 303 (&((struct e1000_adapter *)adapter)->vfdata) 304 305 #define E1000_DEV_PRIVATE_TO_FILTER_INFO(adapter) \ 306 (&((struct e1000_adapter *)adapter)->filter) 307 308 struct rte_flow { 309 enum rte_filter_type filter_type; 310 void *rule; 311 }; 312 313 /* ntuple filter list structure */ 314 struct igb_ntuple_filter_ele { 315 TAILQ_ENTRY(igb_ntuple_filter_ele) entries; 316 struct rte_eth_ntuple_filter filter_info; 317 }; 318 319 /* ethertype filter list structure */ 320 struct igb_ethertype_filter_ele { 321 TAILQ_ENTRY(igb_ethertype_filter_ele) entries; 322 struct rte_eth_ethertype_filter filter_info; 323 }; 324 325 /* syn filter list structure */ 326 struct igb_eth_syn_filter_ele { 327 TAILQ_ENTRY(igb_eth_syn_filter_ele) entries; 328 struct rte_eth_syn_filter filter_info; 329 }; 330 331 /* flex filter list structure */ 332 struct igb_flex_filter_ele { 333 TAILQ_ENTRY(igb_flex_filter_ele) entries; 334 struct rte_eth_flex_filter filter_info; 335 }; 336 337 /* rss filter list structure */ 338 struct igb_rss_conf_ele { 339 TAILQ_ENTRY(igb_rss_conf_ele) entries; 340 struct igb_rte_flow_rss_conf filter_info; 341 }; 342 343 /* igb_flow memory list structure */ 344 struct igb_flow_mem { 345 TAILQ_ENTRY(igb_flow_mem) entries; 346 struct rte_flow *flow; 347 struct rte_eth_dev *dev; 348 }; 349 350 TAILQ_HEAD(igb_ntuple_filter_list, igb_ntuple_filter_ele); 351 struct igb_ntuple_filter_list igb_filter_ntuple_list; 352 TAILQ_HEAD(igb_ethertype_filter_list, igb_ethertype_filter_ele); 353 struct igb_ethertype_filter_list igb_filter_ethertype_list; 354 TAILQ_HEAD(igb_syn_filter_list, igb_eth_syn_filter_ele); 355 struct igb_syn_filter_list igb_filter_syn_list; 356 TAILQ_HEAD(igb_flex_filter_list, igb_flex_filter_ele); 357 struct igb_flex_filter_list igb_filter_flex_list; 358 TAILQ_HEAD(igb_rss_filter_list, igb_rss_conf_ele); 359 struct igb_rss_filter_list igb_filter_rss_list; 360 TAILQ_HEAD(igb_flow_mem_list, igb_flow_mem); 361 struct igb_flow_mem_list igb_flow_list; 362 363 extern const struct rte_flow_ops igb_flow_ops; 364 365 /* 366 * RX/TX IGB function prototypes 367 */ 368 void eth_igb_tx_queue_release(void *txq); 369 void eth_igb_rx_queue_release(void *rxq); 370 void igb_dev_clear_queues(struct rte_eth_dev *dev); 371 void igb_dev_free_queues(struct rte_eth_dev *dev); 372 373 uint64_t igb_get_rx_port_offloads_capa(struct rte_eth_dev *dev); 374 uint64_t igb_get_rx_queue_offloads_capa(struct rte_eth_dev *dev); 375 376 int eth_igb_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 377 uint16_t nb_rx_desc, unsigned int socket_id, 378 const struct rte_eth_rxconf *rx_conf, 379 struct rte_mempool *mb_pool); 380 381 uint32_t eth_igb_rx_queue_count(struct rte_eth_dev *dev, 382 uint16_t rx_queue_id); 383 384 int eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset); 385 386 int eth_igb_rx_descriptor_status(void *rx_queue, uint16_t offset); 387 int eth_igb_tx_descriptor_status(void *tx_queue, uint16_t offset); 388 389 uint64_t igb_get_tx_port_offloads_capa(struct rte_eth_dev *dev); 390 uint64_t igb_get_tx_queue_offloads_capa(struct rte_eth_dev *dev); 391 392 int eth_igb_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 393 uint16_t nb_tx_desc, unsigned int socket_id, 394 const struct rte_eth_txconf *tx_conf); 395 396 int eth_igb_tx_done_cleanup(void *txq, uint32_t free_cnt); 397 398 int eth_igb_rx_init(struct rte_eth_dev *dev); 399 400 void eth_igb_tx_init(struct rte_eth_dev *dev); 401 402 uint16_t eth_igb_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts, 403 uint16_t nb_pkts); 404 405 uint16_t eth_igb_prep_pkts(void *txq, struct rte_mbuf **tx_pkts, 406 uint16_t nb_pkts); 407 408 uint16_t eth_igb_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts, 409 uint16_t nb_pkts); 410 411 uint16_t eth_igb_recv_scattered_pkts(void *rxq, 412 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 413 414 int eth_igb_rss_hash_update(struct rte_eth_dev *dev, 415 struct rte_eth_rss_conf *rss_conf); 416 417 int eth_igb_rss_hash_conf_get(struct rte_eth_dev *dev, 418 struct rte_eth_rss_conf *rss_conf); 419 420 int eth_igbvf_rx_init(struct rte_eth_dev *dev); 421 422 void eth_igbvf_tx_init(struct rte_eth_dev *dev); 423 424 /* 425 * misc function prototypes 426 */ 427 void igb_pf_host_init(struct rte_eth_dev *eth_dev); 428 429 void igb_pf_mbx_process(struct rte_eth_dev *eth_dev); 430 431 int igb_pf_host_configure(struct rte_eth_dev *eth_dev); 432 433 void igb_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 434 struct rte_eth_rxq_info *qinfo); 435 436 void igb_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 437 struct rte_eth_txq_info *qinfo); 438 439 uint32_t em_get_max_pktlen(struct rte_eth_dev *dev); 440 441 /* 442 * RX/TX EM function prototypes 443 */ 444 void eth_em_tx_queue_release(void *txq); 445 void eth_em_rx_queue_release(void *rxq); 446 447 void em_dev_clear_queues(struct rte_eth_dev *dev); 448 void em_dev_free_queues(struct rte_eth_dev *dev); 449 450 uint64_t em_get_rx_port_offloads_capa(struct rte_eth_dev *dev); 451 uint64_t em_get_rx_queue_offloads_capa(struct rte_eth_dev *dev); 452 453 int eth_em_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 454 uint16_t nb_rx_desc, unsigned int socket_id, 455 const struct rte_eth_rxconf *rx_conf, 456 struct rte_mempool *mb_pool); 457 458 uint32_t eth_em_rx_queue_count(struct rte_eth_dev *dev, 459 uint16_t rx_queue_id); 460 461 int eth_em_rx_descriptor_done(void *rx_queue, uint16_t offset); 462 463 int eth_em_rx_descriptor_status(void *rx_queue, uint16_t offset); 464 int eth_em_tx_descriptor_status(void *tx_queue, uint16_t offset); 465 466 uint64_t em_get_tx_port_offloads_capa(struct rte_eth_dev *dev); 467 uint64_t em_get_tx_queue_offloads_capa(struct rte_eth_dev *dev); 468 469 int eth_em_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 470 uint16_t nb_tx_desc, unsigned int socket_id, 471 const struct rte_eth_txconf *tx_conf); 472 473 int eth_em_rx_init(struct rte_eth_dev *dev); 474 475 void eth_em_tx_init(struct rte_eth_dev *dev); 476 477 uint16_t eth_em_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 478 uint16_t nb_pkts); 479 480 uint16_t eth_em_prep_pkts(void *txq, struct rte_mbuf **tx_pkts, 481 uint16_t nb_pkts); 482 483 uint16_t eth_em_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 484 uint16_t nb_pkts); 485 486 uint16_t eth_em_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 487 uint16_t nb_pkts); 488 489 void em_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 490 struct rte_eth_rxq_info *qinfo); 491 492 void em_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 493 struct rte_eth_txq_info *qinfo); 494 495 void igb_pf_host_uninit(struct rte_eth_dev *dev); 496 497 void igb_filterlist_flush(struct rte_eth_dev *dev); 498 int igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev, 499 struct e1000_5tuple_filter *filter); 500 int igb_delete_2tuple_filter(struct rte_eth_dev *dev, 501 struct e1000_2tuple_filter *filter); 502 void igb_remove_flex_filter(struct rte_eth_dev *dev, 503 struct e1000_flex_filter *filter); 504 int igb_ethertype_filter_remove(struct e1000_filter_info *filter_info, 505 uint8_t idx); 506 int igb_add_del_ntuple_filter(struct rte_eth_dev *dev, 507 struct rte_eth_ntuple_filter *ntuple_filter, bool add); 508 int igb_add_del_ethertype_filter(struct rte_eth_dev *dev, 509 struct rte_eth_ethertype_filter *filter, 510 bool add); 511 int eth_igb_syn_filter_set(struct rte_eth_dev *dev, 512 struct rte_eth_syn_filter *filter, 513 bool add); 514 int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev, 515 struct rte_eth_flex_filter *filter, 516 bool add); 517 int igb_rss_conf_init(struct rte_eth_dev *dev, 518 struct igb_rte_flow_rss_conf *out, 519 const struct rte_flow_action_rss *in); 520 int igb_action_rss_same(const struct rte_flow_action_rss *comp, 521 const struct rte_flow_action_rss *with); 522 int igb_config_rss_filter(struct rte_eth_dev *dev, 523 struct igb_rte_flow_rss_conf *conf, 524 bool add); 525 526 #endif /* _E1000_ETHDEV_H_ */ 527