1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2015 Intel Corporation 3 */ 4 5 #ifndef _E1000_ETHDEV_H_ 6 #define _E1000_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include <rte_flow.h> 11 #include <rte_time.h> 12 #include <rte_pci.h> 13 14 #define E1000_INTEL_VENDOR_ID 0x8086 15 16 /* need update link, bit flag */ 17 #define E1000_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) 18 #define E1000_FLAG_MAILBOX (uint32_t)(1 << 1) 19 20 /* 21 * Defines that were not part of e1000_hw.h as they are not used by the FreeBSD 22 * driver. 23 */ 24 #define E1000_ADVTXD_POPTS_TXSM 0x00000200 /* L4 Checksum offload request */ 25 #define E1000_ADVTXD_POPTS_IXSM 0x00000100 /* IP Checksum offload request */ 26 #define E1000_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE of Reserved */ 27 #define E1000_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */ 28 #define E1000_RXD_ERR_CKSUM_BIT 29 29 #define E1000_RXD_ERR_CKSUM_MSK 3 30 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */ 31 #define E1000_CTRL_EXT_EXTEND_VLAN (1<<26) /* EXTENDED VLAN */ 32 #define IGB_VFTA_SIZE 128 33 34 #define IGB_HKEY_MAX_INDEX 10 35 #define IGB_MAX_RX_QUEUE_NUM 8 36 #define IGB_MAX_RX_QUEUE_NUM_82576 16 37 38 #define E1000_I219_MAX_RX_QUEUE_NUM 2 39 #define E1000_I219_MAX_TX_QUEUE_NUM 2 40 41 #define E1000_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */ 42 #define E1000_SYN_FILTER_QUEUE 0x0000000E /* syn filter queue field */ 43 #define E1000_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field */ 44 #define E1000_RFCTL_SYNQFP 0x00080000 /* SYNQFP in RFCTL register */ 45 46 #define E1000_ETQF_ETHERTYPE 0x0000FFFF 47 #define E1000_ETQF_QUEUE 0x00070000 48 #define E1000_ETQF_QUEUE_SHIFT 16 49 #define E1000_MAX_ETQF_FILTERS 8 50 51 #define E1000_IMIR_DSTPORT 0x0000FFFF 52 #define E1000_IMIR_PRIORITY 0xE0000000 53 #define E1000_MAX_TTQF_FILTERS 8 54 #define E1000_2TUPLE_MAX_PRI 7 55 56 #define E1000_MAX_FLEX_FILTERS 8 57 #define E1000_MAX_FHFT 4 58 #define E1000_MAX_FHFT_EXT 4 59 #define E1000_FHFT_SIZE_IN_DWD 64 60 #define E1000_MAX_FLEX_FILTER_PRI 7 61 #define E1000_MAX_FLEX_FILTER_LEN 128 62 #define E1000_MAX_FLEX_FILTER_DWDS \ 63 (E1000_MAX_FLEX_FILTER_LEN / sizeof(uint32_t)) 64 #define E1000_FLEX_FILTERS_MASK_SIZE \ 65 (E1000_MAX_FLEX_FILTER_DWDS / 2) 66 #define E1000_FHFT_QUEUEING_LEN 0x0000007F 67 #define E1000_FHFT_QUEUEING_QUEUE 0x00000700 68 #define E1000_FHFT_QUEUEING_PRIO 0x00070000 69 #define E1000_FHFT_QUEUEING_OFFSET 0xFC 70 #define E1000_FHFT_QUEUEING_QUEUE_SHIFT 8 71 #define E1000_FHFT_QUEUEING_PRIO_SHIFT 16 72 #define E1000_WUFC_FLEX_HQ 0x00004000 73 74 #define E1000_SPQF_SRCPORT 0x0000FFFF 75 76 #define E1000_MAX_FTQF_FILTERS 8 77 #define E1000_FTQF_PROTOCOL_MASK 0x000000FF 78 #define E1000_FTQF_5TUPLE_MASK_SHIFT 28 79 #define E1000_FTQF_QUEUE_MASK 0x03ff0000 80 #define E1000_FTQF_QUEUE_SHIFT 16 81 #define E1000_FTQF_QUEUE_ENABLE 0x00000100 82 83 #define IGB_RSS_OFFLOAD_ALL ( \ 84 ETH_RSS_IPV4 | \ 85 ETH_RSS_NONFRAG_IPV4_TCP | \ 86 ETH_RSS_NONFRAG_IPV4_UDP | \ 87 ETH_RSS_IPV6 | \ 88 ETH_RSS_NONFRAG_IPV6_TCP | \ 89 ETH_RSS_NONFRAG_IPV6_UDP | \ 90 ETH_RSS_IPV6_EX | \ 91 ETH_RSS_IPV6_TCP_EX | \ 92 ETH_RSS_IPV6_UDP_EX) 93 94 /* 95 * The overhead from MTU to max frame size. 96 * Considering VLAN so a tag needs to be counted. 97 */ 98 #define E1000_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \ 99 VLAN_TAG_SIZE) 100 #define E1000_ETH_MAX_LEN (RTE_ETHER_MTU + E1000_ETH_OVERHEAD) 101 /* 102 * Maximum number of Ring Descriptors. 103 * 104 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring 105 * desscriptors should meet the following condition: 106 * (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0 107 */ 108 #define E1000_MIN_RING_DESC 32 109 #define E1000_MAX_RING_DESC 4096 110 111 /* 112 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 113 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. 114 * This will also optimize cache line size effect. 115 * H/W supports up to cache line size 128. 116 */ 117 #define E1000_ALIGN 128 118 119 #define IGB_RXD_ALIGN (E1000_ALIGN / sizeof(union e1000_adv_rx_desc)) 120 #define IGB_TXD_ALIGN (E1000_ALIGN / sizeof(union e1000_adv_tx_desc)) 121 122 #define EM_RXD_ALIGN (E1000_ALIGN / sizeof(struct e1000_rx_desc)) 123 #define EM_TXD_ALIGN (E1000_ALIGN / sizeof(struct e1000_data_desc)) 124 125 #define E1000_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 126 #define E1000_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 127 128 #define IGB_TX_MAX_SEG UINT8_MAX 129 #define IGB_TX_MAX_MTU_SEG UINT8_MAX 130 #define EM_TX_MAX_SEG UINT8_MAX 131 #define EM_TX_MAX_MTU_SEG UINT8_MAX 132 133 #define MAC_TYPE_FILTER_SUP(type) do {\ 134 if ((type) != e1000_82580 && (type) != e1000_i350 &&\ 135 (type) != e1000_82576 && (type) != e1000_i210 &&\ 136 (type) != e1000_i211)\ 137 return -ENOTSUP;\ 138 } while (0) 139 140 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\ 141 if ((type) != e1000_82580 && (type) != e1000_i350 &&\ 142 (type) != e1000_i210 && (type) != e1000_i211)\ 143 return -ENOTSUP; \ 144 } while (0) 145 146 /* structure for interrupt relative data */ 147 struct e1000_interrupt { 148 uint32_t flags; 149 uint32_t mask; 150 }; 151 152 /* local vfta copy */ 153 struct e1000_vfta { 154 uint32_t vfta[IGB_VFTA_SIZE]; 155 }; 156 157 /* 158 * VF data which used by PF host only 159 */ 160 #define E1000_MAX_VF_MC_ENTRIES 30 161 struct e1000_vf_info { 162 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN]; 163 uint16_t vf_mc_hashes[E1000_MAX_VF_MC_ENTRIES]; 164 uint16_t num_vf_mc_hashes; 165 uint16_t default_vf_vlan_id; 166 uint16_t vlans_enabled; 167 uint16_t pf_qos; 168 uint16_t vlan_count; 169 uint16_t tx_rate; 170 }; 171 172 TAILQ_HEAD(e1000_flex_filter_list, e1000_flex_filter); 173 174 struct e1000_flex_filter_info { 175 uint16_t len; 176 uint32_t dwords[E1000_MAX_FLEX_FILTER_DWDS]; /* flex bytes in dword. */ 177 /* if mask bit is 1b, do not compare corresponding byte in dwords. */ 178 uint8_t mask[E1000_FLEX_FILTERS_MASK_SIZE]; 179 uint8_t priority; 180 }; 181 182 /* Flex filter structure */ 183 struct e1000_flex_filter { 184 TAILQ_ENTRY(e1000_flex_filter) entries; 185 uint16_t index; /* index of flex filter */ 186 struct e1000_flex_filter_info filter_info; 187 uint16_t queue; /* rx queue assigned to */ 188 }; 189 190 TAILQ_HEAD(e1000_5tuple_filter_list, e1000_5tuple_filter); 191 TAILQ_HEAD(e1000_2tuple_filter_list, e1000_2tuple_filter); 192 193 struct e1000_5tuple_filter_info { 194 uint32_t dst_ip; 195 uint32_t src_ip; 196 uint16_t dst_port; 197 uint16_t src_port; 198 uint8_t proto; /* l4 protocol. */ 199 /* the packet matched above 5tuple and contain any set bit will hit this filter. */ 200 uint8_t tcp_flags; 201 uint8_t priority; /* seven levels (001b-111b), 111b is highest, 202 used when more than one filter matches. */ 203 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */ 204 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */ 205 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */ 206 src_port_mask:1, /* if mask is 1b, do not compare src port. */ 207 proto_mask:1; /* if mask is 1b, do not compare protocol. */ 208 }; 209 210 struct e1000_2tuple_filter_info { 211 uint16_t dst_port; 212 uint8_t proto; /* l4 protocol. */ 213 /* the packet matched above 2tuple and contain any set bit will hit this filter. */ 214 uint8_t tcp_flags; 215 uint8_t priority; /* seven levels (001b-111b), 111b is highest, 216 used when more than one filter matches. */ 217 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */ 218 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */ 219 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */ 220 src_port_mask:1, /* if mask is 1b, do not compare src port. */ 221 proto_mask:1; /* if mask is 1b, do not compare protocol. */ 222 }; 223 224 /* 5tuple filter structure */ 225 struct e1000_5tuple_filter { 226 TAILQ_ENTRY(e1000_5tuple_filter) entries; 227 uint16_t index; /* the index of 5tuple filter */ 228 struct e1000_5tuple_filter_info filter_info; 229 uint16_t queue; /* rx queue assigned to */ 230 }; 231 232 /* 2tuple filter structure */ 233 struct e1000_2tuple_filter { 234 TAILQ_ENTRY(e1000_2tuple_filter) entries; 235 uint16_t index; /* the index of 2tuple filter */ 236 struct e1000_2tuple_filter_info filter_info; 237 uint16_t queue; /* rx queue assigned to */ 238 }; 239 240 /* ethertype filter structure */ 241 struct igb_ethertype_filter { 242 uint16_t ethertype; 243 uint32_t etqf; 244 }; 245 246 struct igb_rte_flow_rss_conf { 247 struct rte_flow_action_rss conf; /**< RSS parameters. */ 248 uint8_t key[IGB_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */ 249 /* Queues indices to use. */ 250 uint16_t queue[IGB_MAX_RX_QUEUE_NUM_82576]; 251 }; 252 253 /* 254 * Structure to store filters'info. 255 */ 256 struct e1000_filter_info { 257 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */ 258 /* store used ethertype filters*/ 259 struct igb_ethertype_filter ethertype_filters[E1000_MAX_ETQF_FILTERS]; 260 uint8_t flex_mask; /* Bit mask for every used flex filter */ 261 struct e1000_flex_filter_list flex_list; 262 /* Bit mask for every used 5tuple filter */ 263 uint8_t fivetuple_mask; 264 struct e1000_5tuple_filter_list fivetuple_list; 265 /* Bit mask for every used 2tuple filter */ 266 uint8_t twotuple_mask; 267 struct e1000_2tuple_filter_list twotuple_list; 268 /* store the SYN filter info */ 269 uint32_t syn_info; 270 /* store the rss filter info */ 271 struct igb_rte_flow_rss_conf rss_info; 272 }; 273 274 /* 275 * Structure to store private data for each driver instance (for each port). 276 */ 277 struct e1000_adapter { 278 struct e1000_hw hw; 279 struct e1000_hw_stats stats; 280 struct e1000_interrupt intr; 281 struct e1000_vfta shadow_vfta; 282 struct e1000_vf_info *vfdata; 283 struct e1000_filter_info filter; 284 bool stopped; 285 struct rte_timecounter systime_tc; 286 struct rte_timecounter rx_tstamp_tc; 287 struct rte_timecounter tx_tstamp_tc; 288 }; 289 290 #define E1000_DEV_PRIVATE(adapter) \ 291 ((struct e1000_adapter *)adapter) 292 293 #define E1000_DEV_PRIVATE_TO_HW(adapter) \ 294 (&((struct e1000_adapter *)adapter)->hw) 295 296 #define E1000_DEV_PRIVATE_TO_STATS(adapter) \ 297 (&((struct e1000_adapter *)adapter)->stats) 298 299 #define E1000_DEV_PRIVATE_TO_INTR(adapter) \ 300 (&((struct e1000_adapter *)adapter)->intr) 301 302 #define E1000_DEV_PRIVATE_TO_VFTA(adapter) \ 303 (&((struct e1000_adapter *)adapter)->shadow_vfta) 304 305 #define E1000_DEV_PRIVATE_TO_P_VFDATA(adapter) \ 306 (&((struct e1000_adapter *)adapter)->vfdata) 307 308 #define E1000_DEV_PRIVATE_TO_FILTER_INFO(adapter) \ 309 (&((struct e1000_adapter *)adapter)->filter) 310 311 struct rte_flow { 312 enum rte_filter_type filter_type; 313 void *rule; 314 }; 315 316 /* ntuple filter list structure */ 317 struct igb_ntuple_filter_ele { 318 TAILQ_ENTRY(igb_ntuple_filter_ele) entries; 319 struct rte_eth_ntuple_filter filter_info; 320 }; 321 322 /* ethertype filter list structure */ 323 struct igb_ethertype_filter_ele { 324 TAILQ_ENTRY(igb_ethertype_filter_ele) entries; 325 struct rte_eth_ethertype_filter filter_info; 326 }; 327 328 /* syn filter list structure */ 329 struct igb_eth_syn_filter_ele { 330 TAILQ_ENTRY(igb_eth_syn_filter_ele) entries; 331 struct rte_eth_syn_filter filter_info; 332 }; 333 334 #define IGB_FLEX_FILTER_MAXLEN 128 /**< bytes to use in flex filter. */ 335 #define IGB_FLEX_FILTER_MASK_SIZE \ 336 (RTE_ALIGN(IGB_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT) 337 /**< mask bytes in flex filter. */ 338 339 /** 340 * A structure used to define the flex filter entry 341 * to support RTE_ETH_FILTER_FLEXIBLE data representation. 342 */ 343 struct igb_flex_filter { 344 uint16_t len; 345 uint8_t bytes[IGB_FLEX_FILTER_MAXLEN]; /**< flex bytes in big endian. */ 346 uint8_t mask[IGB_FLEX_FILTER_MASK_SIZE]; 347 /**< if mask bit is 1b, do not compare corresponding byte. */ 348 uint8_t priority; 349 uint16_t queue; /**< Queue assigned to when match. */ 350 }; 351 352 /* flex filter list structure */ 353 struct igb_flex_filter_ele { 354 TAILQ_ENTRY(igb_flex_filter_ele) entries; 355 struct igb_flex_filter filter_info; 356 }; 357 358 /* rss filter list structure */ 359 struct igb_rss_conf_ele { 360 TAILQ_ENTRY(igb_rss_conf_ele) entries; 361 struct igb_rte_flow_rss_conf filter_info; 362 }; 363 364 /* igb_flow memory list structure */ 365 struct igb_flow_mem { 366 TAILQ_ENTRY(igb_flow_mem) entries; 367 struct rte_flow *flow; 368 struct rte_eth_dev *dev; 369 }; 370 371 TAILQ_HEAD(igb_ntuple_filter_list, igb_ntuple_filter_ele); 372 extern struct igb_ntuple_filter_list igb_filter_ntuple_list; 373 TAILQ_HEAD(igb_ethertype_filter_list, igb_ethertype_filter_ele); 374 extern struct igb_ethertype_filter_list igb_filter_ethertype_list; 375 TAILQ_HEAD(igb_syn_filter_list, igb_eth_syn_filter_ele); 376 extern struct igb_syn_filter_list igb_filter_syn_list; 377 TAILQ_HEAD(igb_flex_filter_list, igb_flex_filter_ele); 378 extern struct igb_flex_filter_list igb_filter_flex_list; 379 TAILQ_HEAD(igb_rss_filter_list, igb_rss_conf_ele); 380 extern struct igb_rss_filter_list igb_filter_rss_list; 381 TAILQ_HEAD(igb_flow_mem_list, igb_flow_mem); 382 extern struct igb_flow_mem_list igb_flow_list; 383 384 extern const struct rte_flow_ops igb_flow_ops; 385 386 /* 387 * RX/TX IGB function prototypes 388 */ 389 void eth_igb_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid); 390 void eth_igb_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid); 391 void igb_dev_clear_queues(struct rte_eth_dev *dev); 392 void igb_dev_free_queues(struct rte_eth_dev *dev); 393 394 uint64_t igb_get_rx_port_offloads_capa(struct rte_eth_dev *dev); 395 uint64_t igb_get_rx_queue_offloads_capa(struct rte_eth_dev *dev); 396 397 int eth_igb_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 398 uint16_t nb_rx_desc, unsigned int socket_id, 399 const struct rte_eth_rxconf *rx_conf, 400 struct rte_mempool *mb_pool); 401 402 uint32_t eth_igb_rx_queue_count(struct rte_eth_dev *dev, 403 uint16_t rx_queue_id); 404 405 int eth_igb_rx_descriptor_status(void *rx_queue, uint16_t offset); 406 int eth_igb_tx_descriptor_status(void *tx_queue, uint16_t offset); 407 408 uint64_t igb_get_tx_port_offloads_capa(struct rte_eth_dev *dev); 409 uint64_t igb_get_tx_queue_offloads_capa(struct rte_eth_dev *dev); 410 411 int eth_igb_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 412 uint16_t nb_tx_desc, unsigned int socket_id, 413 const struct rte_eth_txconf *tx_conf); 414 415 int eth_igb_tx_done_cleanup(void *txq, uint32_t free_cnt); 416 417 int eth_igb_rx_init(struct rte_eth_dev *dev); 418 419 void eth_igb_tx_init(struct rte_eth_dev *dev); 420 421 uint16_t eth_igb_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts, 422 uint16_t nb_pkts); 423 424 uint16_t eth_igb_prep_pkts(void *txq, struct rte_mbuf **tx_pkts, 425 uint16_t nb_pkts); 426 427 uint16_t eth_igb_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts, 428 uint16_t nb_pkts); 429 430 uint16_t eth_igb_recv_scattered_pkts(void *rxq, 431 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 432 433 int eth_igb_rss_hash_update(struct rte_eth_dev *dev, 434 struct rte_eth_rss_conf *rss_conf); 435 436 int eth_igb_rss_hash_conf_get(struct rte_eth_dev *dev, 437 struct rte_eth_rss_conf *rss_conf); 438 439 int eth_igbvf_rx_init(struct rte_eth_dev *dev); 440 441 void eth_igbvf_tx_init(struct rte_eth_dev *dev); 442 443 /* 444 * misc function prototypes 445 */ 446 void igb_pf_host_init(struct rte_eth_dev *eth_dev); 447 448 void igb_pf_mbx_process(struct rte_eth_dev *eth_dev); 449 450 int igb_pf_host_configure(struct rte_eth_dev *eth_dev); 451 452 void igb_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 453 struct rte_eth_rxq_info *qinfo); 454 455 void igb_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 456 struct rte_eth_txq_info *qinfo); 457 458 uint32_t em_get_max_pktlen(struct rte_eth_dev *dev); 459 460 /* 461 * RX/TX EM function prototypes 462 */ 463 void eth_em_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid); 464 void eth_em_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid); 465 466 void em_dev_clear_queues(struct rte_eth_dev *dev); 467 void em_dev_free_queues(struct rte_eth_dev *dev); 468 469 uint64_t em_get_rx_port_offloads_capa(struct rte_eth_dev *dev); 470 uint64_t em_get_rx_queue_offloads_capa(struct rte_eth_dev *dev); 471 472 int eth_em_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 473 uint16_t nb_rx_desc, unsigned int socket_id, 474 const struct rte_eth_rxconf *rx_conf, 475 struct rte_mempool *mb_pool); 476 477 uint32_t eth_em_rx_queue_count(struct rte_eth_dev *dev, 478 uint16_t rx_queue_id); 479 480 int eth_em_rx_descriptor_status(void *rx_queue, uint16_t offset); 481 int eth_em_tx_descriptor_status(void *tx_queue, uint16_t offset); 482 483 uint64_t em_get_tx_port_offloads_capa(struct rte_eth_dev *dev); 484 uint64_t em_get_tx_queue_offloads_capa(struct rte_eth_dev *dev); 485 486 int eth_em_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 487 uint16_t nb_tx_desc, unsigned int socket_id, 488 const struct rte_eth_txconf *tx_conf); 489 490 int eth_em_rx_init(struct rte_eth_dev *dev); 491 492 void eth_em_tx_init(struct rte_eth_dev *dev); 493 494 uint16_t eth_em_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 495 uint16_t nb_pkts); 496 497 uint16_t eth_em_prep_pkts(void *txq, struct rte_mbuf **tx_pkts, 498 uint16_t nb_pkts); 499 500 uint16_t eth_em_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 501 uint16_t nb_pkts); 502 503 uint16_t eth_em_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 504 uint16_t nb_pkts); 505 506 void em_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 507 struct rte_eth_rxq_info *qinfo); 508 509 void em_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 510 struct rte_eth_txq_info *qinfo); 511 512 void igb_pf_host_uninit(struct rte_eth_dev *dev); 513 514 void igb_filterlist_flush(struct rte_eth_dev *dev); 515 int igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev, 516 struct e1000_5tuple_filter *filter); 517 int igb_delete_2tuple_filter(struct rte_eth_dev *dev, 518 struct e1000_2tuple_filter *filter); 519 void igb_remove_flex_filter(struct rte_eth_dev *dev, 520 struct e1000_flex_filter *filter); 521 int igb_ethertype_filter_remove(struct e1000_filter_info *filter_info, 522 uint8_t idx); 523 int igb_add_del_ntuple_filter(struct rte_eth_dev *dev, 524 struct rte_eth_ntuple_filter *ntuple_filter, bool add); 525 int igb_add_del_ethertype_filter(struct rte_eth_dev *dev, 526 struct rte_eth_ethertype_filter *filter, 527 bool add); 528 int eth_igb_syn_filter_set(struct rte_eth_dev *dev, 529 struct rte_eth_syn_filter *filter, 530 bool add); 531 int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev, 532 struct igb_flex_filter *filter, 533 bool add); 534 int igb_rss_conf_init(struct rte_eth_dev *dev, 535 struct igb_rte_flow_rss_conf *out, 536 const struct rte_flow_action_rss *in); 537 int igb_action_rss_same(const struct rte_flow_action_rss *comp, 538 const struct rte_flow_action_rss *with); 539 int igb_config_rss_filter(struct rte_eth_dev *dev, 540 struct igb_rte_flow_rss_conf *conf, 541 bool add); 542 void em_flush_desc_rings(struct rte_eth_dev *dev); 543 544 #endif /* _E1000_ETHDEV_H_ */ 545