1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2020 Intel Corporation 3 */ 4 5 #include "e1000_api.h" 6 7 STATIC s32 e1000_wait_autoneg(struct e1000_hw *hw); 8 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 9 u16 *data, bool read, bool page_set); 10 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page); 11 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 12 u16 *data, bool read); 13 14 /* Cable length tables */ 15 STATIC const u16 e1000_m88_cable_length_table[] = { 16 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 17 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 18 (sizeof(e1000_m88_cable_length_table) / \ 19 sizeof(e1000_m88_cable_length_table[0])) 20 21 STATIC const u16 e1000_igp_2_cable_length_table[] = { 22 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 23 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 24 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 25 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 26 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 27 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 28 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 29 124}; 30 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 31 (sizeof(e1000_igp_2_cable_length_table) / \ 32 sizeof(e1000_igp_2_cable_length_table[0])) 33 34 /** 35 * e1000_init_phy_ops_generic - Initialize PHY function pointers 36 * @hw: pointer to the HW structure 37 * 38 * Setups up the function pointers to no-op functions 39 **/ 40 void e1000_init_phy_ops_generic(struct e1000_hw *hw) 41 { 42 struct e1000_phy_info *phy = &hw->phy; 43 DEBUGFUNC("e1000_init_phy_ops_generic"); 44 45 /* Initialize function pointers */ 46 phy->ops.init_params = e1000_null_ops_generic; 47 phy->ops.acquire = e1000_null_ops_generic; 48 phy->ops.check_polarity = e1000_null_ops_generic; 49 phy->ops.check_reset_block = e1000_null_ops_generic; 50 phy->ops.commit = e1000_null_ops_generic; 51 phy->ops.force_speed_duplex = e1000_null_ops_generic; 52 phy->ops.get_cfg_done = e1000_null_ops_generic; 53 phy->ops.get_cable_length = e1000_null_ops_generic; 54 phy->ops.get_info = e1000_null_ops_generic; 55 phy->ops.set_page = e1000_null_set_page; 56 phy->ops.read_reg = e1000_null_read_reg; 57 phy->ops.read_reg_locked = e1000_null_read_reg; 58 phy->ops.read_reg_page = e1000_null_read_reg; 59 phy->ops.release = e1000_null_phy_generic; 60 phy->ops.reset = e1000_null_ops_generic; 61 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 62 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 63 phy->ops.write_reg = e1000_null_write_reg; 64 phy->ops.write_reg_locked = e1000_null_write_reg; 65 phy->ops.write_reg_page = e1000_null_write_reg; 66 phy->ops.power_up = e1000_null_phy_generic; 67 phy->ops.power_down = e1000_null_phy_generic; 68 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null; 69 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null; 70 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 71 } 72 73 /** 74 * e1000_null_set_page - No-op function, return 0 75 * @hw: pointer to the HW structure 76 * @data: dummy variable 77 **/ 78 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw, 79 u16 E1000_UNUSEDARG data) 80 { 81 DEBUGFUNC("e1000_null_set_page"); 82 UNREFERENCED_2PARAMETER(hw, data); 83 return E1000_SUCCESS; 84 } 85 86 /** 87 * e1000_null_read_reg - No-op function, return 0 88 * @hw: pointer to the HW structure 89 * @offset: dummy variable 90 * @data: dummy variable 91 **/ 92 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw, 93 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data) 94 { 95 DEBUGFUNC("e1000_null_read_reg"); 96 UNREFERENCED_3PARAMETER(hw, offset, data); 97 return E1000_SUCCESS; 98 } 99 100 /** 101 * e1000_null_phy_generic - No-op function, return void 102 * @hw: pointer to the HW structure 103 **/ 104 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw) 105 { 106 DEBUGFUNC("e1000_null_phy_generic"); 107 UNREFERENCED_1PARAMETER(hw); 108 return; 109 } 110 111 /** 112 * e1000_null_lplu_state - No-op function, return 0 113 * @hw: pointer to the HW structure 114 * @active: dummy variable 115 **/ 116 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw, 117 bool E1000_UNUSEDARG active) 118 { 119 DEBUGFUNC("e1000_null_lplu_state"); 120 UNREFERENCED_2PARAMETER(hw, active); 121 return E1000_SUCCESS; 122 } 123 124 /** 125 * e1000_null_write_reg - No-op function, return 0 126 * @hw: pointer to the HW structure 127 * @offset: dummy variable 128 * @data: dummy variable 129 **/ 130 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw, 131 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data) 132 { 133 DEBUGFUNC("e1000_null_write_reg"); 134 UNREFERENCED_3PARAMETER(hw, offset, data); 135 return E1000_SUCCESS; 136 } 137 138 /** 139 * e1000_read_i2c_byte_null - No-op function, return 0 140 * @hw: pointer to hardware structure 141 * @byte_offset: byte offset to write 142 * @dev_addr: device address 143 * @data: data value read 144 * 145 **/ 146 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw, 147 u8 E1000_UNUSEDARG byte_offset, 148 u8 E1000_UNUSEDARG dev_addr, 149 u8 E1000_UNUSEDARG *data) 150 { 151 DEBUGFUNC("e1000_read_i2c_byte_null"); 152 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data); 153 return E1000_SUCCESS; 154 } 155 156 /** 157 * e1000_write_i2c_byte_null - No-op function, return 0 158 * @hw: pointer to hardware structure 159 * @byte_offset: byte offset to write 160 * @dev_addr: device address 161 * @data: data value to write 162 * 163 **/ 164 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw, 165 u8 E1000_UNUSEDARG byte_offset, 166 u8 E1000_UNUSEDARG dev_addr, 167 u8 E1000_UNUSEDARG data) 168 { 169 DEBUGFUNC("e1000_write_i2c_byte_null"); 170 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data); 171 return E1000_SUCCESS; 172 } 173 174 /** 175 * e1000_check_reset_block_generic - Check if PHY reset is blocked 176 * @hw: pointer to the HW structure 177 * 178 * Read the PHY management control register and check whether a PHY reset 179 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 180 * return E1000_BLK_PHY_RESET (12). 181 **/ 182 s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 183 { 184 u32 manc; 185 186 DEBUGFUNC("e1000_check_reset_block"); 187 188 manc = E1000_READ_REG(hw, E1000_MANC); 189 190 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 191 E1000_BLK_PHY_RESET : E1000_SUCCESS; 192 } 193 194 /** 195 * e1000_get_phy_id - Retrieve the PHY ID and revision 196 * @hw: pointer to the HW structure 197 * 198 * Reads the PHY registers and stores the PHY ID and possibly the PHY 199 * revision in the hardware structure. 200 **/ 201 s32 e1000_get_phy_id(struct e1000_hw *hw) 202 { 203 struct e1000_phy_info *phy = &hw->phy; 204 s32 ret_val = E1000_SUCCESS; 205 u16 phy_id; 206 u16 retry_count = 0; 207 208 DEBUGFUNC("e1000_get_phy_id"); 209 210 if (!phy->ops.read_reg) 211 return E1000_SUCCESS; 212 213 while (retry_count < 2) { 214 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 215 if (ret_val) 216 return ret_val; 217 218 phy->id = (u32)(phy_id << 16); 219 usec_delay(20); 220 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 221 if (ret_val) 222 return ret_val; 223 224 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 225 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 226 227 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 228 return E1000_SUCCESS; 229 230 retry_count++; 231 } 232 233 return E1000_SUCCESS; 234 } 235 236 /** 237 * e1000_phy_reset_dsp_generic - Reset PHY DSP 238 * @hw: pointer to the HW structure 239 * 240 * Reset the digital signal processor. 241 **/ 242 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 243 { 244 s32 ret_val; 245 246 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 247 248 if (!hw->phy.ops.write_reg) 249 return E1000_SUCCESS; 250 251 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 252 if (ret_val) 253 return ret_val; 254 255 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 256 } 257 258 /** 259 * e1000_read_phy_reg_mdic - Read MDI control register 260 * @hw: pointer to the HW structure 261 * @offset: register offset to be read 262 * @data: pointer to the read data 263 * 264 * Reads the MDI control register in the PHY at offset and stores the 265 * information read to data. 266 **/ 267 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 268 { 269 struct e1000_phy_info *phy = &hw->phy; 270 u32 i, mdic = 0; 271 272 DEBUGFUNC("e1000_read_phy_reg_mdic"); 273 274 if (offset > MAX_PHY_REG_ADDRESS) { 275 DEBUGOUT1("PHY Address %d is out of range\n", offset); 276 return -E1000_ERR_PARAM; 277 } 278 279 /* Set up Op-code, Phy Address, and register offset in the MDI 280 * Control register. The MAC will take care of interfacing with the 281 * PHY to retrieve the desired data. 282 */ 283 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 284 (phy->addr << E1000_MDIC_PHY_SHIFT) | 285 (E1000_MDIC_OP_READ)); 286 287 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 288 289 /* Poll the ready bit to see if the MDI read completed 290 * Increasing the time out as testing showed failures with 291 * the lower time out 292 */ 293 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 294 usec_delay_irq(50); 295 mdic = E1000_READ_REG(hw, E1000_MDIC); 296 if (mdic & E1000_MDIC_READY) 297 break; 298 } 299 if (!(mdic & E1000_MDIC_READY)) { 300 DEBUGOUT("MDI Read did not complete\n"); 301 return -E1000_ERR_PHY; 302 } 303 if (mdic & E1000_MDIC_ERROR) { 304 DEBUGOUT("MDI Error\n"); 305 return -E1000_ERR_PHY; 306 } 307 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 308 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", 309 offset, 310 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 311 return -E1000_ERR_PHY; 312 } 313 *data = (u16) mdic; 314 315 /* Allow some time after each MDIC transaction to avoid 316 * reading duplicate data in the next MDIC transaction. 317 */ 318 if (hw->mac.type == e1000_pch2lan) 319 usec_delay_irq(100); 320 321 return E1000_SUCCESS; 322 } 323 324 /** 325 * e1000_write_phy_reg_mdic - Write MDI control register 326 * @hw: pointer to the HW structure 327 * @offset: register offset to write to 328 * @data: data to write to register at offset 329 * 330 * Writes data to MDI control register in the PHY at offset. 331 **/ 332 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 333 { 334 struct e1000_phy_info *phy = &hw->phy; 335 u32 i, mdic = 0; 336 337 DEBUGFUNC("e1000_write_phy_reg_mdic"); 338 339 if (offset > MAX_PHY_REG_ADDRESS) { 340 DEBUGOUT1("PHY Address %d is out of range\n", offset); 341 return -E1000_ERR_PARAM; 342 } 343 344 /* Set up Op-code, Phy Address, and register offset in the MDI 345 * Control register. The MAC will take care of interfacing with the 346 * PHY to retrieve the desired data. 347 */ 348 mdic = (((u32)data) | 349 (offset << E1000_MDIC_REG_SHIFT) | 350 (phy->addr << E1000_MDIC_PHY_SHIFT) | 351 (E1000_MDIC_OP_WRITE)); 352 353 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 354 355 /* Poll the ready bit to see if the MDI read completed 356 * Increasing the time out as testing showed failures with 357 * the lower time out 358 */ 359 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 360 usec_delay_irq(50); 361 mdic = E1000_READ_REG(hw, E1000_MDIC); 362 if (mdic & E1000_MDIC_READY) 363 break; 364 } 365 if (!(mdic & E1000_MDIC_READY)) { 366 DEBUGOUT("MDI Write did not complete\n"); 367 return -E1000_ERR_PHY; 368 } 369 if (mdic & E1000_MDIC_ERROR) { 370 DEBUGOUT("MDI Error\n"); 371 return -E1000_ERR_PHY; 372 } 373 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 374 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n", 375 offset, 376 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 377 return -E1000_ERR_PHY; 378 } 379 380 /* Allow some time after each MDIC transaction to avoid 381 * reading duplicate data in the next MDIC transaction. 382 */ 383 if (hw->mac.type == e1000_pch2lan) 384 usec_delay_irq(100); 385 386 return E1000_SUCCESS; 387 } 388 389 /** 390 * e1000_read_phy_reg_i2c - Read PHY register using i2c 391 * @hw: pointer to the HW structure 392 * @offset: register offset to be read 393 * @data: pointer to the read data 394 * 395 * Reads the PHY register at offset using the i2c interface and stores the 396 * retrieved information in data. 397 **/ 398 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 399 { 400 struct e1000_phy_info *phy = &hw->phy; 401 u32 i, i2ccmd = 0; 402 403 DEBUGFUNC("e1000_read_phy_reg_i2c"); 404 405 /* Set up Op-code, Phy Address, and register address in the I2CCMD 406 * register. The MAC will take care of interfacing with the 407 * PHY to retrieve the desired data. 408 */ 409 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 410 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 411 (E1000_I2CCMD_OPCODE_READ)); 412 413 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 414 415 /* Poll the ready bit to see if the I2C read completed */ 416 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 417 usec_delay(50); 418 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 419 if (i2ccmd & E1000_I2CCMD_READY) 420 break; 421 } 422 if (!(i2ccmd & E1000_I2CCMD_READY)) { 423 DEBUGOUT("I2CCMD Read did not complete\n"); 424 return -E1000_ERR_PHY; 425 } 426 if (i2ccmd & E1000_I2CCMD_ERROR) { 427 DEBUGOUT("I2CCMD Error bit set\n"); 428 return -E1000_ERR_PHY; 429 } 430 431 /* Need to byte-swap the 16-bit value. */ 432 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 433 434 return E1000_SUCCESS; 435 } 436 437 /** 438 * e1000_write_phy_reg_i2c - Write PHY register using i2c 439 * @hw: pointer to the HW structure 440 * @offset: register offset to write to 441 * @data: data to write at register offset 442 * 443 * Writes the data to PHY register at the offset using the i2c interface. 444 **/ 445 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 446 { 447 struct e1000_phy_info *phy = &hw->phy; 448 u32 i, i2ccmd = 0; 449 u16 phy_data_swapped; 450 451 DEBUGFUNC("e1000_write_phy_reg_i2c"); 452 453 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 454 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 455 DEBUGOUT1("PHY I2C Address %d is out of range.\n", 456 hw->phy.addr); 457 return -E1000_ERR_CONFIG; 458 } 459 460 /* Swap the data bytes for the I2C interface */ 461 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 462 463 /* Set up Op-code, Phy Address, and register address in the I2CCMD 464 * register. The MAC will take care of interfacing with the 465 * PHY to retrieve the desired data. 466 */ 467 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 468 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 469 E1000_I2CCMD_OPCODE_WRITE | 470 phy_data_swapped); 471 472 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 473 474 /* Poll the ready bit to see if the I2C read completed */ 475 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 476 usec_delay(50); 477 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 478 if (i2ccmd & E1000_I2CCMD_READY) 479 break; 480 } 481 if (!(i2ccmd & E1000_I2CCMD_READY)) { 482 DEBUGOUT("I2CCMD Write did not complete\n"); 483 return -E1000_ERR_PHY; 484 } 485 if (i2ccmd & E1000_I2CCMD_ERROR) { 486 DEBUGOUT("I2CCMD Error bit set\n"); 487 return -E1000_ERR_PHY; 488 } 489 490 return E1000_SUCCESS; 491 } 492 493 /** 494 * e1000_read_sfp_data_byte - Reads SFP module data. 495 * @hw: pointer to the HW structure 496 * @offset: byte location offset to be read 497 * @data: read data buffer pointer 498 * 499 * Reads one byte from SFP module data stored 500 * in SFP resided EEPROM memory or SFP diagnostic area. 501 * Function should be called with 502 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 503 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 504 * access 505 **/ 506 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 507 { 508 u32 i = 0; 509 u32 i2ccmd = 0; 510 u32 data_local = 0; 511 512 DEBUGFUNC("e1000_read_sfp_data_byte"); 513 514 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 515 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 516 return -E1000_ERR_PHY; 517 } 518 519 /* Set up Op-code, EEPROM Address,in the I2CCMD 520 * register. The MAC will take care of interfacing with the 521 * EEPROM to retrieve the desired data. 522 */ 523 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 524 E1000_I2CCMD_OPCODE_READ); 525 526 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 527 528 /* Poll the ready bit to see if the I2C read completed */ 529 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 530 usec_delay(50); 531 data_local = E1000_READ_REG(hw, E1000_I2CCMD); 532 if (data_local & E1000_I2CCMD_READY) 533 break; 534 } 535 if (!(data_local & E1000_I2CCMD_READY)) { 536 DEBUGOUT("I2CCMD Read did not complete\n"); 537 return -E1000_ERR_PHY; 538 } 539 if (data_local & E1000_I2CCMD_ERROR) { 540 DEBUGOUT("I2CCMD Error bit set\n"); 541 return -E1000_ERR_PHY; 542 } 543 *data = (u8) data_local & 0xFF; 544 545 return E1000_SUCCESS; 546 } 547 548 /** 549 * e1000_write_sfp_data_byte - Writes SFP module data. 550 * @hw: pointer to the HW structure 551 * @offset: byte location offset to write to 552 * @data: data to write 553 * 554 * Writes one byte to SFP module data stored 555 * in SFP resided EEPROM memory or SFP diagnostic area. 556 * Function should be called with 557 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 558 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 559 * access 560 **/ 561 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) 562 { 563 u32 i = 0; 564 u32 i2ccmd = 0; 565 u32 data_local = 0; 566 567 DEBUGFUNC("e1000_write_sfp_data_byte"); 568 569 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 570 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 571 return -E1000_ERR_PHY; 572 } 573 /* The programming interface is 16 bits wide 574 * so we need to read the whole word first 575 * then update appropriate byte lane and write 576 * the updated word back. 577 */ 578 /* Set up Op-code, EEPROM Address,in the I2CCMD 579 * register. The MAC will take care of interfacing 580 * with an EEPROM to write the data given. 581 */ 582 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 583 E1000_I2CCMD_OPCODE_READ); 584 /* Set a command to read single word */ 585 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 586 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 587 usec_delay(50); 588 /* Poll the ready bit to see if lastly 589 * launched I2C operation completed 590 */ 591 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 592 if (i2ccmd & E1000_I2CCMD_READY) { 593 /* Check if this is READ or WRITE phase */ 594 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) == 595 E1000_I2CCMD_OPCODE_READ) { 596 /* Write the selected byte 597 * lane and update whole word 598 */ 599 data_local = i2ccmd & 0xFF00; 600 data_local |= (u32)data; 601 i2ccmd = ((offset << 602 E1000_I2CCMD_REG_ADDR_SHIFT) | 603 E1000_I2CCMD_OPCODE_WRITE | data_local); 604 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 605 } else { 606 break; 607 } 608 } 609 } 610 if (!(i2ccmd & E1000_I2CCMD_READY)) { 611 DEBUGOUT("I2CCMD Write did not complete\n"); 612 return -E1000_ERR_PHY; 613 } 614 if (i2ccmd & E1000_I2CCMD_ERROR) { 615 DEBUGOUT("I2CCMD Error bit set\n"); 616 return -E1000_ERR_PHY; 617 } 618 return E1000_SUCCESS; 619 } 620 621 /** 622 * e1000_read_phy_reg_m88 - Read m88 PHY register 623 * @hw: pointer to the HW structure 624 * @offset: register offset to be read 625 * @data: pointer to the read data 626 * 627 * Acquires semaphore, if necessary, then reads the PHY register at offset 628 * and storing the retrieved information in data. Release any acquired 629 * semaphores before exiting. 630 **/ 631 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 632 { 633 s32 ret_val; 634 635 DEBUGFUNC("e1000_read_phy_reg_m88"); 636 637 if (!hw->phy.ops.acquire) 638 return E1000_SUCCESS; 639 640 ret_val = hw->phy.ops.acquire(hw); 641 if (ret_val) 642 return ret_val; 643 644 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 645 data); 646 647 hw->phy.ops.release(hw); 648 649 return ret_val; 650 } 651 652 /** 653 * e1000_write_phy_reg_m88 - Write m88 PHY register 654 * @hw: pointer to the HW structure 655 * @offset: register offset to write to 656 * @data: data to write at register offset 657 * 658 * Acquires semaphore, if necessary, then writes the data to PHY register 659 * at the offset. Release any acquired semaphores before exiting. 660 **/ 661 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 662 { 663 s32 ret_val; 664 665 DEBUGFUNC("e1000_write_phy_reg_m88"); 666 667 if (!hw->phy.ops.acquire) 668 return E1000_SUCCESS; 669 670 ret_val = hw->phy.ops.acquire(hw); 671 if (ret_val) 672 return ret_val; 673 674 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 675 data); 676 677 hw->phy.ops.release(hw); 678 679 return ret_val; 680 } 681 682 /** 683 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 684 * @hw: pointer to the HW structure 685 * @page: page to set (shifted left when necessary) 686 * 687 * Sets PHY page required for PHY register access. Assumes semaphore is 688 * already acquired. Note, this function sets phy.addr to 1 so the caller 689 * must set it appropriately (if necessary) after this function returns. 690 **/ 691 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 692 { 693 DEBUGFUNC("e1000_set_page_igp"); 694 695 DEBUGOUT1("Setting page 0x%x\n", page); 696 697 hw->phy.addr = 1; 698 699 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 700 } 701 702 /** 703 * __e1000_read_phy_reg_igp - Read igp PHY register 704 * @hw: pointer to the HW structure 705 * @offset: register offset to be read 706 * @data: pointer to the read data 707 * @locked: semaphore has already been acquired or not 708 * 709 * Acquires semaphore, if necessary, then reads the PHY register at offset 710 * and stores the retrieved information in data. Release any acquired 711 * semaphores before exiting. 712 **/ 713 STATIC s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 714 bool locked) 715 { 716 s32 ret_val = E1000_SUCCESS; 717 718 DEBUGFUNC("__e1000_read_phy_reg_igp"); 719 720 if (!locked) { 721 if (!hw->phy.ops.acquire) 722 return E1000_SUCCESS; 723 724 ret_val = hw->phy.ops.acquire(hw); 725 if (ret_val) 726 return ret_val; 727 } 728 729 if (offset > MAX_PHY_MULTI_PAGE_REG) 730 ret_val = e1000_write_phy_reg_mdic(hw, 731 IGP01E1000_PHY_PAGE_SELECT, 732 (u16)offset); 733 if (!ret_val) 734 ret_val = e1000_read_phy_reg_mdic(hw, 735 MAX_PHY_REG_ADDRESS & offset, 736 data); 737 if (!locked) 738 hw->phy.ops.release(hw); 739 740 return ret_val; 741 } 742 743 /** 744 * e1000_read_phy_reg_igp - Read igp PHY register 745 * @hw: pointer to the HW structure 746 * @offset: register offset to be read 747 * @data: pointer to the read data 748 * 749 * Acquires semaphore then reads the PHY register at offset and stores the 750 * retrieved information in data. 751 * Release the acquired semaphore before exiting. 752 **/ 753 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 754 { 755 return __e1000_read_phy_reg_igp(hw, offset, data, false); 756 } 757 758 /** 759 * e1000_read_phy_reg_igp_locked - Read igp PHY register 760 * @hw: pointer to the HW structure 761 * @offset: register offset to be read 762 * @data: pointer to the read data 763 * 764 * Reads the PHY register at offset and stores the retrieved information 765 * in data. Assumes semaphore already acquired. 766 **/ 767 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 768 { 769 return __e1000_read_phy_reg_igp(hw, offset, data, true); 770 } 771 772 /** 773 * e1000_write_phy_reg_igp - Write igp PHY register 774 * @hw: pointer to the HW structure 775 * @offset: register offset to write to 776 * @data: data to write at register offset 777 * @locked: semaphore has already been acquired or not 778 * 779 * Acquires semaphore, if necessary, then writes the data to PHY register 780 * at the offset. Release any acquired semaphores before exiting. 781 **/ 782 STATIC s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 783 bool locked) 784 { 785 s32 ret_val = E1000_SUCCESS; 786 787 DEBUGFUNC("e1000_write_phy_reg_igp"); 788 789 if (!locked) { 790 if (!hw->phy.ops.acquire) 791 return E1000_SUCCESS; 792 793 ret_val = hw->phy.ops.acquire(hw); 794 if (ret_val) 795 return ret_val; 796 } 797 798 if (offset > MAX_PHY_MULTI_PAGE_REG) 799 ret_val = e1000_write_phy_reg_mdic(hw, 800 IGP01E1000_PHY_PAGE_SELECT, 801 (u16)offset); 802 if (!ret_val) 803 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & 804 offset, 805 data); 806 if (!locked) 807 hw->phy.ops.release(hw); 808 809 return ret_val; 810 } 811 812 /** 813 * e1000_write_phy_reg_igp - Write igp PHY register 814 * @hw: pointer to the HW structure 815 * @offset: register offset to write to 816 * @data: data to write at register offset 817 * 818 * Acquires semaphore then writes the data to PHY register 819 * at the offset. Release any acquired semaphores before exiting. 820 **/ 821 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 822 { 823 return __e1000_write_phy_reg_igp(hw, offset, data, false); 824 } 825 826 /** 827 * e1000_write_phy_reg_igp_locked - Write igp PHY register 828 * @hw: pointer to the HW structure 829 * @offset: register offset to write to 830 * @data: data to write at register offset 831 * 832 * Writes the data to PHY register at the offset. 833 * Assumes semaphore already acquired. 834 **/ 835 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 836 { 837 return __e1000_write_phy_reg_igp(hw, offset, data, true); 838 } 839 840 /** 841 * __e1000_read_kmrn_reg - Read kumeran register 842 * @hw: pointer to the HW structure 843 * @offset: register offset to be read 844 * @data: pointer to the read data 845 * @locked: semaphore has already been acquired or not 846 * 847 * Acquires semaphore, if necessary. Then reads the PHY register at offset 848 * using the kumeran interface. The information retrieved is stored in data. 849 * Release any acquired semaphores before exiting. 850 **/ 851 STATIC s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 852 bool locked) 853 { 854 u32 kmrnctrlsta; 855 856 DEBUGFUNC("__e1000_read_kmrn_reg"); 857 858 if (!locked) { 859 s32 ret_val = E1000_SUCCESS; 860 861 if (!hw->phy.ops.acquire) 862 return E1000_SUCCESS; 863 864 ret_val = hw->phy.ops.acquire(hw); 865 if (ret_val) 866 return ret_val; 867 } 868 869 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 870 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 871 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 872 E1000_WRITE_FLUSH(hw); 873 874 usec_delay(2); 875 876 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 877 *data = (u16)kmrnctrlsta; 878 879 if (!locked) 880 hw->phy.ops.release(hw); 881 882 return E1000_SUCCESS; 883 } 884 885 /** 886 * e1000_read_kmrn_reg_generic - Read kumeran register 887 * @hw: pointer to the HW structure 888 * @offset: register offset to be read 889 * @data: pointer to the read data 890 * 891 * Acquires semaphore then reads the PHY register at offset using the 892 * kumeran interface. The information retrieved is stored in data. 893 * Release the acquired semaphore before exiting. 894 **/ 895 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 896 { 897 return __e1000_read_kmrn_reg(hw, offset, data, false); 898 } 899 900 /** 901 * e1000_read_kmrn_reg_locked - Read kumeran register 902 * @hw: pointer to the HW structure 903 * @offset: register offset to be read 904 * @data: pointer to the read data 905 * 906 * Reads the PHY register at offset using the kumeran interface. The 907 * information retrieved is stored in data. 908 * Assumes semaphore already acquired. 909 **/ 910 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 911 { 912 return __e1000_read_kmrn_reg(hw, offset, data, true); 913 } 914 915 /** 916 * __e1000_write_kmrn_reg - Write kumeran register 917 * @hw: pointer to the HW structure 918 * @offset: register offset to write to 919 * @data: data to write at register offset 920 * @locked: semaphore has already been acquired or not 921 * 922 * Acquires semaphore, if necessary. Then write the data to PHY register 923 * at the offset using the kumeran interface. Release any acquired semaphores 924 * before exiting. 925 **/ 926 STATIC s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 927 bool locked) 928 { 929 u32 kmrnctrlsta; 930 931 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 932 933 if (!locked) { 934 s32 ret_val = E1000_SUCCESS; 935 936 if (!hw->phy.ops.acquire) 937 return E1000_SUCCESS; 938 939 ret_val = hw->phy.ops.acquire(hw); 940 if (ret_val) 941 return ret_val; 942 } 943 944 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 945 E1000_KMRNCTRLSTA_OFFSET) | data; 946 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 947 E1000_WRITE_FLUSH(hw); 948 949 usec_delay(2); 950 951 if (!locked) 952 hw->phy.ops.release(hw); 953 954 return E1000_SUCCESS; 955 } 956 957 /** 958 * e1000_write_kmrn_reg_generic - Write kumeran register 959 * @hw: pointer to the HW structure 960 * @offset: register offset to write to 961 * @data: data to write at register offset 962 * 963 * Acquires semaphore then writes the data to the PHY register at the offset 964 * using the kumeran interface. Release the acquired semaphore before exiting. 965 **/ 966 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 967 { 968 return __e1000_write_kmrn_reg(hw, offset, data, false); 969 } 970 971 /** 972 * e1000_write_kmrn_reg_locked - Write kumeran register 973 * @hw: pointer to the HW structure 974 * @offset: register offset to write to 975 * @data: data to write at register offset 976 * 977 * Write the data to PHY register at the offset using the kumeran interface. 978 * Assumes semaphore already acquired. 979 **/ 980 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 981 { 982 return __e1000_write_kmrn_reg(hw, offset, data, true); 983 } 984 985 /** 986 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode 987 * @hw: pointer to the HW structure 988 * 989 * Sets up Master/slave mode 990 **/ 991 STATIC s32 e1000_set_master_slave_mode(struct e1000_hw *hw) 992 { 993 s32 ret_val; 994 u16 phy_data; 995 996 /* Resolve Master/Slave mode */ 997 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 998 if (ret_val) 999 return ret_val; 1000 1001 /* load defaults for future use */ 1002 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 1003 ((phy_data & CR_1000T_MS_VALUE) ? 1004 e1000_ms_force_master : 1005 e1000_ms_force_slave) : e1000_ms_auto; 1006 1007 switch (hw->phy.ms_type) { 1008 case e1000_ms_force_master: 1009 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1010 break; 1011 case e1000_ms_force_slave: 1012 phy_data |= CR_1000T_MS_ENABLE; 1013 phy_data &= ~(CR_1000T_MS_VALUE); 1014 break; 1015 case e1000_ms_auto: 1016 phy_data &= ~CR_1000T_MS_ENABLE; 1017 /* fall-through */ 1018 default: 1019 break; 1020 } 1021 1022 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 1023 } 1024 1025 /** 1026 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 1027 * @hw: pointer to the HW structure 1028 * 1029 * Sets up Carrier-sense on Transmit and downshift values. 1030 **/ 1031 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 1032 { 1033 s32 ret_val; 1034 u16 phy_data; 1035 1036 DEBUGFUNC("e1000_copper_link_setup_82577"); 1037 1038 if (hw->phy.type == e1000_phy_82580) { 1039 ret_val = hw->phy.ops.reset(hw); 1040 if (ret_val) { 1041 DEBUGOUT("Error resetting the PHY.\n"); 1042 return ret_val; 1043 } 1044 } 1045 1046 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1047 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); 1048 if (ret_val) 1049 return ret_val; 1050 1051 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 1052 1053 /* Enable downshift */ 1054 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 1055 1056 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 1057 if (ret_val) 1058 return ret_val; 1059 1060 /* Set MDI/MDIX mode */ 1061 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); 1062 if (ret_val) 1063 return ret_val; 1064 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; 1065 /* Options: 1066 * 0 - Auto (default) 1067 * 1 - MDI mode 1068 * 2 - MDI-X mode 1069 */ 1070 switch (hw->phy.mdix) { 1071 case 1: 1072 break; 1073 case 2: 1074 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; 1075 break; 1076 case 0: 1077 default: 1078 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; 1079 break; 1080 } 1081 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); 1082 if (ret_val) 1083 return ret_val; 1084 1085 return e1000_set_master_slave_mode(hw); 1086 } 1087 1088 /** 1089 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 1090 * @hw: pointer to the HW structure 1091 * 1092 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 1093 * and downshift values are set also. 1094 **/ 1095 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 1096 { 1097 struct e1000_phy_info *phy = &hw->phy; 1098 s32 ret_val; 1099 u16 phy_data; 1100 1101 DEBUGFUNC("e1000_copper_link_setup_m88"); 1102 1103 1104 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1105 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1106 if (ret_val) 1107 return ret_val; 1108 1109 /* For BM PHY this bit is downshift enable */ 1110 if (phy->type != e1000_phy_bm) 1111 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1112 1113 /* Options: 1114 * MDI/MDI-X = 0 (default) 1115 * 0 - Auto for all speeds 1116 * 1 - MDI mode 1117 * 2 - MDI-X mode 1118 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1119 */ 1120 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1121 1122 switch (phy->mdix) { 1123 case 1: 1124 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1125 break; 1126 case 2: 1127 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1128 break; 1129 case 3: 1130 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1131 break; 1132 case 0: 1133 default: 1134 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1135 break; 1136 } 1137 1138 /* Options: 1139 * disable_polarity_correction = 0 (default) 1140 * Automatic Correction for Reversed Cable Polarity 1141 * 0 - Disabled 1142 * 1 - Enabled 1143 */ 1144 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1145 if (phy->disable_polarity_correction) 1146 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1147 1148 /* Enable downshift on BM (disabled by default) */ 1149 if (phy->type == e1000_phy_bm) { 1150 /* For 82574/82583, first disable then enable downshift */ 1151 if (phy->id == BME1000_E_PHY_ID_R2) { 1152 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; 1153 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1154 phy_data); 1155 if (ret_val) 1156 return ret_val; 1157 /* Commit the changes. */ 1158 ret_val = phy->ops.commit(hw); 1159 if (ret_val) { 1160 DEBUGOUT("Error committing the PHY changes\n"); 1161 return ret_val; 1162 } 1163 } 1164 1165 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 1166 } 1167 1168 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1169 if (ret_val) 1170 return ret_val; 1171 1172 if ((phy->type == e1000_phy_m88) && 1173 (phy->revision < E1000_REVISION_4) && 1174 (phy->id != BME1000_E_PHY_ID_R2)) { 1175 /* Force TX_CLK in the Extended PHY Specific Control Register 1176 * to 25MHz clock. 1177 */ 1178 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1179 &phy_data); 1180 if (ret_val) 1181 return ret_val; 1182 1183 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1184 1185 if ((phy->revision == E1000_REVISION_2) && 1186 (phy->id == M88E1111_I_PHY_ID)) { 1187 /* 82573L PHY - set the downshift counter to 5x. */ 1188 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 1189 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1190 } else { 1191 /* Configure Master and Slave downshift values */ 1192 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1193 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1194 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1195 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1196 } 1197 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1198 phy_data); 1199 if (ret_val) 1200 return ret_val; 1201 } 1202 1203 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 1204 /* Set PHY page 0, register 29 to 0x0003 */ 1205 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 1206 if (ret_val) 1207 return ret_val; 1208 1209 /* Set PHY page 0, register 30 to 0x0000 */ 1210 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 1211 if (ret_val) 1212 return ret_val; 1213 } 1214 1215 /* Commit the changes. */ 1216 ret_val = phy->ops.commit(hw); 1217 if (ret_val) { 1218 DEBUGOUT("Error committing the PHY changes\n"); 1219 return ret_val; 1220 } 1221 1222 if (phy->type == e1000_phy_82578) { 1223 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1224 &phy_data); 1225 if (ret_val) 1226 return ret_val; 1227 1228 /* 82578 PHY - set the downshift count to 1x. */ 1229 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 1230 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 1231 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1232 phy_data); 1233 if (ret_val) 1234 return ret_val; 1235 } 1236 1237 return E1000_SUCCESS; 1238 } 1239 1240 /** 1241 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 1242 * @hw: pointer to the HW structure 1243 * 1244 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 1245 * Also enables and sets the downshift parameters. 1246 **/ 1247 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) 1248 { 1249 struct e1000_phy_info *phy = &hw->phy; 1250 s32 ret_val; 1251 u16 phy_data; 1252 1253 DEBUGFUNC("e1000_copper_link_setup_m88_gen2"); 1254 1255 1256 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1257 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1258 if (ret_val) 1259 return ret_val; 1260 1261 /* Options: 1262 * MDI/MDI-X = 0 (default) 1263 * 0 - Auto for all speeds 1264 * 1 - MDI mode 1265 * 2 - MDI-X mode 1266 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1267 */ 1268 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1269 1270 switch (phy->mdix) { 1271 case 1: 1272 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1273 break; 1274 case 2: 1275 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1276 break; 1277 case 3: 1278 /* M88E1112 does not support this mode) */ 1279 if (phy->id != M88E1112_E_PHY_ID) { 1280 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1281 break; 1282 } 1283 /* Fall through */ 1284 case 0: 1285 default: 1286 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1287 break; 1288 } 1289 1290 /* Options: 1291 * disable_polarity_correction = 0 (default) 1292 * Automatic Correction for Reversed Cable Polarity 1293 * 0 - Disabled 1294 * 1 - Enabled 1295 */ 1296 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1297 if (phy->disable_polarity_correction) 1298 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1299 1300 /* Enable downshift and setting it to X6 */ 1301 if (phy->id == M88E1543_E_PHY_ID) { 1302 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE; 1303 ret_val = 1304 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1305 if (ret_val) 1306 return ret_val; 1307 1308 ret_val = phy->ops.commit(hw); 1309 if (ret_val) { 1310 DEBUGOUT("Error committing the PHY changes\n"); 1311 return ret_val; 1312 } 1313 } 1314 1315 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 1316 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 1317 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 1318 1319 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1320 if (ret_val) 1321 return ret_val; 1322 1323 /* Commit the changes. */ 1324 ret_val = phy->ops.commit(hw); 1325 if (ret_val) { 1326 DEBUGOUT("Error committing the PHY changes\n"); 1327 return ret_val; 1328 } 1329 1330 ret_val = e1000_set_master_slave_mode(hw); 1331 if (ret_val) 1332 return ret_val; 1333 1334 return E1000_SUCCESS; 1335 } 1336 1337 /** 1338 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 1339 * @hw: pointer to the HW structure 1340 * 1341 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 1342 * igp PHY's. 1343 **/ 1344 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 1345 { 1346 struct e1000_phy_info *phy = &hw->phy; 1347 s32 ret_val; 1348 u16 data; 1349 1350 DEBUGFUNC("e1000_copper_link_setup_igp"); 1351 1352 1353 ret_val = hw->phy.ops.reset(hw); 1354 if (ret_val) { 1355 DEBUGOUT("Error resetting the PHY.\n"); 1356 return ret_val; 1357 } 1358 1359 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 1360 * timeout issues when LFS is enabled. 1361 */ 1362 msec_delay(100); 1363 1364 /* The NVM settings will configure LPLU in D3 for 1365 * non-IGP1 PHYs. 1366 */ 1367 if (phy->type == e1000_phy_igp) { 1368 /* disable lplu d3 during driver init */ 1369 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); 1370 if (ret_val) { 1371 DEBUGOUT("Error Disabling LPLU D3\n"); 1372 return ret_val; 1373 } 1374 } 1375 1376 /* disable lplu d0 during driver init */ 1377 if (hw->phy.ops.set_d0_lplu_state) { 1378 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); 1379 if (ret_val) { 1380 DEBUGOUT("Error Disabling LPLU D0\n"); 1381 return ret_val; 1382 } 1383 } 1384 /* Configure mdi-mdix settings */ 1385 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1386 if (ret_val) 1387 return ret_val; 1388 1389 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1390 1391 switch (phy->mdix) { 1392 case 1: 1393 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1394 break; 1395 case 2: 1396 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1397 break; 1398 case 0: 1399 default: 1400 data |= IGP01E1000_PSCR_AUTO_MDIX; 1401 break; 1402 } 1403 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1404 if (ret_val) 1405 return ret_val; 1406 1407 /* set auto-master slave resolution settings */ 1408 if (hw->mac.autoneg) { 1409 /* when autonegotiation advertisement is only 1000Mbps then we 1410 * should disable SmartSpeed and enable Auto MasterSlave 1411 * resolution as hardware default. 1412 */ 1413 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1414 /* Disable SmartSpeed */ 1415 ret_val = phy->ops.read_reg(hw, 1416 IGP01E1000_PHY_PORT_CONFIG, 1417 &data); 1418 if (ret_val) 1419 return ret_val; 1420 1421 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1422 ret_val = phy->ops.write_reg(hw, 1423 IGP01E1000_PHY_PORT_CONFIG, 1424 data); 1425 if (ret_val) 1426 return ret_val; 1427 1428 /* Set auto Master/Slave resolution process */ 1429 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1430 if (ret_val) 1431 return ret_val; 1432 1433 data &= ~CR_1000T_MS_ENABLE; 1434 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1435 if (ret_val) 1436 return ret_val; 1437 } 1438 1439 ret_val = e1000_set_master_slave_mode(hw); 1440 } 1441 1442 return ret_val; 1443 } 1444 1445 /** 1446 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1447 * @hw: pointer to the HW structure 1448 * 1449 * Reads the MII auto-neg advertisement register and/or the 1000T control 1450 * register and if the PHY is already setup for auto-negotiation, then 1451 * return successful. Otherwise, setup advertisement and flow control to 1452 * the appropriate values for the wanted auto-negotiation. 1453 **/ 1454 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1455 { 1456 struct e1000_phy_info *phy = &hw->phy; 1457 s32 ret_val; 1458 u16 mii_autoneg_adv_reg; 1459 u16 mii_1000t_ctrl_reg = 0; 1460 1461 DEBUGFUNC("e1000_phy_setup_autoneg"); 1462 1463 phy->autoneg_advertised &= phy->autoneg_mask; 1464 1465 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1466 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1467 if (ret_val) 1468 return ret_val; 1469 1470 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1471 /* Read the MII 1000Base-T Control Register (Address 9). */ 1472 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1473 &mii_1000t_ctrl_reg); 1474 if (ret_val) 1475 return ret_val; 1476 } 1477 1478 /* Need to parse both autoneg_advertised and fc and set up 1479 * the appropriate PHY registers. First we will parse for 1480 * autoneg_advertised software override. Since we can advertise 1481 * a plethora of combinations, we need to check each bit 1482 * individually. 1483 */ 1484 1485 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1486 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1487 * the 1000Base-T Control Register (Address 9). 1488 */ 1489 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1490 NWAY_AR_100TX_HD_CAPS | 1491 NWAY_AR_10T_FD_CAPS | 1492 NWAY_AR_10T_HD_CAPS); 1493 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1494 1495 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1496 1497 /* Do we want to advertise 10 Mb Half Duplex? */ 1498 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1499 DEBUGOUT("Advertise 10mb Half duplex\n"); 1500 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1501 } 1502 1503 /* Do we want to advertise 10 Mb Full Duplex? */ 1504 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1505 DEBUGOUT("Advertise 10mb Full duplex\n"); 1506 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1507 } 1508 1509 /* Do we want to advertise 100 Mb Half Duplex? */ 1510 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1511 DEBUGOUT("Advertise 100mb Half duplex\n"); 1512 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1513 } 1514 1515 /* Do we want to advertise 100 Mb Full Duplex? */ 1516 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1517 DEBUGOUT("Advertise 100mb Full duplex\n"); 1518 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1519 } 1520 1521 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1522 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1523 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1524 1525 /* Do we want to advertise 1000 Mb Full Duplex? */ 1526 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1527 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1528 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1529 } 1530 1531 /* Check for a software override of the flow control settings, and 1532 * setup the PHY advertisement registers accordingly. If 1533 * auto-negotiation is enabled, then software will have to set the 1534 * "PAUSE" bits to the correct value in the Auto-Negotiation 1535 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1536 * negotiation. 1537 * 1538 * The possible values of the "fc" parameter are: 1539 * 0: Flow control is completely disabled 1540 * 1: Rx flow control is enabled (we can receive pause frames 1541 * but not send pause frames). 1542 * 2: Tx flow control is enabled (we can send pause frames 1543 * but we do not support receiving pause frames). 1544 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1545 * other: No software override. The flow control configuration 1546 * in the EEPROM is used. 1547 */ 1548 switch (hw->fc.current_mode) { 1549 case e1000_fc_none: 1550 /* Flow control (Rx & Tx) is completely disabled by a 1551 * software over-ride. 1552 */ 1553 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1554 break; 1555 case e1000_fc_rx_pause: 1556 /* Rx Flow control is enabled, and Tx Flow control is 1557 * disabled, by a software over-ride. 1558 * 1559 * Since there really isn't a way to advertise that we are 1560 * capable of Rx Pause ONLY, we will advertise that we 1561 * support both symmetric and asymmetric Rx PAUSE. Later 1562 * (in e1000_config_fc_after_link_up) we will disable the 1563 * hw's ability to send PAUSE frames. 1564 */ 1565 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1566 break; 1567 case e1000_fc_tx_pause: 1568 /* Tx Flow control is enabled, and Rx Flow control is 1569 * disabled, by a software over-ride. 1570 */ 1571 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1572 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1573 break; 1574 case e1000_fc_full: 1575 /* Flow control (both Rx and Tx) is enabled by a software 1576 * over-ride. 1577 */ 1578 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1579 break; 1580 default: 1581 DEBUGOUT("Flow control param set incorrectly\n"); 1582 return -E1000_ERR_CONFIG; 1583 } 1584 1585 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1586 if (ret_val) 1587 return ret_val; 1588 1589 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1590 1591 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1592 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 1593 mii_1000t_ctrl_reg); 1594 1595 return ret_val; 1596 } 1597 1598 /** 1599 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1600 * @hw: pointer to the HW structure 1601 * 1602 * Performs initial bounds checking on autoneg advertisement parameter, then 1603 * configure to advertise the full capability. Setup the PHY to autoneg 1604 * and restart the negotiation process between the link partner. If 1605 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1606 **/ 1607 s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1608 { 1609 struct e1000_phy_info *phy = &hw->phy; 1610 s32 ret_val; 1611 u16 phy_ctrl; 1612 1613 DEBUGFUNC("e1000_copper_link_autoneg"); 1614 1615 /* Perform some bounds checking on the autoneg advertisement 1616 * parameter. 1617 */ 1618 phy->autoneg_advertised &= phy->autoneg_mask; 1619 1620 /* If autoneg_advertised is zero, we assume it was not defaulted 1621 * by the calling code so we set to advertise full capability. 1622 */ 1623 if (!phy->autoneg_advertised) 1624 phy->autoneg_advertised = phy->autoneg_mask; 1625 1626 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1627 ret_val = e1000_phy_setup_autoneg(hw); 1628 if (ret_val) { 1629 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1630 return ret_val; 1631 } 1632 DEBUGOUT("Restarting Auto-Neg\n"); 1633 1634 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1635 * the Auto Neg Restart bit in the PHY control register. 1636 */ 1637 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1638 if (ret_val) 1639 return ret_val; 1640 1641 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1642 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1643 if (ret_val) 1644 return ret_val; 1645 1646 /* Does the user want to wait for Auto-Neg to complete here, or 1647 * check at a later time (for example, callback routine). 1648 */ 1649 if (phy->autoneg_wait_to_complete) { 1650 ret_val = e1000_wait_autoneg(hw); 1651 if (ret_val) { 1652 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1653 return ret_val; 1654 } 1655 } 1656 1657 hw->mac.get_link_status = true; 1658 1659 return ret_val; 1660 } 1661 1662 /** 1663 * e1000_setup_copper_link_generic - Configure copper link settings 1664 * @hw: pointer to the HW structure 1665 * 1666 * Calls the appropriate function to configure the link for auto-neg or forced 1667 * speed and duplex. Then we check for link, once link is established calls 1668 * to configure collision distance and flow control are called. If link is 1669 * not established, we return -E1000_ERR_PHY (-2). 1670 **/ 1671 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1672 { 1673 s32 ret_val; 1674 bool link = true; 1675 1676 DEBUGFUNC("e1000_setup_copper_link_generic"); 1677 1678 if (hw->mac.autoneg) { 1679 /* Setup autoneg and flow control advertisement and perform 1680 * autonegotiation. 1681 */ 1682 ret_val = e1000_copper_link_autoneg(hw); 1683 if (ret_val) 1684 return ret_val; 1685 } else { 1686 /* PHY will be set to 10H, 10F, 100H or 100F 1687 * depending on user settings. 1688 */ 1689 DEBUGOUT("Forcing Speed and Duplex\n"); 1690 ret_val = hw->phy.ops.force_speed_duplex(hw); 1691 if (ret_val) { 1692 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1693 return ret_val; 1694 } 1695 } 1696 1697 /* Check link status. Wait up to 100 microseconds for link to become 1698 * valid. 1699 */ 1700 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1701 &link); 1702 if (ret_val) 1703 return ret_val; 1704 1705 if (link) { 1706 DEBUGOUT("Valid link established!!!\n"); 1707 hw->mac.ops.config_collision_dist(hw); 1708 ret_val = e1000_config_fc_after_link_up_generic(hw); 1709 } else { 1710 DEBUGOUT("Unable to establish link!!!\n"); 1711 } 1712 1713 return ret_val; 1714 } 1715 1716 /** 1717 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1718 * @hw: pointer to the HW structure 1719 * 1720 * Calls the PHY setup function to force speed and duplex. Clears the 1721 * auto-crossover to force MDI manually. Waits for link and returns 1722 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1723 **/ 1724 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1725 { 1726 struct e1000_phy_info *phy = &hw->phy; 1727 s32 ret_val; 1728 u16 phy_data; 1729 bool link; 1730 1731 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1732 1733 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1734 if (ret_val) 1735 return ret_val; 1736 1737 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1738 1739 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1740 if (ret_val) 1741 return ret_val; 1742 1743 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1744 * forced whenever speed and duplex are forced. 1745 */ 1746 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1747 if (ret_val) 1748 return ret_val; 1749 1750 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1751 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1752 1753 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1754 if (ret_val) 1755 return ret_val; 1756 1757 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1758 1759 usec_delay(1); 1760 1761 if (phy->autoneg_wait_to_complete) { 1762 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1763 1764 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1765 100000, &link); 1766 if (ret_val) 1767 return ret_val; 1768 1769 if (!link) 1770 DEBUGOUT("Link taking longer than expected.\n"); 1771 1772 /* Try once more */ 1773 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1774 100000, &link); 1775 } 1776 1777 return ret_val; 1778 } 1779 1780 /** 1781 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1782 * @hw: pointer to the HW structure 1783 * 1784 * Calls the PHY setup function to force speed and duplex. Clears the 1785 * auto-crossover to force MDI manually. Resets the PHY to commit the 1786 * changes. If time expires while waiting for link up, we reset the DSP. 1787 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1788 * successful completion, else return corresponding error code. 1789 **/ 1790 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1791 { 1792 struct e1000_phy_info *phy = &hw->phy; 1793 s32 ret_val; 1794 u16 phy_data; 1795 bool link; 1796 1797 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1798 1799 /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1800 if (phy->type != e1000_phy_i210) { 1801 /* Clear Auto-Crossover to force MDI manually. M88E1000 1802 * requires MDI forced whenever speed and duplex are forced. 1803 */ 1804 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1805 &phy_data); 1806 if (ret_val) 1807 return ret_val; 1808 1809 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1810 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1811 phy_data); 1812 if (ret_val) 1813 return ret_val; 1814 1815 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1816 } 1817 1818 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1819 if (ret_val) 1820 return ret_val; 1821 1822 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1823 1824 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1825 if (ret_val) 1826 return ret_val; 1827 1828 /* Reset the phy to commit changes. */ 1829 ret_val = hw->phy.ops.commit(hw); 1830 if (ret_val) 1831 return ret_val; 1832 1833 if (phy->autoneg_wait_to_complete) { 1834 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1835 1836 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1837 100000, &link); 1838 if (ret_val) 1839 return ret_val; 1840 1841 if (!link) { 1842 bool reset_dsp = true; 1843 1844 switch (hw->phy.id) { 1845 case I347AT4_E_PHY_ID: 1846 case M88E1340M_E_PHY_ID: 1847 case M88E1112_E_PHY_ID: 1848 case M88E1543_E_PHY_ID: 1849 case M88E1512_E_PHY_ID: 1850 case I210_I_PHY_ID: 1851 reset_dsp = false; 1852 break; 1853 default: 1854 if (hw->phy.type != e1000_phy_m88) 1855 reset_dsp = false; 1856 break; 1857 } 1858 1859 if (!reset_dsp) { 1860 DEBUGOUT("Link taking longer than expected.\n"); 1861 } else { 1862 /* We didn't get link. 1863 * Reset the DSP and cross our fingers. 1864 */ 1865 ret_val = phy->ops.write_reg(hw, 1866 M88E1000_PHY_PAGE_SELECT, 1867 0x001d); 1868 if (ret_val) 1869 return ret_val; 1870 ret_val = e1000_phy_reset_dsp_generic(hw); 1871 if (ret_val) 1872 return ret_val; 1873 } 1874 } 1875 1876 /* Try once more */ 1877 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1878 100000, &link); 1879 if (ret_val) 1880 return ret_val; 1881 } 1882 1883 if (hw->phy.type != e1000_phy_m88) 1884 return E1000_SUCCESS; 1885 1886 if (hw->phy.id == I347AT4_E_PHY_ID || 1887 hw->phy.id == M88E1340M_E_PHY_ID || 1888 hw->phy.id == M88E1112_E_PHY_ID) 1889 return E1000_SUCCESS; 1890 if (hw->phy.id == I210_I_PHY_ID) 1891 return E1000_SUCCESS; 1892 if ((hw->phy.id == M88E1543_E_PHY_ID) || 1893 (hw->phy.id == M88E1512_E_PHY_ID)) 1894 return E1000_SUCCESS; 1895 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1896 if (ret_val) 1897 return ret_val; 1898 1899 /* Resetting the phy means we need to re-force TX_CLK in the 1900 * Extended PHY Specific Control Register to 25MHz clock from 1901 * the reset value of 2.5MHz. 1902 */ 1903 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1904 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1905 if (ret_val) 1906 return ret_val; 1907 1908 /* In addition, we must re-enable CRS on Tx for both half and full 1909 * duplex. 1910 */ 1911 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1912 if (ret_val) 1913 return ret_val; 1914 1915 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1916 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1917 1918 return ret_val; 1919 } 1920 1921 /** 1922 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1923 * @hw: pointer to the HW structure 1924 * 1925 * Forces the speed and duplex settings of the PHY. 1926 * This is a function pointer entry point only called by 1927 * PHY setup routines. 1928 **/ 1929 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1930 { 1931 struct e1000_phy_info *phy = &hw->phy; 1932 s32 ret_val; 1933 u16 data; 1934 bool link; 1935 1936 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1937 1938 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1939 if (ret_val) 1940 return ret_val; 1941 1942 e1000_phy_force_speed_duplex_setup(hw, &data); 1943 1944 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1945 if (ret_val) 1946 return ret_val; 1947 1948 /* Disable MDI-X support for 10/100 */ 1949 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1950 if (ret_val) 1951 return ret_val; 1952 1953 data &= ~IFE_PMC_AUTO_MDIX; 1954 data &= ~IFE_PMC_FORCE_MDIX; 1955 1956 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1957 if (ret_val) 1958 return ret_val; 1959 1960 DEBUGOUT1("IFE PMC: %X\n", data); 1961 1962 usec_delay(1); 1963 1964 if (phy->autoneg_wait_to_complete) { 1965 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1966 1967 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1968 100000, &link); 1969 if (ret_val) 1970 return ret_val; 1971 1972 if (!link) 1973 DEBUGOUT("Link taking longer than expected.\n"); 1974 1975 /* Try once more */ 1976 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1977 100000, &link); 1978 if (ret_val) 1979 return ret_val; 1980 } 1981 1982 return E1000_SUCCESS; 1983 } 1984 1985 /** 1986 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1987 * @hw: pointer to the HW structure 1988 * @phy_ctrl: pointer to current value of PHY_CONTROL 1989 * 1990 * Forces speed and duplex on the PHY by doing the following: disable flow 1991 * control, force speed/duplex on the MAC, disable auto speed detection, 1992 * disable auto-negotiation, configure duplex, configure speed, configure 1993 * the collision distance, write configuration to CTRL register. The 1994 * caller must write to the PHY_CONTROL register for these settings to 1995 * take affect. 1996 **/ 1997 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1998 { 1999 struct e1000_mac_info *mac = &hw->mac; 2000 u32 ctrl; 2001 2002 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 2003 2004 /* Turn off flow control when forcing speed/duplex */ 2005 hw->fc.current_mode = e1000_fc_none; 2006 2007 /* Force speed/duplex on the mac */ 2008 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2009 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2010 ctrl &= ~E1000_CTRL_SPD_SEL; 2011 2012 /* Disable Auto Speed Detection */ 2013 ctrl &= ~E1000_CTRL_ASDE; 2014 2015 /* Disable autoneg on the phy */ 2016 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 2017 2018 /* Forcing Full or Half Duplex? */ 2019 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 2020 ctrl &= ~E1000_CTRL_FD; 2021 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 2022 DEBUGOUT("Half Duplex\n"); 2023 } else { 2024 ctrl |= E1000_CTRL_FD; 2025 *phy_ctrl |= MII_CR_FULL_DUPLEX; 2026 DEBUGOUT("Full Duplex\n"); 2027 } 2028 2029 /* Forcing 10mb or 100mb? */ 2030 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 2031 ctrl |= E1000_CTRL_SPD_100; 2032 *phy_ctrl |= MII_CR_SPEED_100; 2033 *phy_ctrl &= ~MII_CR_SPEED_1000; 2034 DEBUGOUT("Forcing 100mb\n"); 2035 } else { 2036 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2037 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 2038 DEBUGOUT("Forcing 10mb\n"); 2039 } 2040 2041 hw->mac.ops.config_collision_dist(hw); 2042 2043 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2044 } 2045 2046 /** 2047 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 2048 * @hw: pointer to the HW structure 2049 * @active: boolean used to enable/disable lplu 2050 * 2051 * Success returns 0, Failure returns 1 2052 * 2053 * The low power link up (lplu) state is set to the power management level D3 2054 * and SmartSpeed is disabled when active is true, else clear lplu for D3 2055 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 2056 * is used during Dx states where the power conservation is most important. 2057 * During driver activity, SmartSpeed should be enabled so performance is 2058 * maintained. 2059 **/ 2060 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 2061 { 2062 struct e1000_phy_info *phy = &hw->phy; 2063 s32 ret_val; 2064 u16 data; 2065 2066 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 2067 2068 if (!hw->phy.ops.read_reg) 2069 return E1000_SUCCESS; 2070 2071 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 2072 if (ret_val) 2073 return ret_val; 2074 2075 if (!active) { 2076 data &= ~IGP02E1000_PM_D3_LPLU; 2077 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2078 data); 2079 if (ret_val) 2080 return ret_val; 2081 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2082 * during Dx states where the power conservation is most 2083 * important. During driver activity we should enable 2084 * SmartSpeed, so performance is maintained. 2085 */ 2086 if (phy->smart_speed == e1000_smart_speed_on) { 2087 ret_val = phy->ops.read_reg(hw, 2088 IGP01E1000_PHY_PORT_CONFIG, 2089 &data); 2090 if (ret_val) 2091 return ret_val; 2092 2093 data |= IGP01E1000_PSCFR_SMART_SPEED; 2094 ret_val = phy->ops.write_reg(hw, 2095 IGP01E1000_PHY_PORT_CONFIG, 2096 data); 2097 if (ret_val) 2098 return ret_val; 2099 } else if (phy->smart_speed == e1000_smart_speed_off) { 2100 ret_val = phy->ops.read_reg(hw, 2101 IGP01E1000_PHY_PORT_CONFIG, 2102 &data); 2103 if (ret_val) 2104 return ret_val; 2105 2106 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2107 ret_val = phy->ops.write_reg(hw, 2108 IGP01E1000_PHY_PORT_CONFIG, 2109 data); 2110 if (ret_val) 2111 return ret_val; 2112 } 2113 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2114 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2115 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2116 data |= IGP02E1000_PM_D3_LPLU; 2117 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2118 data); 2119 if (ret_val) 2120 return ret_val; 2121 2122 /* When LPLU is enabled, we should disable SmartSpeed */ 2123 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2124 &data); 2125 if (ret_val) 2126 return ret_val; 2127 2128 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2129 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2130 data); 2131 } 2132 2133 return ret_val; 2134 } 2135 2136 /** 2137 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 2138 * @hw: pointer to the HW structure 2139 * 2140 * Success returns 0, Failure returns 1 2141 * 2142 * A downshift is detected by querying the PHY link health. 2143 **/ 2144 s32 e1000_check_downshift_generic(struct e1000_hw *hw) 2145 { 2146 struct e1000_phy_info *phy = &hw->phy; 2147 s32 ret_val; 2148 u16 phy_data, offset, mask; 2149 2150 DEBUGFUNC("e1000_check_downshift_generic"); 2151 2152 switch (phy->type) { 2153 case e1000_phy_i210: 2154 case e1000_phy_m88: 2155 case e1000_phy_gg82563: 2156 case e1000_phy_bm: 2157 case e1000_phy_82578: 2158 offset = M88E1000_PHY_SPEC_STATUS; 2159 mask = M88E1000_PSSR_DOWNSHIFT; 2160 break; 2161 case e1000_phy_igp: 2162 case e1000_phy_igp_2: 2163 case e1000_phy_igp_3: 2164 offset = IGP01E1000_PHY_LINK_HEALTH; 2165 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 2166 break; 2167 default: 2168 /* speed downshift not supported */ 2169 phy->speed_downgraded = false; 2170 return E1000_SUCCESS; 2171 } 2172 2173 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2174 2175 if (!ret_val) 2176 phy->speed_downgraded = !!(phy_data & mask); 2177 2178 return ret_val; 2179 } 2180 2181 /** 2182 * e1000_check_polarity_m88 - Checks the polarity. 2183 * @hw: pointer to the HW structure 2184 * 2185 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2186 * 2187 * Polarity is determined based on the PHY specific status register. 2188 **/ 2189 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 2190 { 2191 struct e1000_phy_info *phy = &hw->phy; 2192 s32 ret_val; 2193 u16 data; 2194 2195 DEBUGFUNC("e1000_check_polarity_m88"); 2196 2197 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 2198 2199 if (!ret_val) 2200 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY) 2201 ? e1000_rev_polarity_reversed 2202 : e1000_rev_polarity_normal); 2203 2204 return ret_val; 2205 } 2206 2207 /** 2208 * e1000_check_polarity_igp - Checks the polarity. 2209 * @hw: pointer to the HW structure 2210 * 2211 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2212 * 2213 * Polarity is determined based on the PHY port status register, and the 2214 * current speed (since there is no polarity at 100Mbps). 2215 **/ 2216 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 2217 { 2218 struct e1000_phy_info *phy = &hw->phy; 2219 s32 ret_val; 2220 u16 data, offset, mask; 2221 2222 DEBUGFUNC("e1000_check_polarity_igp"); 2223 2224 /* Polarity is determined based on the speed of 2225 * our connection. 2226 */ 2227 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2228 if (ret_val) 2229 return ret_val; 2230 2231 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2232 IGP01E1000_PSSR_SPEED_1000MBPS) { 2233 offset = IGP01E1000_PHY_PCS_INIT_REG; 2234 mask = IGP01E1000_PHY_POLARITY_MASK; 2235 } else { 2236 /* This really only applies to 10Mbps since 2237 * there is no polarity for 100Mbps (always 0). 2238 */ 2239 offset = IGP01E1000_PHY_PORT_STATUS; 2240 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 2241 } 2242 2243 ret_val = phy->ops.read_reg(hw, offset, &data); 2244 2245 if (!ret_val) 2246 phy->cable_polarity = ((data & mask) 2247 ? e1000_rev_polarity_reversed 2248 : e1000_rev_polarity_normal); 2249 2250 return ret_val; 2251 } 2252 2253 /** 2254 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 2255 * @hw: pointer to the HW structure 2256 * 2257 * Polarity is determined on the polarity reversal feature being enabled. 2258 **/ 2259 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 2260 { 2261 struct e1000_phy_info *phy = &hw->phy; 2262 s32 ret_val; 2263 u16 phy_data, offset, mask; 2264 2265 DEBUGFUNC("e1000_check_polarity_ife"); 2266 2267 /* Polarity is determined based on the reversal feature being enabled. 2268 */ 2269 if (phy->polarity_correction) { 2270 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 2271 mask = IFE_PESC_POLARITY_REVERSED; 2272 } else { 2273 offset = IFE_PHY_SPECIAL_CONTROL; 2274 mask = IFE_PSC_FORCE_POLARITY; 2275 } 2276 2277 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2278 2279 if (!ret_val) 2280 phy->cable_polarity = ((phy_data & mask) 2281 ? e1000_rev_polarity_reversed 2282 : e1000_rev_polarity_normal); 2283 2284 return ret_val; 2285 } 2286 2287 /** 2288 * e1000_wait_autoneg - Wait for auto-neg completion 2289 * @hw: pointer to the HW structure 2290 * 2291 * Waits for auto-negotiation to complete or for the auto-negotiation time 2292 * limit to expire, which ever happens first. 2293 **/ 2294 STATIC s32 e1000_wait_autoneg(struct e1000_hw *hw) 2295 { 2296 s32 ret_val = E1000_SUCCESS; 2297 u16 i, phy_status; 2298 2299 DEBUGFUNC("e1000_wait_autoneg"); 2300 2301 if (!hw->phy.ops.read_reg) 2302 return E1000_SUCCESS; 2303 2304 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 2305 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 2306 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2307 if (ret_val) 2308 break; 2309 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2310 if (ret_val) 2311 break; 2312 if (phy_status & MII_SR_AUTONEG_COMPLETE) 2313 break; 2314 msec_delay(100); 2315 } 2316 2317 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2318 * has completed. 2319 */ 2320 return ret_val; 2321 } 2322 2323 /** 2324 * e1000_phy_has_link_generic - Polls PHY for link 2325 * @hw: pointer to the HW structure 2326 * @iterations: number of times to poll for link 2327 * @usec_interval: delay between polling attempts 2328 * @success: pointer to whether polling was successful or not 2329 * 2330 * Polls the PHY status register for link, 'iterations' number of times. 2331 **/ 2332 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2333 u32 usec_interval, bool *success) 2334 { 2335 s32 ret_val = E1000_SUCCESS; 2336 u16 i, phy_status; 2337 2338 DEBUGFUNC("e1000_phy_has_link_generic"); 2339 2340 if (!hw->phy.ops.read_reg) 2341 return E1000_SUCCESS; 2342 2343 for (i = 0; i < iterations; i++) { 2344 /* Some PHYs require the PHY_STATUS register to be read 2345 * twice due to the link bit being sticky. No harm doing 2346 * it across the board. 2347 */ 2348 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2349 if (ret_val) { 2350 /* If the first read fails, another entity may have 2351 * ownership of the resources, wait and try again to 2352 * see if they have relinquished the resources yet. 2353 */ 2354 if (usec_interval >= 1000) 2355 msec_delay(usec_interval/1000); 2356 else 2357 usec_delay(usec_interval); 2358 } 2359 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2360 if (ret_val) 2361 break; 2362 if (phy_status & MII_SR_LINK_STATUS) 2363 break; 2364 if (usec_interval >= 1000) 2365 msec_delay(usec_interval/1000); 2366 else 2367 usec_delay(usec_interval); 2368 } 2369 2370 *success = (i < iterations); 2371 2372 return ret_val; 2373 } 2374 2375 /** 2376 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2377 * @hw: pointer to the HW structure 2378 * 2379 * Reads the PHY specific status register to retrieve the cable length 2380 * information. The cable length is determined by averaging the minimum and 2381 * maximum values to get the "average" cable length. The m88 PHY has four 2382 * possible cable length values, which are: 2383 * Register Value Cable Length 2384 * 0 < 50 meters 2385 * 1 50 - 80 meters 2386 * 2 80 - 110 meters 2387 * 3 110 - 140 meters 2388 * 4 > 140 meters 2389 **/ 2390 s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2391 { 2392 struct e1000_phy_info *phy = &hw->phy; 2393 s32 ret_val; 2394 u16 phy_data, index; 2395 2396 DEBUGFUNC("e1000_get_cable_length_m88"); 2397 2398 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2399 if (ret_val) 2400 return ret_val; 2401 2402 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2403 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 2404 2405 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2406 return -E1000_ERR_PHY; 2407 2408 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2409 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2410 2411 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2412 2413 return E1000_SUCCESS; 2414 } 2415 2416 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) 2417 { 2418 struct e1000_phy_info *phy = &hw->phy; 2419 s32 ret_val; 2420 u16 phy_data, phy_data2, is_cm; 2421 u16 index, default_page; 2422 2423 DEBUGFUNC("e1000_get_cable_length_m88_gen2"); 2424 2425 switch (hw->phy.id) { 2426 case I210_I_PHY_ID: 2427 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2428 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2429 (I347AT4_PCDL + phy->addr), 2430 &phy_data); 2431 if (ret_val) 2432 return ret_val; 2433 2434 /* Check if the unit of cable length is meters or cm */ 2435 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2436 I347AT4_PCDC, &phy_data2); 2437 if (ret_val) 2438 return ret_val; 2439 2440 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2441 2442 /* Populate the phy structure with cable length in meters */ 2443 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2444 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2445 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2446 break; 2447 case M88E1543_E_PHY_ID: 2448 case M88E1512_E_PHY_ID: 2449 case M88E1340M_E_PHY_ID: 2450 case I347AT4_E_PHY_ID: 2451 /* Remember the original page select and set it to 7 */ 2452 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2453 &default_page); 2454 if (ret_val) 2455 return ret_val; 2456 2457 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 2458 if (ret_val) 2459 return ret_val; 2460 2461 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2462 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 2463 &phy_data); 2464 if (ret_val) 2465 return ret_val; 2466 2467 /* Check if the unit of cable length is meters or cm */ 2468 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 2469 if (ret_val) 2470 return ret_val; 2471 2472 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2473 2474 /* Populate the phy structure with cable length in meters */ 2475 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2476 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2477 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2478 2479 /* Reset the page select to its original value */ 2480 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2481 default_page); 2482 if (ret_val) 2483 return ret_val; 2484 break; 2485 2486 case M88E1112_E_PHY_ID: 2487 /* Remember the original page select and set it to 5 */ 2488 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2489 &default_page); 2490 if (ret_val) 2491 return ret_val; 2492 2493 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 2494 if (ret_val) 2495 return ret_val; 2496 2497 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 2498 &phy_data); 2499 if (ret_val) 2500 return ret_val; 2501 2502 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2503 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2504 2505 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2506 return -E1000_ERR_PHY; 2507 2508 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2509 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2510 2511 phy->cable_length = (phy->min_cable_length + 2512 phy->max_cable_length) / 2; 2513 2514 /* Reset the page select to its original value */ 2515 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2516 default_page); 2517 if (ret_val) 2518 return ret_val; 2519 2520 break; 2521 default: 2522 return -E1000_ERR_PHY; 2523 } 2524 2525 return ret_val; 2526 } 2527 2528 /** 2529 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2530 * @hw: pointer to the HW structure 2531 * 2532 * The automatic gain control (agc) normalizes the amplitude of the 2533 * received signal, adjusting for the attenuation produced by the 2534 * cable. By reading the AGC registers, which represent the 2535 * combination of coarse and fine gain value, the value can be put 2536 * into a lookup table to obtain the approximate cable length 2537 * for each channel. 2538 **/ 2539 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2540 { 2541 struct e1000_phy_info *phy = &hw->phy; 2542 s32 ret_val; 2543 u16 phy_data, i, agc_value = 0; 2544 u16 cur_agc_index, max_agc_index = 0; 2545 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2546 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 2547 IGP02E1000_PHY_AGC_A, 2548 IGP02E1000_PHY_AGC_B, 2549 IGP02E1000_PHY_AGC_C, 2550 IGP02E1000_PHY_AGC_D 2551 }; 2552 2553 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2554 2555 /* Read the AGC registers for all channels */ 2556 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2557 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2558 if (ret_val) 2559 return ret_val; 2560 2561 /* Getting bits 15:9, which represent the combination of 2562 * coarse and fine gain values. The result is a number 2563 * that can be put into the lookup table to obtain the 2564 * approximate cable length. 2565 */ 2566 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2567 IGP02E1000_AGC_LENGTH_MASK); 2568 2569 /* Array index bound check. */ 2570 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2571 (cur_agc_index == 0)) 2572 return -E1000_ERR_PHY; 2573 2574 /* Remove min & max AGC values from calculation. */ 2575 if (e1000_igp_2_cable_length_table[min_agc_index] > 2576 e1000_igp_2_cable_length_table[cur_agc_index]) 2577 min_agc_index = cur_agc_index; 2578 if (e1000_igp_2_cable_length_table[max_agc_index] < 2579 e1000_igp_2_cable_length_table[cur_agc_index]) 2580 max_agc_index = cur_agc_index; 2581 2582 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2583 } 2584 2585 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2586 e1000_igp_2_cable_length_table[max_agc_index]); 2587 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2588 2589 /* Calculate cable length with the error range of +/- 10 meters. */ 2590 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2591 (agc_value - IGP02E1000_AGC_RANGE) : 0); 2592 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2593 2594 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2595 2596 return E1000_SUCCESS; 2597 } 2598 2599 /** 2600 * e1000_get_phy_info_m88 - Retrieve PHY information 2601 * @hw: pointer to the HW structure 2602 * 2603 * Valid for only copper links. Read the PHY status register (sticky read) 2604 * to verify that link is up. Read the PHY special control register to 2605 * determine the polarity and 10base-T extended distance. Read the PHY 2606 * special status register to determine MDI/MDIx and current speed. If 2607 * speed is 1000, then determine cable length, local and remote receiver. 2608 **/ 2609 s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2610 { 2611 struct e1000_phy_info *phy = &hw->phy; 2612 s32 ret_val; 2613 u16 phy_data; 2614 bool link; 2615 2616 DEBUGFUNC("e1000_get_phy_info_m88"); 2617 2618 if (phy->media_type != e1000_media_type_copper) { 2619 DEBUGOUT("Phy info is only valid for copper media\n"); 2620 return -E1000_ERR_CONFIG; 2621 } 2622 2623 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2624 if (ret_val) 2625 return ret_val; 2626 2627 if (!link) { 2628 DEBUGOUT("Phy info is only valid if link is up\n"); 2629 return -E1000_ERR_CONFIG; 2630 } 2631 2632 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2633 if (ret_val) 2634 return ret_val; 2635 2636 phy->polarity_correction = !!(phy_data & 2637 M88E1000_PSCR_POLARITY_REVERSAL); 2638 2639 ret_val = e1000_check_polarity_m88(hw); 2640 if (ret_val) 2641 return ret_val; 2642 2643 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2644 if (ret_val) 2645 return ret_val; 2646 2647 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); 2648 2649 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2650 ret_val = hw->phy.ops.get_cable_length(hw); 2651 if (ret_val) 2652 return ret_val; 2653 2654 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2655 if (ret_val) 2656 return ret_val; 2657 2658 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2659 ? e1000_1000t_rx_status_ok 2660 : e1000_1000t_rx_status_not_ok; 2661 2662 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2663 ? e1000_1000t_rx_status_ok 2664 : e1000_1000t_rx_status_not_ok; 2665 } else { 2666 /* Set values to "undefined" */ 2667 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2668 phy->local_rx = e1000_1000t_rx_status_undefined; 2669 phy->remote_rx = e1000_1000t_rx_status_undefined; 2670 } 2671 2672 return ret_val; 2673 } 2674 2675 /** 2676 * e1000_get_phy_info_igp - Retrieve igp PHY information 2677 * @hw: pointer to the HW structure 2678 * 2679 * Read PHY status to determine if link is up. If link is up, then 2680 * set/determine 10base-T extended distance and polarity correction. Read 2681 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2682 * determine on the cable length, local and remote receiver. 2683 **/ 2684 s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2685 { 2686 struct e1000_phy_info *phy = &hw->phy; 2687 s32 ret_val; 2688 u16 data; 2689 bool link; 2690 2691 DEBUGFUNC("e1000_get_phy_info_igp"); 2692 2693 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2694 if (ret_val) 2695 return ret_val; 2696 2697 if (!link) { 2698 DEBUGOUT("Phy info is only valid if link is up\n"); 2699 return -E1000_ERR_CONFIG; 2700 } 2701 2702 phy->polarity_correction = true; 2703 2704 ret_val = e1000_check_polarity_igp(hw); 2705 if (ret_val) 2706 return ret_val; 2707 2708 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2709 if (ret_val) 2710 return ret_val; 2711 2712 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); 2713 2714 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2715 IGP01E1000_PSSR_SPEED_1000MBPS) { 2716 ret_val = phy->ops.get_cable_length(hw); 2717 if (ret_val) 2718 return ret_val; 2719 2720 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2721 if (ret_val) 2722 return ret_val; 2723 2724 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2725 ? e1000_1000t_rx_status_ok 2726 : e1000_1000t_rx_status_not_ok; 2727 2728 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2729 ? e1000_1000t_rx_status_ok 2730 : e1000_1000t_rx_status_not_ok; 2731 } else { 2732 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2733 phy->local_rx = e1000_1000t_rx_status_undefined; 2734 phy->remote_rx = e1000_1000t_rx_status_undefined; 2735 } 2736 2737 return ret_val; 2738 } 2739 2740 /** 2741 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2742 * @hw: pointer to the HW structure 2743 * 2744 * Populates "phy" structure with various feature states. 2745 **/ 2746 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2747 { 2748 struct e1000_phy_info *phy = &hw->phy; 2749 s32 ret_val; 2750 u16 data; 2751 bool link; 2752 2753 DEBUGFUNC("e1000_get_phy_info_ife"); 2754 2755 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2756 if (ret_val) 2757 return ret_val; 2758 2759 if (!link) { 2760 DEBUGOUT("Phy info is only valid if link is up\n"); 2761 return -E1000_ERR_CONFIG; 2762 } 2763 2764 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2765 if (ret_val) 2766 return ret_val; 2767 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); 2768 2769 if (phy->polarity_correction) { 2770 ret_val = e1000_check_polarity_ife(hw); 2771 if (ret_val) 2772 return ret_val; 2773 } else { 2774 /* Polarity is forced */ 2775 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY) 2776 ? e1000_rev_polarity_reversed 2777 : e1000_rev_polarity_normal); 2778 } 2779 2780 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2781 if (ret_val) 2782 return ret_val; 2783 2784 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); 2785 2786 /* The following parameters are undefined for 10/100 operation. */ 2787 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2788 phy->local_rx = e1000_1000t_rx_status_undefined; 2789 phy->remote_rx = e1000_1000t_rx_status_undefined; 2790 2791 return E1000_SUCCESS; 2792 } 2793 2794 /** 2795 * e1000_phy_sw_reset_generic - PHY software reset 2796 * @hw: pointer to the HW structure 2797 * 2798 * Does a software reset of the PHY by reading the PHY control register and 2799 * setting/write the control register reset bit to the PHY. 2800 **/ 2801 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2802 { 2803 s32 ret_val; 2804 u16 phy_ctrl; 2805 2806 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2807 2808 if (!hw->phy.ops.read_reg) 2809 return E1000_SUCCESS; 2810 2811 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2812 if (ret_val) 2813 return ret_val; 2814 2815 phy_ctrl |= MII_CR_RESET; 2816 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2817 if (ret_val) 2818 return ret_val; 2819 2820 usec_delay(1); 2821 2822 return ret_val; 2823 } 2824 2825 /** 2826 * e1000_phy_hw_reset_generic - PHY hardware reset 2827 * @hw: pointer to the HW structure 2828 * 2829 * Verify the reset block is not blocking us from resetting. Acquire 2830 * semaphore (if necessary) and read/set/write the device control reset 2831 * bit in the PHY. Wait the appropriate delay time for the device to 2832 * reset and release the semaphore (if necessary). 2833 **/ 2834 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2835 { 2836 struct e1000_phy_info *phy = &hw->phy; 2837 s32 ret_val; 2838 u32 ctrl; 2839 2840 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2841 2842 if (phy->ops.check_reset_block) { 2843 ret_val = phy->ops.check_reset_block(hw); 2844 if (ret_val) 2845 return E1000_SUCCESS; 2846 } 2847 2848 ret_val = phy->ops.acquire(hw); 2849 if (ret_val) 2850 return ret_val; 2851 2852 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2853 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2854 E1000_WRITE_FLUSH(hw); 2855 2856 usec_delay(phy->reset_delay_us); 2857 2858 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2859 E1000_WRITE_FLUSH(hw); 2860 2861 usec_delay(150); 2862 2863 phy->ops.release(hw); 2864 2865 return phy->ops.get_cfg_done(hw); 2866 } 2867 2868 /** 2869 * e1000_get_cfg_done_generic - Generic configuration done 2870 * @hw: pointer to the HW structure 2871 * 2872 * Generic function to wait 10 milli-seconds for configuration to complete 2873 * and return success. 2874 **/ 2875 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2876 { 2877 DEBUGFUNC("e1000_get_cfg_done_generic"); 2878 UNREFERENCED_1PARAMETER(hw); 2879 2880 msec_delay_irq(10); 2881 2882 return E1000_SUCCESS; 2883 } 2884 2885 /** 2886 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2887 * @hw: pointer to the HW structure 2888 * 2889 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2890 **/ 2891 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2892 { 2893 DEBUGOUT("Running IGP 3 PHY init script\n"); 2894 2895 /* PHY init IGP 3 */ 2896 /* Enable rise/fall, 10-mode work in class-A */ 2897 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2898 /* Remove all caps from Replica path filter */ 2899 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2900 /* Bias trimming for ADC, AFE and Driver (Default) */ 2901 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2902 /* Increase Hybrid poly bias */ 2903 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2904 /* Add 4% to Tx amplitude in Gig mode */ 2905 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2906 /* Disable trimming (TTT) */ 2907 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2908 /* Poly DC correction to 94.6% + 2% for all channels */ 2909 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2910 /* ABS DC correction to 95.9% */ 2911 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2912 /* BG temp curve trim */ 2913 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2914 /* Increasing ADC OPAMP stage 1 currents to max */ 2915 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2916 /* Force 1000 ( required for enabling PHY regs configuration) */ 2917 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2918 /* Set upd_freq to 6 */ 2919 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2920 /* Disable NPDFE */ 2921 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2922 /* Disable adaptive fixed FFE (Default) */ 2923 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2924 /* Enable FFE hysteresis */ 2925 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2926 /* Fixed FFE for short cable lengths */ 2927 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2928 /* Fixed FFE for medium cable lengths */ 2929 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2930 /* Fixed FFE for long cable lengths */ 2931 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2932 /* Enable Adaptive Clip Threshold */ 2933 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2934 /* AHT reset limit to 1 */ 2935 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2936 /* Set AHT master delay to 127 msec */ 2937 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2938 /* Set scan bits for AHT */ 2939 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2940 /* Set AHT Preset bits */ 2941 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2942 /* Change integ_factor of channel A to 3 */ 2943 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2944 /* Change prop_factor of channels BCD to 8 */ 2945 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2946 /* Change cg_icount + enable integbp for channels BCD */ 2947 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2948 /* Change cg_icount + enable integbp + change prop_factor_master 2949 * to 8 for channel A 2950 */ 2951 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2952 /* Disable AHT in Slave mode on channel A */ 2953 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2954 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2955 * Enable SPD+B2B 2956 */ 2957 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2958 /* Enable restart AN on an1000_dis change */ 2959 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2960 /* Enable wh_fifo read clock in 10/100 modes */ 2961 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2962 /* Restart AN, Speed selection is 1000 */ 2963 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2964 2965 return E1000_SUCCESS; 2966 } 2967 2968 /** 2969 * e1000_get_phy_type_from_id - Get PHY type from id 2970 * @phy_id: phy_id read from the phy 2971 * 2972 * Returns the phy type from the id. 2973 **/ 2974 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2975 { 2976 enum e1000_phy_type phy_type = e1000_phy_unknown; 2977 2978 switch (phy_id) { 2979 case M88E1000_I_PHY_ID: 2980 case M88E1000_E_PHY_ID: 2981 case M88E1111_I_PHY_ID: 2982 case M88E1011_I_PHY_ID: 2983 case M88E1543_E_PHY_ID: 2984 case M88E1512_E_PHY_ID: 2985 case I347AT4_E_PHY_ID: 2986 case M88E1112_E_PHY_ID: 2987 case M88E1340M_E_PHY_ID: 2988 phy_type = e1000_phy_m88; 2989 break; 2990 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2991 phy_type = e1000_phy_igp_2; 2992 break; 2993 case GG82563_E_PHY_ID: 2994 phy_type = e1000_phy_gg82563; 2995 break; 2996 case IGP03E1000_E_PHY_ID: 2997 phy_type = e1000_phy_igp_3; 2998 break; 2999 case IFE_E_PHY_ID: 3000 case IFE_PLUS_E_PHY_ID: 3001 case IFE_C_E_PHY_ID: 3002 phy_type = e1000_phy_ife; 3003 break; 3004 case BME1000_E_PHY_ID: 3005 case BME1000_E_PHY_ID_R2: 3006 phy_type = e1000_phy_bm; 3007 break; 3008 case I82578_E_PHY_ID: 3009 phy_type = e1000_phy_82578; 3010 break; 3011 case I82577_E_PHY_ID: 3012 phy_type = e1000_phy_82577; 3013 break; 3014 case I82579_E_PHY_ID: 3015 phy_type = e1000_phy_82579; 3016 break; 3017 case I217_E_PHY_ID: 3018 phy_type = e1000_phy_i217; 3019 break; 3020 case I82580_I_PHY_ID: 3021 phy_type = e1000_phy_82580; 3022 break; 3023 case I210_I_PHY_ID: 3024 phy_type = e1000_phy_i210; 3025 break; 3026 default: 3027 phy_type = e1000_phy_unknown; 3028 break; 3029 } 3030 return phy_type; 3031 } 3032 3033 /** 3034 * e1000_determine_phy_address - Determines PHY address. 3035 * @hw: pointer to the HW structure 3036 * 3037 * This uses a trial and error method to loop through possible PHY 3038 * addresses. It tests each by reading the PHY ID registers and 3039 * checking for a match. 3040 **/ 3041 s32 e1000_determine_phy_address(struct e1000_hw *hw) 3042 { 3043 u32 phy_addr = 0; 3044 u32 i; 3045 enum e1000_phy_type phy_type = e1000_phy_unknown; 3046 3047 hw->phy.id = phy_type; 3048 3049 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 3050 hw->phy.addr = phy_addr; 3051 i = 0; 3052 3053 do { 3054 e1000_get_phy_id(hw); 3055 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 3056 3057 /* If phy_type is valid, break - we found our 3058 * PHY address 3059 */ 3060 if (phy_type != e1000_phy_unknown) 3061 return E1000_SUCCESS; 3062 3063 msec_delay(1); 3064 i++; 3065 } while (i < 10); 3066 } 3067 3068 return -E1000_ERR_PHY_TYPE; 3069 } 3070 3071 /** 3072 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 3073 * @page: page to access 3074 * @reg: register to access 3075 * 3076 * Returns the phy address for the page requested. 3077 **/ 3078 STATIC u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 3079 { 3080 u32 phy_addr = 2; 3081 3082 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 3083 phy_addr = 1; 3084 3085 return phy_addr; 3086 } 3087 3088 /** 3089 * e1000_write_phy_reg_bm - Write BM PHY register 3090 * @hw: pointer to the HW structure 3091 * @offset: register offset to write to 3092 * @data: data to write at register offset 3093 * 3094 * Acquires semaphore, if necessary, then writes the data to PHY register 3095 * at the offset. Release any acquired semaphores before exiting. 3096 **/ 3097 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 3098 { 3099 s32 ret_val; 3100 u32 page = offset >> IGP_PAGE_SHIFT; 3101 3102 DEBUGFUNC("e1000_write_phy_reg_bm"); 3103 3104 ret_val = hw->phy.ops.acquire(hw); 3105 if (ret_val) 3106 return ret_val; 3107 3108 /* Page 800 works differently than the rest so it has its own func */ 3109 if (page == BM_WUC_PAGE) { 3110 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3111 false, false); 3112 goto release; 3113 } 3114 3115 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3116 3117 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3118 u32 page_shift, page_select; 3119 3120 /* Page select is register 31 for phy address 1 and 22 for 3121 * phy address 2 and 3. Page select is shifted only for 3122 * phy address 1. 3123 */ 3124 if (hw->phy.addr == 1) { 3125 page_shift = IGP_PAGE_SHIFT; 3126 page_select = IGP01E1000_PHY_PAGE_SELECT; 3127 } else { 3128 page_shift = 0; 3129 page_select = BM_PHY_PAGE_SELECT; 3130 } 3131 3132 /* Page is shifted left, PHY expects (page x 32) */ 3133 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3134 (page << page_shift)); 3135 if (ret_val) 3136 goto release; 3137 } 3138 3139 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3140 data); 3141 3142 release: 3143 hw->phy.ops.release(hw); 3144 return ret_val; 3145 } 3146 3147 /** 3148 * e1000_read_phy_reg_bm - Read BM PHY register 3149 * @hw: pointer to the HW structure 3150 * @offset: register offset to be read 3151 * @data: pointer to the read data 3152 * 3153 * Acquires semaphore, if necessary, then reads the PHY register at offset 3154 * and storing the retrieved information in data. Release any acquired 3155 * semaphores before exiting. 3156 **/ 3157 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 3158 { 3159 s32 ret_val; 3160 u32 page = offset >> IGP_PAGE_SHIFT; 3161 3162 DEBUGFUNC("e1000_read_phy_reg_bm"); 3163 3164 ret_val = hw->phy.ops.acquire(hw); 3165 if (ret_val) 3166 return ret_val; 3167 3168 /* Page 800 works differently than the rest so it has its own func */ 3169 if (page == BM_WUC_PAGE) { 3170 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3171 true, false); 3172 goto release; 3173 } 3174 3175 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3176 3177 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3178 u32 page_shift, page_select; 3179 3180 /* Page select is register 31 for phy address 1 and 22 for 3181 * phy address 2 and 3. Page select is shifted only for 3182 * phy address 1. 3183 */ 3184 if (hw->phy.addr == 1) { 3185 page_shift = IGP_PAGE_SHIFT; 3186 page_select = IGP01E1000_PHY_PAGE_SELECT; 3187 } else { 3188 page_shift = 0; 3189 page_select = BM_PHY_PAGE_SELECT; 3190 } 3191 3192 /* Page is shifted left, PHY expects (page x 32) */ 3193 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3194 (page << page_shift)); 3195 if (ret_val) 3196 goto release; 3197 } 3198 3199 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3200 data); 3201 release: 3202 hw->phy.ops.release(hw); 3203 return ret_val; 3204 } 3205 3206 /** 3207 * e1000_read_phy_reg_bm2 - Read BM PHY register 3208 * @hw: pointer to the HW structure 3209 * @offset: register offset to be read 3210 * @data: pointer to the read data 3211 * 3212 * Acquires semaphore, if necessary, then reads the PHY register at offset 3213 * and storing the retrieved information in data. Release any acquired 3214 * semaphores before exiting. 3215 **/ 3216 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 3217 { 3218 s32 ret_val; 3219 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3220 3221 DEBUGFUNC("e1000_read_phy_reg_bm2"); 3222 3223 ret_val = hw->phy.ops.acquire(hw); 3224 if (ret_val) 3225 return ret_val; 3226 3227 /* Page 800 works differently than the rest so it has its own func */ 3228 if (page == BM_WUC_PAGE) { 3229 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3230 true, false); 3231 goto release; 3232 } 3233 3234 hw->phy.addr = 1; 3235 3236 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3237 /* Page is shifted left, PHY expects (page x 32) */ 3238 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3239 page); 3240 3241 if (ret_val) 3242 goto release; 3243 } 3244 3245 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3246 data); 3247 release: 3248 hw->phy.ops.release(hw); 3249 return ret_val; 3250 } 3251 3252 /** 3253 * e1000_write_phy_reg_bm2 - Write BM PHY register 3254 * @hw: pointer to the HW structure 3255 * @offset: register offset to write to 3256 * @data: data to write at register offset 3257 * 3258 * Acquires semaphore, if necessary, then writes the data to PHY register 3259 * at the offset. Release any acquired semaphores before exiting. 3260 **/ 3261 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 3262 { 3263 s32 ret_val; 3264 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3265 3266 DEBUGFUNC("e1000_write_phy_reg_bm2"); 3267 3268 ret_val = hw->phy.ops.acquire(hw); 3269 if (ret_val) 3270 return ret_val; 3271 3272 /* Page 800 works differently than the rest so it has its own func */ 3273 if (page == BM_WUC_PAGE) { 3274 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3275 false, false); 3276 goto release; 3277 } 3278 3279 hw->phy.addr = 1; 3280 3281 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3282 /* Page is shifted left, PHY expects (page x 32) */ 3283 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3284 page); 3285 3286 if (ret_val) 3287 goto release; 3288 } 3289 3290 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3291 data); 3292 3293 release: 3294 hw->phy.ops.release(hw); 3295 return ret_val; 3296 } 3297 3298 /** 3299 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 3300 * @hw: pointer to the HW structure 3301 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 3302 * 3303 * Assumes semaphore already acquired and phy_reg points to a valid memory 3304 * address to store contents of the BM_WUC_ENABLE_REG register. 3305 **/ 3306 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3307 { 3308 s32 ret_val; 3309 u16 temp; 3310 3311 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm"); 3312 3313 if (!phy_reg) 3314 return -E1000_ERR_PARAM; 3315 3316 /* All page select, port ctrl and wakeup registers use phy address 1 */ 3317 hw->phy.addr = 1; 3318 3319 /* Select Port Control Registers page */ 3320 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3321 if (ret_val) { 3322 DEBUGOUT("Could not set Port Control page\n"); 3323 return ret_val; 3324 } 3325 3326 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3327 if (ret_val) { 3328 DEBUGOUT2("Could not read PHY register %d.%d\n", 3329 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3330 return ret_val; 3331 } 3332 3333 /* Enable both PHY wakeup mode and Wakeup register page writes. 3334 * Prevent a power state change by disabling ME and Host PHY wakeup. 3335 */ 3336 temp = *phy_reg; 3337 temp |= BM_WUC_ENABLE_BIT; 3338 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 3339 3340 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 3341 if (ret_val) { 3342 DEBUGOUT2("Could not write PHY register %d.%d\n", 3343 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3344 return ret_val; 3345 } 3346 3347 /* Select Host Wakeup Registers page - caller now able to write 3348 * registers on the Wakeup registers page 3349 */ 3350 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 3351 } 3352 3353 /** 3354 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 3355 * @hw: pointer to the HW structure 3356 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 3357 * 3358 * Restore BM_WUC_ENABLE_REG to its original value. 3359 * 3360 * Assumes semaphore already acquired and *phy_reg is the contents of the 3361 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 3362 * caller. 3363 **/ 3364 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3365 { 3366 s32 ret_val; 3367 3368 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm"); 3369 3370 if (!phy_reg) 3371 return -E1000_ERR_PARAM; 3372 3373 /* Select Port Control Registers page */ 3374 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3375 if (ret_val) { 3376 DEBUGOUT("Could not set Port Control page\n"); 3377 return ret_val; 3378 } 3379 3380 /* Restore 769.17 to its original value */ 3381 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 3382 if (ret_val) 3383 DEBUGOUT2("Could not restore PHY register %d.%d\n", 3384 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3385 3386 return ret_val; 3387 } 3388 3389 /** 3390 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 3391 * @hw: pointer to the HW structure 3392 * @offset: register offset to be read or written 3393 * @data: pointer to the data to read or write 3394 * @read: determines if operation is read or write 3395 * @page_set: BM_WUC_PAGE already set and access enabled 3396 * 3397 * Read the PHY register at offset and store the retrieved information in 3398 * data, or write data to PHY register at offset. Note the procedure to 3399 * access the PHY wakeup registers is different than reading the other PHY 3400 * registers. It works as such: 3401 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 3402 * 2) Set page to 800 for host (801 if we were manageability) 3403 * 3) Write the address using the address opcode (0x11) 3404 * 4) Read or write the data using the data opcode (0x12) 3405 * 5) Restore 769.17.2 to its original value 3406 * 3407 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 3408 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 3409 * 3410 * Assumes semaphore is already acquired. When page_set==true, assumes 3411 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 3412 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 3413 **/ 3414 STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 3415 u16 *data, bool read, bool page_set) 3416 { 3417 s32 ret_val; 3418 u16 reg = BM_PHY_REG_NUM(offset); 3419 u16 page = BM_PHY_REG_PAGE(offset); 3420 u16 phy_reg = 0; 3421 3422 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 3423 3424 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 3425 if ((hw->mac.type == e1000_pchlan) && 3426 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 3427 DEBUGOUT1("Attempting to access page %d while gig enabled.\n", 3428 page); 3429 3430 if (!page_set) { 3431 /* Enable access to PHY wakeup registers */ 3432 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3433 if (ret_val) { 3434 DEBUGOUT("Could not enable PHY wakeup reg access\n"); 3435 return ret_val; 3436 } 3437 } 3438 3439 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg); 3440 3441 /* Write the Wakeup register page offset value using opcode 0x11 */ 3442 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 3443 if (ret_val) { 3444 DEBUGOUT1("Could not write address opcode to page %d\n", page); 3445 return ret_val; 3446 } 3447 3448 if (read) { 3449 /* Read the Wakeup register page value using opcode 0x12 */ 3450 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3451 data); 3452 } else { 3453 /* Write the Wakeup register page value using opcode 0x12 */ 3454 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3455 *data); 3456 } 3457 3458 if (ret_val) { 3459 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg); 3460 return ret_val; 3461 } 3462 3463 if (!page_set) 3464 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3465 3466 return ret_val; 3467 } 3468 3469 /** 3470 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 3471 * @hw: pointer to the HW structure 3472 * 3473 * In the case of a PHY power down to save power, or to turn off link during a 3474 * driver unload, or wake on lan is not enabled, restore the link to previous 3475 * settings. 3476 **/ 3477 void e1000_power_up_phy_copper(struct e1000_hw *hw) 3478 { 3479 u16 mii_reg = 0; 3480 3481 /* The PHY will retain its settings across a power down/up cycle */ 3482 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3483 mii_reg &= ~MII_CR_POWER_DOWN; 3484 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3485 } 3486 3487 /** 3488 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 3489 * @hw: pointer to the HW structure 3490 * 3491 * In the case of a PHY power down to save power, or to turn off link during a 3492 * driver unload, or wake on lan is not enabled, restore the link to previous 3493 * settings. 3494 **/ 3495 void e1000_power_down_phy_copper(struct e1000_hw *hw) 3496 { 3497 u16 mii_reg = 0; 3498 3499 /* The PHY will retain its settings across a power down/up cycle */ 3500 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3501 mii_reg |= MII_CR_POWER_DOWN; 3502 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3503 msec_delay(1); 3504 } 3505 3506 /** 3507 * __e1000_read_phy_reg_hv - Read HV PHY register 3508 * @hw: pointer to the HW structure 3509 * @offset: register offset to be read 3510 * @data: pointer to the read data 3511 * @locked: semaphore has already been acquired or not 3512 * @page_set: BM_WUC_PAGE already set and access enabled 3513 * 3514 * Acquires semaphore, if necessary, then reads the PHY register at offset 3515 * and stores the retrieved information in data. Release any acquired 3516 * semaphore before exiting. 3517 **/ 3518 STATIC s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 3519 bool locked, bool page_set) 3520 { 3521 s32 ret_val; 3522 u16 page = BM_PHY_REG_PAGE(offset); 3523 u16 reg = BM_PHY_REG_NUM(offset); 3524 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3525 3526 DEBUGFUNC("__e1000_read_phy_reg_hv"); 3527 3528 if (!locked) { 3529 ret_val = hw->phy.ops.acquire(hw); 3530 if (ret_val) 3531 return ret_val; 3532 } 3533 /* Page 800 works differently than the rest so it has its own func */ 3534 if (page == BM_WUC_PAGE) { 3535 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3536 true, page_set); 3537 goto out; 3538 } 3539 3540 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3541 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3542 data, true); 3543 goto out; 3544 } 3545 3546 if (!page_set) { 3547 if (page == HV_INTC_FC_PAGE_START) 3548 page = 0; 3549 3550 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3551 /* Page is shifted left, PHY expects (page x 32) */ 3552 ret_val = e1000_set_page_igp(hw, 3553 (page << IGP_PAGE_SHIFT)); 3554 3555 hw->phy.addr = phy_addr; 3556 3557 if (ret_val) 3558 goto out; 3559 } 3560 } 3561 3562 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3563 page << IGP_PAGE_SHIFT, reg); 3564 3565 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3566 data); 3567 out: 3568 if (!locked) 3569 hw->phy.ops.release(hw); 3570 3571 return ret_val; 3572 } 3573 3574 /** 3575 * e1000_read_phy_reg_hv - Read HV PHY register 3576 * @hw: pointer to the HW structure 3577 * @offset: register offset to be read 3578 * @data: pointer to the read data 3579 * 3580 * Acquires semaphore then reads the PHY register at offset and stores 3581 * the retrieved information in data. Release the acquired semaphore 3582 * before exiting. 3583 **/ 3584 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3585 { 3586 return __e1000_read_phy_reg_hv(hw, offset, data, false, false); 3587 } 3588 3589 /** 3590 * e1000_read_phy_reg_hv_locked - Read HV PHY register 3591 * @hw: pointer to the HW structure 3592 * @offset: register offset to be read 3593 * @data: pointer to the read data 3594 * 3595 * Reads the PHY register at offset and stores the retrieved information 3596 * in data. Assumes semaphore already acquired. 3597 **/ 3598 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3599 { 3600 return __e1000_read_phy_reg_hv(hw, offset, data, true, false); 3601 } 3602 3603 /** 3604 * e1000_read_phy_reg_page_hv - Read HV PHY register 3605 * @hw: pointer to the HW structure 3606 * @offset: register offset to write to 3607 * @data: data to write at register offset 3608 * 3609 * Reads the PHY register at offset and stores the retrieved information 3610 * in data. Assumes semaphore already acquired and page already set. 3611 **/ 3612 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3613 { 3614 return __e1000_read_phy_reg_hv(hw, offset, data, true, true); 3615 } 3616 3617 /** 3618 * __e1000_write_phy_reg_hv - Write HV PHY register 3619 * @hw: pointer to the HW structure 3620 * @offset: register offset to write to 3621 * @data: data to write at register offset 3622 * @locked: semaphore has already been acquired or not 3623 * @page_set: BM_WUC_PAGE already set and access enabled 3624 * 3625 * Acquires semaphore, if necessary, then writes the data to PHY register 3626 * at the offset. Release any acquired semaphores before exiting. 3627 **/ 3628 STATIC s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3629 bool locked, bool page_set) 3630 { 3631 s32 ret_val; 3632 u16 page = BM_PHY_REG_PAGE(offset); 3633 u16 reg = BM_PHY_REG_NUM(offset); 3634 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3635 3636 DEBUGFUNC("__e1000_write_phy_reg_hv"); 3637 3638 if (!locked) { 3639 ret_val = hw->phy.ops.acquire(hw); 3640 if (ret_val) 3641 return ret_val; 3642 } 3643 /* Page 800 works differently than the rest so it has its own func */ 3644 if (page == BM_WUC_PAGE) { 3645 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3646 false, page_set); 3647 goto out; 3648 } 3649 3650 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3651 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3652 &data, false); 3653 goto out; 3654 } 3655 3656 if (!page_set) { 3657 if (page == HV_INTC_FC_PAGE_START) 3658 page = 0; 3659 3660 /* Workaround MDIO accesses being disabled after entering IEEE 3661 * Power Down (when bit 11 of the PHY Control register is set) 3662 */ 3663 if ((hw->phy.type == e1000_phy_82578) && 3664 (hw->phy.revision >= 1) && 3665 (hw->phy.addr == 2) && 3666 !(MAX_PHY_REG_ADDRESS & reg) && 3667 (data & (1 << 11))) { 3668 u16 data2 = 0x7EFF; 3669 ret_val = e1000_access_phy_debug_regs_hv(hw, 3670 (1 << 6) | 0x3, 3671 &data2, false); 3672 if (ret_val) 3673 goto out; 3674 } 3675 3676 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3677 /* Page is shifted left, PHY expects (page x 32) */ 3678 ret_val = e1000_set_page_igp(hw, 3679 (page << IGP_PAGE_SHIFT)); 3680 3681 hw->phy.addr = phy_addr; 3682 3683 if (ret_val) 3684 goto out; 3685 } 3686 } 3687 3688 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3689 page << IGP_PAGE_SHIFT, reg); 3690 3691 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3692 data); 3693 3694 out: 3695 if (!locked) 3696 hw->phy.ops.release(hw); 3697 3698 return ret_val; 3699 } 3700 3701 /** 3702 * e1000_write_phy_reg_hv - Write HV PHY register 3703 * @hw: pointer to the HW structure 3704 * @offset: register offset to write to 3705 * @data: data to write at register offset 3706 * 3707 * Acquires semaphore then writes the data to PHY register at the offset. 3708 * Release the acquired semaphores before exiting. 3709 **/ 3710 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3711 { 3712 return __e1000_write_phy_reg_hv(hw, offset, data, false, false); 3713 } 3714 3715 /** 3716 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3717 * @hw: pointer to the HW structure 3718 * @offset: register offset to write to 3719 * @data: data to write at register offset 3720 * 3721 * Writes the data to PHY register at the offset. Assumes semaphore 3722 * already acquired. 3723 **/ 3724 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3725 { 3726 return __e1000_write_phy_reg_hv(hw, offset, data, true, false); 3727 } 3728 3729 /** 3730 * e1000_write_phy_reg_page_hv - Write HV PHY register 3731 * @hw: pointer to the HW structure 3732 * @offset: register offset to write to 3733 * @data: data to write at register offset 3734 * 3735 * Writes the data to PHY register at the offset. Assumes semaphore 3736 * already acquired and page already set. 3737 **/ 3738 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 3739 { 3740 return __e1000_write_phy_reg_hv(hw, offset, data, true, true); 3741 } 3742 3743 /** 3744 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3745 * @page: page to be accessed 3746 **/ 3747 STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page) 3748 { 3749 u32 phy_addr = 2; 3750 3751 if (page >= HV_INTC_FC_PAGE_START) 3752 phy_addr = 1; 3753 3754 return phy_addr; 3755 } 3756 3757 /** 3758 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3759 * @hw: pointer to the HW structure 3760 * @offset: register offset to be read or written 3761 * @data: pointer to the data to be read or written 3762 * @read: determines if operation is read or write 3763 * 3764 * Reads the PHY register at offset and stores the retreived information 3765 * in data. Assumes semaphore already acquired. Note that the procedure 3766 * to access these regs uses the address port and data port to read/write. 3767 * These accesses done with PHY address 2 and without using pages. 3768 **/ 3769 STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3770 u16 *data, bool read) 3771 { 3772 s32 ret_val; 3773 u32 addr_reg; 3774 u32 data_reg; 3775 3776 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3777 3778 /* This takes care of the difference with desktop vs mobile phy */ 3779 addr_reg = ((hw->phy.type == e1000_phy_82578) ? 3780 I82578_ADDR_REG : I82577_ADDR_REG); 3781 data_reg = addr_reg + 1; 3782 3783 /* All operations in this function are phy address 2 */ 3784 hw->phy.addr = 2; 3785 3786 /* masking with 0x3F to remove the page from offset */ 3787 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3788 if (ret_val) { 3789 DEBUGOUT("Could not write the Address Offset port register\n"); 3790 return ret_val; 3791 } 3792 3793 /* Read or write the data value next */ 3794 if (read) 3795 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3796 else 3797 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3798 3799 if (ret_val) 3800 DEBUGOUT("Could not access the Data port register\n"); 3801 3802 return ret_val; 3803 } 3804 3805 /** 3806 * e1000_link_stall_workaround_hv - Si workaround 3807 * @hw: pointer to the HW structure 3808 * 3809 * This function works around a Si bug where the link partner can get 3810 * a link up indication before the PHY does. If small packets are sent 3811 * by the link partner they can be placed in the packet buffer without 3812 * being properly accounted for by the PHY and will stall preventing 3813 * further packets from being received. The workaround is to clear the 3814 * packet buffer after the PHY detects link up. 3815 **/ 3816 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3817 { 3818 s32 ret_val = E1000_SUCCESS; 3819 u16 data; 3820 3821 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3822 3823 if (hw->phy.type != e1000_phy_82578) 3824 return E1000_SUCCESS; 3825 3826 /* Do not apply workaround if in PHY loopback bit 14 set */ 3827 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3828 if (data & PHY_CONTROL_LB) 3829 return E1000_SUCCESS; 3830 3831 /* check if link is up and at 1Gbps */ 3832 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3833 if (ret_val) 3834 return ret_val; 3835 3836 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3837 BM_CS_STATUS_SPEED_MASK); 3838 3839 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3840 BM_CS_STATUS_SPEED_1000)) 3841 return E1000_SUCCESS; 3842 3843 msec_delay(200); 3844 3845 /* flush the packets in the fifo buffer */ 3846 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3847 (HV_MUX_DATA_CTRL_GEN_TO_MAC | 3848 HV_MUX_DATA_CTRL_FORCE_SPEED)); 3849 if (ret_val) 3850 return ret_val; 3851 3852 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3853 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3854 } 3855 3856 /** 3857 * e1000_check_polarity_82577 - Checks the polarity. 3858 * @hw: pointer to the HW structure 3859 * 3860 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3861 * 3862 * Polarity is determined based on the PHY specific status register. 3863 **/ 3864 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3865 { 3866 struct e1000_phy_info *phy = &hw->phy; 3867 s32 ret_val; 3868 u16 data; 3869 3870 DEBUGFUNC("e1000_check_polarity_82577"); 3871 3872 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3873 3874 if (!ret_val) 3875 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY) 3876 ? e1000_rev_polarity_reversed 3877 : e1000_rev_polarity_normal); 3878 3879 return ret_val; 3880 } 3881 3882 /** 3883 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3884 * @hw: pointer to the HW structure 3885 * 3886 * Calls the PHY setup function to force speed and duplex. 3887 **/ 3888 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3889 { 3890 struct e1000_phy_info *phy = &hw->phy; 3891 s32 ret_val; 3892 u16 phy_data; 3893 bool link; 3894 3895 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3896 3897 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3898 if (ret_val) 3899 return ret_val; 3900 3901 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3902 3903 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3904 if (ret_val) 3905 return ret_val; 3906 3907 usec_delay(1); 3908 3909 if (phy->autoneg_wait_to_complete) { 3910 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3911 3912 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3913 100000, &link); 3914 if (ret_val) 3915 return ret_val; 3916 3917 if (!link) 3918 DEBUGOUT("Link taking longer than expected.\n"); 3919 3920 /* Try once more */ 3921 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3922 100000, &link); 3923 } 3924 3925 return ret_val; 3926 } 3927 3928 /** 3929 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3930 * @hw: pointer to the HW structure 3931 * 3932 * Read PHY status to determine if link is up. If link is up, then 3933 * set/determine 10base-T extended distance and polarity correction. Read 3934 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3935 * determine on the cable length, local and remote receiver. 3936 **/ 3937 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3938 { 3939 struct e1000_phy_info *phy = &hw->phy; 3940 s32 ret_val; 3941 u16 data; 3942 bool link; 3943 3944 DEBUGFUNC("e1000_get_phy_info_82577"); 3945 3946 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3947 if (ret_val) 3948 return ret_val; 3949 3950 if (!link) { 3951 DEBUGOUT("Phy info is only valid if link is up\n"); 3952 return -E1000_ERR_CONFIG; 3953 } 3954 3955 phy->polarity_correction = true; 3956 3957 ret_val = e1000_check_polarity_82577(hw); 3958 if (ret_val) 3959 return ret_val; 3960 3961 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3962 if (ret_val) 3963 return ret_val; 3964 3965 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); 3966 3967 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3968 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3969 ret_val = hw->phy.ops.get_cable_length(hw); 3970 if (ret_val) 3971 return ret_val; 3972 3973 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3974 if (ret_val) 3975 return ret_val; 3976 3977 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3978 ? e1000_1000t_rx_status_ok 3979 : e1000_1000t_rx_status_not_ok; 3980 3981 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3982 ? e1000_1000t_rx_status_ok 3983 : e1000_1000t_rx_status_not_ok; 3984 } else { 3985 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3986 phy->local_rx = e1000_1000t_rx_status_undefined; 3987 phy->remote_rx = e1000_1000t_rx_status_undefined; 3988 } 3989 3990 return E1000_SUCCESS; 3991 } 3992 3993 /** 3994 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3995 * @hw: pointer to the HW structure 3996 * 3997 * Reads the diagnostic status register and verifies result is valid before 3998 * placing it in the phy_cable_length field. 3999 **/ 4000 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 4001 { 4002 struct e1000_phy_info *phy = &hw->phy; 4003 s32 ret_val; 4004 u16 phy_data, length; 4005 4006 DEBUGFUNC("e1000_get_cable_length_82577"); 4007 4008 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 4009 if (ret_val) 4010 return ret_val; 4011 4012 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 4013 I82577_DSTATUS_CABLE_LENGTH_SHIFT); 4014 4015 if (length == E1000_CABLE_LENGTH_UNDEFINED) 4016 return -E1000_ERR_PHY; 4017 4018 phy->cable_length = length; 4019 4020 return E1000_SUCCESS; 4021 } 4022 4023 /** 4024 * e1000_write_phy_reg_gs40g - Write GS40G PHY register 4025 * @hw: pointer to the HW structure 4026 * @offset: register offset to write to 4027 * @data: data to write at register offset 4028 * 4029 * Acquires semaphore, if necessary, then writes the data to PHY register 4030 * at the offset. Release any acquired semaphores before exiting. 4031 **/ 4032 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 4033 { 4034 s32 ret_val; 4035 u16 page = offset >> GS40G_PAGE_SHIFT; 4036 4037 DEBUGFUNC("e1000_write_phy_reg_gs40g"); 4038 4039 offset = offset & GS40G_OFFSET_MASK; 4040 ret_val = hw->phy.ops.acquire(hw); 4041 if (ret_val) 4042 return ret_val; 4043 4044 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4045 if (ret_val) 4046 goto release; 4047 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 4048 4049 release: 4050 hw->phy.ops.release(hw); 4051 return ret_val; 4052 } 4053 4054 /** 4055 * e1000_read_phy_reg_gs40g - Read GS40G PHY register 4056 * @hw: pointer to the HW structure 4057 * @offset: lower half is register offset to read to 4058 * upper half is page to use. 4059 * @data: data to read at register offset 4060 * 4061 * Acquires semaphore, if necessary, then reads the data in the PHY register 4062 * at the offset. Release any acquired semaphores before exiting. 4063 **/ 4064 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 4065 { 4066 s32 ret_val; 4067 u16 page = offset >> GS40G_PAGE_SHIFT; 4068 4069 DEBUGFUNC("e1000_read_phy_reg_gs40g"); 4070 4071 offset = offset & GS40G_OFFSET_MASK; 4072 ret_val = hw->phy.ops.acquire(hw); 4073 if (ret_val) 4074 return ret_val; 4075 4076 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4077 if (ret_val) 4078 goto release; 4079 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 4080 4081 release: 4082 hw->phy.ops.release(hw); 4083 return ret_val; 4084 } 4085 4086 /** 4087 * e1000_read_phy_reg_mphy - Read mPHY control register 4088 * @hw: pointer to the HW structure 4089 * @address: address to be read 4090 * @data: pointer to the read data 4091 * 4092 * Reads the mPHY control register in the PHY at offset and stores the 4093 * information read to data. 4094 **/ 4095 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data) 4096 { 4097 u32 mphy_ctrl = 0; 4098 bool locked = false; 4099 bool ready; 4100 4101 DEBUGFUNC("e1000_read_phy_reg_mphy"); 4102 4103 /* Check if mPHY is ready to read/write operations */ 4104 ready = e1000_is_mphy_ready(hw); 4105 if (!ready) 4106 return -E1000_ERR_PHY; 4107 4108 /* Check if mPHY access is disabled and enable it if so */ 4109 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4110 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) { 4111 locked = true; 4112 ready = e1000_is_mphy_ready(hw); 4113 if (!ready) 4114 return -E1000_ERR_PHY; 4115 mphy_ctrl |= E1000_MPHY_ENA_ACCESS; 4116 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4117 } 4118 4119 /* Set the address that we want to read */ 4120 ready = e1000_is_mphy_ready(hw); 4121 if (!ready) 4122 return -E1000_ERR_PHY; 4123 4124 /* We mask address, because we want to use only current lane */ 4125 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK & 4126 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) | 4127 (address & E1000_MPHY_ADDRESS_MASK); 4128 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4129 4130 /* Read data from the address */ 4131 ready = e1000_is_mphy_ready(hw); 4132 if (!ready) 4133 return -E1000_ERR_PHY; 4134 *data = E1000_READ_REG(hw, E1000_MPHY_DATA); 4135 4136 /* Disable access to mPHY if it was originally disabled */ 4137 if (locked) { 4138 ready = e1000_is_mphy_ready(hw); 4139 if (!ready) 4140 return -E1000_ERR_PHY; 4141 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, 4142 E1000_MPHY_DIS_ACCESS); 4143 } 4144 4145 return E1000_SUCCESS; 4146 } 4147 4148 /** 4149 * e1000_write_phy_reg_mphy - Write mPHY control register 4150 * @hw: pointer to the HW structure 4151 * @address: address to write to 4152 * @data: data to write to register at offset 4153 * @line_override: used when we want to use different line than default one 4154 * 4155 * Writes data to mPHY control register. 4156 **/ 4157 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data, 4158 bool line_override) 4159 { 4160 u32 mphy_ctrl = 0; 4161 bool locked = false; 4162 bool ready; 4163 4164 DEBUGFUNC("e1000_write_phy_reg_mphy"); 4165 4166 /* Check if mPHY is ready to read/write operations */ 4167 ready = e1000_is_mphy_ready(hw); 4168 if (!ready) 4169 return -E1000_ERR_PHY; 4170 4171 /* Check if mPHY access is disabled and enable it if so */ 4172 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4173 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) { 4174 locked = true; 4175 ready = e1000_is_mphy_ready(hw); 4176 if (!ready) 4177 return -E1000_ERR_PHY; 4178 mphy_ctrl |= E1000_MPHY_ENA_ACCESS; 4179 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4180 } 4181 4182 /* Set the address that we want to read */ 4183 ready = e1000_is_mphy_ready(hw); 4184 if (!ready) 4185 return -E1000_ERR_PHY; 4186 4187 /* We mask address, because we want to use only current lane */ 4188 if (line_override) 4189 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE; 4190 else 4191 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE; 4192 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) | 4193 (address & E1000_MPHY_ADDRESS_MASK); 4194 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4195 4196 /* Read data from the address */ 4197 ready = e1000_is_mphy_ready(hw); 4198 if (!ready) 4199 return -E1000_ERR_PHY; 4200 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data); 4201 4202 /* Disable access to mPHY if it was originally disabled */ 4203 if (locked) { 4204 ready = e1000_is_mphy_ready(hw); 4205 if (!ready) 4206 return -E1000_ERR_PHY; 4207 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, 4208 E1000_MPHY_DIS_ACCESS); 4209 } 4210 4211 return E1000_SUCCESS; 4212 } 4213 4214 /** 4215 * e1000_is_mphy_ready - Check if mPHY control register is not busy 4216 * @hw: pointer to the HW structure 4217 * 4218 * Returns mPHY control register status. 4219 **/ 4220 bool e1000_is_mphy_ready(struct e1000_hw *hw) 4221 { 4222 u16 retry_count = 0; 4223 u32 mphy_ctrl = 0; 4224 bool ready = false; 4225 4226 while (retry_count < 2) { 4227 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4228 if (mphy_ctrl & E1000_MPHY_BUSY) { 4229 usec_delay(20); 4230 retry_count++; 4231 continue; 4232 } 4233 ready = true; 4234 break; 4235 } 4236 4237 if (!ready) 4238 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n"); 4239 4240 return ready; 4241 } 4242 4243 /** 4244 * __e1000_access_xmdio_reg - Read/write XMDIO register 4245 * @hw: pointer to the HW structure 4246 * @address: XMDIO address to program 4247 * @dev_addr: device address to program 4248 * @data: pointer to value to read/write from/to the XMDIO address 4249 * @read: boolean flag to indicate read or write 4250 **/ 4251 STATIC s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address, 4252 u8 dev_addr, u16 *data, bool read) 4253 { 4254 s32 ret_val; 4255 4256 DEBUGFUNC("__e1000_access_xmdio_reg"); 4257 4258 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr); 4259 if (ret_val) 4260 return ret_val; 4261 4262 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address); 4263 if (ret_val) 4264 return ret_val; 4265 4266 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA | 4267 dev_addr); 4268 if (ret_val) 4269 return ret_val; 4270 4271 if (read) 4272 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data); 4273 else 4274 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data); 4275 if (ret_val) 4276 return ret_val; 4277 4278 /* Recalibrate the device back to 0 */ 4279 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0); 4280 if (ret_val) 4281 return ret_val; 4282 4283 return ret_val; 4284 } 4285 4286 /** 4287 * e1000_read_xmdio_reg - Read XMDIO register 4288 * @hw: pointer to the HW structure 4289 * @addr: XMDIO address to program 4290 * @dev_addr: device address to program 4291 * @data: value to be read from the EMI address 4292 **/ 4293 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data) 4294 { 4295 DEBUGFUNC("e1000_read_xmdio_reg"); 4296 4297 return __e1000_access_xmdio_reg(hw, addr, dev_addr, data, true); 4298 } 4299 4300 /** 4301 * e1000_write_xmdio_reg - Write XMDIO register 4302 * @hw: pointer to the HW structure 4303 * @addr: XMDIO address to program 4304 * @dev_addr: device address to program 4305 * @data: value to be written to the XMDIO address 4306 **/ 4307 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data) 4308 { 4309 DEBUGFUNC("e1000_write_xmdio_reg"); 4310 4311 return __e1000_access_xmdio_reg(hw, addr, dev_addr, &data, 4312 false); 4313 } 4314