1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001 - 2015 Intel Corporation 3 */ 4 5 #include "e1000_api.h" 6 7 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 8 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 9 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw); 10 STATIC int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 11 12 /** 13 * e1000_init_mac_ops_generic - Initialize MAC function pointers 14 * @hw: pointer to the HW structure 15 * 16 * Setups up the function pointers to no-op functions 17 **/ 18 void e1000_init_mac_ops_generic(struct e1000_hw *hw) 19 { 20 struct e1000_mac_info *mac = &hw->mac; 21 DEBUGFUNC("e1000_init_mac_ops_generic"); 22 23 /* General Setup */ 24 mac->ops.init_params = e1000_null_ops_generic; 25 mac->ops.init_hw = e1000_null_ops_generic; 26 mac->ops.reset_hw = e1000_null_ops_generic; 27 mac->ops.setup_physical_interface = e1000_null_ops_generic; 28 mac->ops.get_bus_info = e1000_null_ops_generic; 29 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 30 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 31 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 32 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 33 /* LED */ 34 mac->ops.cleanup_led = e1000_null_ops_generic; 35 mac->ops.setup_led = e1000_null_ops_generic; 36 mac->ops.blink_led = e1000_null_ops_generic; 37 mac->ops.led_on = e1000_null_ops_generic; 38 mac->ops.led_off = e1000_null_ops_generic; 39 /* LINK */ 40 mac->ops.setup_link = e1000_null_ops_generic; 41 mac->ops.get_link_up_info = e1000_null_link_info; 42 mac->ops.check_for_link = e1000_null_ops_generic; 43 /* Management */ 44 mac->ops.check_mng_mode = e1000_null_mng_mode; 45 /* VLAN, MC, etc. */ 46 mac->ops.update_mc_addr_list = e1000_null_update_mc; 47 mac->ops.clear_vfta = e1000_null_mac_generic; 48 mac->ops.write_vfta = e1000_null_write_vfta; 49 mac->ops.rar_set = e1000_rar_set_generic; 50 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 51 } 52 53 /** 54 * e1000_null_ops_generic - No-op function, returns 0 55 * @hw: pointer to the HW structure 56 **/ 57 s32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw) 58 { 59 DEBUGFUNC("e1000_null_ops_generic"); 60 UNREFERENCED_1PARAMETER(hw); 61 return E1000_SUCCESS; 62 } 63 64 /** 65 * e1000_null_mac_generic - No-op function, return void 66 * @hw: pointer to the HW structure 67 **/ 68 void e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw) 69 { 70 DEBUGFUNC("e1000_null_mac_generic"); 71 UNREFERENCED_1PARAMETER(hw); 72 return; 73 } 74 75 /** 76 * e1000_null_link_info - No-op function, return 0 77 * @hw: pointer to the HW structure 78 **/ 79 s32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw, 80 u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d) 81 { 82 DEBUGFUNC("e1000_null_link_info"); 83 UNREFERENCED_3PARAMETER(hw, s, d); 84 return E1000_SUCCESS; 85 } 86 87 /** 88 * e1000_null_mng_mode - No-op function, return false 89 * @hw: pointer to the HW structure 90 **/ 91 bool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw) 92 { 93 DEBUGFUNC("e1000_null_mng_mode"); 94 UNREFERENCED_1PARAMETER(hw); 95 return false; 96 } 97 98 /** 99 * e1000_null_update_mc - No-op function, return void 100 * @hw: pointer to the HW structure 101 **/ 102 void e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw, 103 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 104 { 105 DEBUGFUNC("e1000_null_update_mc"); 106 UNREFERENCED_3PARAMETER(hw, h, a); 107 return; 108 } 109 110 /** 111 * e1000_null_write_vfta - No-op function, return void 112 * @hw: pointer to the HW structure 113 **/ 114 void e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw, 115 u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b) 116 { 117 DEBUGFUNC("e1000_null_write_vfta"); 118 UNREFERENCED_3PARAMETER(hw, a, b); 119 return; 120 } 121 122 /** 123 * e1000_null_rar_set - No-op function, return 0 124 * @hw: pointer to the HW structure 125 **/ 126 int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw, 127 u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a) 128 { 129 DEBUGFUNC("e1000_null_rar_set"); 130 UNREFERENCED_3PARAMETER(hw, h, a); 131 return E1000_SUCCESS; 132 } 133 134 /** 135 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 136 * @hw: pointer to the HW structure 137 * 138 * Determines and stores the system bus information for a particular 139 * network interface. The following bus information is determined and stored: 140 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 141 **/ 142 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 143 { 144 struct e1000_mac_info *mac = &hw->mac; 145 struct e1000_bus_info *bus = &hw->bus; 146 u32 status = E1000_READ_REG(hw, E1000_STATUS); 147 s32 ret_val = E1000_SUCCESS; 148 149 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 150 151 /* PCI or PCI-X? */ 152 bus->type = (status & E1000_STATUS_PCIX_MODE) 153 ? e1000_bus_type_pcix 154 : e1000_bus_type_pci; 155 156 /* Bus speed */ 157 if (bus->type == e1000_bus_type_pci) { 158 bus->speed = (status & E1000_STATUS_PCI66) 159 ? e1000_bus_speed_66 160 : e1000_bus_speed_33; 161 } else { 162 switch (status & E1000_STATUS_PCIX_SPEED) { 163 case E1000_STATUS_PCIX_SPEED_66: 164 bus->speed = e1000_bus_speed_66; 165 break; 166 case E1000_STATUS_PCIX_SPEED_100: 167 bus->speed = e1000_bus_speed_100; 168 break; 169 case E1000_STATUS_PCIX_SPEED_133: 170 bus->speed = e1000_bus_speed_133; 171 break; 172 default: 173 bus->speed = e1000_bus_speed_reserved; 174 break; 175 } 176 } 177 178 /* Bus width */ 179 bus->width = (status & E1000_STATUS_BUS64) 180 ? e1000_bus_width_64 181 : e1000_bus_width_32; 182 183 /* Which PCI(-X) function? */ 184 mac->ops.set_lan_id(hw); 185 186 return ret_val; 187 } 188 189 /** 190 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 191 * @hw: pointer to the HW structure 192 * 193 * Determines and stores the system bus information for a particular 194 * network interface. The following bus information is determined and stored: 195 * bus speed, bus width, type (PCIe), and PCIe function. 196 **/ 197 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 198 { 199 struct e1000_mac_info *mac = &hw->mac; 200 struct e1000_bus_info *bus = &hw->bus; 201 s32 ret_val; 202 u16 pcie_link_status; 203 204 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 205 206 bus->type = e1000_bus_type_pci_express; 207 208 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS, 209 &pcie_link_status); 210 if (ret_val) { 211 bus->width = e1000_bus_width_unknown; 212 bus->speed = e1000_bus_speed_unknown; 213 } else { 214 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) { 215 case PCIE_LINK_SPEED_2500: 216 bus->speed = e1000_bus_speed_2500; 217 break; 218 case PCIE_LINK_SPEED_5000: 219 bus->speed = e1000_bus_speed_5000; 220 break; 221 default: 222 bus->speed = e1000_bus_speed_unknown; 223 break; 224 } 225 226 bus->width = (enum e1000_bus_width)((pcie_link_status & 227 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 228 } 229 230 mac->ops.set_lan_id(hw); 231 232 return E1000_SUCCESS; 233 } 234 235 /** 236 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 237 * 238 * @hw: pointer to the HW structure 239 * 240 * Determines the LAN function id by reading memory-mapped registers 241 * and swaps the port value if requested. 242 **/ 243 STATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 244 { 245 struct e1000_bus_info *bus = &hw->bus; 246 u32 reg; 247 248 /* The status register reports the correct function number 249 * for the device regardless of function swap state. 250 */ 251 reg = E1000_READ_REG(hw, E1000_STATUS); 252 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 253 } 254 255 /** 256 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices 257 * @hw: pointer to the HW structure 258 * 259 * Determines the LAN function id by reading PCI config space. 260 **/ 261 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw) 262 { 263 struct e1000_bus_info *bus = &hw->bus; 264 u16 pci_header_type; 265 u32 status; 266 267 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 268 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 269 status = E1000_READ_REG(hw, E1000_STATUS); 270 bus->func = (status & E1000_STATUS_FUNC_MASK) 271 >> E1000_STATUS_FUNC_SHIFT; 272 } else { 273 bus->func = 0; 274 } 275 } 276 277 /** 278 * e1000_set_lan_id_single_port - Set LAN id for a single port device 279 * @hw: pointer to the HW structure 280 * 281 * Sets the LAN function id to zero for a single port device. 282 **/ 283 void e1000_set_lan_id_single_port(struct e1000_hw *hw) 284 { 285 struct e1000_bus_info *bus = &hw->bus; 286 287 bus->func = 0; 288 } 289 290 /** 291 * e1000_clear_vfta_generic - Clear VLAN filter table 292 * @hw: pointer to the HW structure 293 * 294 * Clears the register array which contains the VLAN filter table by 295 * setting all the values to 0. 296 **/ 297 void e1000_clear_vfta_generic(struct e1000_hw *hw) 298 { 299 u32 offset; 300 301 DEBUGFUNC("e1000_clear_vfta_generic"); 302 303 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 304 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 305 E1000_WRITE_FLUSH(hw); 306 } 307 } 308 309 /** 310 * e1000_write_vfta_generic - Write value to VLAN filter table 311 * @hw: pointer to the HW structure 312 * @offset: register offset in VLAN filter table 313 * @value: register value written to VLAN filter table 314 * 315 * Writes value at the given offset in the register array which stores 316 * the VLAN filter table. 317 **/ 318 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 319 { 320 DEBUGFUNC("e1000_write_vfta_generic"); 321 322 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 323 E1000_WRITE_FLUSH(hw); 324 } 325 326 /** 327 * e1000_init_rx_addrs_generic - Initialize receive address's 328 * @hw: pointer to the HW structure 329 * @rar_count: receive address registers 330 * 331 * Setup the receive address registers by setting the base receive address 332 * register to the devices MAC address and clearing all the other receive 333 * address registers to 0. 334 **/ 335 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 336 { 337 u32 i; 338 u8 mac_addr[ETH_ADDR_LEN] = {0}; 339 340 DEBUGFUNC("e1000_init_rx_addrs_generic"); 341 342 /* Setup the receive address */ 343 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 344 345 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 346 347 /* Zero out the other (rar_entry_count - 1) receive addresses */ 348 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 349 for (i = 1; i < rar_count; i++) 350 hw->mac.ops.rar_set(hw, mac_addr, i); 351 } 352 353 /** 354 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 355 * @hw: pointer to the HW structure 356 * 357 * Checks the nvm for an alternate MAC address. An alternate MAC address 358 * can be setup by pre-boot software and must be treated like a permanent 359 * address and must override the actual permanent MAC address. If an 360 * alternate MAC address is found it is programmed into RAR0, replacing 361 * the permanent address that was installed into RAR0 by the Si on reset. 362 * This function will return SUCCESS unless it encounters an error while 363 * reading the EEPROM. 364 **/ 365 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 366 { 367 u32 i; 368 s32 ret_val; 369 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 370 u8 alt_mac_addr[ETH_ADDR_LEN]; 371 372 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 373 374 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 375 if (ret_val) 376 return ret_val; 377 378 /* not supported on older hardware or 82573 */ 379 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573)) 380 return E1000_SUCCESS; 381 382 /* Alternate MAC address is handled by the option ROM for 82580 383 * and newer. SW support not required. 384 */ 385 if (hw->mac.type >= e1000_82580) 386 return E1000_SUCCESS; 387 388 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 389 &nvm_alt_mac_addr_offset); 390 if (ret_val) { 391 DEBUGOUT("NVM Read Error\n"); 392 return ret_val; 393 } 394 395 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 396 (nvm_alt_mac_addr_offset == 0x0000)) 397 /* There is no Alternate MAC Address */ 398 return E1000_SUCCESS; 399 400 if (hw->bus.func == E1000_FUNC_1) 401 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 402 if (hw->bus.func == E1000_FUNC_2) 403 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 404 405 if (hw->bus.func == E1000_FUNC_3) 406 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 407 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 408 offset = nvm_alt_mac_addr_offset + (i >> 1); 409 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 410 if (ret_val) { 411 DEBUGOUT("NVM Read Error\n"); 412 return ret_val; 413 } 414 415 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 416 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 417 } 418 419 /* if multicast bit is set, the alternate address will not be used */ 420 if (alt_mac_addr[0] & 0x01) { 421 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 422 return E1000_SUCCESS; 423 } 424 425 /* We have a valid alternate MAC address, and we want to treat it the 426 * same as the normal permanent MAC address stored by the HW into the 427 * RAR. Do this by mapping this address into RAR0. 428 */ 429 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 430 431 return E1000_SUCCESS; 432 } 433 434 /** 435 * e1000_rar_set_generic - Set receive address register 436 * @hw: pointer to the HW structure 437 * @addr: pointer to the receive address 438 * @index: receive address array register 439 * 440 * Sets the receive address array register at index to the address passed 441 * in by addr. 442 **/ 443 STATIC int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 444 { 445 u32 rar_low, rar_high; 446 447 DEBUGFUNC("e1000_rar_set_generic"); 448 449 /* HW expects these in little endian so we reverse the byte order 450 * from network order (big endian) to little endian 451 */ 452 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 453 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 454 455 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 456 457 /* If MAC address zero, no need to set the AV bit */ 458 if (rar_low || rar_high) 459 rar_high |= E1000_RAH_AV; 460 461 /* Some bridges will combine consecutive 32-bit writes into 462 * a single burst write, which will malfunction on some parts. 463 * The flushes avoid this. 464 */ 465 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 466 E1000_WRITE_FLUSH(hw); 467 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 468 E1000_WRITE_FLUSH(hw); 469 470 return E1000_SUCCESS; 471 } 472 473 /** 474 * e1000_hash_mc_addr_generic - Generate a multicast hash value 475 * @hw: pointer to the HW structure 476 * @mc_addr: pointer to a multicast address 477 * 478 * Generates a multicast address hash value which is used to determine 479 * the multicast filter table array address and new table value. 480 **/ 481 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 482 { 483 u32 hash_value, hash_mask; 484 u8 bit_shift = 0; 485 486 DEBUGFUNC("e1000_hash_mc_addr_generic"); 487 488 /* Register count multiplied by bits per register */ 489 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 490 491 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 492 * where 0xFF would still fall within the hash mask. 493 */ 494 while (hash_mask >> bit_shift != 0xFF) 495 bit_shift++; 496 497 /* The portion of the address that is used for the hash table 498 * is determined by the mc_filter_type setting. 499 * The algorithm is such that there is a total of 8 bits of shifting. 500 * The bit_shift for a mc_filter_type of 0 represents the number of 501 * left-shifts where the MSB of mc_addr[5] would still fall within 502 * the hash_mask. Case 0 does this exactly. Since there are a total 503 * of 8 bits of shifting, then mc_addr[4] will shift right the 504 * remaining number of bits. Thus 8 - bit_shift. The rest of the 505 * cases are a variation of this algorithm...essentially raising the 506 * number of bits to shift mc_addr[5] left, while still keeping the 507 * 8-bit shifting total. 508 * 509 * For example, given the following Destination MAC Address and an 510 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 511 * we can see that the bit_shift for case 0 is 4. These are the hash 512 * values resulting from each mc_filter_type... 513 * [0] [1] [2] [3] [4] [5] 514 * 01 AA 00 12 34 56 515 * LSB MSB 516 * 517 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 518 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 519 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 520 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 521 */ 522 switch (hw->mac.mc_filter_type) { 523 default: 524 case 0: 525 break; 526 case 1: 527 bit_shift += 1; 528 break; 529 case 2: 530 bit_shift += 2; 531 break; 532 case 3: 533 bit_shift += 4; 534 break; 535 } 536 537 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 538 (((u16) mc_addr[5]) << bit_shift))); 539 540 return hash_value; 541 } 542 543 /** 544 * e1000_update_mc_addr_list_generic - Update Multicast addresses 545 * @hw: pointer to the HW structure 546 * @mc_addr_list: array of multicast addresses to program 547 * @mc_addr_count: number of multicast addresses to program 548 * 549 * Updates entire Multicast Table Array. 550 * The caller must have a packed mc_addr_list of multicast addresses. 551 **/ 552 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 553 u8 *mc_addr_list, u32 mc_addr_count) 554 { 555 u32 hash_value, hash_bit, hash_reg; 556 int i; 557 558 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 559 560 /* clear mta_shadow */ 561 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 562 563 /* update mta_shadow from mc_addr_list */ 564 for (i = 0; (u32) i < mc_addr_count; i++) { 565 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 566 567 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 568 hash_bit = hash_value & 0x1F; 569 570 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 571 mc_addr_list += (ETH_ADDR_LEN); 572 } 573 574 /* replace the entire MTA table */ 575 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 576 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 577 E1000_WRITE_FLUSH(hw); 578 } 579 580 /** 581 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 582 * @hw: pointer to the HW structure 583 * 584 * In certain situations, a system BIOS may report that the PCIx maximum 585 * memory read byte count (MMRBC) value is higher than than the actual 586 * value. We check the PCIx command register with the current PCIx status 587 * register. 588 **/ 589 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 590 { 591 u16 cmd_mmrbc; 592 u16 pcix_cmd; 593 u16 pcix_stat_hi_word; 594 u16 stat_mmrbc; 595 596 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 597 598 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 599 if (hw->bus.type != e1000_bus_type_pcix) 600 return; 601 602 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 603 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 604 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 605 PCIX_COMMAND_MMRBC_SHIFT; 606 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 607 PCIX_STATUS_HI_MMRBC_SHIFT; 608 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 609 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 610 if (cmd_mmrbc > stat_mmrbc) { 611 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 612 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 613 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 614 } 615 } 616 617 /** 618 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 619 * @hw: pointer to the HW structure 620 * 621 * Clears the base hardware counters by reading the counter registers. 622 **/ 623 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 624 { 625 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 626 627 E1000_READ_REG(hw, E1000_CRCERRS); 628 E1000_READ_REG(hw, E1000_SYMERRS); 629 E1000_READ_REG(hw, E1000_MPC); 630 E1000_READ_REG(hw, E1000_SCC); 631 E1000_READ_REG(hw, E1000_ECOL); 632 E1000_READ_REG(hw, E1000_MCC); 633 E1000_READ_REG(hw, E1000_LATECOL); 634 E1000_READ_REG(hw, E1000_COLC); 635 E1000_READ_REG(hw, E1000_DC); 636 E1000_READ_REG(hw, E1000_SEC); 637 E1000_READ_REG(hw, E1000_RLEC); 638 E1000_READ_REG(hw, E1000_XONRXC); 639 E1000_READ_REG(hw, E1000_XONTXC); 640 E1000_READ_REG(hw, E1000_XOFFRXC); 641 E1000_READ_REG(hw, E1000_XOFFTXC); 642 E1000_READ_REG(hw, E1000_FCRUC); 643 E1000_READ_REG(hw, E1000_GPRC); 644 E1000_READ_REG(hw, E1000_BPRC); 645 E1000_READ_REG(hw, E1000_MPRC); 646 E1000_READ_REG(hw, E1000_GPTC); 647 E1000_READ_REG(hw, E1000_GORCL); 648 E1000_READ_REG(hw, E1000_GORCH); 649 E1000_READ_REG(hw, E1000_GOTCL); 650 E1000_READ_REG(hw, E1000_GOTCH); 651 E1000_READ_REG(hw, E1000_RNBC); 652 E1000_READ_REG(hw, E1000_RUC); 653 E1000_READ_REG(hw, E1000_RFC); 654 E1000_READ_REG(hw, E1000_ROC); 655 E1000_READ_REG(hw, E1000_RJC); 656 E1000_READ_REG(hw, E1000_TORL); 657 E1000_READ_REG(hw, E1000_TORH); 658 E1000_READ_REG(hw, E1000_TOTL); 659 E1000_READ_REG(hw, E1000_TOTH); 660 E1000_READ_REG(hw, E1000_TPR); 661 E1000_READ_REG(hw, E1000_TPT); 662 E1000_READ_REG(hw, E1000_MPTC); 663 E1000_READ_REG(hw, E1000_BPTC); 664 } 665 666 /** 667 * e1000_check_for_copper_link_generic - Check for link (Copper) 668 * @hw: pointer to the HW structure 669 * 670 * Checks to see of the link status of the hardware has changed. If a 671 * change in link status has been detected, then we read the PHY registers 672 * to get the current speed/duplex if link exists. 673 **/ 674 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw) 675 { 676 struct e1000_mac_info *mac = &hw->mac; 677 s32 ret_val; 678 bool link; 679 680 DEBUGFUNC("e1000_check_for_copper_link"); 681 682 /* We only want to go out to the PHY registers to see if Auto-Neg 683 * has completed and/or if our link status has changed. The 684 * get_link_status flag is set upon receiving a Link Status 685 * Change or Rx Sequence Error interrupt. 686 */ 687 if (!mac->get_link_status) 688 return E1000_SUCCESS; 689 690 /* First we want to see if the MII Status Register reports 691 * link. If so, then we want to get the current speed/duplex 692 * of the PHY. 693 */ 694 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 695 if (ret_val) 696 return ret_val; 697 698 if (!link) 699 return E1000_SUCCESS; /* No link detected */ 700 701 mac->get_link_status = false; 702 703 /* Check if there was DownShift, must be checked 704 * immediately after link-up 705 */ 706 e1000_check_downshift_generic(hw); 707 708 /* If we are forcing speed/duplex, then we simply return since 709 * we have already determined whether we have link or not. 710 */ 711 if (!mac->autoneg) 712 return -E1000_ERR_CONFIG; 713 714 /* Auto-Neg is enabled. Auto Speed Detection takes care 715 * of MAC speed/duplex configuration. So we only need to 716 * configure Collision Distance in the MAC. 717 */ 718 mac->ops.config_collision_dist(hw); 719 720 /* Configure Flow Control now that Auto-Neg has completed. 721 * First, we need to restore the desired flow control 722 * settings because we may have had to re-autoneg with a 723 * different link partner. 724 */ 725 ret_val = e1000_config_fc_after_link_up_generic(hw); 726 if (ret_val) 727 DEBUGOUT("Error configuring flow control\n"); 728 729 return ret_val; 730 } 731 732 /** 733 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 734 * @hw: pointer to the HW structure 735 * 736 * Checks for link up on the hardware. If link is not up and we have 737 * a signal, then we need to force link up. 738 **/ 739 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 740 { 741 struct e1000_mac_info *mac = &hw->mac; 742 u32 rxcw; 743 u32 ctrl; 744 u32 status; 745 s32 ret_val; 746 747 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 748 749 ctrl = E1000_READ_REG(hw, E1000_CTRL); 750 status = E1000_READ_REG(hw, E1000_STATUS); 751 rxcw = E1000_READ_REG(hw, E1000_RXCW); 752 753 /* If we don't have link (auto-negotiation failed or link partner 754 * cannot auto-negotiate), the cable is plugged in (we have signal), 755 * and our link partner is not trying to auto-negotiate with us (we 756 * are receiving idles or data), we need to force link up. We also 757 * need to give auto-negotiation time to complete, in case the cable 758 * was just plugged in. The autoneg_failed flag does this. 759 */ 760 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 761 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 762 !(rxcw & E1000_RXCW_C)) { 763 if (!mac->autoneg_failed) { 764 mac->autoneg_failed = true; 765 return E1000_SUCCESS; 766 } 767 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 768 769 /* Disable auto-negotiation in the TXCW register */ 770 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 771 772 /* Force link-up and also force full-duplex. */ 773 ctrl = E1000_READ_REG(hw, E1000_CTRL); 774 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 775 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 776 777 /* Configure Flow Control after forcing link up. */ 778 ret_val = e1000_config_fc_after_link_up_generic(hw); 779 if (ret_val) { 780 DEBUGOUT("Error configuring flow control\n"); 781 return ret_val; 782 } 783 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 784 /* If we are forcing link and we are receiving /C/ ordered 785 * sets, re-enable auto-negotiation in the TXCW register 786 * and disable forced link in the Device Control register 787 * in an attempt to auto-negotiate with our link partner. 788 */ 789 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 790 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 791 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 792 793 mac->serdes_has_link = true; 794 } 795 796 return E1000_SUCCESS; 797 } 798 799 /** 800 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 801 * @hw: pointer to the HW structure 802 * 803 * Checks for link up on the hardware. If link is not up and we have 804 * a signal, then we need to force link up. 805 **/ 806 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 807 { 808 struct e1000_mac_info *mac = &hw->mac; 809 u32 rxcw; 810 u32 ctrl; 811 u32 status; 812 s32 ret_val; 813 814 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 815 816 ctrl = E1000_READ_REG(hw, E1000_CTRL); 817 status = E1000_READ_REG(hw, E1000_STATUS); 818 rxcw = E1000_READ_REG(hw, E1000_RXCW); 819 820 /* If we don't have link (auto-negotiation failed or link partner 821 * cannot auto-negotiate), and our link partner is not trying to 822 * auto-negotiate with us (we are receiving idles or data), 823 * we need to force link up. We also need to give auto-negotiation 824 * time to complete. 825 */ 826 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 827 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 828 if (!mac->autoneg_failed) { 829 mac->autoneg_failed = true; 830 return E1000_SUCCESS; 831 } 832 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 833 834 /* Disable auto-negotiation in the TXCW register */ 835 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 836 837 /* Force link-up and also force full-duplex. */ 838 ctrl = E1000_READ_REG(hw, E1000_CTRL); 839 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 840 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 841 842 /* Configure Flow Control after forcing link up. */ 843 ret_val = e1000_config_fc_after_link_up_generic(hw); 844 if (ret_val) { 845 DEBUGOUT("Error configuring flow control\n"); 846 return ret_val; 847 } 848 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 849 /* If we are forcing link and we are receiving /C/ ordered 850 * sets, re-enable auto-negotiation in the TXCW register 851 * and disable forced link in the Device Control register 852 * in an attempt to auto-negotiate with our link partner. 853 */ 854 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 855 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 856 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 857 858 mac->serdes_has_link = true; 859 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 860 /* If we force link for non-auto-negotiation switch, check 861 * link status based on MAC synchronization for internal 862 * serdes media type. 863 */ 864 /* SYNCH bit and IV bit are sticky. */ 865 usec_delay(10); 866 rxcw = E1000_READ_REG(hw, E1000_RXCW); 867 if (rxcw & E1000_RXCW_SYNCH) { 868 if (!(rxcw & E1000_RXCW_IV)) { 869 mac->serdes_has_link = true; 870 DEBUGOUT("SERDES: Link up - forced.\n"); 871 } 872 } else { 873 mac->serdes_has_link = false; 874 DEBUGOUT("SERDES: Link down - force failed.\n"); 875 } 876 } 877 878 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 879 status = E1000_READ_REG(hw, E1000_STATUS); 880 if (status & E1000_STATUS_LU) { 881 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 882 usec_delay(10); 883 rxcw = E1000_READ_REG(hw, E1000_RXCW); 884 if (rxcw & E1000_RXCW_SYNCH) { 885 if (!(rxcw & E1000_RXCW_IV)) { 886 mac->serdes_has_link = true; 887 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n"); 888 } else { 889 mac->serdes_has_link = false; 890 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n"); 891 } 892 } else { 893 mac->serdes_has_link = false; 894 DEBUGOUT("SERDES: Link down - no sync.\n"); 895 } 896 } else { 897 mac->serdes_has_link = false; 898 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 899 } 900 } 901 902 return E1000_SUCCESS; 903 } 904 905 /** 906 * e1000_set_default_fc_generic - Set flow control default values 907 * @hw: pointer to the HW structure 908 * 909 * Read the EEPROM for the default values for flow control and store the 910 * values. 911 **/ 912 s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 913 { 914 s32 ret_val; 915 u16 nvm_data; 916 u16 nvm_offset = 0; 917 918 DEBUGFUNC("e1000_set_default_fc_generic"); 919 920 /* Read and store word 0x0F of the EEPROM. This word contains bits 921 * that determine the hardware's default PAUSE (flow control) mode, 922 * a bit that determines whether the HW defaults to enabling or 923 * disabling auto-negotiation, and the direction of the 924 * SW defined pins. If there is no SW over-ride of the flow 925 * control setting, then the variable hw->fc will 926 * be initialized based on a value in the EEPROM. 927 */ 928 if (hw->mac.type == e1000_i350) { 929 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func); 930 ret_val = hw->nvm.ops.read(hw, 931 NVM_INIT_CONTROL2_REG + 932 nvm_offset, 933 1, &nvm_data); 934 } else { 935 ret_val = hw->nvm.ops.read(hw, 936 NVM_INIT_CONTROL2_REG, 937 1, &nvm_data); 938 } 939 940 941 if (ret_val) { 942 DEBUGOUT("NVM Read Error\n"); 943 return ret_val; 944 } 945 946 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK)) 947 hw->fc.requested_mode = e1000_fc_none; 948 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 949 NVM_WORD0F_ASM_DIR) 950 hw->fc.requested_mode = e1000_fc_tx_pause; 951 else 952 hw->fc.requested_mode = e1000_fc_full; 953 954 return E1000_SUCCESS; 955 } 956 957 /** 958 * e1000_setup_link_generic - Setup flow control and link settings 959 * @hw: pointer to the HW structure 960 * 961 * Determines which flow control settings to use, then configures flow 962 * control. Calls the appropriate media-specific link configuration 963 * function. Assuming the adapter has a valid link partner, a valid link 964 * should be established. Assumes the hardware has previously been reset 965 * and the transmitter and receiver are not enabled. 966 **/ 967 s32 e1000_setup_link_generic(struct e1000_hw *hw) 968 { 969 s32 ret_val; 970 971 DEBUGFUNC("e1000_setup_link_generic"); 972 973 /* In the case of the phy reset being blocked, we already have a link. 974 * We do not need to set it up again. 975 */ 976 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 977 return E1000_SUCCESS; 978 979 /* If requested flow control is set to default, set flow control 980 * based on the EEPROM flow control settings. 981 */ 982 if (hw->fc.requested_mode == e1000_fc_default) { 983 ret_val = e1000_set_default_fc_generic(hw); 984 if (ret_val) 985 return ret_val; 986 } 987 988 /* Save off the requested flow control mode for use later. Depending 989 * on the link partner's capabilities, we may or may not use this mode. 990 */ 991 hw->fc.current_mode = hw->fc.requested_mode; 992 993 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 994 hw->fc.current_mode); 995 996 /* Call the necessary media_type subroutine to configure the link. */ 997 ret_val = hw->mac.ops.setup_physical_interface(hw); 998 if (ret_val) 999 return ret_val; 1000 1001 /* Initialize the flow control address, type, and PAUSE timer 1002 * registers to their default values. This is done even if flow 1003 * control is disabled, because it does not hurt anything to 1004 * initialize these registers. 1005 */ 1006 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1007 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 1008 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1009 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 1010 1011 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 1012 1013 return e1000_set_fc_watermarks_generic(hw); 1014 } 1015 1016 /** 1017 * e1000_commit_fc_settings_generic - Configure flow control 1018 * @hw: pointer to the HW structure 1019 * 1020 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1021 * base on the flow control settings in e1000_mac_info. 1022 **/ 1023 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1024 { 1025 struct e1000_mac_info *mac = &hw->mac; 1026 u32 txcw; 1027 1028 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1029 1030 /* Check for a software override of the flow control settings, and 1031 * setup the device accordingly. If auto-negotiation is enabled, then 1032 * software will have to set the "PAUSE" bits to the correct value in 1033 * the Transmit Config Word Register (TXCW) and re-start auto- 1034 * negotiation. However, if auto-negotiation is disabled, then 1035 * software will have to manually configure the two flow control enable 1036 * bits in the CTRL register. 1037 * 1038 * The possible values of the "fc" parameter are: 1039 * 0: Flow control is completely disabled 1040 * 1: Rx flow control is enabled (we can receive pause frames, 1041 * but not send pause frames). 1042 * 2: Tx flow control is enabled (we can send pause frames but we 1043 * do not support receiving pause frames). 1044 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1045 */ 1046 switch (hw->fc.current_mode) { 1047 case e1000_fc_none: 1048 /* Flow control completely disabled by a software over-ride. */ 1049 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1050 break; 1051 case e1000_fc_rx_pause: 1052 /* Rx Flow control is enabled and Tx Flow control is disabled 1053 * by a software over-ride. Since there really isn't a way to 1054 * advertise that we are capable of Rx Pause ONLY, we will 1055 * advertise that we support both symmetric and asymmetric Rx 1056 * PAUSE. Later, we will disable the adapter's ability to send 1057 * PAUSE frames. 1058 */ 1059 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1060 break; 1061 case e1000_fc_tx_pause: 1062 /* Tx Flow control is enabled, and Rx Flow control is disabled, 1063 * by a software over-ride. 1064 */ 1065 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1066 break; 1067 case e1000_fc_full: 1068 /* Flow control (both Rx and Tx) is enabled by a software 1069 * over-ride. 1070 */ 1071 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1072 break; 1073 default: 1074 DEBUGOUT("Flow control param set incorrectly\n"); 1075 return -E1000_ERR_CONFIG; 1076 break; 1077 } 1078 1079 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1080 mac->txcw = txcw; 1081 1082 return E1000_SUCCESS; 1083 } 1084 1085 /** 1086 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1087 * @hw: pointer to the HW structure 1088 * 1089 * Polls for link up by reading the status register, if link fails to come 1090 * up with auto-negotiation, then the link is forced if a signal is detected. 1091 **/ 1092 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1093 { 1094 struct e1000_mac_info *mac = &hw->mac; 1095 u32 i, status; 1096 s32 ret_val; 1097 1098 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1099 1100 /* If we have a signal (the cable is plugged in, or assumed true for 1101 * serdes media) then poll for a "Link-Up" indication in the Device 1102 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1103 * seconds (Auto-negotiation should complete in less than 500 1104 * milliseconds even if the other end is doing it in SW). 1105 */ 1106 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1107 msec_delay(10); 1108 status = E1000_READ_REG(hw, E1000_STATUS); 1109 if (status & E1000_STATUS_LU) 1110 break; 1111 } 1112 if (i == FIBER_LINK_UP_LIMIT) { 1113 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1114 mac->autoneg_failed = true; 1115 /* AutoNeg failed to achieve a link, so we'll call 1116 * mac->check_for_link. This routine will force the 1117 * link up if we detect a signal. This will allow us to 1118 * communicate with non-autonegotiating link partners. 1119 */ 1120 ret_val = mac->ops.check_for_link(hw); 1121 if (ret_val) { 1122 DEBUGOUT("Error while checking for link\n"); 1123 return ret_val; 1124 } 1125 mac->autoneg_failed = false; 1126 } else { 1127 mac->autoneg_failed = false; 1128 DEBUGOUT("Valid Link Found\n"); 1129 } 1130 1131 return E1000_SUCCESS; 1132 } 1133 1134 /** 1135 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 1136 * @hw: pointer to the HW structure 1137 * 1138 * Configures collision distance and flow control for fiber and serdes 1139 * links. Upon successful setup, poll for link. 1140 **/ 1141 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 1142 { 1143 u32 ctrl; 1144 s32 ret_val; 1145 1146 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 1147 1148 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1149 1150 /* Take the link out of reset */ 1151 ctrl &= ~E1000_CTRL_LRST; 1152 1153 hw->mac.ops.config_collision_dist(hw); 1154 1155 ret_val = e1000_commit_fc_settings_generic(hw); 1156 if (ret_val) 1157 return ret_val; 1158 1159 /* Since auto-negotiation is enabled, take the link out of reset (the 1160 * link will be in reset, because we previously reset the chip). This 1161 * will restart auto-negotiation. If auto-negotiation is successful 1162 * then the link-up status bit will be set and the flow control enable 1163 * bits (RFCE and TFCE) will be set according to their negotiated value. 1164 */ 1165 DEBUGOUT("Auto-negotiation enabled\n"); 1166 1167 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1168 E1000_WRITE_FLUSH(hw); 1169 msec_delay(1); 1170 1171 /* For these adapters, the SW definable pin 1 is set when the optics 1172 * detect a signal. If we have a signal, then poll for a "Link-Up" 1173 * indication. 1174 */ 1175 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1176 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 1177 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1178 } else { 1179 DEBUGOUT("No signal detected\n"); 1180 } 1181 1182 return ret_val; 1183 } 1184 1185 /** 1186 * e1000_config_collision_dist_generic - Configure collision distance 1187 * @hw: pointer to the HW structure 1188 * 1189 * Configures the collision distance to the default value and is used 1190 * during link setup. 1191 **/ 1192 STATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw) 1193 { 1194 u32 tctl; 1195 1196 DEBUGFUNC("e1000_config_collision_dist_generic"); 1197 1198 tctl = E1000_READ_REG(hw, E1000_TCTL); 1199 1200 tctl &= ~E1000_TCTL_COLD; 1201 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1202 1203 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1204 E1000_WRITE_FLUSH(hw); 1205 } 1206 1207 /** 1208 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1209 * @hw: pointer to the HW structure 1210 * 1211 * Sets the flow control high/low threshold (watermark) registers. If 1212 * flow control XON frame transmission is enabled, then set XON frame 1213 * transmission as well. 1214 **/ 1215 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1216 { 1217 u32 fcrtl = 0, fcrth = 0; 1218 1219 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1220 1221 /* Set the flow control receive threshold registers. Normally, 1222 * these registers will be set to a default threshold that may be 1223 * adjusted later by the driver's runtime code. However, if the 1224 * ability to transmit pause frames is not enabled, then these 1225 * registers will be set to 0. 1226 */ 1227 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1228 /* We need to set up the Receive Threshold high and low water 1229 * marks as well as (optionally) enabling the transmission of 1230 * XON frames. 1231 */ 1232 fcrtl = hw->fc.low_water; 1233 if (hw->fc.send_xon) 1234 fcrtl |= E1000_FCRTL_XONE; 1235 1236 fcrth = hw->fc.high_water; 1237 } 1238 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1239 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1240 1241 return E1000_SUCCESS; 1242 } 1243 1244 /** 1245 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1246 * @hw: pointer to the HW structure 1247 * 1248 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1249 * device control register to reflect the adapter settings. TFCE and RFCE 1250 * need to be explicitly set by software when a copper PHY is used because 1251 * autonegotiation is managed by the PHY rather than the MAC. Software must 1252 * also configure these bits when link is forced on a fiber connection. 1253 **/ 1254 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw) 1255 { 1256 u32 ctrl; 1257 1258 DEBUGFUNC("e1000_force_mac_fc_generic"); 1259 1260 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1261 1262 /* Because we didn't get link via the internal auto-negotiation 1263 * mechanism (we either forced link or we got link via PHY 1264 * auto-neg), we have to manually enable/disable transmit an 1265 * receive flow control. 1266 * 1267 * The "Case" statement below enables/disable flow control 1268 * according to the "hw->fc.current_mode" parameter. 1269 * 1270 * The possible values of the "fc" parameter are: 1271 * 0: Flow control is completely disabled 1272 * 1: Rx flow control is enabled (we can receive pause 1273 * frames but not send pause frames). 1274 * 2: Tx flow control is enabled (we can send pause frames 1275 * frames but we do not receive pause frames). 1276 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1277 * other: No other values should be possible at this point. 1278 */ 1279 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1280 1281 switch (hw->fc.current_mode) { 1282 case e1000_fc_none: 1283 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1284 break; 1285 case e1000_fc_rx_pause: 1286 ctrl &= (~E1000_CTRL_TFCE); 1287 ctrl |= E1000_CTRL_RFCE; 1288 break; 1289 case e1000_fc_tx_pause: 1290 ctrl &= (~E1000_CTRL_RFCE); 1291 ctrl |= E1000_CTRL_TFCE; 1292 break; 1293 case e1000_fc_full: 1294 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1295 break; 1296 default: 1297 DEBUGOUT("Flow control param set incorrectly\n"); 1298 return -E1000_ERR_CONFIG; 1299 } 1300 1301 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1302 1303 return E1000_SUCCESS; 1304 } 1305 1306 /** 1307 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1308 * @hw: pointer to the HW structure 1309 * 1310 * Checks the status of auto-negotiation after link up to ensure that the 1311 * speed and duplex were not forced. If the link needed to be forced, then 1312 * flow control needs to be forced also. If auto-negotiation is enabled 1313 * and did not fail, then we configure flow control based on our link 1314 * partner. 1315 **/ 1316 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1317 { 1318 struct e1000_mac_info *mac = &hw->mac; 1319 s32 ret_val = E1000_SUCCESS; 1320 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg; 1321 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1322 u16 speed, duplex; 1323 1324 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1325 1326 /* Check for the case where we have fiber media and auto-neg failed 1327 * so we had to force link. In this case, we need to force the 1328 * configuration of the MAC to match the "fc" parameter. 1329 */ 1330 if (mac->autoneg_failed) { 1331 if (hw->phy.media_type == e1000_media_type_fiber || 1332 hw->phy.media_type == e1000_media_type_internal_serdes) 1333 ret_val = e1000_force_mac_fc_generic(hw); 1334 } else { 1335 if (hw->phy.media_type == e1000_media_type_copper) 1336 ret_val = e1000_force_mac_fc_generic(hw); 1337 } 1338 1339 if (ret_val) { 1340 DEBUGOUT("Error forcing flow control settings\n"); 1341 return ret_val; 1342 } 1343 1344 /* Check for the case where we have copper media and auto-neg is 1345 * enabled. In this case, we need to check and see if Auto-Neg 1346 * has completed, and if so, how the PHY and link partner has 1347 * flow control configured. 1348 */ 1349 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1350 /* Read the MII Status Register and check to see if AutoNeg 1351 * has completed. We read this twice because this reg has 1352 * some "sticky" (latched) bits. 1353 */ 1354 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1355 if (ret_val) 1356 return ret_val; 1357 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1358 if (ret_val) 1359 return ret_val; 1360 1361 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1362 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 1363 return ret_val; 1364 } 1365 1366 /* The AutoNeg process has completed, so we now need to 1367 * read both the Auto Negotiation Advertisement 1368 * Register (Address 4) and the Auto_Negotiation Base 1369 * Page Ability Register (Address 5) to determine how 1370 * flow control was negotiated. 1371 */ 1372 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1373 &mii_nway_adv_reg); 1374 if (ret_val) 1375 return ret_val; 1376 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1377 &mii_nway_lp_ability_reg); 1378 if (ret_val) 1379 return ret_val; 1380 1381 /* Two bits in the Auto Negotiation Advertisement Register 1382 * (Address 4) and two bits in the Auto Negotiation Base 1383 * Page Ability Register (Address 5) determine flow control 1384 * for both the PHY and the link partner. The following 1385 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1386 * 1999, describes these PAUSE resolution bits and how flow 1387 * control is determined based upon these settings. 1388 * NOTE: DC = Don't Care 1389 * 1390 * LOCAL DEVICE | LINK PARTNER 1391 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1392 *-------|---------|-------|---------|-------------------- 1393 * 0 | 0 | DC | DC | e1000_fc_none 1394 * 0 | 1 | 0 | DC | e1000_fc_none 1395 * 0 | 1 | 1 | 0 | e1000_fc_none 1396 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1397 * 1 | 0 | 0 | DC | e1000_fc_none 1398 * 1 | DC | 1 | DC | e1000_fc_full 1399 * 1 | 1 | 0 | 0 | e1000_fc_none 1400 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1401 * 1402 * Are both PAUSE bits set to 1? If so, this implies 1403 * Symmetric Flow Control is enabled at both ends. The 1404 * ASM_DIR bits are irrelevant per the spec. 1405 * 1406 * For Symmetric Flow Control: 1407 * 1408 * LOCAL DEVICE | LINK PARTNER 1409 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1410 *-------|---------|-------|---------|-------------------- 1411 * 1 | DC | 1 | DC | E1000_fc_full 1412 * 1413 */ 1414 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1415 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1416 /* Now we need to check if the user selected Rx ONLY 1417 * of pause frames. In this case, we had to advertise 1418 * FULL flow control because we could not advertise Rx 1419 * ONLY. Hence, we must now check to see if we need to 1420 * turn OFF the TRANSMISSION of PAUSE frames. 1421 */ 1422 if (hw->fc.requested_mode == e1000_fc_full) { 1423 hw->fc.current_mode = e1000_fc_full; 1424 DEBUGOUT("Flow Control = FULL.\n"); 1425 } else { 1426 hw->fc.current_mode = e1000_fc_rx_pause; 1427 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1428 } 1429 } 1430 /* For receiving PAUSE frames ONLY. 1431 * 1432 * LOCAL DEVICE | LINK PARTNER 1433 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1434 *-------|---------|-------|---------|-------------------- 1435 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1436 */ 1437 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1438 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1439 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1440 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1441 hw->fc.current_mode = e1000_fc_tx_pause; 1442 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1443 } 1444 /* For transmitting PAUSE frames ONLY. 1445 * 1446 * LOCAL DEVICE | LINK PARTNER 1447 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1448 *-------|---------|-------|---------|-------------------- 1449 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1450 */ 1451 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1452 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1453 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1454 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1455 hw->fc.current_mode = e1000_fc_rx_pause; 1456 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1457 } else { 1458 /* Per the IEEE spec, at this point flow control 1459 * should be disabled. 1460 */ 1461 hw->fc.current_mode = e1000_fc_none; 1462 DEBUGOUT("Flow Control = NONE.\n"); 1463 } 1464 1465 /* Now we need to do one last check... If we auto- 1466 * negotiated to HALF DUPLEX, flow control should not be 1467 * enabled per IEEE 802.3 spec. 1468 */ 1469 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1470 if (ret_val) { 1471 DEBUGOUT("Error getting link speed and duplex\n"); 1472 return ret_val; 1473 } 1474 1475 if (duplex == HALF_DUPLEX) 1476 hw->fc.current_mode = e1000_fc_none; 1477 1478 /* Now we call a subroutine to actually force the MAC 1479 * controller to use the correct flow control settings. 1480 */ 1481 ret_val = e1000_force_mac_fc_generic(hw); 1482 if (ret_val) { 1483 DEBUGOUT("Error forcing flow control settings\n"); 1484 return ret_val; 1485 } 1486 } 1487 1488 /* Check for the case where we have SerDes media and auto-neg is 1489 * enabled. In this case, we need to check and see if Auto-Neg 1490 * has completed, and if so, how the PHY and link partner has 1491 * flow control configured. 1492 */ 1493 if ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1494 mac->autoneg) { 1495 /* Read the PCS_LSTS and check to see if AutoNeg 1496 * has completed. 1497 */ 1498 pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1499 1500 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) { 1501 DEBUGOUT("PCS Auto Neg has not completed.\n"); 1502 return ret_val; 1503 } 1504 1505 /* The AutoNeg process has completed, so we now need to 1506 * read both the Auto Negotiation Advertisement 1507 * Register (PCS_ANADV) and the Auto_Negotiation Base 1508 * Page Ability Register (PCS_LPAB) to determine how 1509 * flow control was negotiated. 1510 */ 1511 pcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1512 pcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB); 1513 1514 /* Two bits in the Auto Negotiation Advertisement Register 1515 * (PCS_ANADV) and two bits in the Auto Negotiation Base 1516 * Page Ability Register (PCS_LPAB) determine flow control 1517 * for both the PHY and the link partner. The following 1518 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1519 * 1999, describes these PAUSE resolution bits and how flow 1520 * control is determined based upon these settings. 1521 * NOTE: DC = Don't Care 1522 * 1523 * LOCAL DEVICE | LINK PARTNER 1524 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1525 *-------|---------|-------|---------|-------------------- 1526 * 0 | 0 | DC | DC | e1000_fc_none 1527 * 0 | 1 | 0 | DC | e1000_fc_none 1528 * 0 | 1 | 1 | 0 | e1000_fc_none 1529 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1530 * 1 | 0 | 0 | DC | e1000_fc_none 1531 * 1 | DC | 1 | DC | e1000_fc_full 1532 * 1 | 1 | 0 | 0 | e1000_fc_none 1533 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1534 * 1535 * Are both PAUSE bits set to 1? If so, this implies 1536 * Symmetric Flow Control is enabled at both ends. The 1537 * ASM_DIR bits are irrelevant per the spec. 1538 * 1539 * For Symmetric Flow Control: 1540 * 1541 * LOCAL DEVICE | LINK PARTNER 1542 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1543 *-------|---------|-------|---------|-------------------- 1544 * 1 | DC | 1 | DC | e1000_fc_full 1545 * 1546 */ 1547 if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1548 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) { 1549 /* Now we need to check if the user selected Rx ONLY 1550 * of pause frames. In this case, we had to advertise 1551 * FULL flow control because we could not advertise Rx 1552 * ONLY. Hence, we must now check to see if we need to 1553 * turn OFF the TRANSMISSION of PAUSE frames. 1554 */ 1555 if (hw->fc.requested_mode == e1000_fc_full) { 1556 hw->fc.current_mode = e1000_fc_full; 1557 DEBUGOUT("Flow Control = FULL.\n"); 1558 } else { 1559 hw->fc.current_mode = e1000_fc_rx_pause; 1560 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1561 } 1562 } 1563 /* For receiving PAUSE frames ONLY. 1564 * 1565 * LOCAL DEVICE | LINK PARTNER 1566 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1567 *-------|---------|-------|---------|-------------------- 1568 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1569 */ 1570 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) && 1571 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1572 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1573 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1574 hw->fc.current_mode = e1000_fc_tx_pause; 1575 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 1576 } 1577 /* For transmitting PAUSE frames ONLY. 1578 * 1579 * LOCAL DEVICE | LINK PARTNER 1580 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1581 *-------|---------|-------|---------|-------------------- 1582 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1583 */ 1584 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) && 1585 (pcs_adv_reg & E1000_TXCW_ASM_DIR) && 1586 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) && 1587 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) { 1588 hw->fc.current_mode = e1000_fc_rx_pause; 1589 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 1590 } else { 1591 /* Per the IEEE spec, at this point flow control 1592 * should be disabled. 1593 */ 1594 hw->fc.current_mode = e1000_fc_none; 1595 DEBUGOUT("Flow Control = NONE.\n"); 1596 } 1597 1598 /* Now we call a subroutine to actually force the MAC 1599 * controller to use the correct flow control settings. 1600 */ 1601 pcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1602 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1603 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg); 1604 1605 ret_val = e1000_force_mac_fc_generic(hw); 1606 if (ret_val) { 1607 DEBUGOUT("Error forcing flow control settings\n"); 1608 return ret_val; 1609 } 1610 } 1611 1612 return E1000_SUCCESS; 1613 } 1614 1615 /** 1616 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1617 * @hw: pointer to the HW structure 1618 * @speed: stores the current speed 1619 * @duplex: stores the current duplex 1620 * 1621 * Read the status register for the current speed/duplex and store the current 1622 * speed and duplex for copper connections. 1623 **/ 1624 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1625 u16 *duplex) 1626 { 1627 u32 status; 1628 1629 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1630 1631 status = E1000_READ_REG(hw, E1000_STATUS); 1632 if (status & E1000_STATUS_SPEED_1000) { 1633 *speed = SPEED_1000; 1634 DEBUGOUT("1000 Mbs, "); 1635 } else if (status & E1000_STATUS_SPEED_100) { 1636 *speed = SPEED_100; 1637 DEBUGOUT("100 Mbs, "); 1638 } else { 1639 *speed = SPEED_10; 1640 DEBUGOUT("10 Mbs, "); 1641 } 1642 1643 if (status & E1000_STATUS_FD) { 1644 *duplex = FULL_DUPLEX; 1645 DEBUGOUT("Full Duplex\n"); 1646 } else { 1647 *duplex = HALF_DUPLEX; 1648 DEBUGOUT("Half Duplex\n"); 1649 } 1650 1651 return E1000_SUCCESS; 1652 } 1653 1654 /** 1655 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1656 * @hw: pointer to the HW structure 1657 * @speed: stores the current speed 1658 * @duplex: stores the current duplex 1659 * 1660 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1661 * for fiber/serdes links. 1662 **/ 1663 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw, 1664 u16 *speed, u16 *duplex) 1665 { 1666 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1667 UNREFERENCED_1PARAMETER(hw); 1668 1669 *speed = SPEED_1000; 1670 *duplex = FULL_DUPLEX; 1671 1672 return E1000_SUCCESS; 1673 } 1674 1675 /** 1676 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1677 * @hw: pointer to the HW structure 1678 * 1679 * Acquire the HW semaphore to access the PHY or NVM 1680 **/ 1681 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1682 { 1683 u32 swsm; 1684 s32 timeout = hw->nvm.word_size + 1; 1685 s32 i = 0; 1686 1687 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1688 1689 /* Get the SW semaphore */ 1690 while (i < timeout) { 1691 swsm = E1000_READ_REG(hw, E1000_SWSM); 1692 if (!(swsm & E1000_SWSM_SMBI)) 1693 break; 1694 1695 usec_delay(50); 1696 i++; 1697 } 1698 1699 if (i == timeout) { 1700 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1701 return -E1000_ERR_NVM; 1702 } 1703 1704 /* Get the FW semaphore. */ 1705 for (i = 0; i < timeout; i++) { 1706 swsm = E1000_READ_REG(hw, E1000_SWSM); 1707 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1708 1709 /* Semaphore acquired if bit latched */ 1710 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1711 break; 1712 1713 usec_delay(50); 1714 } 1715 1716 if (i == timeout) { 1717 /* Release semaphores */ 1718 e1000_put_hw_semaphore_generic(hw); 1719 DEBUGOUT("Driver can't access the NVM\n"); 1720 return -E1000_ERR_NVM; 1721 } 1722 1723 return E1000_SUCCESS; 1724 } 1725 1726 /** 1727 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1728 * @hw: pointer to the HW structure 1729 * 1730 * Release hardware semaphore used to access the PHY or NVM 1731 **/ 1732 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1733 { 1734 u32 swsm; 1735 1736 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1737 1738 swsm = E1000_READ_REG(hw, E1000_SWSM); 1739 1740 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1741 1742 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1743 } 1744 1745 /** 1746 * e1000_get_auto_rd_done_generic - Check for auto read completion 1747 * @hw: pointer to the HW structure 1748 * 1749 * Check EEPROM for Auto Read done bit. 1750 **/ 1751 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1752 { 1753 s32 i = 0; 1754 1755 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1756 1757 while (i < AUTO_READ_DONE_TIMEOUT) { 1758 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1759 break; 1760 msec_delay(1); 1761 i++; 1762 } 1763 1764 if (i == AUTO_READ_DONE_TIMEOUT) { 1765 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1766 return -E1000_ERR_RESET; 1767 } 1768 1769 return E1000_SUCCESS; 1770 } 1771 1772 /** 1773 * e1000_valid_led_default_generic - Verify a valid default LED config 1774 * @hw: pointer to the HW structure 1775 * @data: pointer to the NVM (EEPROM) 1776 * 1777 * Read the EEPROM for the current default LED configuration. If the 1778 * LED configuration is not valid, set to a valid LED configuration. 1779 **/ 1780 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1781 { 1782 s32 ret_val; 1783 1784 DEBUGFUNC("e1000_valid_led_default_generic"); 1785 1786 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1787 if (ret_val) { 1788 DEBUGOUT("NVM Read Error\n"); 1789 return ret_val; 1790 } 1791 1792 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1793 *data = ID_LED_DEFAULT; 1794 1795 return E1000_SUCCESS; 1796 } 1797 1798 /** 1799 * e1000_id_led_init_generic - 1800 * @hw: pointer to the HW structure 1801 * 1802 **/ 1803 s32 e1000_id_led_init_generic(struct e1000_hw *hw) 1804 { 1805 struct e1000_mac_info *mac = &hw->mac; 1806 s32 ret_val; 1807 const u32 ledctl_mask = 0x000000FF; 1808 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1809 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1810 u16 data, i, temp; 1811 const u16 led_mask = 0x0F; 1812 1813 DEBUGFUNC("e1000_id_led_init_generic"); 1814 1815 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1816 if (ret_val) 1817 return ret_val; 1818 1819 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1820 mac->ledctl_mode1 = mac->ledctl_default; 1821 mac->ledctl_mode2 = mac->ledctl_default; 1822 1823 for (i = 0; i < 4; i++) { 1824 temp = (data >> (i << 2)) & led_mask; 1825 switch (temp) { 1826 case ID_LED_ON1_DEF2: 1827 case ID_LED_ON1_ON2: 1828 case ID_LED_ON1_OFF2: 1829 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1830 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1831 break; 1832 case ID_LED_OFF1_DEF2: 1833 case ID_LED_OFF1_ON2: 1834 case ID_LED_OFF1_OFF2: 1835 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1836 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1837 break; 1838 default: 1839 /* Do nothing */ 1840 break; 1841 } 1842 switch (temp) { 1843 case ID_LED_DEF1_ON2: 1844 case ID_LED_ON1_ON2: 1845 case ID_LED_OFF1_ON2: 1846 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1847 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1848 break; 1849 case ID_LED_DEF1_OFF2: 1850 case ID_LED_ON1_OFF2: 1851 case ID_LED_OFF1_OFF2: 1852 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1853 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1854 break; 1855 default: 1856 /* Do nothing */ 1857 break; 1858 } 1859 } 1860 1861 return E1000_SUCCESS; 1862 } 1863 1864 /** 1865 * e1000_setup_led_generic - Configures SW controllable LED 1866 * @hw: pointer to the HW structure 1867 * 1868 * This prepares the SW controllable LED for use and saves the current state 1869 * of the LED so it can be later restored. 1870 **/ 1871 s32 e1000_setup_led_generic(struct e1000_hw *hw) 1872 { 1873 u32 ledctl; 1874 1875 DEBUGFUNC("e1000_setup_led_generic"); 1876 1877 if (hw->mac.ops.setup_led != e1000_setup_led_generic) 1878 return -E1000_ERR_CONFIG; 1879 1880 if (hw->phy.media_type == e1000_media_type_fiber) { 1881 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1882 hw->mac.ledctl_default = ledctl; 1883 /* Turn off LED0 */ 1884 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1885 E1000_LEDCTL_LED0_MODE_MASK); 1886 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1887 E1000_LEDCTL_LED0_MODE_SHIFT); 1888 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1889 } else if (hw->phy.media_type == e1000_media_type_copper) { 1890 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1891 } 1892 1893 return E1000_SUCCESS; 1894 } 1895 1896 /** 1897 * e1000_cleanup_led_generic - Set LED config to default operation 1898 * @hw: pointer to the HW structure 1899 * 1900 * Remove the current LED configuration and set the LED configuration 1901 * to the default value, saved from the EEPROM. 1902 **/ 1903 s32 e1000_cleanup_led_generic(struct e1000_hw *hw) 1904 { 1905 DEBUGFUNC("e1000_cleanup_led_generic"); 1906 1907 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1908 return E1000_SUCCESS; 1909 } 1910 1911 /** 1912 * e1000_blink_led_generic - Blink LED 1913 * @hw: pointer to the HW structure 1914 * 1915 * Blink the LEDs which are set to be on. 1916 **/ 1917 s32 e1000_blink_led_generic(struct e1000_hw *hw) 1918 { 1919 u32 ledctl_blink = 0; 1920 u32 i; 1921 1922 DEBUGFUNC("e1000_blink_led_generic"); 1923 1924 if (hw->phy.media_type == e1000_media_type_fiber) { 1925 /* always blink LED0 for PCI-E fiber */ 1926 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1927 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1928 } else { 1929 /* Set the blink bit for each LED that's "on" (0x0E) 1930 * (or "off" if inverted) in ledctl_mode2. The blink 1931 * logic in hardware only works when mode is set to "on" 1932 * so it must be changed accordingly when the mode is 1933 * "off" and inverted. 1934 */ 1935 ledctl_blink = hw->mac.ledctl_mode2; 1936 for (i = 0; i < 32; i += 8) { 1937 u32 mode = (hw->mac.ledctl_mode2 >> i) & 1938 E1000_LEDCTL_LED0_MODE_MASK; 1939 u32 led_default = hw->mac.ledctl_default >> i; 1940 1941 if ((!(led_default & E1000_LEDCTL_LED0_IVRT) && 1942 (mode == E1000_LEDCTL_MODE_LED_ON)) || 1943 ((led_default & E1000_LEDCTL_LED0_IVRT) && 1944 (mode == E1000_LEDCTL_MODE_LED_OFF))) { 1945 ledctl_blink &= 1946 ~(E1000_LEDCTL_LED0_MODE_MASK << i); 1947 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK | 1948 E1000_LEDCTL_MODE_LED_ON) << i; 1949 } 1950 } 1951 } 1952 1953 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1954 1955 return E1000_SUCCESS; 1956 } 1957 1958 /** 1959 * e1000_led_on_generic - Turn LED on 1960 * @hw: pointer to the HW structure 1961 * 1962 * Turn LED on. 1963 **/ 1964 s32 e1000_led_on_generic(struct e1000_hw *hw) 1965 { 1966 u32 ctrl; 1967 1968 DEBUGFUNC("e1000_led_on_generic"); 1969 1970 switch (hw->phy.media_type) { 1971 case e1000_media_type_fiber: 1972 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1973 ctrl &= ~E1000_CTRL_SWDPIN0; 1974 ctrl |= E1000_CTRL_SWDPIO0; 1975 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1976 break; 1977 case e1000_media_type_copper: 1978 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1979 break; 1980 default: 1981 break; 1982 } 1983 1984 return E1000_SUCCESS; 1985 } 1986 1987 /** 1988 * e1000_led_off_generic - Turn LED off 1989 * @hw: pointer to the HW structure 1990 * 1991 * Turn LED off. 1992 **/ 1993 s32 e1000_led_off_generic(struct e1000_hw *hw) 1994 { 1995 u32 ctrl; 1996 1997 DEBUGFUNC("e1000_led_off_generic"); 1998 1999 switch (hw->phy.media_type) { 2000 case e1000_media_type_fiber: 2001 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2002 ctrl |= E1000_CTRL_SWDPIN0; 2003 ctrl |= E1000_CTRL_SWDPIO0; 2004 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2005 break; 2006 case e1000_media_type_copper: 2007 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 2008 break; 2009 default: 2010 break; 2011 } 2012 2013 return E1000_SUCCESS; 2014 } 2015 2016 /** 2017 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 2018 * @hw: pointer to the HW structure 2019 * @no_snoop: bitmap of snoop events 2020 * 2021 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 2022 **/ 2023 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 2024 { 2025 u32 gcr; 2026 2027 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 2028 2029 if (hw->bus.type != e1000_bus_type_pci_express) 2030 return; 2031 2032 if (no_snoop) { 2033 gcr = E1000_READ_REG(hw, E1000_GCR); 2034 gcr &= ~(PCIE_NO_SNOOP_ALL); 2035 gcr |= no_snoop; 2036 E1000_WRITE_REG(hw, E1000_GCR, gcr); 2037 } 2038 } 2039 2040 /** 2041 * e1000_disable_pcie_master_generic - Disables PCI-express master access 2042 * @hw: pointer to the HW structure 2043 * 2044 * Returns E1000_SUCCESS if successful, else returns -10 2045 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 2046 * the master requests to be disabled. 2047 * 2048 * Disables PCI-Express master access and verifies there are no pending 2049 * requests. 2050 **/ 2051 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw) 2052 { 2053 u32 ctrl; 2054 s32 timeout = MASTER_DISABLE_TIMEOUT; 2055 2056 DEBUGFUNC("e1000_disable_pcie_master_generic"); 2057 2058 if (hw->bus.type != e1000_bus_type_pci_express) 2059 return E1000_SUCCESS; 2060 2061 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2062 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 2063 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2064 2065 while (timeout) { 2066 if (!(E1000_READ_REG(hw, E1000_STATUS) & 2067 E1000_STATUS_GIO_MASTER_ENABLE) || 2068 E1000_REMOVED(hw->hw_addr)) 2069 break; 2070 usec_delay(100); 2071 timeout--; 2072 } 2073 2074 if (!timeout) { 2075 DEBUGOUT("Master requests are pending.\n"); 2076 return -E1000_ERR_MASTER_REQUESTS_PENDING; 2077 } 2078 2079 return E1000_SUCCESS; 2080 } 2081 2082 /** 2083 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2084 * @hw: pointer to the HW structure 2085 * 2086 * Reset the Adaptive Interframe Spacing throttle to default values. 2087 **/ 2088 void e1000_reset_adaptive_generic(struct e1000_hw *hw) 2089 { 2090 struct e1000_mac_info *mac = &hw->mac; 2091 2092 DEBUGFUNC("e1000_reset_adaptive_generic"); 2093 2094 if (!mac->adaptive_ifs) { 2095 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2096 return; 2097 } 2098 2099 mac->current_ifs_val = 0; 2100 mac->ifs_min_val = IFS_MIN; 2101 mac->ifs_max_val = IFS_MAX; 2102 mac->ifs_step_size = IFS_STEP; 2103 mac->ifs_ratio = IFS_RATIO; 2104 2105 mac->in_ifs_mode = false; 2106 E1000_WRITE_REG(hw, E1000_AIT, 0); 2107 } 2108 2109 /** 2110 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2111 * @hw: pointer to the HW structure 2112 * 2113 * Update the Adaptive Interframe Spacing Throttle value based on the 2114 * time between transmitted packets and time between collisions. 2115 **/ 2116 void e1000_update_adaptive_generic(struct e1000_hw *hw) 2117 { 2118 struct e1000_mac_info *mac = &hw->mac; 2119 2120 DEBUGFUNC("e1000_update_adaptive_generic"); 2121 2122 if (!mac->adaptive_ifs) { 2123 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2124 return; 2125 } 2126 2127 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2128 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2129 mac->in_ifs_mode = true; 2130 if (mac->current_ifs_val < mac->ifs_max_val) { 2131 if (!mac->current_ifs_val) 2132 mac->current_ifs_val = mac->ifs_min_val; 2133 else 2134 mac->current_ifs_val += 2135 mac->ifs_step_size; 2136 E1000_WRITE_REG(hw, E1000_AIT, 2137 mac->current_ifs_val); 2138 } 2139 } 2140 } else { 2141 if (mac->in_ifs_mode && 2142 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2143 mac->current_ifs_val = 0; 2144 mac->in_ifs_mode = false; 2145 E1000_WRITE_REG(hw, E1000_AIT, 0); 2146 } 2147 } 2148 } 2149 2150 /** 2151 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2152 * @hw: pointer to the HW structure 2153 * 2154 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2155 * set, which is forced to MDI mode only. 2156 **/ 2157 STATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2158 { 2159 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2160 2161 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2162 DEBUGOUT("Invalid MDI setting detected\n"); 2163 hw->phy.mdix = 1; 2164 return -E1000_ERR_CONFIG; 2165 } 2166 2167 return E1000_SUCCESS; 2168 } 2169 2170 /** 2171 * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings 2172 * @hw: pointer to the HW structure 2173 * 2174 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced 2175 * operation. 2176 **/ 2177 s32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2178 { 2179 DEBUGFUNC("e1000_validate_mdi_setting_crossover_generic"); 2180 UNREFERENCED_1PARAMETER(hw); 2181 2182 return E1000_SUCCESS; 2183 } 2184 2185 /** 2186 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2187 * @hw: pointer to the HW structure 2188 * @reg: 32bit register offset such as E1000_SCTL 2189 * @offset: register offset to write to 2190 * @data: data to write at register offset 2191 * 2192 * Writes an address/data control type register. There are several of these 2193 * and they all have the format address << 8 | data and bit 31 is polled for 2194 * completion. 2195 **/ 2196 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2197 u32 offset, u8 data) 2198 { 2199 u32 i, regvalue = 0; 2200 2201 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2202 2203 /* Set up the address and data */ 2204 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2205 E1000_WRITE_REG(hw, reg, regvalue); 2206 2207 /* Poll the ready bit to see if the MDI read completed */ 2208 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2209 usec_delay(5); 2210 regvalue = E1000_READ_REG(hw, reg); 2211 if (regvalue & E1000_GEN_CTL_READY) 2212 break; 2213 } 2214 if (!(regvalue & E1000_GEN_CTL_READY)) { 2215 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2216 return -E1000_ERR_PHY; 2217 } 2218 2219 return E1000_SUCCESS; 2220 } 2221