1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2019 NXP 5 * 6 */ 7 8 #ifndef _DPAA2_ETHDEV_H 9 #define _DPAA2_ETHDEV_H 10 11 #include <rte_event_eth_rx_adapter.h> 12 #include <rte_pmd_dpaa2.h> 13 14 #include <dpaa2_hw_pvt.h> 15 16 #include <mc/fsl_dpni.h> 17 #include <mc/fsl_mc_sys.h> 18 19 #define DPAA2_MIN_RX_BUF_SIZE 512 20 #define DPAA2_MAX_RX_PKT_LEN 10240 /*WRIOP support*/ 21 22 #define MAX_TCS DPNI_MAX_TC 23 #define MAX_RX_QUEUES 128 24 #define MAX_TX_QUEUES 16 25 #define MAX_DPNI 8 26 27 #define DPAA2_RX_DEFAULT_NBDESC 512 28 29 /*default tc to be used for ,congestion, distribution etc configuration. */ 30 #define DPAA2_DEF_TC 0 31 32 /* Threshold for a Tx queue to *Enter* Congestion state. 33 */ 34 #define CONG_ENTER_TX_THRESHOLD 512 35 36 /* Threshold for a queue to *Exit* Congestion state. 37 */ 38 #define CONG_EXIT_TX_THRESHOLD 480 39 40 #define CONG_RETRY_COUNT 18000 41 42 /* RX queue tail drop threshold 43 * currently considering 64 KB packets 44 */ 45 #define CONG_THRESHOLD_RX_BYTES_Q (64 * 1024) 46 #define CONG_RX_OAL 128 47 48 /* Size of the input SMMU mapped memory required by MC */ 49 #define DIST_PARAM_IOVA_SIZE 256 50 51 /* Enable TX Congestion control support 52 * default is disable 53 */ 54 #define DPAA2_TX_CGR_OFF 0x01 55 56 /* Disable RX tail drop, default is enable */ 57 #define DPAA2_RX_TAILDROP_OFF 0x04 58 59 #define DPAA2_RSS_OFFLOAD_ALL ( \ 60 ETH_RSS_L2_PAYLOAD | \ 61 ETH_RSS_IP | \ 62 ETH_RSS_UDP | \ 63 ETH_RSS_TCP | \ 64 ETH_RSS_SCTP) 65 66 /* LX2 FRC Parsed values (Little Endian) */ 67 #define DPAA2_PKT_TYPE_ETHER 0x0060 68 #define DPAA2_PKT_TYPE_IPV4 0x0000 69 #define DPAA2_PKT_TYPE_IPV6 0x0020 70 #define DPAA2_PKT_TYPE_IPV4_EXT \ 71 (0x0001 | DPAA2_PKT_TYPE_IPV4) 72 #define DPAA2_PKT_TYPE_IPV6_EXT \ 73 (0x0001 | DPAA2_PKT_TYPE_IPV6) 74 #define DPAA2_PKT_TYPE_IPV4_TCP \ 75 (0x000e | DPAA2_PKT_TYPE_IPV4) 76 #define DPAA2_PKT_TYPE_IPV6_TCP \ 77 (0x000e | DPAA2_PKT_TYPE_IPV6) 78 #define DPAA2_PKT_TYPE_IPV4_UDP \ 79 (0x0010 | DPAA2_PKT_TYPE_IPV4) 80 #define DPAA2_PKT_TYPE_IPV6_UDP \ 81 (0x0010 | DPAA2_PKT_TYPE_IPV6) 82 #define DPAA2_PKT_TYPE_IPV4_SCTP \ 83 (0x000f | DPAA2_PKT_TYPE_IPV4) 84 #define DPAA2_PKT_TYPE_IPV6_SCTP \ 85 (0x000f | DPAA2_PKT_TYPE_IPV6) 86 #define DPAA2_PKT_TYPE_IPV4_ICMP \ 87 (0x0003 | DPAA2_PKT_TYPE_IPV4_EXT) 88 #define DPAA2_PKT_TYPE_IPV6_ICMP \ 89 (0x0003 | DPAA2_PKT_TYPE_IPV6_EXT) 90 #define DPAA2_PKT_TYPE_VLAN_1 0x0160 91 #define DPAA2_PKT_TYPE_VLAN_2 0x0260 92 93 /* enable timestamp in mbuf*/ 94 extern enum pmd_dpaa2_ts dpaa2_enable_ts; 95 96 #define DPAA2_QOS_TABLE_RECONFIGURE 1 97 #define DPAA2_FS_TABLE_RECONFIGURE 2 98 99 /*Externaly defined*/ 100 extern const struct rte_flow_ops dpaa2_flow_ops; 101 extern enum rte_filter_type dpaa2_filter_type; 102 103 struct dpaa2_dev_priv { 104 void *hw; 105 int32_t hw_id; 106 int32_t qdid; 107 uint16_t token; 108 uint8_t nb_tx_queues; 109 uint8_t nb_rx_queues; 110 uint32_t options; 111 void *rx_vq[MAX_RX_QUEUES]; 112 void *tx_vq[MAX_TX_QUEUES]; 113 struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */ 114 void *tx_conf_vq[MAX_TX_QUEUES]; 115 uint8_t tx_conf_en; 116 uint8_t max_mac_filters; 117 uint8_t max_vlan_filters; 118 uint8_t num_rx_tc; 119 uint8_t flags; /*dpaa2 config flags */ 120 uint8_t en_ordered; 121 uint8_t en_loose_ordered; 122 uint8_t max_cgs; 123 uint8_t cgid_in_use[MAX_RX_QUEUES]; 124 125 struct pattern_s { 126 uint8_t item_count; 127 uint8_t pattern_type[DPKG_MAX_NUM_OF_EXTRACTS]; 128 } pattern[MAX_TCS + 1]; 129 130 struct extract_s { 131 struct dpkg_profile_cfg qos_key_cfg; 132 struct dpkg_profile_cfg fs_key_cfg[MAX_TCS]; 133 uint64_t qos_extract_param; 134 uint64_t fs_extract_param[MAX_TCS]; 135 } extract; 136 137 uint16_t ss_offset; 138 uint64_t ss_iova; 139 uint64_t ss_param_iova; 140 #if defined(RTE_LIBRTE_IEEE1588) 141 /*stores timestamp of last received packet on dev*/ 142 uint64_t rx_timestamp; 143 /*stores timestamp of last received tx confirmation packet on dev*/ 144 uint64_t tx_timestamp; 145 /* stores pointer to next tx_conf queue that should be processed, 146 * it corresponds to last packet transmitted 147 */ 148 struct dpaa2_queue *next_tx_conf_queue; 149 #endif 150 151 struct rte_eth_dev *eth_dev; /**< Pointer back to holding ethdev */ 152 153 LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */ 154 }; 155 156 int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set, 157 struct dpkg_profile_cfg *kg_cfg); 158 159 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev, 160 uint64_t req_dist_set); 161 162 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev, 163 uint8_t tc_index); 164 165 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist); 166 167 __rte_internal 168 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 169 int eth_rx_queue_id, 170 struct dpaa2_dpcon_dev *dpcon, 171 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf); 172 173 __rte_internal 174 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 175 int eth_rx_queue_id); 176 177 uint16_t dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts); 178 179 uint16_t dpaa2_dev_loopback_rx(void *queue, struct rte_mbuf **bufs, 180 uint16_t nb_pkts); 181 182 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, 183 uint16_t nb_pkts); 184 void dpaa2_dev_process_parallel_event(struct qbman_swp *swp, 185 const struct qbman_fd *fd, 186 const struct qbman_result *dq, 187 struct dpaa2_queue *rxq, 188 struct rte_event *ev); 189 void dpaa2_dev_process_atomic_event(struct qbman_swp *swp, 190 const struct qbman_fd *fd, 191 const struct qbman_result *dq, 192 struct dpaa2_queue *rxq, 193 struct rte_event *ev); 194 void dpaa2_dev_process_ordered_event(struct qbman_swp *swp, 195 const struct qbman_fd *fd, 196 const struct qbman_result *dq, 197 struct dpaa2_queue *rxq, 198 struct rte_event *ev); 199 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts); 200 uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs, 201 uint16_t nb_pkts); 202 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts); 203 void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci); 204 void dpaa2_flow_clean(struct rte_eth_dev *dev); 205 uint16_t dpaa2_dev_tx_conf(void *queue) __rte_unused; 206 207 #if defined(RTE_LIBRTE_IEEE1588) 208 int dpaa2_timesync_enable(struct rte_eth_dev *dev); 209 int dpaa2_timesync_disable(struct rte_eth_dev *dev); 210 int dpaa2_timesync_read_time(struct rte_eth_dev *dev, 211 struct timespec *timestamp); 212 int dpaa2_timesync_write_time(struct rte_eth_dev *dev, 213 const struct timespec *timestamp); 214 int dpaa2_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 215 int dpaa2_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 216 struct timespec *timestamp, 217 uint32_t flags __rte_unused); 218 int dpaa2_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 219 struct timespec *timestamp); 220 #endif 221 #endif /* _DPAA2_ETHDEV_H */ 222