xref: /dpdk/drivers/net/dpaa2/dpaa2_ethdev.h (revision b677d4c6)
1c147eae0SHemant Agrawal /*-
2c147eae0SHemant Agrawal  *   BSD LICENSE
3c147eae0SHemant Agrawal  *
4c147eae0SHemant Agrawal  *   Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
5fcee050aSShreyansh Jain  *   Copyright 2016 NXP.
6c147eae0SHemant Agrawal  *
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8c147eae0SHemant Agrawal  *   modification, are permitted provided that the following conditions
9c147eae0SHemant Agrawal  *   are met:
10c147eae0SHemant Agrawal  *
11c147eae0SHemant Agrawal  *     * Redistributions of source code must retain the above copyright
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18c147eae0SHemant Agrawal  *       contributors may be used to endorse or promote products derived
19c147eae0SHemant Agrawal  *       from this software without specific prior written permission.
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32c147eae0SHemant Agrawal  */
33c147eae0SHemant Agrawal 
34c147eae0SHemant Agrawal #ifndef _DPAA2_ETHDEV_H
35c147eae0SHemant Agrawal #define _DPAA2_ETHDEV_H
36c147eae0SHemant Agrawal 
37*b677d4c6SNipun Gupta #include <rte_event_eth_rx_adapter.h>
38*b677d4c6SNipun Gupta 
393e5a335dSHemant Agrawal #include <mc/fsl_dpni.h>
403e5a335dSHemant Agrawal #include <mc/fsl_mc_sys.h>
413e5a335dSHemant Agrawal 
42bee61d86SHemant Agrawal #define DPAA2_MIN_RX_BUF_SIZE 512
43bee61d86SHemant Agrawal #define DPAA2_MAX_RX_PKT_LEN  10240 /*WRIOP support*/
44bee61d86SHemant Agrawal 
4589c2ea8fSHemant Agrawal #define MAX_TCS			DPNI_MAX_TC
463e5a335dSHemant Agrawal #define MAX_RX_QUEUES		16
473e5a335dSHemant Agrawal #define MAX_TX_QUEUES		16
483e5a335dSHemant Agrawal 
493e5a335dSHemant Agrawal /*default tc to be used for ,congestion, distribution etc configuration. */
503e5a335dSHemant Agrawal #define DPAA2_DEF_TC		0
513e5a335dSHemant Agrawal 
5229dfa62fSHemant Agrawal /* Threshold for a Tx queue to *Enter* Congestion state.
537ae777d0SHemant Agrawal  */
5429dfa62fSHemant Agrawal #define CONG_ENTER_TX_THRESHOLD   512
557ae777d0SHemant Agrawal 
567ae777d0SHemant Agrawal /* Threshold for a queue to *Exit* Congestion state.
577ae777d0SHemant Agrawal  */
5829dfa62fSHemant Agrawal #define CONG_EXIT_TX_THRESHOLD    480
597ae777d0SHemant Agrawal 
60a0840963SHemant Agrawal #define CONG_RETRY_COUNT 18000
61a0840963SHemant Agrawal 
6223d6a87eSHemant Agrawal /* RX queue tail drop threshold
6323d6a87eSHemant Agrawal  * currently considering 32 KB packets
6423d6a87eSHemant Agrawal  */
6529dfa62fSHemant Agrawal #define CONG_THRESHOLD_RX_Q  (64 * 1024)
66d47f0292SHemant Agrawal #define CONG_RX_OAL	128
6723d6a87eSHemant Agrawal 
6889c2ea8fSHemant Agrawal /* Size of the input SMMU mapped memory required by MC */
6989c2ea8fSHemant Agrawal #define DIST_PARAM_IOVA_SIZE 256
7089c2ea8fSHemant Agrawal 
717ae777d0SHemant Agrawal /* Enable TX Congestion control support
727ae777d0SHemant Agrawal  * default is disable
737ae777d0SHemant Agrawal  */
74a0840963SHemant Agrawal #define DPAA2_TX_CGR_OFF	0x01
757ae777d0SHemant Agrawal 
7623d6a87eSHemant Agrawal /* Disable RX tail drop, default is enable */
7723d6a87eSHemant Agrawal #define DPAA2_RX_TAILDROP_OFF	0x04
7823d6a87eSHemant Agrawal 
79c147eae0SHemant Agrawal struct dpaa2_dev_priv {
80c147eae0SHemant Agrawal 	void *hw;
81c147eae0SHemant Agrawal 	int32_t hw_id;
823e5a335dSHemant Agrawal 	int32_t qdid;
83c147eae0SHemant Agrawal 	uint16_t token;
843e5a335dSHemant Agrawal 	uint8_t nb_tx_queues;
853e5a335dSHemant Agrawal 	uint8_t nb_rx_queues;
863e5a335dSHemant Agrawal 	void *rx_vq[MAX_RX_QUEUES];
873e5a335dSHemant Agrawal 	void *tx_vq[MAX_TX_QUEUES];
88c147eae0SHemant Agrawal 
89bee61d86SHemant Agrawal 	struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
9033fad432SHemant Agrawal 	uint32_t options;
9133fad432SHemant Agrawal 	uint8_t max_mac_filters;
9233fad432SHemant Agrawal 	uint8_t max_vlan_filters;
9316bbc98aSShreyansh Jain 	uint8_t num_rx_tc;
94c147eae0SHemant Agrawal 	uint8_t flags; /*dpaa2 config flags */
95c147eae0SHemant Agrawal };
9689c2ea8fSHemant Agrawal 
9789c2ea8fSHemant Agrawal int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
98bd4d9419SHemant Agrawal 			  uint64_t req_dist_set);
9989c2ea8fSHemant Agrawal 
10089c2ea8fSHemant Agrawal int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
10189c2ea8fSHemant Agrawal 			   uint8_t tc_index);
10289c2ea8fSHemant Agrawal 
103bee61d86SHemant Agrawal int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
104bee61d86SHemant Agrawal 
105*b677d4c6SNipun Gupta int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
106*b677d4c6SNipun Gupta 		int eth_rx_queue_id,
107*b677d4c6SNipun Gupta 		uint16_t dpcon_id,
108*b677d4c6SNipun Gupta 		const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
109*b677d4c6SNipun Gupta 
110*b677d4c6SNipun Gupta int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
111*b677d4c6SNipun Gupta 		int eth_rx_queue_id);
112*b677d4c6SNipun Gupta 
1135c6942fdSHemant Agrawal uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs,
1145c6942fdSHemant Agrawal 			       uint16_t nb_pkts);
115*b677d4c6SNipun Gupta void dpaa2_dev_process_parallel_event(struct qbman_swp *swp,
116*b677d4c6SNipun Gupta 				      const struct qbman_fd *fd,
117*b677d4c6SNipun Gupta 				      const struct qbman_result *dq,
118*b677d4c6SNipun Gupta 				      struct dpaa2_queue *rxq,
119*b677d4c6SNipun Gupta 				      struct rte_event *ev);
120cd9935ceSHemant Agrawal uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
121a1f3a12cSHemant Agrawal uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
122c147eae0SHemant Agrawal #endif /* _DPAA2_ETHDEV_H */
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