xref: /dpdk/drivers/net/dpaa2/dpaa2_ethdev.h (revision 16bbc98a)
1c147eae0SHemant Agrawal /*-
2c147eae0SHemant Agrawal  *   BSD LICENSE
3c147eae0SHemant Agrawal  *
4c147eae0SHemant Agrawal  *   Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
5fcee050aSShreyansh Jain  *   Copyright 2016 NXP.
6c147eae0SHemant Agrawal  *
7c147eae0SHemant Agrawal  *   Redistribution and use in source and binary forms, with or without
8c147eae0SHemant Agrawal  *   modification, are permitted provided that the following conditions
9c147eae0SHemant Agrawal  *   are met:
10c147eae0SHemant Agrawal  *
11c147eae0SHemant Agrawal  *     * Redistributions of source code must retain the above copyright
12c147eae0SHemant Agrawal  *       notice, this list of conditions and the following disclaimer.
13c147eae0SHemant Agrawal  *     * Redistributions in binary form must reproduce the above copyright
14c147eae0SHemant Agrawal  *       notice, this list of conditions and the following disclaimer in
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16c147eae0SHemant Agrawal  *       distribution.
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18c147eae0SHemant Agrawal  *       contributors may be used to endorse or promote products derived
19c147eae0SHemant Agrawal  *       from this software without specific prior written permission.
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21c147eae0SHemant Agrawal  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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30c147eae0SHemant Agrawal  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31c147eae0SHemant Agrawal  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32c147eae0SHemant Agrawal  */
33c147eae0SHemant Agrawal 
34c147eae0SHemant Agrawal #ifndef _DPAA2_ETHDEV_H
35c147eae0SHemant Agrawal #define _DPAA2_ETHDEV_H
36c147eae0SHemant Agrawal 
373e5a335dSHemant Agrawal #include <mc/fsl_dpni.h>
383e5a335dSHemant Agrawal #include <mc/fsl_mc_sys.h>
393e5a335dSHemant Agrawal 
40bee61d86SHemant Agrawal #define DPAA2_MIN_RX_BUF_SIZE 512
41bee61d86SHemant Agrawal #define DPAA2_MAX_RX_PKT_LEN  10240 /*WRIOP support*/
42bee61d86SHemant Agrawal 
4389c2ea8fSHemant Agrawal #define MAX_TCS			DPNI_MAX_TC
443e5a335dSHemant Agrawal #define MAX_RX_QUEUES		16
453e5a335dSHemant Agrawal #define MAX_TX_QUEUES		16
463e5a335dSHemant Agrawal 
473e5a335dSHemant Agrawal /*default tc to be used for ,congestion, distribution etc configuration. */
483e5a335dSHemant Agrawal #define DPAA2_DEF_TC		0
493e5a335dSHemant Agrawal 
5029dfa62fSHemant Agrawal /* Threshold for a Tx queue to *Enter* Congestion state.
517ae777d0SHemant Agrawal  */
5229dfa62fSHemant Agrawal #define CONG_ENTER_TX_THRESHOLD   512
537ae777d0SHemant Agrawal 
547ae777d0SHemant Agrawal /* Threshold for a queue to *Exit* Congestion state.
557ae777d0SHemant Agrawal  */
5629dfa62fSHemant Agrawal #define CONG_EXIT_TX_THRESHOLD    480
577ae777d0SHemant Agrawal 
58a0840963SHemant Agrawal #define CONG_RETRY_COUNT 18000
59a0840963SHemant Agrawal 
6023d6a87eSHemant Agrawal /* RX queue tail drop threshold
6123d6a87eSHemant Agrawal  * currently considering 32 KB packets
6223d6a87eSHemant Agrawal  */
6329dfa62fSHemant Agrawal #define CONG_THRESHOLD_RX_Q  (64 * 1024)
6423d6a87eSHemant Agrawal 
6589c2ea8fSHemant Agrawal /* Size of the input SMMU mapped memory required by MC */
6689c2ea8fSHemant Agrawal #define DIST_PARAM_IOVA_SIZE 256
6789c2ea8fSHemant Agrawal 
687ae777d0SHemant Agrawal /* Enable TX Congestion control support
697ae777d0SHemant Agrawal  * default is disable
707ae777d0SHemant Agrawal  */
71a0840963SHemant Agrawal #define DPAA2_TX_CGR_OFF	0x01
727ae777d0SHemant Agrawal 
7323d6a87eSHemant Agrawal /* Disable RX tail drop, default is enable */
7423d6a87eSHemant Agrawal #define DPAA2_RX_TAILDROP_OFF	0x04
7523d6a87eSHemant Agrawal 
76c147eae0SHemant Agrawal struct dpaa2_dev_priv {
77c147eae0SHemant Agrawal 	void *hw;
78c147eae0SHemant Agrawal 	int32_t hw_id;
793e5a335dSHemant Agrawal 	int32_t qdid;
80c147eae0SHemant Agrawal 	uint16_t token;
813e5a335dSHemant Agrawal 	uint8_t nb_tx_queues;
823e5a335dSHemant Agrawal 	uint8_t nb_rx_queues;
833e5a335dSHemant Agrawal 	void *rx_vq[MAX_RX_QUEUES];
843e5a335dSHemant Agrawal 	void *tx_vq[MAX_TX_QUEUES];
85c147eae0SHemant Agrawal 
86bee61d86SHemant Agrawal 	struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */
8733fad432SHemant Agrawal 	uint32_t options;
8833fad432SHemant Agrawal 	uint8_t max_mac_filters;
8933fad432SHemant Agrawal 	uint8_t max_vlan_filters;
90*16bbc98aSShreyansh Jain 	uint8_t num_rx_tc;
91c147eae0SHemant Agrawal 	uint8_t flags; /*dpaa2 config flags */
92c147eae0SHemant Agrawal };
9389c2ea8fSHemant Agrawal 
9489c2ea8fSHemant Agrawal int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
9589c2ea8fSHemant Agrawal 			  uint32_t req_dist_set);
9689c2ea8fSHemant Agrawal 
9789c2ea8fSHemant Agrawal int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev,
9889c2ea8fSHemant Agrawal 			   uint8_t tc_index);
9989c2ea8fSHemant Agrawal 
100bee61d86SHemant Agrawal int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist);
101bee61d86SHemant Agrawal 
1025c6942fdSHemant Agrawal uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs,
1035c6942fdSHemant Agrawal 			       uint16_t nb_pkts);
104cd9935ceSHemant Agrawal uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
105a1f3a12cSHemant Agrawal uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
106c147eae0SHemant Agrawal #endif /* _DPAA2_ETHDEV_H */
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