1 /* * SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016 NXP 5 * 6 */ 7 8 #include <time.h> 9 #include <net/if.h> 10 11 #include <rte_mbuf.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_malloc.h> 14 #include <rte_memcpy.h> 15 #include <rte_string_fns.h> 16 #include <rte_cycles.h> 17 #include <rte_kvargs.h> 18 #include <rte_dev.h> 19 #include <rte_fslmc.h> 20 21 #include "dpaa2_pmd_logs.h" 22 #include <fslmc_vfio.h> 23 #include <dpaa2_hw_pvt.h> 24 #include <dpaa2_hw_mempool.h> 25 #include <dpaa2_hw_dpio.h> 26 #include <mc/fsl_dpmng.h> 27 #include "dpaa2_ethdev.h" 28 #include <fsl_qbman_debug.h> 29 30 /* Supported Rx offloads */ 31 static uint64_t dev_rx_offloads_sup = 32 DEV_RX_OFFLOAD_VLAN_STRIP | 33 DEV_RX_OFFLOAD_IPV4_CKSUM | 34 DEV_RX_OFFLOAD_UDP_CKSUM | 35 DEV_RX_OFFLOAD_TCP_CKSUM | 36 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 37 DEV_RX_OFFLOAD_VLAN_FILTER | 38 DEV_RX_OFFLOAD_JUMBO_FRAME; 39 40 /* Rx offloads which cannot be disabled */ 41 static uint64_t dev_rx_offloads_nodis = 42 DEV_RX_OFFLOAD_SCATTER; 43 44 /* Supported Tx offloads */ 45 static uint64_t dev_tx_offloads_sup = 46 DEV_TX_OFFLOAD_VLAN_INSERT | 47 DEV_TX_OFFLOAD_IPV4_CKSUM | 48 DEV_TX_OFFLOAD_UDP_CKSUM | 49 DEV_TX_OFFLOAD_TCP_CKSUM | 50 DEV_TX_OFFLOAD_SCTP_CKSUM | 51 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 52 53 /* Tx offloads which cannot be disabled */ 54 static uint64_t dev_tx_offloads_nodis = 55 DEV_TX_OFFLOAD_MULTI_SEGS | 56 DEV_TX_OFFLOAD_MT_LOCKFREE | 57 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 58 59 /* enable timestamp in mbuf */ 60 enum pmd_dpaa2_ts dpaa2_enable_ts; 61 62 struct rte_dpaa2_xstats_name_off { 63 char name[RTE_ETH_XSTATS_NAME_SIZE]; 64 uint8_t page_id; /* dpni statistics page id */ 65 uint8_t stats_id; /* stats id in the given page */ 66 }; 67 68 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { 69 {"ingress_multicast_frames", 0, 2}, 70 {"ingress_multicast_bytes", 0, 3}, 71 {"ingress_broadcast_frames", 0, 4}, 72 {"ingress_broadcast_bytes", 0, 5}, 73 {"egress_multicast_frames", 1, 2}, 74 {"egress_multicast_bytes", 1, 3}, 75 {"egress_broadcast_frames", 1, 4}, 76 {"egress_broadcast_bytes", 1, 5}, 77 {"ingress_filtered_frames", 2, 0}, 78 {"ingress_discarded_frames", 2, 1}, 79 {"ingress_nobuffer_discards", 2, 2}, 80 {"egress_discarded_frames", 2, 3}, 81 {"egress_confirmed_frames", 2, 4}, 82 }; 83 84 static struct rte_dpaa2_driver rte_dpaa2_pmd; 85 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev); 86 static int dpaa2_dev_link_update(struct rte_eth_dev *dev, 87 int wait_to_complete); 88 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); 89 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); 90 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 91 92 int dpaa2_logtype_pmd; 93 94 __rte_experimental void 95 rte_pmd_dpaa2_set_timestamp(enum pmd_dpaa2_ts enable) 96 { 97 dpaa2_enable_ts = enable; 98 } 99 100 static int 101 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 102 { 103 int ret; 104 struct dpaa2_dev_priv *priv = dev->data->dev_private; 105 struct fsl_mc_io *dpni = priv->hw; 106 107 PMD_INIT_FUNC_TRACE(); 108 109 if (dpni == NULL) { 110 DPAA2_PMD_ERR("dpni is NULL"); 111 return -1; 112 } 113 114 if (on) 115 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, 116 priv->token, vlan_id); 117 else 118 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, 119 priv->token, vlan_id); 120 121 if (ret < 0) 122 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d", 123 ret, vlan_id, priv->hw_id); 124 125 return ret; 126 } 127 128 static int 129 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) 130 { 131 struct dpaa2_dev_priv *priv = dev->data->dev_private; 132 struct fsl_mc_io *dpni = priv->hw; 133 int ret; 134 135 PMD_INIT_FUNC_TRACE(); 136 137 if (mask & ETH_VLAN_FILTER_MASK) { 138 /* VLAN Filter not avaialble */ 139 if (!priv->max_vlan_filters) { 140 DPAA2_PMD_INFO("VLAN filter not available"); 141 goto next_mask; 142 } 143 144 if (dev->data->dev_conf.rxmode.offloads & 145 DEV_RX_OFFLOAD_VLAN_FILTER) 146 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 147 priv->token, true); 148 else 149 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 150 priv->token, false); 151 if (ret < 0) 152 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret); 153 } 154 next_mask: 155 if (mask & ETH_VLAN_EXTEND_MASK) { 156 if (dev->data->dev_conf.rxmode.offloads & 157 DEV_RX_OFFLOAD_VLAN_EXTEND) 158 DPAA2_PMD_INFO("VLAN extend offload not supported"); 159 } 160 161 return 0; 162 } 163 164 static int 165 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev, 166 enum rte_vlan_type vlan_type __rte_unused, 167 uint16_t tpid) 168 { 169 struct dpaa2_dev_priv *priv = dev->data->dev_private; 170 struct fsl_mc_io *dpni = priv->hw; 171 int ret = -ENOTSUP; 172 173 PMD_INIT_FUNC_TRACE(); 174 175 /* nothing to be done for standard vlan tpids */ 176 if (tpid == 0x8100 || tpid == 0x88A8) 177 return 0; 178 179 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 180 priv->token, tpid); 181 if (ret < 0) 182 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret); 183 /* if already configured tpids, remove them first */ 184 if (ret == -EBUSY) { 185 struct dpni_custom_tpid_cfg tpid_list = {0}; 186 187 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW, 188 priv->token, &tpid_list); 189 if (ret < 0) 190 goto fail; 191 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW, 192 priv->token, tpid_list.tpid1); 193 if (ret < 0) 194 goto fail; 195 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 196 priv->token, tpid); 197 } 198 fail: 199 return ret; 200 } 201 202 static int 203 dpaa2_fw_version_get(struct rte_eth_dev *dev, 204 char *fw_version, 205 size_t fw_size) 206 { 207 int ret; 208 struct dpaa2_dev_priv *priv = dev->data->dev_private; 209 struct fsl_mc_io *dpni = priv->hw; 210 struct mc_soc_version mc_plat_info = {0}; 211 struct mc_version mc_ver_info = {0}; 212 213 PMD_INIT_FUNC_TRACE(); 214 215 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) 216 DPAA2_PMD_WARN("\tmc_get_soc_version failed"); 217 218 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info)) 219 DPAA2_PMD_WARN("\tmc_get_version failed"); 220 221 ret = snprintf(fw_version, fw_size, 222 "%x-%d.%d.%d", 223 mc_plat_info.svr, 224 mc_ver_info.major, 225 mc_ver_info.minor, 226 mc_ver_info.revision); 227 228 ret += 1; /* add the size of '\0' */ 229 if (fw_size < (uint32_t)ret) 230 return ret; 231 else 232 return 0; 233 } 234 235 static void 236 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 237 { 238 struct dpaa2_dev_priv *priv = dev->data->dev_private; 239 240 PMD_INIT_FUNC_TRACE(); 241 242 dev_info->if_index = priv->hw_id; 243 244 dev_info->max_mac_addrs = priv->max_mac_filters; 245 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN; 246 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE; 247 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues; 248 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues; 249 dev_info->rx_offload_capa = dev_rx_offloads_sup | 250 dev_rx_offloads_nodis; 251 dev_info->tx_offload_capa = dev_tx_offloads_sup | 252 dev_tx_offloads_nodis; 253 dev_info->speed_capa = ETH_LINK_SPEED_1G | 254 ETH_LINK_SPEED_2_5G | 255 ETH_LINK_SPEED_10G; 256 257 dev_info->max_hash_mac_addrs = 0; 258 dev_info->max_vfs = 0; 259 dev_info->max_vmdq_pools = ETH_16_POOLS; 260 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; 261 } 262 263 static int 264 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) 265 { 266 struct dpaa2_dev_priv *priv = dev->data->dev_private; 267 uint16_t dist_idx; 268 uint32_t vq_id; 269 struct dpaa2_queue *mc_q, *mcq; 270 uint32_t tot_queues; 271 int i; 272 struct dpaa2_queue *dpaa2_q; 273 274 PMD_INIT_FUNC_TRACE(); 275 276 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; 277 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, 278 RTE_CACHE_LINE_SIZE); 279 if (!mc_q) { 280 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues"); 281 return -1; 282 } 283 284 for (i = 0; i < priv->nb_rx_queues; i++) { 285 mc_q->eth_data = dev->data; 286 priv->rx_vq[i] = mc_q++; 287 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 288 dpaa2_q->q_storage = rte_malloc("dq_storage", 289 sizeof(struct queue_storage_info_t), 290 RTE_CACHE_LINE_SIZE); 291 if (!dpaa2_q->q_storage) 292 goto fail; 293 294 memset(dpaa2_q->q_storage, 0, 295 sizeof(struct queue_storage_info_t)); 296 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 297 goto fail; 298 } 299 300 for (i = 0; i < priv->nb_tx_queues; i++) { 301 mc_q->eth_data = dev->data; 302 mc_q->flow_id = 0xffff; 303 priv->tx_vq[i] = mc_q++; 304 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 305 dpaa2_q->cscn = rte_malloc(NULL, 306 sizeof(struct qbman_result), 16); 307 if (!dpaa2_q->cscn) 308 goto fail_tx; 309 } 310 311 vq_id = 0; 312 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { 313 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id]; 314 mcq->tc_index = DPAA2_DEF_TC; 315 mcq->flow_id = dist_idx; 316 vq_id++; 317 } 318 319 return 0; 320 fail_tx: 321 i -= 1; 322 while (i >= 0) { 323 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 324 rte_free(dpaa2_q->cscn); 325 priv->tx_vq[i--] = NULL; 326 } 327 i = priv->nb_rx_queues; 328 fail: 329 i -= 1; 330 mc_q = priv->rx_vq[0]; 331 while (i >= 0) { 332 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 333 dpaa2_free_dq_storage(dpaa2_q->q_storage); 334 rte_free(dpaa2_q->q_storage); 335 priv->rx_vq[i--] = NULL; 336 } 337 rte_free(mc_q); 338 return -1; 339 } 340 341 static void 342 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) 343 { 344 struct dpaa2_dev_priv *priv = dev->data->dev_private; 345 struct dpaa2_queue *dpaa2_q; 346 int i; 347 348 PMD_INIT_FUNC_TRACE(); 349 350 /* Queue allocation base */ 351 if (priv->rx_vq[0]) { 352 /* cleaning up queue storage */ 353 for (i = 0; i < priv->nb_rx_queues; i++) { 354 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 355 if (dpaa2_q->q_storage) 356 rte_free(dpaa2_q->q_storage); 357 } 358 /* cleanup tx queue cscn */ 359 for (i = 0; i < priv->nb_tx_queues; i++) { 360 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 361 rte_free(dpaa2_q->cscn); 362 } 363 /*free memory for all queues (RX+TX) */ 364 rte_free(priv->rx_vq[0]); 365 priv->rx_vq[0] = NULL; 366 } 367 } 368 369 static int 370 dpaa2_eth_dev_configure(struct rte_eth_dev *dev) 371 { 372 struct dpaa2_dev_priv *priv = dev->data->dev_private; 373 struct fsl_mc_io *dpni = priv->hw; 374 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 375 uint64_t rx_offloads = eth_conf->rxmode.offloads; 376 uint64_t tx_offloads = eth_conf->txmode.offloads; 377 int rx_l3_csum_offload = false; 378 int rx_l4_csum_offload = false; 379 int tx_l3_csum_offload = false; 380 int tx_l4_csum_offload = false; 381 int ret; 382 383 PMD_INIT_FUNC_TRACE(); 384 385 /* Rx offloads validation */ 386 if (dev_rx_offloads_nodis & ~rx_offloads) { 387 DPAA2_PMD_WARN( 388 "Rx offloads non configurable - requested 0x%" PRIx64 389 " ignored 0x%" PRIx64, 390 rx_offloads, dev_rx_offloads_nodis); 391 } 392 393 /* Tx offloads validation */ 394 if (dev_tx_offloads_nodis & ~tx_offloads) { 395 DPAA2_PMD_WARN( 396 "Tx offloads non configurable - requested 0x%" PRIx64 397 " ignored 0x%" PRIx64, 398 tx_offloads, dev_tx_offloads_nodis); 399 } 400 401 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 402 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) { 403 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, 404 priv->token, eth_conf->rxmode.max_rx_pkt_len); 405 if (ret) { 406 DPAA2_PMD_ERR( 407 "Unable to set mtu. check config"); 408 return ret; 409 } 410 } else { 411 return -1; 412 } 413 } 414 415 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) { 416 ret = dpaa2_setup_flow_dist(dev, 417 eth_conf->rx_adv_conf.rss_conf.rss_hf); 418 if (ret) { 419 DPAA2_PMD_ERR("Unable to set flow distribution." 420 "Check queue config"); 421 return ret; 422 } 423 } 424 425 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) 426 rx_l3_csum_offload = true; 427 428 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) || 429 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM)) 430 rx_l4_csum_offload = true; 431 432 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 433 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload); 434 if (ret) { 435 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret); 436 return ret; 437 } 438 439 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 440 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload); 441 if (ret) { 442 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret); 443 return ret; 444 } 445 446 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) 447 tx_l3_csum_offload = true; 448 449 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) || 450 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || 451 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM)) 452 tx_l4_csum_offload = true; 453 454 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 455 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload); 456 if (ret) { 457 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret); 458 return ret; 459 } 460 461 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 462 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload); 463 if (ret) { 464 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret); 465 return ret; 466 } 467 468 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in 469 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC] 470 * to 0 for LS2 in the hardware thus disabling data/annotation 471 * stashing. For LX2 this is fixed in hardware and thus hash result and 472 * parse results can be received in FD using this option. 473 */ 474 if (dpaa2_svr_family == SVR_LX2160A) { 475 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 476 DPNI_FLCTYPE_HASH, true); 477 if (ret) { 478 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret); 479 return ret; 480 } 481 } 482 483 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 484 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); 485 486 /* update the current status */ 487 dpaa2_dev_link_update(dev, 0); 488 489 return 0; 490 } 491 492 /* Function to setup RX flow information. It contains traffic class ID, 493 * flow ID, destination configuration etc. 494 */ 495 static int 496 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, 497 uint16_t rx_queue_id, 498 uint16_t nb_rx_desc __rte_unused, 499 unsigned int socket_id __rte_unused, 500 const struct rte_eth_rxconf *rx_conf __rte_unused, 501 struct rte_mempool *mb_pool) 502 { 503 struct dpaa2_dev_priv *priv = dev->data->dev_private; 504 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 505 struct dpaa2_queue *dpaa2_q; 506 struct dpni_queue cfg; 507 uint8_t options = 0; 508 uint8_t flow_id; 509 uint32_t bpid; 510 int ret; 511 512 PMD_INIT_FUNC_TRACE(); 513 514 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p", 515 dev, rx_queue_id, mb_pool, rx_conf); 516 517 if (!priv->bp_list || priv->bp_list->mp != mb_pool) { 518 bpid = mempool_to_bpid(mb_pool); 519 ret = dpaa2_attach_bp_list(priv, 520 rte_dpaa2_bpid_info[bpid].bp_list); 521 if (ret) 522 return ret; 523 } 524 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 525 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ 526 dpaa2_q->bp_array = rte_dpaa2_bpid_info; 527 528 /*Get the flow id from given VQ id*/ 529 flow_id = rx_queue_id % priv->nb_rx_queues; 530 memset(&cfg, 0, sizeof(struct dpni_queue)); 531 532 options = options | DPNI_QUEUE_OPT_USER_CTX; 533 cfg.user_context = (size_t)(dpaa2_q); 534 535 /*if ls2088 or rev2 device, enable the stashing */ 536 537 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { 538 options |= DPNI_QUEUE_OPT_FLC; 539 cfg.flc.stash_control = true; 540 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0; 541 /* 00 00 00 - last 6 bit represent annotation, context stashing, 542 * data stashing setting 01 01 00 (0x14) 543 * (in following order ->DS AS CS) 544 * to enable 1 line data, 1 line annotation. 545 * For LX2, this setting should be 01 00 00 (0x10) 546 */ 547 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A) 548 cfg.flc.value |= 0x10; 549 else 550 cfg.flc.value |= 0x14; 551 } 552 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, 553 dpaa2_q->tc_index, flow_id, options, &cfg); 554 if (ret) { 555 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret); 556 return -1; 557 } 558 559 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) { 560 struct dpni_taildrop taildrop; 561 562 taildrop.enable = 1; 563 /*enabling per rx queue congestion control */ 564 taildrop.threshold = CONG_THRESHOLD_RX_Q; 565 taildrop.units = DPNI_CONGESTION_UNIT_BYTES; 566 taildrop.oal = CONG_RX_OAL; 567 DPAA2_PMD_DEBUG("Enabling Early Drop on queue = %d", 568 rx_queue_id); 569 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 570 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 571 dpaa2_q->tc_index, flow_id, &taildrop); 572 if (ret) { 573 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 574 ret); 575 return -1; 576 } 577 } 578 579 dev->data->rx_queues[rx_queue_id] = dpaa2_q; 580 return 0; 581 } 582 583 static int 584 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, 585 uint16_t tx_queue_id, 586 uint16_t nb_tx_desc __rte_unused, 587 unsigned int socket_id __rte_unused, 588 const struct rte_eth_txconf *tx_conf __rte_unused) 589 { 590 struct dpaa2_dev_priv *priv = dev->data->dev_private; 591 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *) 592 priv->tx_vq[tx_queue_id]; 593 struct fsl_mc_io *dpni = priv->hw; 594 struct dpni_queue tx_conf_cfg; 595 struct dpni_queue tx_flow_cfg; 596 uint8_t options = 0, flow_id; 597 uint32_t tc_id; 598 int ret; 599 600 PMD_INIT_FUNC_TRACE(); 601 602 /* Return if queue already configured */ 603 if (dpaa2_q->flow_id != 0xffff) { 604 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 605 return 0; 606 } 607 608 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue)); 609 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue)); 610 611 tc_id = tx_queue_id; 612 flow_id = 0; 613 614 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX, 615 tc_id, flow_id, options, &tx_flow_cfg); 616 if (ret) { 617 DPAA2_PMD_ERR("Error in setting the tx flow: " 618 "tc_id=%d, flow=%d err=%d", 619 tc_id, flow_id, ret); 620 return -1; 621 } 622 623 dpaa2_q->flow_id = flow_id; 624 625 if (tx_queue_id == 0) { 626 /*Set tx-conf and error configuration*/ 627 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 628 priv->token, 629 DPNI_CONF_DISABLE); 630 if (ret) { 631 DPAA2_PMD_ERR("Error in set tx conf mode settings: " 632 "err=%d", ret); 633 return -1; 634 } 635 } 636 dpaa2_q->tc_index = tc_id; 637 638 if (!(priv->flags & DPAA2_TX_CGR_OFF)) { 639 struct dpni_congestion_notification_cfg cong_notif_cfg; 640 641 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; 642 cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD; 643 /* Notify that the queue is not congested when the data in 644 * the queue is below this thershold. 645 */ 646 cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD; 647 cong_notif_cfg.message_ctx = 0; 648 cong_notif_cfg.message_iova = 649 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); 650 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; 651 cong_notif_cfg.notification_mode = 652 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | 653 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | 654 DPNI_CONG_OPT_COHERENT_WRITE; 655 656 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW, 657 priv->token, 658 DPNI_QUEUE_TX, 659 tc_id, 660 &cong_notif_cfg); 661 if (ret) { 662 DPAA2_PMD_ERR( 663 "Error in setting tx congestion notification: " 664 "err=%d", ret); 665 return -ret; 666 } 667 } 668 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 669 return 0; 670 } 671 672 static void 673 dpaa2_dev_rx_queue_release(void *q __rte_unused) 674 { 675 PMD_INIT_FUNC_TRACE(); 676 } 677 678 static void 679 dpaa2_dev_tx_queue_release(void *q __rte_unused) 680 { 681 PMD_INIT_FUNC_TRACE(); 682 } 683 684 static uint32_t 685 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 686 { 687 int32_t ret; 688 struct dpaa2_dev_priv *priv = dev->data->dev_private; 689 struct dpaa2_queue *dpaa2_q; 690 struct qbman_swp *swp; 691 struct qbman_fq_query_np_rslt state; 692 uint32_t frame_cnt = 0; 693 694 PMD_INIT_FUNC_TRACE(); 695 696 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 697 ret = dpaa2_affine_qbman_swp(); 698 if (ret) { 699 DPAA2_PMD_ERR("Failure in affining portal"); 700 return -EINVAL; 701 } 702 } 703 swp = DPAA2_PER_LCORE_PORTAL; 704 705 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 706 707 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { 708 frame_cnt = qbman_fq_state_frame_count(&state); 709 DPAA2_PMD_DEBUG("RX frame count for q(%d) is %u", 710 rx_queue_id, frame_cnt); 711 } 712 return frame_cnt; 713 } 714 715 static const uint32_t * 716 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev) 717 { 718 static const uint32_t ptypes[] = { 719 /*todo -= add more types */ 720 RTE_PTYPE_L2_ETHER, 721 RTE_PTYPE_L3_IPV4, 722 RTE_PTYPE_L3_IPV4_EXT, 723 RTE_PTYPE_L3_IPV6, 724 RTE_PTYPE_L3_IPV6_EXT, 725 RTE_PTYPE_L4_TCP, 726 RTE_PTYPE_L4_UDP, 727 RTE_PTYPE_L4_SCTP, 728 RTE_PTYPE_L4_ICMP, 729 RTE_PTYPE_UNKNOWN 730 }; 731 732 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx) 733 return ptypes; 734 return NULL; 735 } 736 737 /** 738 * Dpaa2 link Interrupt handler 739 * 740 * @param param 741 * The address of parameter (struct rte_eth_dev *) regsitered before. 742 * 743 * @return 744 * void 745 */ 746 static void 747 dpaa2_interrupt_handler(void *param) 748 { 749 struct rte_eth_dev *dev = param; 750 struct dpaa2_dev_priv *priv = dev->data->dev_private; 751 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 752 int ret; 753 int irq_index = DPNI_IRQ_INDEX; 754 unsigned int status = 0, clear = 0; 755 756 PMD_INIT_FUNC_TRACE(); 757 758 if (dpni == NULL) { 759 DPAA2_PMD_ERR("dpni is NULL"); 760 return; 761 } 762 763 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, 764 irq_index, &status); 765 if (unlikely(ret)) { 766 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret); 767 clear = 0xffffffff; 768 goto out; 769 } 770 771 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { 772 clear = DPNI_IRQ_EVENT_LINK_CHANGED; 773 dpaa2_dev_link_update(dev, 0); 774 /* calling all the apps registered for link status event */ 775 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 776 NULL); 777 } 778 out: 779 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, 780 irq_index, clear); 781 if (unlikely(ret)) 782 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret); 783 } 784 785 static int 786 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) 787 { 788 int err = 0; 789 struct dpaa2_dev_priv *priv = dev->data->dev_private; 790 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 791 int irq_index = DPNI_IRQ_INDEX; 792 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; 793 794 PMD_INIT_FUNC_TRACE(); 795 796 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, 797 irq_index, mask); 798 if (err < 0) { 799 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err, 800 strerror(-err)); 801 return err; 802 } 803 804 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, 805 irq_index, enable); 806 if (err < 0) 807 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err, 808 strerror(-err)); 809 810 return err; 811 } 812 813 static int 814 dpaa2_dev_start(struct rte_eth_dev *dev) 815 { 816 struct rte_device *rdev = dev->device; 817 struct rte_dpaa2_device *dpaa2_dev; 818 struct rte_eth_dev_data *data = dev->data; 819 struct dpaa2_dev_priv *priv = data->dev_private; 820 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 821 struct dpni_queue cfg; 822 struct dpni_error_cfg err_cfg; 823 uint16_t qdid; 824 struct dpni_queue_id qid; 825 struct dpaa2_queue *dpaa2_q; 826 int ret, i; 827 struct rte_intr_handle *intr_handle; 828 829 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 830 intr_handle = &dpaa2_dev->intr_handle; 831 832 PMD_INIT_FUNC_TRACE(); 833 834 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 835 if (ret) { 836 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d", 837 priv->hw_id, ret); 838 return ret; 839 } 840 841 /* Power up the phy. Needed to make the link go UP */ 842 dpaa2_dev_set_link_up(dev); 843 844 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token, 845 DPNI_QUEUE_TX, &qdid); 846 if (ret) { 847 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret); 848 return ret; 849 } 850 priv->qdid = qdid; 851 852 for (i = 0; i < data->nb_rx_queues; i++) { 853 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i]; 854 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 855 DPNI_QUEUE_RX, dpaa2_q->tc_index, 856 dpaa2_q->flow_id, &cfg, &qid); 857 if (ret) { 858 DPAA2_PMD_ERR("Error in getting flow information: " 859 "err=%d", ret); 860 return ret; 861 } 862 dpaa2_q->fqid = qid.fqid; 863 } 864 865 /*checksum errors, send them to normal path and set it in annotation */ 866 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 867 868 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; 869 err_cfg.set_frame_annotation = true; 870 871 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, 872 priv->token, &err_cfg); 873 if (ret) { 874 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d", 875 ret); 876 return ret; 877 } 878 879 /* if the interrupts were configured on this devices*/ 880 if (intr_handle && (intr_handle->fd) && 881 (dev->data->dev_conf.intr_conf.lsc != 0)) { 882 /* Registering LSC interrupt handler */ 883 rte_intr_callback_register(intr_handle, 884 dpaa2_interrupt_handler, 885 (void *)dev); 886 887 /* enable vfio intr/eventfd mapping 888 * Interrupt index 0 is required, so we can not use 889 * rte_intr_enable. 890 */ 891 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); 892 893 /* enable dpni_irqs */ 894 dpaa2_eth_setup_irqs(dev, 1); 895 } 896 897 return 0; 898 } 899 900 /** 901 * This routine disables all traffic on the adapter by issuing a 902 * global reset on the MAC. 903 */ 904 static void 905 dpaa2_dev_stop(struct rte_eth_dev *dev) 906 { 907 struct dpaa2_dev_priv *priv = dev->data->dev_private; 908 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 909 int ret; 910 struct rte_eth_link link; 911 struct rte_intr_handle *intr_handle = dev->intr_handle; 912 913 PMD_INIT_FUNC_TRACE(); 914 915 /* reset interrupt callback */ 916 if (intr_handle && (intr_handle->fd) && 917 (dev->data->dev_conf.intr_conf.lsc != 0)) { 918 /*disable dpni irqs */ 919 dpaa2_eth_setup_irqs(dev, 0); 920 921 /* disable vfio intr before callback unregister */ 922 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); 923 924 /* Unregistering LSC interrupt handler */ 925 rte_intr_callback_unregister(intr_handle, 926 dpaa2_interrupt_handler, 927 (void *)dev); 928 } 929 930 dpaa2_dev_set_link_down(dev); 931 932 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); 933 if (ret) { 934 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", 935 ret, priv->hw_id); 936 return; 937 } 938 939 /* clear the recorded link status */ 940 memset(&link, 0, sizeof(link)); 941 rte_eth_linkstatus_set(dev, &link); 942 } 943 944 static void 945 dpaa2_dev_close(struct rte_eth_dev *dev) 946 { 947 struct dpaa2_dev_priv *priv = dev->data->dev_private; 948 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 949 int ret; 950 struct rte_eth_link link; 951 952 PMD_INIT_FUNC_TRACE(); 953 954 /* Clean the device first */ 955 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); 956 if (ret) { 957 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret); 958 return; 959 } 960 961 memset(&link, 0, sizeof(link)); 962 rte_eth_linkstatus_set(dev, &link); 963 } 964 965 static void 966 dpaa2_dev_promiscuous_enable( 967 struct rte_eth_dev *dev) 968 { 969 int ret; 970 struct dpaa2_dev_priv *priv = dev->data->dev_private; 971 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 972 973 PMD_INIT_FUNC_TRACE(); 974 975 if (dpni == NULL) { 976 DPAA2_PMD_ERR("dpni is NULL"); 977 return; 978 } 979 980 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 981 if (ret < 0) 982 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret); 983 984 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 985 if (ret < 0) 986 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret); 987 } 988 989 static void 990 dpaa2_dev_promiscuous_disable( 991 struct rte_eth_dev *dev) 992 { 993 int ret; 994 struct dpaa2_dev_priv *priv = dev->data->dev_private; 995 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 996 997 PMD_INIT_FUNC_TRACE(); 998 999 if (dpni == NULL) { 1000 DPAA2_PMD_ERR("dpni is NULL"); 1001 return; 1002 } 1003 1004 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1005 if (ret < 0) 1006 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret); 1007 1008 if (dev->data->all_multicast == 0) { 1009 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, 1010 priv->token, false); 1011 if (ret < 0) 1012 DPAA2_PMD_ERR("Unable to disable M promisc mode %d", 1013 ret); 1014 } 1015 } 1016 1017 static void 1018 dpaa2_dev_allmulticast_enable( 1019 struct rte_eth_dev *dev) 1020 { 1021 int ret; 1022 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1023 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1024 1025 PMD_INIT_FUNC_TRACE(); 1026 1027 if (dpni == NULL) { 1028 DPAA2_PMD_ERR("dpni is NULL"); 1029 return; 1030 } 1031 1032 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1033 if (ret < 0) 1034 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret); 1035 } 1036 1037 static void 1038 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev) 1039 { 1040 int ret; 1041 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1042 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1043 1044 PMD_INIT_FUNC_TRACE(); 1045 1046 if (dpni == NULL) { 1047 DPAA2_PMD_ERR("dpni is NULL"); 1048 return; 1049 } 1050 1051 /* must remain on for all promiscuous */ 1052 if (dev->data->promiscuous == 1) 1053 return; 1054 1055 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1056 if (ret < 0) 1057 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret); 1058 } 1059 1060 static int 1061 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1062 { 1063 int ret; 1064 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1065 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1066 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 1067 + VLAN_TAG_SIZE; 1068 1069 PMD_INIT_FUNC_TRACE(); 1070 1071 if (dpni == NULL) { 1072 DPAA2_PMD_ERR("dpni is NULL"); 1073 return -EINVAL; 1074 } 1075 1076 /* check that mtu is within the allowed range */ 1077 if ((mtu < ETHER_MIN_MTU) || (frame_size > DPAA2_MAX_RX_PKT_LEN)) 1078 return -EINVAL; 1079 1080 if (frame_size > ETHER_MAX_LEN) 1081 dev->data->dev_conf.rxmode.offloads &= 1082 DEV_RX_OFFLOAD_JUMBO_FRAME; 1083 else 1084 dev->data->dev_conf.rxmode.offloads &= 1085 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1086 1087 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1088 1089 /* Set the Max Rx frame length as 'mtu' + 1090 * Maximum Ethernet header length 1091 */ 1092 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 1093 frame_size); 1094 if (ret) { 1095 DPAA2_PMD_ERR("Setting the max frame length failed"); 1096 return -1; 1097 } 1098 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu); 1099 return 0; 1100 } 1101 1102 static int 1103 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev, 1104 struct ether_addr *addr, 1105 __rte_unused uint32_t index, 1106 __rte_unused uint32_t pool) 1107 { 1108 int ret; 1109 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1110 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1111 1112 PMD_INIT_FUNC_TRACE(); 1113 1114 if (dpni == NULL) { 1115 DPAA2_PMD_ERR("dpni is NULL"); 1116 return -1; 1117 } 1118 1119 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, 1120 priv->token, addr->addr_bytes); 1121 if (ret) 1122 DPAA2_PMD_ERR( 1123 "error: Adding the MAC ADDR failed: err = %d", ret); 1124 return 0; 1125 } 1126 1127 static void 1128 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev, 1129 uint32_t index) 1130 { 1131 int ret; 1132 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1133 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1134 struct rte_eth_dev_data *data = dev->data; 1135 struct ether_addr *macaddr; 1136 1137 PMD_INIT_FUNC_TRACE(); 1138 1139 macaddr = &data->mac_addrs[index]; 1140 1141 if (dpni == NULL) { 1142 DPAA2_PMD_ERR("dpni is NULL"); 1143 return; 1144 } 1145 1146 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW, 1147 priv->token, macaddr->addr_bytes); 1148 if (ret) 1149 DPAA2_PMD_ERR( 1150 "error: Removing the MAC ADDR failed: err = %d", ret); 1151 } 1152 1153 static int 1154 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev, 1155 struct ether_addr *addr) 1156 { 1157 int ret; 1158 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1159 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1160 1161 PMD_INIT_FUNC_TRACE(); 1162 1163 if (dpni == NULL) { 1164 DPAA2_PMD_ERR("dpni is NULL"); 1165 return -EINVAL; 1166 } 1167 1168 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW, 1169 priv->token, addr->addr_bytes); 1170 1171 if (ret) 1172 DPAA2_PMD_ERR( 1173 "error: Setting the MAC ADDR failed %d", ret); 1174 1175 return ret; 1176 } 1177 1178 static 1179 int dpaa2_dev_stats_get(struct rte_eth_dev *dev, 1180 struct rte_eth_stats *stats) 1181 { 1182 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1183 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1184 int32_t retcode; 1185 uint8_t page0 = 0, page1 = 1, page2 = 2; 1186 union dpni_statistics value; 1187 int i; 1188 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq; 1189 1190 memset(&value, 0, sizeof(union dpni_statistics)); 1191 1192 PMD_INIT_FUNC_TRACE(); 1193 1194 if (!dpni) { 1195 DPAA2_PMD_ERR("dpni is NULL"); 1196 return -EINVAL; 1197 } 1198 1199 if (!stats) { 1200 DPAA2_PMD_ERR("stats is NULL"); 1201 return -EINVAL; 1202 } 1203 1204 /*Get Counters from page_0*/ 1205 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1206 page0, 0, &value); 1207 if (retcode) 1208 goto err; 1209 1210 stats->ipackets = value.page_0.ingress_all_frames; 1211 stats->ibytes = value.page_0.ingress_all_bytes; 1212 1213 /*Get Counters from page_1*/ 1214 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1215 page1, 0, &value); 1216 if (retcode) 1217 goto err; 1218 1219 stats->opackets = value.page_1.egress_all_frames; 1220 stats->obytes = value.page_1.egress_all_bytes; 1221 1222 /*Get Counters from page_2*/ 1223 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1224 page2, 0, &value); 1225 if (retcode) 1226 goto err; 1227 1228 /* Ingress drop frame count due to configured rules */ 1229 stats->ierrors = value.page_2.ingress_filtered_frames; 1230 /* Ingress drop frame count due to error */ 1231 stats->ierrors += value.page_2.ingress_discarded_frames; 1232 1233 stats->oerrors = value.page_2.egress_discarded_frames; 1234 stats->imissed = value.page_2.ingress_nobuffer_discards; 1235 1236 /* Fill in per queue stats */ 1237 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) && 1238 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) { 1239 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i]; 1240 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i]; 1241 if (dpaa2_rxq) 1242 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts; 1243 if (dpaa2_txq) 1244 stats->q_opackets[i] = dpaa2_txq->tx_pkts; 1245 1246 /* Byte counting is not implemented */ 1247 stats->q_ibytes[i] = 0; 1248 stats->q_obytes[i] = 0; 1249 } 1250 1251 return 0; 1252 1253 err: 1254 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1255 return retcode; 1256 }; 1257 1258 static int 1259 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1260 unsigned int n) 1261 { 1262 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1263 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1264 int32_t retcode; 1265 union dpni_statistics value[3] = {}; 1266 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); 1267 1268 if (n < num) 1269 return num; 1270 1271 if (xstats == NULL) 1272 return 0; 1273 1274 /* Get Counters from page_0*/ 1275 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1276 0, 0, &value[0]); 1277 if (retcode) 1278 goto err; 1279 1280 /* Get Counters from page_1*/ 1281 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1282 1, 0, &value[1]); 1283 if (retcode) 1284 goto err; 1285 1286 /* Get Counters from page_2*/ 1287 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1288 2, 0, &value[2]); 1289 if (retcode) 1290 goto err; 1291 1292 for (i = 0; i < num; i++) { 1293 xstats[i].id = i; 1294 xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. 1295 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1296 } 1297 return i; 1298 err: 1299 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode); 1300 return retcode; 1301 } 1302 1303 static int 1304 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1305 struct rte_eth_xstat_name *xstats_names, 1306 unsigned int limit) 1307 { 1308 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1309 1310 if (limit < stat_cnt) 1311 return stat_cnt; 1312 1313 if (xstats_names != NULL) 1314 for (i = 0; i < stat_cnt; i++) 1315 snprintf(xstats_names[i].name, 1316 sizeof(xstats_names[i].name), 1317 "%s", 1318 dpaa2_xstats_strings[i].name); 1319 1320 return stat_cnt; 1321 } 1322 1323 static int 1324 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1325 uint64_t *values, unsigned int n) 1326 { 1327 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1328 uint64_t values_copy[stat_cnt]; 1329 1330 if (!ids) { 1331 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1332 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1333 int32_t retcode; 1334 union dpni_statistics value[3] = {}; 1335 1336 if (n < stat_cnt) 1337 return stat_cnt; 1338 1339 if (!values) 1340 return 0; 1341 1342 /* Get Counters from page_0*/ 1343 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1344 0, 0, &value[0]); 1345 if (retcode) 1346 return 0; 1347 1348 /* Get Counters from page_1*/ 1349 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1350 1, 0, &value[1]); 1351 if (retcode) 1352 return 0; 1353 1354 /* Get Counters from page_2*/ 1355 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1356 2, 0, &value[2]); 1357 if (retcode) 1358 return 0; 1359 1360 for (i = 0; i < stat_cnt; i++) { 1361 values[i] = value[dpaa2_xstats_strings[i].page_id]. 1362 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1363 } 1364 return stat_cnt; 1365 } 1366 1367 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 1368 1369 for (i = 0; i < n; i++) { 1370 if (ids[i] >= stat_cnt) { 1371 DPAA2_PMD_ERR("xstats id value isn't valid"); 1372 return -1; 1373 } 1374 values[i] = values_copy[ids[i]]; 1375 } 1376 return n; 1377 } 1378 1379 static int 1380 dpaa2_xstats_get_names_by_id( 1381 struct rte_eth_dev *dev, 1382 struct rte_eth_xstat_name *xstats_names, 1383 const uint64_t *ids, 1384 unsigned int limit) 1385 { 1386 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1387 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 1388 1389 if (!ids) 1390 return dpaa2_xstats_get_names(dev, xstats_names, limit); 1391 1392 dpaa2_xstats_get_names(dev, xstats_names_copy, limit); 1393 1394 for (i = 0; i < limit; i++) { 1395 if (ids[i] >= stat_cnt) { 1396 DPAA2_PMD_ERR("xstats id value isn't valid"); 1397 return -1; 1398 } 1399 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1400 } 1401 return limit; 1402 } 1403 1404 static void 1405 dpaa2_dev_stats_reset(struct rte_eth_dev *dev) 1406 { 1407 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1408 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1409 int32_t retcode; 1410 int i; 1411 struct dpaa2_queue *dpaa2_q; 1412 1413 PMD_INIT_FUNC_TRACE(); 1414 1415 if (dpni == NULL) { 1416 DPAA2_PMD_ERR("dpni is NULL"); 1417 return; 1418 } 1419 1420 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token); 1421 if (retcode) 1422 goto error; 1423 1424 /* Reset the per queue stats in dpaa2_queue structure */ 1425 for (i = 0; i < priv->nb_rx_queues; i++) { 1426 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 1427 if (dpaa2_q) 1428 dpaa2_q->rx_pkts = 0; 1429 } 1430 1431 for (i = 0; i < priv->nb_tx_queues; i++) { 1432 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 1433 if (dpaa2_q) 1434 dpaa2_q->tx_pkts = 0; 1435 } 1436 1437 return; 1438 1439 error: 1440 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1441 return; 1442 }; 1443 1444 /* return 0 means link status changed, -1 means not changed */ 1445 static int 1446 dpaa2_dev_link_update(struct rte_eth_dev *dev, 1447 int wait_to_complete __rte_unused) 1448 { 1449 int ret; 1450 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1451 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1452 struct rte_eth_link link; 1453 struct dpni_link_state state = {0}; 1454 1455 if (dpni == NULL) { 1456 DPAA2_PMD_ERR("dpni is NULL"); 1457 return 0; 1458 } 1459 1460 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1461 if (ret < 0) { 1462 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); 1463 return -1; 1464 } 1465 1466 memset(&link, 0, sizeof(struct rte_eth_link)); 1467 link.link_status = state.up; 1468 link.link_speed = state.rate; 1469 1470 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1471 link.link_duplex = ETH_LINK_HALF_DUPLEX; 1472 else 1473 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1474 1475 ret = rte_eth_linkstatus_set(dev, &link); 1476 if (ret == -1) 1477 DPAA2_PMD_DEBUG("No change in status"); 1478 else 1479 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 1480 link.link_status ? "Up" : "Down"); 1481 1482 return ret; 1483 } 1484 1485 /** 1486 * Toggle the DPNI to enable, if not already enabled. 1487 * This is not strictly PHY up/down - it is more of logical toggling. 1488 */ 1489 static int 1490 dpaa2_dev_set_link_up(struct rte_eth_dev *dev) 1491 { 1492 int ret = -EINVAL; 1493 struct dpaa2_dev_priv *priv; 1494 struct fsl_mc_io *dpni; 1495 int en = 0; 1496 struct dpni_link_state state = {0}; 1497 1498 priv = dev->data->dev_private; 1499 dpni = (struct fsl_mc_io *)priv->hw; 1500 1501 if (dpni == NULL) { 1502 DPAA2_PMD_ERR("dpni is NULL"); 1503 return ret; 1504 } 1505 1506 /* Check if DPNI is currently enabled */ 1507 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en); 1508 if (ret) { 1509 /* Unable to obtain dpni status; Not continuing */ 1510 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1511 return -EINVAL; 1512 } 1513 1514 /* Enable link if not already enabled */ 1515 if (!en) { 1516 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1517 if (ret) { 1518 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1519 return -EINVAL; 1520 } 1521 } 1522 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1523 if (ret < 0) { 1524 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret); 1525 return -1; 1526 } 1527 1528 /* changing tx burst function to start enqueues */ 1529 dev->tx_pkt_burst = dpaa2_dev_tx; 1530 dev->data->dev_link.link_status = state.up; 1531 1532 if (state.up) 1533 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id); 1534 else 1535 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id); 1536 return ret; 1537 } 1538 1539 /** 1540 * Toggle the DPNI to disable, if not already disabled. 1541 * This is not strictly PHY up/down - it is more of logical toggling. 1542 */ 1543 static int 1544 dpaa2_dev_set_link_down(struct rte_eth_dev *dev) 1545 { 1546 int ret = -EINVAL; 1547 struct dpaa2_dev_priv *priv; 1548 struct fsl_mc_io *dpni; 1549 int dpni_enabled = 0; 1550 int retries = 10; 1551 1552 PMD_INIT_FUNC_TRACE(); 1553 1554 priv = dev->data->dev_private; 1555 dpni = (struct fsl_mc_io *)priv->hw; 1556 1557 if (dpni == NULL) { 1558 DPAA2_PMD_ERR("Device has not yet been configured"); 1559 return ret; 1560 } 1561 1562 /*changing tx burst function to avoid any more enqueues */ 1563 dev->tx_pkt_burst = dummy_dev_tx; 1564 1565 /* Loop while dpni_disable() attempts to drain the egress FQs 1566 * and confirm them back to us. 1567 */ 1568 do { 1569 ret = dpni_disable(dpni, 0, priv->token); 1570 if (ret) { 1571 DPAA2_PMD_ERR("dpni disable failed (%d)", ret); 1572 return ret; 1573 } 1574 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled); 1575 if (ret) { 1576 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret); 1577 return ret; 1578 } 1579 if (dpni_enabled) 1580 /* Allow the MC some slack */ 1581 rte_delay_us(100 * 1000); 1582 } while (dpni_enabled && --retries); 1583 1584 if (!retries) { 1585 DPAA2_PMD_WARN("Retry count exceeded disabling dpni"); 1586 /* todo- we may have to manually cleanup queues. 1587 */ 1588 } else { 1589 DPAA2_PMD_INFO("Port %d Link DOWN successful", 1590 dev->data->port_id); 1591 } 1592 1593 dev->data->dev_link.link_status = 0; 1594 1595 return ret; 1596 } 1597 1598 static int 1599 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1600 { 1601 int ret = -EINVAL; 1602 struct dpaa2_dev_priv *priv; 1603 struct fsl_mc_io *dpni; 1604 struct dpni_link_state state = {0}; 1605 1606 PMD_INIT_FUNC_TRACE(); 1607 1608 priv = dev->data->dev_private; 1609 dpni = (struct fsl_mc_io *)priv->hw; 1610 1611 if (dpni == NULL || fc_conf == NULL) { 1612 DPAA2_PMD_ERR("device not configured"); 1613 return ret; 1614 } 1615 1616 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1617 if (ret) { 1618 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret); 1619 return ret; 1620 } 1621 1622 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 1623 if (state.options & DPNI_LINK_OPT_PAUSE) { 1624 /* DPNI_LINK_OPT_PAUSE set 1625 * if ASYM_PAUSE not set, 1626 * RX Side flow control (handle received Pause frame) 1627 * TX side flow control (send Pause frame) 1628 * if ASYM_PAUSE set, 1629 * RX Side flow control (handle received Pause frame) 1630 * No TX side flow control (send Pause frame disabled) 1631 */ 1632 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE)) 1633 fc_conf->mode = RTE_FC_FULL; 1634 else 1635 fc_conf->mode = RTE_FC_RX_PAUSE; 1636 } else { 1637 /* DPNI_LINK_OPT_PAUSE not set 1638 * if ASYM_PAUSE set, 1639 * TX side flow control (send Pause frame) 1640 * No RX side flow control (No action on pause frame rx) 1641 * if ASYM_PAUSE not set, 1642 * Flow control disabled 1643 */ 1644 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE) 1645 fc_conf->mode = RTE_FC_TX_PAUSE; 1646 else 1647 fc_conf->mode = RTE_FC_NONE; 1648 } 1649 1650 return ret; 1651 } 1652 1653 static int 1654 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1655 { 1656 int ret = -EINVAL; 1657 struct dpaa2_dev_priv *priv; 1658 struct fsl_mc_io *dpni; 1659 struct dpni_link_state state = {0}; 1660 struct dpni_link_cfg cfg = {0}; 1661 1662 PMD_INIT_FUNC_TRACE(); 1663 1664 priv = dev->data->dev_private; 1665 dpni = (struct fsl_mc_io *)priv->hw; 1666 1667 if (dpni == NULL) { 1668 DPAA2_PMD_ERR("dpni is NULL"); 1669 return ret; 1670 } 1671 1672 /* It is necessary to obtain the current state before setting fc_conf 1673 * as MC would return error in case rate, autoneg or duplex values are 1674 * different. 1675 */ 1676 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1677 if (ret) { 1678 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret); 1679 return -1; 1680 } 1681 1682 /* Disable link before setting configuration */ 1683 dpaa2_dev_set_link_down(dev); 1684 1685 /* Based on fc_conf, update cfg */ 1686 cfg.rate = state.rate; 1687 cfg.options = state.options; 1688 1689 /* update cfg with fc_conf */ 1690 switch (fc_conf->mode) { 1691 case RTE_FC_FULL: 1692 /* Full flow control; 1693 * OPT_PAUSE set, ASYM_PAUSE not set 1694 */ 1695 cfg.options |= DPNI_LINK_OPT_PAUSE; 1696 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 1697 break; 1698 case RTE_FC_TX_PAUSE: 1699 /* Enable RX flow control 1700 * OPT_PAUSE not set; 1701 * ASYM_PAUSE set; 1702 */ 1703 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 1704 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 1705 break; 1706 case RTE_FC_RX_PAUSE: 1707 /* Enable TX Flow control 1708 * OPT_PAUSE set 1709 * ASYM_PAUSE set 1710 */ 1711 cfg.options |= DPNI_LINK_OPT_PAUSE; 1712 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 1713 break; 1714 case RTE_FC_NONE: 1715 /* Disable Flow control 1716 * OPT_PAUSE not set 1717 * ASYM_PAUSE not set 1718 */ 1719 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 1720 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 1721 break; 1722 default: 1723 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)", 1724 fc_conf->mode); 1725 return -1; 1726 } 1727 1728 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 1729 if (ret) 1730 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)", 1731 ret); 1732 1733 /* Enable link */ 1734 dpaa2_dev_set_link_up(dev); 1735 1736 return ret; 1737 } 1738 1739 static int 1740 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, 1741 struct rte_eth_rss_conf *rss_conf) 1742 { 1743 struct rte_eth_dev_data *data = dev->data; 1744 struct rte_eth_conf *eth_conf = &data->dev_conf; 1745 int ret; 1746 1747 PMD_INIT_FUNC_TRACE(); 1748 1749 if (rss_conf->rss_hf) { 1750 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf); 1751 if (ret) { 1752 DPAA2_PMD_ERR("Unable to set flow dist"); 1753 return ret; 1754 } 1755 } else { 1756 ret = dpaa2_remove_flow_dist(dev, 0); 1757 if (ret) { 1758 DPAA2_PMD_ERR("Unable to remove flow dist"); 1759 return ret; 1760 } 1761 } 1762 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 1763 return 0; 1764 } 1765 1766 static int 1767 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1768 struct rte_eth_rss_conf *rss_conf) 1769 { 1770 struct rte_eth_dev_data *data = dev->data; 1771 struct rte_eth_conf *eth_conf = &data->dev_conf; 1772 1773 /* dpaa2 does not support rss_key, so length should be 0*/ 1774 rss_conf->rss_key_len = 0; 1775 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 1776 return 0; 1777 } 1778 1779 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 1780 int eth_rx_queue_id, 1781 uint16_t dpcon_id, 1782 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 1783 { 1784 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 1785 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_priv->hw; 1786 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 1787 uint8_t flow_id = dpaa2_ethq->flow_id; 1788 struct dpni_queue cfg; 1789 uint8_t options; 1790 int ret; 1791 1792 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL) 1793 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event; 1794 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) 1795 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event; 1796 else 1797 return -EINVAL; 1798 1799 memset(&cfg, 0, sizeof(struct dpni_queue)); 1800 options = DPNI_QUEUE_OPT_DEST; 1801 cfg.destination.type = DPNI_DEST_DPCON; 1802 cfg.destination.id = dpcon_id; 1803 cfg.destination.priority = queue_conf->ev.priority; 1804 1805 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 1806 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE; 1807 cfg.destination.hold_active = 1; 1808 } 1809 1810 options |= DPNI_QUEUE_OPT_USER_CTX; 1811 cfg.user_context = (size_t)(dpaa2_ethq); 1812 1813 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 1814 dpaa2_ethq->tc_index, flow_id, options, &cfg); 1815 if (ret) { 1816 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 1817 return ret; 1818 } 1819 1820 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event)); 1821 1822 return 0; 1823 } 1824 1825 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 1826 int eth_rx_queue_id) 1827 { 1828 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 1829 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_priv->hw; 1830 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 1831 uint8_t flow_id = dpaa2_ethq->flow_id; 1832 struct dpni_queue cfg; 1833 uint8_t options; 1834 int ret; 1835 1836 memset(&cfg, 0, sizeof(struct dpni_queue)); 1837 options = DPNI_QUEUE_OPT_DEST; 1838 cfg.destination.type = DPNI_DEST_NONE; 1839 1840 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 1841 dpaa2_ethq->tc_index, flow_id, options, &cfg); 1842 if (ret) 1843 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 1844 1845 return ret; 1846 } 1847 1848 static struct eth_dev_ops dpaa2_ethdev_ops = { 1849 .dev_configure = dpaa2_eth_dev_configure, 1850 .dev_start = dpaa2_dev_start, 1851 .dev_stop = dpaa2_dev_stop, 1852 .dev_close = dpaa2_dev_close, 1853 .promiscuous_enable = dpaa2_dev_promiscuous_enable, 1854 .promiscuous_disable = dpaa2_dev_promiscuous_disable, 1855 .allmulticast_enable = dpaa2_dev_allmulticast_enable, 1856 .allmulticast_disable = dpaa2_dev_allmulticast_disable, 1857 .dev_set_link_up = dpaa2_dev_set_link_up, 1858 .dev_set_link_down = dpaa2_dev_set_link_down, 1859 .link_update = dpaa2_dev_link_update, 1860 .stats_get = dpaa2_dev_stats_get, 1861 .xstats_get = dpaa2_dev_xstats_get, 1862 .xstats_get_by_id = dpaa2_xstats_get_by_id, 1863 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, 1864 .xstats_get_names = dpaa2_xstats_get_names, 1865 .stats_reset = dpaa2_dev_stats_reset, 1866 .xstats_reset = dpaa2_dev_stats_reset, 1867 .fw_version_get = dpaa2_fw_version_get, 1868 .dev_infos_get = dpaa2_dev_info_get, 1869 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, 1870 .mtu_set = dpaa2_dev_mtu_set, 1871 .vlan_filter_set = dpaa2_vlan_filter_set, 1872 .vlan_offload_set = dpaa2_vlan_offload_set, 1873 .vlan_tpid_set = dpaa2_vlan_tpid_set, 1874 .rx_queue_setup = dpaa2_dev_rx_queue_setup, 1875 .rx_queue_release = dpaa2_dev_rx_queue_release, 1876 .tx_queue_setup = dpaa2_dev_tx_queue_setup, 1877 .tx_queue_release = dpaa2_dev_tx_queue_release, 1878 .rx_queue_count = dpaa2_dev_rx_queue_count, 1879 .flow_ctrl_get = dpaa2_flow_ctrl_get, 1880 .flow_ctrl_set = dpaa2_flow_ctrl_set, 1881 .mac_addr_add = dpaa2_dev_add_mac_addr, 1882 .mac_addr_remove = dpaa2_dev_remove_mac_addr, 1883 .mac_addr_set = dpaa2_dev_set_mac_addr, 1884 .rss_hash_update = dpaa2_dev_rss_hash_update, 1885 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, 1886 }; 1887 1888 /* Populate the mac address from physically available (u-boot/firmware) and/or 1889 * one set by higher layers like MC (restool) etc. 1890 * Returns the table of MAC entries (multiple entries) 1891 */ 1892 static int 1893 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv, 1894 struct ether_addr *mac_entry) 1895 { 1896 int ret; 1897 struct ether_addr phy_mac, prime_mac; 1898 1899 memset(&phy_mac, 0, sizeof(struct ether_addr)); 1900 memset(&prime_mac, 0, sizeof(struct ether_addr)); 1901 1902 /* Get the physical device MAC address */ 1903 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 1904 phy_mac.addr_bytes); 1905 if (ret) { 1906 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret); 1907 goto cleanup; 1908 } 1909 1910 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 1911 prime_mac.addr_bytes); 1912 if (ret) { 1913 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret); 1914 goto cleanup; 1915 } 1916 1917 /* Now that both MAC have been obtained, do: 1918 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy 1919 * and return phy 1920 * If empty_mac(phy), return prime. 1921 * if both are empty, create random MAC, set as prime and return 1922 */ 1923 if (!is_zero_ether_addr(&phy_mac)) { 1924 /* If the addresses are not same, overwrite prime */ 1925 if (!is_same_ether_addr(&phy_mac, &prime_mac)) { 1926 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 1927 priv->token, 1928 phy_mac.addr_bytes); 1929 if (ret) { 1930 DPAA2_PMD_ERR("Unable to set MAC Address: %d", 1931 ret); 1932 goto cleanup; 1933 } 1934 memcpy(&prime_mac, &phy_mac, sizeof(struct ether_addr)); 1935 } 1936 } else if (is_zero_ether_addr(&prime_mac)) { 1937 /* In case phys and prime, both are zero, create random MAC */ 1938 eth_random_addr(prime_mac.addr_bytes); 1939 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 1940 priv->token, 1941 prime_mac.addr_bytes); 1942 if (ret) { 1943 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret); 1944 goto cleanup; 1945 } 1946 } 1947 1948 /* prime_mac the final MAC address */ 1949 memcpy(mac_entry, &prime_mac, sizeof(struct ether_addr)); 1950 return 0; 1951 1952 cleanup: 1953 return -1; 1954 } 1955 1956 static int 1957 dpaa2_dev_init(struct rte_eth_dev *eth_dev) 1958 { 1959 struct rte_device *dev = eth_dev->device; 1960 struct rte_dpaa2_device *dpaa2_dev; 1961 struct fsl_mc_io *dpni_dev; 1962 struct dpni_attr attr; 1963 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 1964 struct dpni_buffer_layout layout; 1965 int ret, hw_id; 1966 1967 PMD_INIT_FUNC_TRACE(); 1968 1969 /* For secondary processes, the primary has done all the work */ 1970 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1971 /* In case of secondary, only burst and ops API need to be 1972 * plugged. 1973 */ 1974 eth_dev->dev_ops = &dpaa2_ethdev_ops; 1975 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 1976 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 1977 return 0; 1978 } 1979 1980 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); 1981 1982 hw_id = dpaa2_dev->object_id; 1983 1984 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0); 1985 if (!dpni_dev) { 1986 DPAA2_PMD_ERR("Memory allocation failed for dpni device"); 1987 return -1; 1988 } 1989 1990 dpni_dev->regs = rte_mcp_ptr_list[0]; 1991 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token); 1992 if (ret) { 1993 DPAA2_PMD_ERR( 1994 "Failure in opening dpni@%d with err code %d", 1995 hw_id, ret); 1996 rte_free(dpni_dev); 1997 return -1; 1998 } 1999 2000 /* Clean the device first */ 2001 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token); 2002 if (ret) { 2003 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d", 2004 hw_id, ret); 2005 goto init_err; 2006 } 2007 2008 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr); 2009 if (ret) { 2010 DPAA2_PMD_ERR( 2011 "Failure in get dpni@%d attribute, err code %d", 2012 hw_id, ret); 2013 goto init_err; 2014 } 2015 2016 priv->num_rx_tc = attr.num_rx_tcs; 2017 2018 /* Resetting the "num_rx_queues" to equal number of queues in first TC 2019 * as only one TC is supported on Rx Side. Once Multiple TCs will be 2020 * in use for Rx processing then this will be changed or removed. 2021 */ 2022 priv->nb_rx_queues = attr.num_queues; 2023 2024 /* Using number of TX queues as number of TX TCs */ 2025 priv->nb_tx_queues = attr.num_tx_tcs; 2026 2027 DPAA2_PMD_DEBUG("RX-TC= %d, nb_rx_queues= %d, nb_tx_queues=%d", 2028 priv->num_rx_tc, priv->nb_rx_queues, 2029 priv->nb_tx_queues); 2030 2031 priv->hw = dpni_dev; 2032 priv->hw_id = hw_id; 2033 priv->options = attr.options; 2034 priv->max_mac_filters = attr.mac_filter_entries; 2035 priv->max_vlan_filters = attr.vlan_filter_entries; 2036 priv->flags = 0; 2037 2038 /* Allocate memory for hardware structure for queues */ 2039 ret = dpaa2_alloc_rx_tx_queues(eth_dev); 2040 if (ret) { 2041 DPAA2_PMD_ERR("Queue allocation Failed"); 2042 goto init_err; 2043 } 2044 2045 /* Allocate memory for storing MAC addresses. 2046 * Table of mac_filter_entries size is allocated so that RTE ether lib 2047 * can add MAC entries when rte_eth_dev_mac_addr_add is called. 2048 */ 2049 eth_dev->data->mac_addrs = rte_zmalloc("dpni", 2050 ETHER_ADDR_LEN * attr.mac_filter_entries, 0); 2051 if (eth_dev->data->mac_addrs == NULL) { 2052 DPAA2_PMD_ERR( 2053 "Failed to allocate %d bytes needed to store MAC addresses", 2054 ETHER_ADDR_LEN * attr.mac_filter_entries); 2055 ret = -ENOMEM; 2056 goto init_err; 2057 } 2058 2059 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]); 2060 if (ret) { 2061 DPAA2_PMD_ERR("Unable to fetch MAC Address for device"); 2062 rte_free(eth_dev->data->mac_addrs); 2063 eth_dev->data->mac_addrs = NULL; 2064 goto init_err; 2065 } 2066 2067 /* ... tx buffer layout ... */ 2068 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2069 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2070 layout.pass_frame_status = 1; 2071 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2072 DPNI_QUEUE_TX, &layout); 2073 if (ret) { 2074 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret); 2075 goto init_err; 2076 } 2077 2078 /* ... tx-conf and error buffer layout ... */ 2079 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2080 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2081 layout.pass_frame_status = 1; 2082 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2083 DPNI_QUEUE_TX_CONFIRM, &layout); 2084 if (ret) { 2085 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout", 2086 ret); 2087 goto init_err; 2088 } 2089 2090 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2091 2092 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2093 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2094 2095 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name); 2096 return 0; 2097 init_err: 2098 dpaa2_dev_uninit(eth_dev); 2099 return ret; 2100 } 2101 2102 static int 2103 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev) 2104 { 2105 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2106 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 2107 int ret; 2108 2109 PMD_INIT_FUNC_TRACE(); 2110 2111 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2112 return 0; 2113 2114 if (!dpni) { 2115 DPAA2_PMD_WARN("Already closed or not started"); 2116 return -1; 2117 } 2118 2119 dpaa2_dev_close(eth_dev); 2120 2121 dpaa2_free_rx_tx_queues(eth_dev); 2122 2123 /* Close the device at underlying layer*/ 2124 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token); 2125 if (ret) { 2126 DPAA2_PMD_ERR( 2127 "Failure closing dpni device with err code %d", 2128 ret); 2129 } 2130 2131 /* Free the allocated memory for ethernet private data and dpni*/ 2132 priv->hw = NULL; 2133 rte_free(dpni); 2134 2135 eth_dev->dev_ops = NULL; 2136 eth_dev->rx_pkt_burst = NULL; 2137 eth_dev->tx_pkt_burst = NULL; 2138 2139 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name); 2140 return 0; 2141 } 2142 2143 static int 2144 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, 2145 struct rte_dpaa2_device *dpaa2_dev) 2146 { 2147 struct rte_eth_dev *eth_dev; 2148 int diag; 2149 2150 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2151 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name); 2152 if (!eth_dev) 2153 return -ENODEV; 2154 eth_dev->data->dev_private = rte_zmalloc( 2155 "ethdev private structure", 2156 sizeof(struct dpaa2_dev_priv), 2157 RTE_CACHE_LINE_SIZE); 2158 if (eth_dev->data->dev_private == NULL) { 2159 DPAA2_PMD_CRIT( 2160 "Unable to allocate memory for private data"); 2161 rte_eth_dev_release_port(eth_dev); 2162 return -ENOMEM; 2163 } 2164 } else { 2165 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); 2166 if (!eth_dev) 2167 return -ENODEV; 2168 } 2169 2170 eth_dev->device = &dpaa2_dev->device; 2171 2172 dpaa2_dev->eth_dev = eth_dev; 2173 eth_dev->data->rx_mbuf_alloc_failed = 0; 2174 2175 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) 2176 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2177 2178 /* Invoke PMD device initialization function */ 2179 diag = dpaa2_dev_init(eth_dev); 2180 if (diag == 0) { 2181 rte_eth_dev_probing_finish(eth_dev); 2182 return 0; 2183 } 2184 2185 rte_eth_dev_release_port(eth_dev); 2186 return diag; 2187 } 2188 2189 static int 2190 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev) 2191 { 2192 struct rte_eth_dev *eth_dev; 2193 2194 eth_dev = dpaa2_dev->eth_dev; 2195 dpaa2_dev_uninit(eth_dev); 2196 2197 rte_eth_dev_release_port(eth_dev); 2198 2199 return 0; 2200 } 2201 2202 static struct rte_dpaa2_driver rte_dpaa2_pmd = { 2203 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA, 2204 .drv_type = DPAA2_ETH, 2205 .probe = rte_dpaa2_probe, 2206 .remove = rte_dpaa2_remove, 2207 }; 2208 2209 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd); 2210 2211 RTE_INIT(dpaa2_pmd_init_log) 2212 { 2213 dpaa2_logtype_pmd = rte_log_register("pmd.net.dpaa2"); 2214 if (dpaa2_logtype_pmd >= 0) 2215 rte_log_set_level(dpaa2_logtype_pmd, RTE_LOG_NOTICE); 2216 } 2217