1 /* * SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2021 NXP 5 * 6 */ 7 8 #include <time.h> 9 #include <net/if.h> 10 11 #include <rte_mbuf.h> 12 #include <ethdev_driver.h> 13 #include <rte_malloc.h> 14 #include <rte_memcpy.h> 15 #include <rte_string_fns.h> 16 #include <rte_cycles.h> 17 #include <rte_kvargs.h> 18 #include <rte_dev.h> 19 #include <rte_fslmc.h> 20 #include <rte_flow_driver.h> 21 22 #include "dpaa2_pmd_logs.h" 23 #include <fslmc_vfio.h> 24 #include <dpaa2_hw_pvt.h> 25 #include <dpaa2_hw_mempool.h> 26 #include <dpaa2_hw_dpio.h> 27 #include <mc/fsl_dpmng.h> 28 #include "dpaa2_ethdev.h" 29 #include "dpaa2_sparser.h" 30 #include <fsl_qbman_debug.h> 31 32 #define DRIVER_LOOPBACK_MODE "drv_loopback" 33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch" 34 #define DRIVER_TX_CONF "drv_tx_conf" 35 #define DRIVER_ERROR_QUEUE "drv_err_queue" 36 #define CHECK_INTERVAL 100 /* 100ms */ 37 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 38 39 /* Supported Rx offloads */ 40 static uint64_t dev_rx_offloads_sup = 41 DEV_RX_OFFLOAD_CHECKSUM | 42 DEV_RX_OFFLOAD_SCTP_CKSUM | 43 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 44 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 45 DEV_RX_OFFLOAD_VLAN_STRIP | 46 DEV_RX_OFFLOAD_VLAN_FILTER | 47 DEV_RX_OFFLOAD_JUMBO_FRAME | 48 DEV_RX_OFFLOAD_TIMESTAMP; 49 50 /* Rx offloads which cannot be disabled */ 51 static uint64_t dev_rx_offloads_nodis = 52 DEV_RX_OFFLOAD_RSS_HASH | 53 DEV_RX_OFFLOAD_SCATTER; 54 55 /* Supported Tx offloads */ 56 static uint64_t dev_tx_offloads_sup = 57 DEV_TX_OFFLOAD_VLAN_INSERT | 58 DEV_TX_OFFLOAD_IPV4_CKSUM | 59 DEV_TX_OFFLOAD_UDP_CKSUM | 60 DEV_TX_OFFLOAD_TCP_CKSUM | 61 DEV_TX_OFFLOAD_SCTP_CKSUM | 62 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 63 DEV_TX_OFFLOAD_MT_LOCKFREE | 64 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 65 66 /* Tx offloads which cannot be disabled */ 67 static uint64_t dev_tx_offloads_nodis = 68 DEV_TX_OFFLOAD_MULTI_SEGS; 69 70 /* enable timestamp in mbuf */ 71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS]; 72 uint64_t dpaa2_timestamp_rx_dynflag; 73 int dpaa2_timestamp_dynfield_offset = -1; 74 75 /* Enable error queue */ 76 bool dpaa2_enable_err_queue; 77 78 struct rte_dpaa2_xstats_name_off { 79 char name[RTE_ETH_XSTATS_NAME_SIZE]; 80 uint8_t page_id; /* dpni statistics page id */ 81 uint8_t stats_id; /* stats id in the given page */ 82 }; 83 84 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { 85 {"ingress_multicast_frames", 0, 2}, 86 {"ingress_multicast_bytes", 0, 3}, 87 {"ingress_broadcast_frames", 0, 4}, 88 {"ingress_broadcast_bytes", 0, 5}, 89 {"egress_multicast_frames", 1, 2}, 90 {"egress_multicast_bytes", 1, 3}, 91 {"egress_broadcast_frames", 1, 4}, 92 {"egress_broadcast_bytes", 1, 5}, 93 {"ingress_filtered_frames", 2, 0}, 94 {"ingress_discarded_frames", 2, 1}, 95 {"ingress_nobuffer_discards", 2, 2}, 96 {"egress_discarded_frames", 2, 3}, 97 {"egress_confirmed_frames", 2, 4}, 98 {"cgr_reject_frames", 4, 0}, 99 {"cgr_reject_bytes", 4, 1}, 100 }; 101 102 static struct rte_dpaa2_driver rte_dpaa2_pmd; 103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev, 104 int wait_to_complete); 105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); 106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); 107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 108 109 static int 110 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 111 { 112 int ret; 113 struct dpaa2_dev_priv *priv = dev->data->dev_private; 114 struct fsl_mc_io *dpni = dev->process_private; 115 116 PMD_INIT_FUNC_TRACE(); 117 118 if (dpni == NULL) { 119 DPAA2_PMD_ERR("dpni is NULL"); 120 return -1; 121 } 122 123 if (on) 124 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token, 125 vlan_id, 0, 0, 0); 126 else 127 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, 128 priv->token, vlan_id); 129 130 if (ret < 0) 131 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d", 132 ret, vlan_id, priv->hw_id); 133 134 return ret; 135 } 136 137 static int 138 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) 139 { 140 struct dpaa2_dev_priv *priv = dev->data->dev_private; 141 struct fsl_mc_io *dpni = dev->process_private; 142 int ret = 0; 143 144 PMD_INIT_FUNC_TRACE(); 145 146 if (mask & ETH_VLAN_FILTER_MASK) { 147 /* VLAN Filter not avaialble */ 148 if (!priv->max_vlan_filters) { 149 DPAA2_PMD_INFO("VLAN filter not available"); 150 return -ENOTSUP; 151 } 152 153 if (dev->data->dev_conf.rxmode.offloads & 154 DEV_RX_OFFLOAD_VLAN_FILTER) 155 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 156 priv->token, true); 157 else 158 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 159 priv->token, false); 160 if (ret < 0) 161 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret); 162 } 163 164 return ret; 165 } 166 167 static int 168 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev, 169 enum rte_vlan_type vlan_type __rte_unused, 170 uint16_t tpid) 171 { 172 struct dpaa2_dev_priv *priv = dev->data->dev_private; 173 struct fsl_mc_io *dpni = dev->process_private; 174 int ret = -ENOTSUP; 175 176 PMD_INIT_FUNC_TRACE(); 177 178 /* nothing to be done for standard vlan tpids */ 179 if (tpid == 0x8100 || tpid == 0x88A8) 180 return 0; 181 182 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 183 priv->token, tpid); 184 if (ret < 0) 185 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret); 186 /* if already configured tpids, remove them first */ 187 if (ret == -EBUSY) { 188 struct dpni_custom_tpid_cfg tpid_list = {0}; 189 190 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW, 191 priv->token, &tpid_list); 192 if (ret < 0) 193 goto fail; 194 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW, 195 priv->token, tpid_list.tpid1); 196 if (ret < 0) 197 goto fail; 198 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 199 priv->token, tpid); 200 } 201 fail: 202 return ret; 203 } 204 205 static int 206 dpaa2_fw_version_get(struct rte_eth_dev *dev, 207 char *fw_version, 208 size_t fw_size) 209 { 210 int ret; 211 struct fsl_mc_io *dpni = dev->process_private; 212 struct mc_soc_version mc_plat_info = {0}; 213 struct mc_version mc_ver_info = {0}; 214 215 PMD_INIT_FUNC_TRACE(); 216 217 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) 218 DPAA2_PMD_WARN("\tmc_get_soc_version failed"); 219 220 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info)) 221 DPAA2_PMD_WARN("\tmc_get_version failed"); 222 223 ret = snprintf(fw_version, fw_size, 224 "%x-%d.%d.%d", 225 mc_plat_info.svr, 226 mc_ver_info.major, 227 mc_ver_info.minor, 228 mc_ver_info.revision); 229 if (ret < 0) 230 return -EINVAL; 231 232 ret += 1; /* add the size of '\0' */ 233 if (fw_size < (size_t)ret) 234 return ret; 235 else 236 return 0; 237 } 238 239 static int 240 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 241 { 242 struct dpaa2_dev_priv *priv = dev->data->dev_private; 243 244 PMD_INIT_FUNC_TRACE(); 245 246 dev_info->max_mac_addrs = priv->max_mac_filters; 247 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN; 248 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE; 249 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues; 250 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues; 251 dev_info->rx_offload_capa = dev_rx_offloads_sup | 252 dev_rx_offloads_nodis; 253 dev_info->tx_offload_capa = dev_tx_offloads_sup | 254 dev_tx_offloads_nodis; 255 dev_info->speed_capa = ETH_LINK_SPEED_1G | 256 ETH_LINK_SPEED_2_5G | 257 ETH_LINK_SPEED_10G; 258 259 dev_info->max_hash_mac_addrs = 0; 260 dev_info->max_vfs = 0; 261 dev_info->max_vmdq_pools = ETH_16_POOLS; 262 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; 263 264 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size; 265 /* same is rx size for best perf */ 266 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size; 267 268 dev_info->default_rxportconf.nb_queues = 1; 269 dev_info->default_txportconf.nb_queues = 1; 270 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD; 271 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC; 272 273 if (dpaa2_svr_family == SVR_LX2160A) { 274 dev_info->speed_capa |= ETH_LINK_SPEED_25G | 275 ETH_LINK_SPEED_40G | 276 ETH_LINK_SPEED_50G | 277 ETH_LINK_SPEED_100G; 278 } 279 280 return 0; 281 } 282 283 static int 284 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 285 __rte_unused uint16_t queue_id, 286 struct rte_eth_burst_mode *mode) 287 { 288 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 289 int ret = -EINVAL; 290 unsigned int i; 291 const struct burst_info { 292 uint64_t flags; 293 const char *output; 294 } rx_offload_map[] = { 295 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"}, 296 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 297 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 298 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"}, 299 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"}, 300 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"}, 301 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"}, 302 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"}, 303 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}, 304 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"} 305 }; 306 307 /* Update Rx offload info */ 308 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 309 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 310 snprintf(mode->info, sizeof(mode->info), "%s", 311 rx_offload_map[i].output); 312 ret = 0; 313 break; 314 } 315 } 316 return ret; 317 } 318 319 static int 320 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 321 __rte_unused uint16_t queue_id, 322 struct rte_eth_burst_mode *mode) 323 { 324 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 325 int ret = -EINVAL; 326 unsigned int i; 327 const struct burst_info { 328 uint64_t flags; 329 const char *output; 330 } tx_offload_map[] = { 331 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"}, 332 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 333 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 334 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 335 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 336 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 337 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 338 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 339 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 340 }; 341 342 /* Update Tx offload info */ 343 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 344 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 345 snprintf(mode->info, sizeof(mode->info), "%s", 346 tx_offload_map[i].output); 347 ret = 0; 348 break; 349 } 350 } 351 return ret; 352 } 353 354 static int 355 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) 356 { 357 struct dpaa2_dev_priv *priv = dev->data->dev_private; 358 uint16_t dist_idx; 359 uint32_t vq_id; 360 uint8_t num_rxqueue_per_tc; 361 struct dpaa2_queue *mc_q, *mcq; 362 uint32_t tot_queues; 363 int i; 364 struct dpaa2_queue *dpaa2_q; 365 366 PMD_INIT_FUNC_TRACE(); 367 368 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); 369 if (priv->flags & DPAA2_TX_CONF_ENABLE) 370 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues; 371 else 372 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; 373 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, 374 RTE_CACHE_LINE_SIZE); 375 if (!mc_q) { 376 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues"); 377 return -1; 378 } 379 380 for (i = 0; i < priv->nb_rx_queues; i++) { 381 mc_q->eth_data = dev->data; 382 priv->rx_vq[i] = mc_q++; 383 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 384 dpaa2_q->q_storage = rte_malloc("dq_storage", 385 sizeof(struct queue_storage_info_t), 386 RTE_CACHE_LINE_SIZE); 387 if (!dpaa2_q->q_storage) 388 goto fail; 389 390 memset(dpaa2_q->q_storage, 0, 391 sizeof(struct queue_storage_info_t)); 392 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 393 goto fail; 394 } 395 396 if (dpaa2_enable_err_queue) { 397 priv->rx_err_vq = rte_zmalloc("dpni_rx_err", 398 sizeof(struct dpaa2_queue), 0); 399 400 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 401 dpaa2_q->q_storage = rte_malloc("err_dq_storage", 402 sizeof(struct queue_storage_info_t) * 403 RTE_MAX_LCORE, 404 RTE_CACHE_LINE_SIZE); 405 if (!dpaa2_q->q_storage) 406 goto fail; 407 408 memset(dpaa2_q->q_storage, 0, 409 sizeof(struct queue_storage_info_t)); 410 for (i = 0; i < RTE_MAX_LCORE; i++) 411 if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i])) 412 goto fail; 413 } 414 415 for (i = 0; i < priv->nb_tx_queues; i++) { 416 mc_q->eth_data = dev->data; 417 mc_q->flow_id = 0xffff; 418 priv->tx_vq[i] = mc_q++; 419 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 420 dpaa2_q->cscn = rte_malloc(NULL, 421 sizeof(struct qbman_result), 16); 422 if (!dpaa2_q->cscn) 423 goto fail_tx; 424 } 425 426 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 427 /*Setup tx confirmation queues*/ 428 for (i = 0; i < priv->nb_tx_queues; i++) { 429 mc_q->eth_data = dev->data; 430 mc_q->tc_index = i; 431 mc_q->flow_id = 0; 432 priv->tx_conf_vq[i] = mc_q++; 433 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 434 dpaa2_q->q_storage = 435 rte_malloc("dq_storage", 436 sizeof(struct queue_storage_info_t), 437 RTE_CACHE_LINE_SIZE); 438 if (!dpaa2_q->q_storage) 439 goto fail_tx_conf; 440 441 memset(dpaa2_q->q_storage, 0, 442 sizeof(struct queue_storage_info_t)); 443 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 444 goto fail_tx_conf; 445 } 446 } 447 448 vq_id = 0; 449 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { 450 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id]; 451 mcq->tc_index = dist_idx / num_rxqueue_per_tc; 452 mcq->flow_id = dist_idx % num_rxqueue_per_tc; 453 vq_id++; 454 } 455 456 return 0; 457 fail_tx_conf: 458 i -= 1; 459 while (i >= 0) { 460 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 461 rte_free(dpaa2_q->q_storage); 462 priv->tx_conf_vq[i--] = NULL; 463 } 464 i = priv->nb_tx_queues; 465 fail_tx: 466 i -= 1; 467 while (i >= 0) { 468 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 469 rte_free(dpaa2_q->cscn); 470 priv->tx_vq[i--] = NULL; 471 } 472 i = priv->nb_rx_queues; 473 fail: 474 i -= 1; 475 mc_q = priv->rx_vq[0]; 476 while (i >= 0) { 477 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 478 dpaa2_free_dq_storage(dpaa2_q->q_storage); 479 rte_free(dpaa2_q->q_storage); 480 priv->rx_vq[i--] = NULL; 481 } 482 483 if (dpaa2_enable_err_queue) { 484 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 485 if (dpaa2_q->q_storage) 486 dpaa2_free_dq_storage(dpaa2_q->q_storage); 487 rte_free(dpaa2_q->q_storage); 488 } 489 490 rte_free(mc_q); 491 return -1; 492 } 493 494 static void 495 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) 496 { 497 struct dpaa2_dev_priv *priv = dev->data->dev_private; 498 struct dpaa2_queue *dpaa2_q; 499 int i; 500 501 PMD_INIT_FUNC_TRACE(); 502 503 /* Queue allocation base */ 504 if (priv->rx_vq[0]) { 505 /* cleaning up queue storage */ 506 for (i = 0; i < priv->nb_rx_queues; i++) { 507 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 508 if (dpaa2_q->q_storage) 509 rte_free(dpaa2_q->q_storage); 510 } 511 /* cleanup tx queue cscn */ 512 for (i = 0; i < priv->nb_tx_queues; i++) { 513 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 514 rte_free(dpaa2_q->cscn); 515 } 516 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 517 /* cleanup tx conf queue storage */ 518 for (i = 0; i < priv->nb_tx_queues; i++) { 519 dpaa2_q = (struct dpaa2_queue *) 520 priv->tx_conf_vq[i]; 521 rte_free(dpaa2_q->q_storage); 522 } 523 } 524 /*free memory for all queues (RX+TX) */ 525 rte_free(priv->rx_vq[0]); 526 priv->rx_vq[0] = NULL; 527 } 528 } 529 530 static int 531 dpaa2_eth_dev_configure(struct rte_eth_dev *dev) 532 { 533 struct dpaa2_dev_priv *priv = dev->data->dev_private; 534 struct fsl_mc_io *dpni = dev->process_private; 535 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 536 uint64_t rx_offloads = eth_conf->rxmode.offloads; 537 uint64_t tx_offloads = eth_conf->txmode.offloads; 538 int rx_l3_csum_offload = false; 539 int rx_l4_csum_offload = false; 540 int tx_l3_csum_offload = false; 541 int tx_l4_csum_offload = false; 542 int ret, tc_index; 543 uint32_t max_rx_pktlen; 544 545 PMD_INIT_FUNC_TRACE(); 546 547 /* Rx offloads which are enabled by default */ 548 if (dev_rx_offloads_nodis & ~rx_offloads) { 549 DPAA2_PMD_INFO( 550 "Some of rx offloads enabled by default - requested 0x%" PRIx64 551 " fixed are 0x%" PRIx64, 552 rx_offloads, dev_rx_offloads_nodis); 553 } 554 555 /* Tx offloads which are enabled by default */ 556 if (dev_tx_offloads_nodis & ~tx_offloads) { 557 DPAA2_PMD_INFO( 558 "Some of tx offloads enabled by default - requested 0x%" PRIx64 559 " fixed are 0x%" PRIx64, 560 tx_offloads, dev_tx_offloads_nodis); 561 } 562 563 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + 564 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; 565 if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) { 566 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, 567 priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN); 568 if (ret != 0) { 569 DPAA2_PMD_ERR("Unable to set mtu. check config"); 570 return ret; 571 } 572 DPAA2_PMD_INFO("MTU configured for the device: %d", 573 dev->data->mtu); 574 } else { 575 return -1; 576 } 577 578 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) { 579 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 580 ret = dpaa2_setup_flow_dist(dev, 581 eth_conf->rx_adv_conf.rss_conf.rss_hf, 582 tc_index); 583 if (ret) { 584 DPAA2_PMD_ERR( 585 "Unable to set flow distribution on tc%d." 586 "Check queue config", tc_index); 587 return ret; 588 } 589 } 590 } 591 592 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) 593 rx_l3_csum_offload = true; 594 595 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) || 596 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) || 597 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM)) 598 rx_l4_csum_offload = true; 599 600 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 601 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload); 602 if (ret) { 603 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret); 604 return ret; 605 } 606 607 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 608 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload); 609 if (ret) { 610 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret); 611 return ret; 612 } 613 614 #if !defined(RTE_LIBRTE_IEEE1588) 615 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) 616 #endif 617 { 618 ret = rte_mbuf_dyn_rx_timestamp_register( 619 &dpaa2_timestamp_dynfield_offset, 620 &dpaa2_timestamp_rx_dynflag); 621 if (ret != 0) { 622 DPAA2_PMD_ERR("Error to register timestamp field/flag"); 623 return -rte_errno; 624 } 625 dpaa2_enable_ts[dev->data->port_id] = true; 626 } 627 628 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) 629 tx_l3_csum_offload = true; 630 631 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) || 632 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || 633 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM)) 634 tx_l4_csum_offload = true; 635 636 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 637 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload); 638 if (ret) { 639 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret); 640 return ret; 641 } 642 643 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 644 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload); 645 if (ret) { 646 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret); 647 return ret; 648 } 649 650 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in 651 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC] 652 * to 0 for LS2 in the hardware thus disabling data/annotation 653 * stashing. For LX2 this is fixed in hardware and thus hash result and 654 * parse results can be received in FD using this option. 655 */ 656 if (dpaa2_svr_family == SVR_LX2160A) { 657 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 658 DPNI_FLCTYPE_HASH, true); 659 if (ret) { 660 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret); 661 return ret; 662 } 663 } 664 665 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 666 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); 667 668 dpaa2_tm_init(dev); 669 670 return 0; 671 } 672 673 /* Function to setup RX flow information. It contains traffic class ID, 674 * flow ID, destination configuration etc. 675 */ 676 static int 677 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, 678 uint16_t rx_queue_id, 679 uint16_t nb_rx_desc, 680 unsigned int socket_id __rte_unused, 681 const struct rte_eth_rxconf *rx_conf, 682 struct rte_mempool *mb_pool) 683 { 684 struct dpaa2_dev_priv *priv = dev->data->dev_private; 685 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 686 struct dpaa2_queue *dpaa2_q; 687 struct dpni_queue cfg; 688 uint8_t options = 0; 689 uint8_t flow_id; 690 uint32_t bpid; 691 int i, ret; 692 693 PMD_INIT_FUNC_TRACE(); 694 695 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p", 696 dev, rx_queue_id, mb_pool, rx_conf); 697 698 /* Rx deferred start is not supported */ 699 if (rx_conf->rx_deferred_start) { 700 DPAA2_PMD_ERR("%p:Rx deferred start not supported", 701 (void *)dev); 702 return -EINVAL; 703 } 704 705 if (!priv->bp_list || priv->bp_list->mp != mb_pool) { 706 bpid = mempool_to_bpid(mb_pool); 707 ret = dpaa2_attach_bp_list(priv, 708 rte_dpaa2_bpid_info[bpid].bp_list); 709 if (ret) 710 return ret; 711 } 712 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 713 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ 714 dpaa2_q->bp_array = rte_dpaa2_bpid_info; 715 dpaa2_q->nb_desc = UINT16_MAX; 716 dpaa2_q->offloads = rx_conf->offloads; 717 718 /*Get the flow id from given VQ id*/ 719 flow_id = dpaa2_q->flow_id; 720 memset(&cfg, 0, sizeof(struct dpni_queue)); 721 722 options = options | DPNI_QUEUE_OPT_USER_CTX; 723 cfg.user_context = (size_t)(dpaa2_q); 724 725 /* check if a private cgr available. */ 726 for (i = 0; i < priv->max_cgs; i++) { 727 if (!priv->cgid_in_use[i]) { 728 priv->cgid_in_use[i] = 1; 729 break; 730 } 731 } 732 733 if (i < priv->max_cgs) { 734 options |= DPNI_QUEUE_OPT_SET_CGID; 735 cfg.cgid = i; 736 dpaa2_q->cgid = cfg.cgid; 737 } else { 738 dpaa2_q->cgid = 0xff; 739 } 740 741 /*if ls2088 or rev2 device, enable the stashing */ 742 743 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { 744 options |= DPNI_QUEUE_OPT_FLC; 745 cfg.flc.stash_control = true; 746 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0; 747 /* 00 00 00 - last 6 bit represent annotation, context stashing, 748 * data stashing setting 01 01 00 (0x14) 749 * (in following order ->DS AS CS) 750 * to enable 1 line data, 1 line annotation. 751 * For LX2, this setting should be 01 00 00 (0x10) 752 */ 753 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A) 754 cfg.flc.value |= 0x10; 755 else 756 cfg.flc.value |= 0x14; 757 } 758 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, 759 dpaa2_q->tc_index, flow_id, options, &cfg); 760 if (ret) { 761 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret); 762 return -1; 763 } 764 765 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) { 766 struct dpni_taildrop taildrop; 767 768 taildrop.enable = 1; 769 dpaa2_q->nb_desc = nb_rx_desc; 770 /* Private CGR will use tail drop length as nb_rx_desc. 771 * for rest cases we can use standard byte based tail drop. 772 * There is no HW restriction, but number of CGRs are limited, 773 * hence this restriction is placed. 774 */ 775 if (dpaa2_q->cgid != 0xff) { 776 /*enabling per rx queue congestion control */ 777 taildrop.threshold = nb_rx_desc; 778 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES; 779 taildrop.oal = 0; 780 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d", 781 rx_queue_id); 782 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 783 DPNI_CP_CONGESTION_GROUP, 784 DPNI_QUEUE_RX, 785 dpaa2_q->tc_index, 786 dpaa2_q->cgid, &taildrop); 787 } else { 788 /*enabling per rx queue congestion control */ 789 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q; 790 taildrop.units = DPNI_CONGESTION_UNIT_BYTES; 791 taildrop.oal = CONG_RX_OAL; 792 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d", 793 rx_queue_id); 794 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 795 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 796 dpaa2_q->tc_index, flow_id, 797 &taildrop); 798 } 799 if (ret) { 800 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 801 ret); 802 return -1; 803 } 804 } else { /* Disable tail Drop */ 805 struct dpni_taildrop taildrop = {0}; 806 DPAA2_PMD_INFO("Tail drop is disabled on queue"); 807 808 taildrop.enable = 0; 809 if (dpaa2_q->cgid != 0xff) { 810 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 811 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX, 812 dpaa2_q->tc_index, 813 dpaa2_q->cgid, &taildrop); 814 } else { 815 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 816 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 817 dpaa2_q->tc_index, flow_id, &taildrop); 818 } 819 if (ret) { 820 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 821 ret); 822 return -1; 823 } 824 } 825 826 dev->data->rx_queues[rx_queue_id] = dpaa2_q; 827 return 0; 828 } 829 830 static int 831 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, 832 uint16_t tx_queue_id, 833 uint16_t nb_tx_desc, 834 unsigned int socket_id __rte_unused, 835 const struct rte_eth_txconf *tx_conf) 836 { 837 struct dpaa2_dev_priv *priv = dev->data->dev_private; 838 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *) 839 priv->tx_vq[tx_queue_id]; 840 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *) 841 priv->tx_conf_vq[tx_queue_id]; 842 struct fsl_mc_io *dpni = dev->process_private; 843 struct dpni_queue tx_conf_cfg; 844 struct dpni_queue tx_flow_cfg; 845 uint8_t options = 0, flow_id; 846 struct dpni_queue_id qid; 847 uint32_t tc_id; 848 int ret; 849 850 PMD_INIT_FUNC_TRACE(); 851 852 /* Tx deferred start is not supported */ 853 if (tx_conf->tx_deferred_start) { 854 DPAA2_PMD_ERR("%p:Tx deferred start not supported", 855 (void *)dev); 856 return -EINVAL; 857 } 858 859 dpaa2_q->nb_desc = UINT16_MAX; 860 dpaa2_q->offloads = tx_conf->offloads; 861 862 /* Return if queue already configured */ 863 if (dpaa2_q->flow_id != 0xffff) { 864 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 865 return 0; 866 } 867 868 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue)); 869 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue)); 870 871 tc_id = tx_queue_id; 872 flow_id = 0; 873 874 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX, 875 tc_id, flow_id, options, &tx_flow_cfg); 876 if (ret) { 877 DPAA2_PMD_ERR("Error in setting the tx flow: " 878 "tc_id=%d, flow=%d err=%d", 879 tc_id, flow_id, ret); 880 return -1; 881 } 882 883 dpaa2_q->flow_id = flow_id; 884 885 if (tx_queue_id == 0) { 886 /*Set tx-conf and error configuration*/ 887 if (priv->flags & DPAA2_TX_CONF_ENABLE) 888 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 889 priv->token, 890 DPNI_CONF_AFFINE); 891 else 892 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 893 priv->token, 894 DPNI_CONF_DISABLE); 895 if (ret) { 896 DPAA2_PMD_ERR("Error in set tx conf mode settings: " 897 "err=%d", ret); 898 return -1; 899 } 900 } 901 dpaa2_q->tc_index = tc_id; 902 903 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 904 DPNI_QUEUE_TX, dpaa2_q->tc_index, 905 dpaa2_q->flow_id, &tx_flow_cfg, &qid); 906 if (ret) { 907 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 908 return -1; 909 } 910 dpaa2_q->fqid = qid.fqid; 911 912 if (!(priv->flags & DPAA2_TX_CGR_OFF)) { 913 struct dpni_congestion_notification_cfg cong_notif_cfg = {0}; 914 915 dpaa2_q->nb_desc = nb_tx_desc; 916 917 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; 918 cong_notif_cfg.threshold_entry = nb_tx_desc; 919 /* Notify that the queue is not congested when the data in 920 * the queue is below this thershold.(90% of value) 921 */ 922 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10; 923 cong_notif_cfg.message_ctx = 0; 924 cong_notif_cfg.message_iova = 925 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); 926 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; 927 cong_notif_cfg.notification_mode = 928 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | 929 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | 930 DPNI_CONG_OPT_COHERENT_WRITE; 931 cong_notif_cfg.cg_point = DPNI_CP_QUEUE; 932 933 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW, 934 priv->token, 935 DPNI_QUEUE_TX, 936 tc_id, 937 &cong_notif_cfg); 938 if (ret) { 939 DPAA2_PMD_ERR( 940 "Error in setting tx congestion notification: " 941 "err=%d", ret); 942 return -ret; 943 } 944 } 945 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf; 946 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 947 948 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 949 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q; 950 options = options | DPNI_QUEUE_OPT_USER_CTX; 951 tx_conf_cfg.user_context = (size_t)(dpaa2_q); 952 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 953 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index, 954 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg); 955 if (ret) { 956 DPAA2_PMD_ERR("Error in setting the tx conf flow: " 957 "tc_index=%d, flow=%d err=%d", 958 dpaa2_tx_conf_q->tc_index, 959 dpaa2_tx_conf_q->flow_id, ret); 960 return -1; 961 } 962 963 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 964 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index, 965 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid); 966 if (ret) { 967 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 968 return -1; 969 } 970 dpaa2_tx_conf_q->fqid = qid.fqid; 971 } 972 return 0; 973 } 974 975 static void 976 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id) 977 { 978 struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id]; 979 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private; 980 struct fsl_mc_io *dpni = 981 (struct fsl_mc_io *)priv->eth_dev->process_private; 982 uint8_t options = 0; 983 int ret; 984 struct dpni_queue cfg; 985 986 memset(&cfg, 0, sizeof(struct dpni_queue)); 987 PMD_INIT_FUNC_TRACE(); 988 if (dpaa2_q->cgid != 0xff) { 989 options = DPNI_QUEUE_OPT_CLEAR_CGID; 990 cfg.cgid = dpaa2_q->cgid; 991 992 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 993 DPNI_QUEUE_RX, 994 dpaa2_q->tc_index, dpaa2_q->flow_id, 995 options, &cfg); 996 if (ret) 997 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d", 998 dpaa2_q->fqid, ret); 999 priv->cgid_in_use[dpaa2_q->cgid] = 0; 1000 dpaa2_q->cgid = 0xff; 1001 } 1002 } 1003 1004 static uint32_t 1005 dpaa2_dev_rx_queue_count(void *rx_queue) 1006 { 1007 int32_t ret; 1008 struct dpaa2_queue *dpaa2_q; 1009 struct qbman_swp *swp; 1010 struct qbman_fq_query_np_rslt state; 1011 uint32_t frame_cnt = 0; 1012 1013 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 1014 ret = dpaa2_affine_qbman_swp(); 1015 if (ret) { 1016 DPAA2_PMD_ERR( 1017 "Failed to allocate IO portal, tid: %d\n", 1018 rte_gettid()); 1019 return -EINVAL; 1020 } 1021 } 1022 swp = DPAA2_PER_LCORE_PORTAL; 1023 1024 dpaa2_q = rx_queue; 1025 1026 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { 1027 frame_cnt = qbman_fq_state_frame_count(&state); 1028 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u", 1029 rx_queue, frame_cnt); 1030 } 1031 return frame_cnt; 1032 } 1033 1034 static const uint32_t * 1035 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev) 1036 { 1037 static const uint32_t ptypes[] = { 1038 /*todo -= add more types */ 1039 RTE_PTYPE_L2_ETHER, 1040 RTE_PTYPE_L3_IPV4, 1041 RTE_PTYPE_L3_IPV4_EXT, 1042 RTE_PTYPE_L3_IPV6, 1043 RTE_PTYPE_L3_IPV6_EXT, 1044 RTE_PTYPE_L4_TCP, 1045 RTE_PTYPE_L4_UDP, 1046 RTE_PTYPE_L4_SCTP, 1047 RTE_PTYPE_L4_ICMP, 1048 RTE_PTYPE_UNKNOWN 1049 }; 1050 1051 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx || 1052 dev->rx_pkt_burst == dpaa2_dev_rx || 1053 dev->rx_pkt_burst == dpaa2_dev_loopback_rx) 1054 return ptypes; 1055 return NULL; 1056 } 1057 1058 /** 1059 * Dpaa2 link Interrupt handler 1060 * 1061 * @param param 1062 * The address of parameter (struct rte_eth_dev *) regsitered before. 1063 * 1064 * @return 1065 * void 1066 */ 1067 static void 1068 dpaa2_interrupt_handler(void *param) 1069 { 1070 struct rte_eth_dev *dev = param; 1071 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1072 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1073 int ret; 1074 int irq_index = DPNI_IRQ_INDEX; 1075 unsigned int status = 0, clear = 0; 1076 1077 PMD_INIT_FUNC_TRACE(); 1078 1079 if (dpni == NULL) { 1080 DPAA2_PMD_ERR("dpni is NULL"); 1081 return; 1082 } 1083 1084 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, 1085 irq_index, &status); 1086 if (unlikely(ret)) { 1087 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret); 1088 clear = 0xffffffff; 1089 goto out; 1090 } 1091 1092 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { 1093 clear = DPNI_IRQ_EVENT_LINK_CHANGED; 1094 dpaa2_dev_link_update(dev, 0); 1095 /* calling all the apps registered for link status event */ 1096 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1097 } 1098 out: 1099 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, 1100 irq_index, clear); 1101 if (unlikely(ret)) 1102 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret); 1103 } 1104 1105 static int 1106 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) 1107 { 1108 int err = 0; 1109 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1110 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1111 int irq_index = DPNI_IRQ_INDEX; 1112 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; 1113 1114 PMD_INIT_FUNC_TRACE(); 1115 1116 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, 1117 irq_index, mask); 1118 if (err < 0) { 1119 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err, 1120 strerror(-err)); 1121 return err; 1122 } 1123 1124 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, 1125 irq_index, enable); 1126 if (err < 0) 1127 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err, 1128 strerror(-err)); 1129 1130 return err; 1131 } 1132 1133 static int 1134 dpaa2_dev_start(struct rte_eth_dev *dev) 1135 { 1136 struct rte_device *rdev = dev->device; 1137 struct rte_dpaa2_device *dpaa2_dev; 1138 struct rte_eth_dev_data *data = dev->data; 1139 struct dpaa2_dev_priv *priv = data->dev_private; 1140 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1141 struct dpni_queue cfg; 1142 struct dpni_error_cfg err_cfg; 1143 uint16_t qdid; 1144 struct dpni_queue_id qid; 1145 struct dpaa2_queue *dpaa2_q; 1146 int ret, i; 1147 struct rte_intr_handle *intr_handle; 1148 1149 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 1150 intr_handle = &dpaa2_dev->intr_handle; 1151 1152 PMD_INIT_FUNC_TRACE(); 1153 1154 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1155 if (ret) { 1156 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d", 1157 priv->hw_id, ret); 1158 return ret; 1159 } 1160 1161 /* Power up the phy. Needed to make the link go UP */ 1162 dpaa2_dev_set_link_up(dev); 1163 1164 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token, 1165 DPNI_QUEUE_TX, &qdid); 1166 if (ret) { 1167 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret); 1168 return ret; 1169 } 1170 priv->qdid = qdid; 1171 1172 for (i = 0; i < data->nb_rx_queues; i++) { 1173 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i]; 1174 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1175 DPNI_QUEUE_RX, dpaa2_q->tc_index, 1176 dpaa2_q->flow_id, &cfg, &qid); 1177 if (ret) { 1178 DPAA2_PMD_ERR("Error in getting flow information: " 1179 "err=%d", ret); 1180 return ret; 1181 } 1182 dpaa2_q->fqid = qid.fqid; 1183 } 1184 1185 if (dpaa2_enable_err_queue) { 1186 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1187 DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid); 1188 if (ret) { 1189 DPAA2_PMD_ERR("Error getting rx err flow information: err=%d", 1190 ret); 1191 return ret; 1192 } 1193 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 1194 dpaa2_q->fqid = qid.fqid; 1195 dpaa2_q->eth_data = dev->data; 1196 1197 err_cfg.errors = DPNI_ERROR_DISC; 1198 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE; 1199 } else { 1200 /* checksum errors, send them to normal path 1201 * and set it in annotation 1202 */ 1203 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 1204 1205 /* if packet with parse error are not to be dropped */ 1206 err_cfg.errors |= DPNI_ERROR_PHE; 1207 1208 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; 1209 } 1210 err_cfg.set_frame_annotation = true; 1211 1212 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, 1213 priv->token, &err_cfg); 1214 if (ret) { 1215 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d", 1216 ret); 1217 return ret; 1218 } 1219 1220 /* if the interrupts were configured on this devices*/ 1221 if (intr_handle && (intr_handle->fd) && 1222 (dev->data->dev_conf.intr_conf.lsc != 0)) { 1223 /* Registering LSC interrupt handler */ 1224 rte_intr_callback_register(intr_handle, 1225 dpaa2_interrupt_handler, 1226 (void *)dev); 1227 1228 /* enable vfio intr/eventfd mapping 1229 * Interrupt index 0 is required, so we can not use 1230 * rte_intr_enable. 1231 */ 1232 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); 1233 1234 /* enable dpni_irqs */ 1235 dpaa2_eth_setup_irqs(dev, 1); 1236 } 1237 1238 /* Change the tx burst function if ordered queues are used */ 1239 if (priv->en_ordered) 1240 dev->tx_pkt_burst = dpaa2_dev_tx_ordered; 1241 1242 return 0; 1243 } 1244 1245 /** 1246 * This routine disables all traffic on the adapter by issuing a 1247 * global reset on the MAC. 1248 */ 1249 static int 1250 dpaa2_dev_stop(struct rte_eth_dev *dev) 1251 { 1252 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1253 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1254 int ret; 1255 struct rte_eth_link link; 1256 struct rte_intr_handle *intr_handle = dev->intr_handle; 1257 1258 PMD_INIT_FUNC_TRACE(); 1259 1260 /* reset interrupt callback */ 1261 if (intr_handle && (intr_handle->fd) && 1262 (dev->data->dev_conf.intr_conf.lsc != 0)) { 1263 /*disable dpni irqs */ 1264 dpaa2_eth_setup_irqs(dev, 0); 1265 1266 /* disable vfio intr before callback unregister */ 1267 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); 1268 1269 /* Unregistering LSC interrupt handler */ 1270 rte_intr_callback_unregister(intr_handle, 1271 dpaa2_interrupt_handler, 1272 (void *)dev); 1273 } 1274 1275 dpaa2_dev_set_link_down(dev); 1276 1277 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); 1278 if (ret) { 1279 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", 1280 ret, priv->hw_id); 1281 return ret; 1282 } 1283 1284 /* clear the recorded link status */ 1285 memset(&link, 0, sizeof(link)); 1286 rte_eth_linkstatus_set(dev, &link); 1287 1288 return 0; 1289 } 1290 1291 static int 1292 dpaa2_dev_close(struct rte_eth_dev *dev) 1293 { 1294 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1295 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1296 int i, ret; 1297 struct rte_eth_link link; 1298 1299 PMD_INIT_FUNC_TRACE(); 1300 1301 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1302 return 0; 1303 1304 if (!dpni) { 1305 DPAA2_PMD_WARN("Already closed or not started"); 1306 return -1; 1307 } 1308 1309 dpaa2_tm_deinit(dev); 1310 dpaa2_flow_clean(dev); 1311 /* Clean the device first */ 1312 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); 1313 if (ret) { 1314 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret); 1315 return -1; 1316 } 1317 1318 memset(&link, 0, sizeof(link)); 1319 rte_eth_linkstatus_set(dev, &link); 1320 1321 /* Free private queues memory */ 1322 dpaa2_free_rx_tx_queues(dev); 1323 /* Close the device at underlying layer*/ 1324 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token); 1325 if (ret) { 1326 DPAA2_PMD_ERR("Failure closing dpni device with err code %d", 1327 ret); 1328 } 1329 1330 /* Free the allocated memory for ethernet private data and dpni*/ 1331 priv->hw = NULL; 1332 dev->process_private = NULL; 1333 rte_free(dpni); 1334 1335 for (i = 0; i < MAX_TCS; i++) 1336 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]); 1337 1338 if (priv->extract.qos_extract_param) 1339 rte_free((void *)(size_t)priv->extract.qos_extract_param); 1340 1341 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name); 1342 return 0; 1343 } 1344 1345 static int 1346 dpaa2_dev_promiscuous_enable( 1347 struct rte_eth_dev *dev) 1348 { 1349 int ret; 1350 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1351 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1352 1353 PMD_INIT_FUNC_TRACE(); 1354 1355 if (dpni == NULL) { 1356 DPAA2_PMD_ERR("dpni is NULL"); 1357 return -ENODEV; 1358 } 1359 1360 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1361 if (ret < 0) 1362 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret); 1363 1364 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1365 if (ret < 0) 1366 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret); 1367 1368 return ret; 1369 } 1370 1371 static int 1372 dpaa2_dev_promiscuous_disable( 1373 struct rte_eth_dev *dev) 1374 { 1375 int ret; 1376 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1377 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1378 1379 PMD_INIT_FUNC_TRACE(); 1380 1381 if (dpni == NULL) { 1382 DPAA2_PMD_ERR("dpni is NULL"); 1383 return -ENODEV; 1384 } 1385 1386 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1387 if (ret < 0) 1388 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret); 1389 1390 if (dev->data->all_multicast == 0) { 1391 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, 1392 priv->token, false); 1393 if (ret < 0) 1394 DPAA2_PMD_ERR("Unable to disable M promisc mode %d", 1395 ret); 1396 } 1397 1398 return ret; 1399 } 1400 1401 static int 1402 dpaa2_dev_allmulticast_enable( 1403 struct rte_eth_dev *dev) 1404 { 1405 int ret; 1406 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1407 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1408 1409 PMD_INIT_FUNC_TRACE(); 1410 1411 if (dpni == NULL) { 1412 DPAA2_PMD_ERR("dpni is NULL"); 1413 return -ENODEV; 1414 } 1415 1416 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1417 if (ret < 0) 1418 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret); 1419 1420 return ret; 1421 } 1422 1423 static int 1424 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev) 1425 { 1426 int ret; 1427 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1428 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1429 1430 PMD_INIT_FUNC_TRACE(); 1431 1432 if (dpni == NULL) { 1433 DPAA2_PMD_ERR("dpni is NULL"); 1434 return -ENODEV; 1435 } 1436 1437 /* must remain on for all promiscuous */ 1438 if (dev->data->promiscuous == 1) 1439 return 0; 1440 1441 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1442 if (ret < 0) 1443 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret); 1444 1445 return ret; 1446 } 1447 1448 static int 1449 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1450 { 1451 int ret; 1452 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1453 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1454 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 1455 + VLAN_TAG_SIZE; 1456 1457 PMD_INIT_FUNC_TRACE(); 1458 1459 if (dpni == NULL) { 1460 DPAA2_PMD_ERR("dpni is NULL"); 1461 return -EINVAL; 1462 } 1463 1464 /* check that mtu is within the allowed range */ 1465 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN) 1466 return -EINVAL; 1467 1468 /* Set the Max Rx frame length as 'mtu' + 1469 * Maximum Ethernet header length 1470 */ 1471 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 1472 frame_size - RTE_ETHER_CRC_LEN); 1473 if (ret) { 1474 DPAA2_PMD_ERR("Setting the max frame length failed"); 1475 return -1; 1476 } 1477 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu); 1478 return 0; 1479 } 1480 1481 static int 1482 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev, 1483 struct rte_ether_addr *addr, 1484 __rte_unused uint32_t index, 1485 __rte_unused uint32_t pool) 1486 { 1487 int ret; 1488 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1489 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1490 1491 PMD_INIT_FUNC_TRACE(); 1492 1493 if (dpni == NULL) { 1494 DPAA2_PMD_ERR("dpni is NULL"); 1495 return -1; 1496 } 1497 1498 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token, 1499 addr->addr_bytes, 0, 0, 0); 1500 if (ret) 1501 DPAA2_PMD_ERR( 1502 "error: Adding the MAC ADDR failed: err = %d", ret); 1503 return 0; 1504 } 1505 1506 static void 1507 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev, 1508 uint32_t index) 1509 { 1510 int ret; 1511 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1512 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1513 struct rte_eth_dev_data *data = dev->data; 1514 struct rte_ether_addr *macaddr; 1515 1516 PMD_INIT_FUNC_TRACE(); 1517 1518 macaddr = &data->mac_addrs[index]; 1519 1520 if (dpni == NULL) { 1521 DPAA2_PMD_ERR("dpni is NULL"); 1522 return; 1523 } 1524 1525 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW, 1526 priv->token, macaddr->addr_bytes); 1527 if (ret) 1528 DPAA2_PMD_ERR( 1529 "error: Removing the MAC ADDR failed: err = %d", ret); 1530 } 1531 1532 static int 1533 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev, 1534 struct rte_ether_addr *addr) 1535 { 1536 int ret; 1537 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1538 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1539 1540 PMD_INIT_FUNC_TRACE(); 1541 1542 if (dpni == NULL) { 1543 DPAA2_PMD_ERR("dpni is NULL"); 1544 return -EINVAL; 1545 } 1546 1547 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW, 1548 priv->token, addr->addr_bytes); 1549 1550 if (ret) 1551 DPAA2_PMD_ERR( 1552 "error: Setting the MAC ADDR failed %d", ret); 1553 1554 return ret; 1555 } 1556 1557 static 1558 int dpaa2_dev_stats_get(struct rte_eth_dev *dev, 1559 struct rte_eth_stats *stats) 1560 { 1561 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1562 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1563 int32_t retcode; 1564 uint8_t page0 = 0, page1 = 1, page2 = 2; 1565 union dpni_statistics value; 1566 int i; 1567 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq; 1568 1569 memset(&value, 0, sizeof(union dpni_statistics)); 1570 1571 PMD_INIT_FUNC_TRACE(); 1572 1573 if (!dpni) { 1574 DPAA2_PMD_ERR("dpni is NULL"); 1575 return -EINVAL; 1576 } 1577 1578 if (!stats) { 1579 DPAA2_PMD_ERR("stats is NULL"); 1580 return -EINVAL; 1581 } 1582 1583 /*Get Counters from page_0*/ 1584 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1585 page0, 0, &value); 1586 if (retcode) 1587 goto err; 1588 1589 stats->ipackets = value.page_0.ingress_all_frames; 1590 stats->ibytes = value.page_0.ingress_all_bytes; 1591 1592 /*Get Counters from page_1*/ 1593 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1594 page1, 0, &value); 1595 if (retcode) 1596 goto err; 1597 1598 stats->opackets = value.page_1.egress_all_frames; 1599 stats->obytes = value.page_1.egress_all_bytes; 1600 1601 /*Get Counters from page_2*/ 1602 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1603 page2, 0, &value); 1604 if (retcode) 1605 goto err; 1606 1607 /* Ingress drop frame count due to configured rules */ 1608 stats->ierrors = value.page_2.ingress_filtered_frames; 1609 /* Ingress drop frame count due to error */ 1610 stats->ierrors += value.page_2.ingress_discarded_frames; 1611 1612 stats->oerrors = value.page_2.egress_discarded_frames; 1613 stats->imissed = value.page_2.ingress_nobuffer_discards; 1614 1615 /* Fill in per queue stats */ 1616 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) && 1617 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) { 1618 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i]; 1619 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i]; 1620 if (dpaa2_rxq) 1621 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts; 1622 if (dpaa2_txq) 1623 stats->q_opackets[i] = dpaa2_txq->tx_pkts; 1624 1625 /* Byte counting is not implemented */ 1626 stats->q_ibytes[i] = 0; 1627 stats->q_obytes[i] = 0; 1628 } 1629 1630 return 0; 1631 1632 err: 1633 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1634 return retcode; 1635 }; 1636 1637 static int 1638 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1639 unsigned int n) 1640 { 1641 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1642 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1643 int32_t retcode; 1644 union dpni_statistics value[5] = {}; 1645 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); 1646 1647 if (n < num) 1648 return num; 1649 1650 if (xstats == NULL) 1651 return 0; 1652 1653 /* Get Counters from page_0*/ 1654 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1655 0, 0, &value[0]); 1656 if (retcode) 1657 goto err; 1658 1659 /* Get Counters from page_1*/ 1660 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1661 1, 0, &value[1]); 1662 if (retcode) 1663 goto err; 1664 1665 /* Get Counters from page_2*/ 1666 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1667 2, 0, &value[2]); 1668 if (retcode) 1669 goto err; 1670 1671 for (i = 0; i < priv->max_cgs; i++) { 1672 if (!priv->cgid_in_use[i]) { 1673 /* Get Counters from page_4*/ 1674 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, 1675 priv->token, 1676 4, 0, &value[4]); 1677 if (retcode) 1678 goto err; 1679 break; 1680 } 1681 } 1682 1683 for (i = 0; i < num; i++) { 1684 xstats[i].id = i; 1685 xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. 1686 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1687 } 1688 return i; 1689 err: 1690 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode); 1691 return retcode; 1692 } 1693 1694 static int 1695 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1696 struct rte_eth_xstat_name *xstats_names, 1697 unsigned int limit) 1698 { 1699 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1700 1701 if (limit < stat_cnt) 1702 return stat_cnt; 1703 1704 if (xstats_names != NULL) 1705 for (i = 0; i < stat_cnt; i++) 1706 strlcpy(xstats_names[i].name, 1707 dpaa2_xstats_strings[i].name, 1708 sizeof(xstats_names[i].name)); 1709 1710 return stat_cnt; 1711 } 1712 1713 static int 1714 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1715 uint64_t *values, unsigned int n) 1716 { 1717 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1718 uint64_t values_copy[stat_cnt]; 1719 1720 if (!ids) { 1721 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1722 struct fsl_mc_io *dpni = 1723 (struct fsl_mc_io *)dev->process_private; 1724 int32_t retcode; 1725 union dpni_statistics value[5] = {}; 1726 1727 if (n < stat_cnt) 1728 return stat_cnt; 1729 1730 if (!values) 1731 return 0; 1732 1733 /* Get Counters from page_0*/ 1734 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1735 0, 0, &value[0]); 1736 if (retcode) 1737 return 0; 1738 1739 /* Get Counters from page_1*/ 1740 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1741 1, 0, &value[1]); 1742 if (retcode) 1743 return 0; 1744 1745 /* Get Counters from page_2*/ 1746 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1747 2, 0, &value[2]); 1748 if (retcode) 1749 return 0; 1750 1751 /* Get Counters from page_4*/ 1752 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1753 4, 0, &value[4]); 1754 if (retcode) 1755 return 0; 1756 1757 for (i = 0; i < stat_cnt; i++) { 1758 values[i] = value[dpaa2_xstats_strings[i].page_id]. 1759 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1760 } 1761 return stat_cnt; 1762 } 1763 1764 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 1765 1766 for (i = 0; i < n; i++) { 1767 if (ids[i] >= stat_cnt) { 1768 DPAA2_PMD_ERR("xstats id value isn't valid"); 1769 return -1; 1770 } 1771 values[i] = values_copy[ids[i]]; 1772 } 1773 return n; 1774 } 1775 1776 static int 1777 dpaa2_xstats_get_names_by_id( 1778 struct rte_eth_dev *dev, 1779 const uint64_t *ids, 1780 struct rte_eth_xstat_name *xstats_names, 1781 unsigned int limit) 1782 { 1783 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1784 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 1785 1786 if (!ids) 1787 return dpaa2_xstats_get_names(dev, xstats_names, limit); 1788 1789 dpaa2_xstats_get_names(dev, xstats_names_copy, limit); 1790 1791 for (i = 0; i < limit; i++) { 1792 if (ids[i] >= stat_cnt) { 1793 DPAA2_PMD_ERR("xstats id value isn't valid"); 1794 return -1; 1795 } 1796 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1797 } 1798 return limit; 1799 } 1800 1801 static int 1802 dpaa2_dev_stats_reset(struct rte_eth_dev *dev) 1803 { 1804 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1805 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1806 int retcode; 1807 int i; 1808 struct dpaa2_queue *dpaa2_q; 1809 1810 PMD_INIT_FUNC_TRACE(); 1811 1812 if (dpni == NULL) { 1813 DPAA2_PMD_ERR("dpni is NULL"); 1814 return -EINVAL; 1815 } 1816 1817 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token); 1818 if (retcode) 1819 goto error; 1820 1821 /* Reset the per queue stats in dpaa2_queue structure */ 1822 for (i = 0; i < priv->nb_rx_queues; i++) { 1823 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 1824 if (dpaa2_q) 1825 dpaa2_q->rx_pkts = 0; 1826 } 1827 1828 for (i = 0; i < priv->nb_tx_queues; i++) { 1829 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 1830 if (dpaa2_q) 1831 dpaa2_q->tx_pkts = 0; 1832 } 1833 1834 return 0; 1835 1836 error: 1837 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1838 return retcode; 1839 }; 1840 1841 /* return 0 means link status changed, -1 means not changed */ 1842 static int 1843 dpaa2_dev_link_update(struct rte_eth_dev *dev, 1844 int wait_to_complete) 1845 { 1846 int ret; 1847 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1848 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1849 struct rte_eth_link link; 1850 struct dpni_link_state state = {0}; 1851 uint8_t count; 1852 1853 if (dpni == NULL) { 1854 DPAA2_PMD_ERR("dpni is NULL"); 1855 return 0; 1856 } 1857 1858 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 1859 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, 1860 &state); 1861 if (ret < 0) { 1862 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); 1863 return -1; 1864 } 1865 if (state.up == ETH_LINK_DOWN && 1866 wait_to_complete) 1867 rte_delay_ms(CHECK_INTERVAL); 1868 else 1869 break; 1870 } 1871 1872 memset(&link, 0, sizeof(struct rte_eth_link)); 1873 link.link_status = state.up; 1874 link.link_speed = state.rate; 1875 1876 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1877 link.link_duplex = ETH_LINK_HALF_DUPLEX; 1878 else 1879 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1880 1881 ret = rte_eth_linkstatus_set(dev, &link); 1882 if (ret == -1) 1883 DPAA2_PMD_DEBUG("No change in status"); 1884 else 1885 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 1886 link.link_status ? "Up" : "Down"); 1887 1888 return ret; 1889 } 1890 1891 /** 1892 * Toggle the DPNI to enable, if not already enabled. 1893 * This is not strictly PHY up/down - it is more of logical toggling. 1894 */ 1895 static int 1896 dpaa2_dev_set_link_up(struct rte_eth_dev *dev) 1897 { 1898 int ret = -EINVAL; 1899 struct dpaa2_dev_priv *priv; 1900 struct fsl_mc_io *dpni; 1901 int en = 0; 1902 struct dpni_link_state state = {0}; 1903 1904 priv = dev->data->dev_private; 1905 dpni = (struct fsl_mc_io *)dev->process_private; 1906 1907 if (dpni == NULL) { 1908 DPAA2_PMD_ERR("dpni is NULL"); 1909 return ret; 1910 } 1911 1912 /* Check if DPNI is currently enabled */ 1913 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en); 1914 if (ret) { 1915 /* Unable to obtain dpni status; Not continuing */ 1916 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1917 return -EINVAL; 1918 } 1919 1920 /* Enable link if not already enabled */ 1921 if (!en) { 1922 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1923 if (ret) { 1924 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1925 return -EINVAL; 1926 } 1927 } 1928 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1929 if (ret < 0) { 1930 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret); 1931 return -1; 1932 } 1933 1934 /* changing tx burst function to start enqueues */ 1935 dev->tx_pkt_burst = dpaa2_dev_tx; 1936 dev->data->dev_link.link_status = state.up; 1937 dev->data->dev_link.link_speed = state.rate; 1938 1939 if (state.up) 1940 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id); 1941 else 1942 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id); 1943 return ret; 1944 } 1945 1946 /** 1947 * Toggle the DPNI to disable, if not already disabled. 1948 * This is not strictly PHY up/down - it is more of logical toggling. 1949 */ 1950 static int 1951 dpaa2_dev_set_link_down(struct rte_eth_dev *dev) 1952 { 1953 int ret = -EINVAL; 1954 struct dpaa2_dev_priv *priv; 1955 struct fsl_mc_io *dpni; 1956 int dpni_enabled = 0; 1957 int retries = 10; 1958 1959 PMD_INIT_FUNC_TRACE(); 1960 1961 priv = dev->data->dev_private; 1962 dpni = (struct fsl_mc_io *)dev->process_private; 1963 1964 if (dpni == NULL) { 1965 DPAA2_PMD_ERR("Device has not yet been configured"); 1966 return ret; 1967 } 1968 1969 /*changing tx burst function to avoid any more enqueues */ 1970 dev->tx_pkt_burst = dummy_dev_tx; 1971 1972 /* Loop while dpni_disable() attempts to drain the egress FQs 1973 * and confirm them back to us. 1974 */ 1975 do { 1976 ret = dpni_disable(dpni, 0, priv->token); 1977 if (ret) { 1978 DPAA2_PMD_ERR("dpni disable failed (%d)", ret); 1979 return ret; 1980 } 1981 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled); 1982 if (ret) { 1983 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret); 1984 return ret; 1985 } 1986 if (dpni_enabled) 1987 /* Allow the MC some slack */ 1988 rte_delay_us(100 * 1000); 1989 } while (dpni_enabled && --retries); 1990 1991 if (!retries) { 1992 DPAA2_PMD_WARN("Retry count exceeded disabling dpni"); 1993 /* todo- we may have to manually cleanup queues. 1994 */ 1995 } else { 1996 DPAA2_PMD_INFO("Port %d Link DOWN successful", 1997 dev->data->port_id); 1998 } 1999 2000 dev->data->dev_link.link_status = 0; 2001 2002 return ret; 2003 } 2004 2005 static int 2006 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2007 { 2008 int ret = -EINVAL; 2009 struct dpaa2_dev_priv *priv; 2010 struct fsl_mc_io *dpni; 2011 struct dpni_link_state state = {0}; 2012 2013 PMD_INIT_FUNC_TRACE(); 2014 2015 priv = dev->data->dev_private; 2016 dpni = (struct fsl_mc_io *)dev->process_private; 2017 2018 if (dpni == NULL || fc_conf == NULL) { 2019 DPAA2_PMD_ERR("device not configured"); 2020 return ret; 2021 } 2022 2023 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 2024 if (ret) { 2025 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret); 2026 return ret; 2027 } 2028 2029 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 2030 if (state.options & DPNI_LINK_OPT_PAUSE) { 2031 /* DPNI_LINK_OPT_PAUSE set 2032 * if ASYM_PAUSE not set, 2033 * RX Side flow control (handle received Pause frame) 2034 * TX side flow control (send Pause frame) 2035 * if ASYM_PAUSE set, 2036 * RX Side flow control (handle received Pause frame) 2037 * No TX side flow control (send Pause frame disabled) 2038 */ 2039 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE)) 2040 fc_conf->mode = RTE_FC_FULL; 2041 else 2042 fc_conf->mode = RTE_FC_RX_PAUSE; 2043 } else { 2044 /* DPNI_LINK_OPT_PAUSE not set 2045 * if ASYM_PAUSE set, 2046 * TX side flow control (send Pause frame) 2047 * No RX side flow control (No action on pause frame rx) 2048 * if ASYM_PAUSE not set, 2049 * Flow control disabled 2050 */ 2051 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE) 2052 fc_conf->mode = RTE_FC_TX_PAUSE; 2053 else 2054 fc_conf->mode = RTE_FC_NONE; 2055 } 2056 2057 return ret; 2058 } 2059 2060 static int 2061 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2062 { 2063 int ret = -EINVAL; 2064 struct dpaa2_dev_priv *priv; 2065 struct fsl_mc_io *dpni; 2066 struct dpni_link_state state = {0}; 2067 struct dpni_link_cfg cfg = {0}; 2068 2069 PMD_INIT_FUNC_TRACE(); 2070 2071 priv = dev->data->dev_private; 2072 dpni = (struct fsl_mc_io *)dev->process_private; 2073 2074 if (dpni == NULL) { 2075 DPAA2_PMD_ERR("dpni is NULL"); 2076 return ret; 2077 } 2078 2079 /* It is necessary to obtain the current state before setting fc_conf 2080 * as MC would return error in case rate, autoneg or duplex values are 2081 * different. 2082 */ 2083 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 2084 if (ret) { 2085 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret); 2086 return -1; 2087 } 2088 2089 /* Disable link before setting configuration */ 2090 dpaa2_dev_set_link_down(dev); 2091 2092 /* Based on fc_conf, update cfg */ 2093 cfg.rate = state.rate; 2094 cfg.options = state.options; 2095 2096 /* update cfg with fc_conf */ 2097 switch (fc_conf->mode) { 2098 case RTE_FC_FULL: 2099 /* Full flow control; 2100 * OPT_PAUSE set, ASYM_PAUSE not set 2101 */ 2102 cfg.options |= DPNI_LINK_OPT_PAUSE; 2103 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2104 break; 2105 case RTE_FC_TX_PAUSE: 2106 /* Enable RX flow control 2107 * OPT_PAUSE not set; 2108 * ASYM_PAUSE set; 2109 */ 2110 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2111 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2112 break; 2113 case RTE_FC_RX_PAUSE: 2114 /* Enable TX Flow control 2115 * OPT_PAUSE set 2116 * ASYM_PAUSE set 2117 */ 2118 cfg.options |= DPNI_LINK_OPT_PAUSE; 2119 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2120 break; 2121 case RTE_FC_NONE: 2122 /* Disable Flow control 2123 * OPT_PAUSE not set 2124 * ASYM_PAUSE not set 2125 */ 2126 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2127 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2128 break; 2129 default: 2130 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)", 2131 fc_conf->mode); 2132 return -1; 2133 } 2134 2135 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 2136 if (ret) 2137 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)", 2138 ret); 2139 2140 /* Enable link */ 2141 dpaa2_dev_set_link_up(dev); 2142 2143 return ret; 2144 } 2145 2146 static int 2147 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, 2148 struct rte_eth_rss_conf *rss_conf) 2149 { 2150 struct rte_eth_dev_data *data = dev->data; 2151 struct dpaa2_dev_priv *priv = data->dev_private; 2152 struct rte_eth_conf *eth_conf = &data->dev_conf; 2153 int ret, tc_index; 2154 2155 PMD_INIT_FUNC_TRACE(); 2156 2157 if (rss_conf->rss_hf) { 2158 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2159 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf, 2160 tc_index); 2161 if (ret) { 2162 DPAA2_PMD_ERR("Unable to set flow dist on tc%d", 2163 tc_index); 2164 return ret; 2165 } 2166 } 2167 } else { 2168 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2169 ret = dpaa2_remove_flow_dist(dev, tc_index); 2170 if (ret) { 2171 DPAA2_PMD_ERR( 2172 "Unable to remove flow dist on tc%d", 2173 tc_index); 2174 return ret; 2175 } 2176 } 2177 } 2178 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 2179 return 0; 2180 } 2181 2182 static int 2183 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 2184 struct rte_eth_rss_conf *rss_conf) 2185 { 2186 struct rte_eth_dev_data *data = dev->data; 2187 struct rte_eth_conf *eth_conf = &data->dev_conf; 2188 2189 /* dpaa2 does not support rss_key, so length should be 0*/ 2190 rss_conf->rss_key_len = 0; 2191 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 2192 return 0; 2193 } 2194 2195 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 2196 int eth_rx_queue_id, 2197 struct dpaa2_dpcon_dev *dpcon, 2198 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 2199 { 2200 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2201 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2202 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2203 uint8_t flow_id = dpaa2_ethq->flow_id; 2204 struct dpni_queue cfg; 2205 uint8_t options, priority; 2206 int ret; 2207 2208 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL) 2209 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event; 2210 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) 2211 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event; 2212 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED) 2213 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event; 2214 else 2215 return -EINVAL; 2216 2217 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) * 2218 (dpcon->num_priorities - 1); 2219 2220 memset(&cfg, 0, sizeof(struct dpni_queue)); 2221 options = DPNI_QUEUE_OPT_DEST; 2222 cfg.destination.type = DPNI_DEST_DPCON; 2223 cfg.destination.id = dpcon->dpcon_id; 2224 cfg.destination.priority = priority; 2225 2226 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 2227 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE; 2228 cfg.destination.hold_active = 1; 2229 } 2230 2231 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED && 2232 !eth_priv->en_ordered) { 2233 struct opr_cfg ocfg; 2234 2235 /* Restoration window size = 256 frames */ 2236 ocfg.oprrws = 3; 2237 /* Restoration window size = 512 frames for LX2 */ 2238 if (dpaa2_svr_family == SVR_LX2160A) 2239 ocfg.oprrws = 4; 2240 /* Auto advance NESN window enabled */ 2241 ocfg.oa = 1; 2242 /* Late arrival window size disabled */ 2243 ocfg.olws = 0; 2244 /* ORL resource exhaustaion advance NESN disabled */ 2245 ocfg.oeane = 0; 2246 /* Loose ordering enabled */ 2247 ocfg.oloe = 1; 2248 eth_priv->en_loose_ordered = 1; 2249 /* Strict ordering enabled if explicitly set */ 2250 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) { 2251 ocfg.oloe = 0; 2252 eth_priv->en_loose_ordered = 0; 2253 } 2254 2255 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token, 2256 dpaa2_ethq->tc_index, flow_id, 2257 OPR_OPT_CREATE, &ocfg, 0); 2258 if (ret) { 2259 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret); 2260 return ret; 2261 } 2262 2263 eth_priv->en_ordered = 1; 2264 } 2265 2266 options |= DPNI_QUEUE_OPT_USER_CTX; 2267 cfg.user_context = (size_t)(dpaa2_ethq); 2268 2269 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2270 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2271 if (ret) { 2272 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2273 return ret; 2274 } 2275 2276 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event)); 2277 2278 return 0; 2279 } 2280 2281 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 2282 int eth_rx_queue_id) 2283 { 2284 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2285 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2286 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2287 uint8_t flow_id = dpaa2_ethq->flow_id; 2288 struct dpni_queue cfg; 2289 uint8_t options; 2290 int ret; 2291 2292 memset(&cfg, 0, sizeof(struct dpni_queue)); 2293 options = DPNI_QUEUE_OPT_DEST; 2294 cfg.destination.type = DPNI_DEST_NONE; 2295 2296 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2297 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2298 if (ret) 2299 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2300 2301 return ret; 2302 } 2303 2304 static int 2305 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev, 2306 const struct rte_flow_ops **ops) 2307 { 2308 if (!dev) 2309 return -ENODEV; 2310 2311 *ops = &dpaa2_flow_ops; 2312 return 0; 2313 } 2314 2315 static void 2316 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2317 struct rte_eth_rxq_info *qinfo) 2318 { 2319 struct dpaa2_queue *rxq; 2320 struct dpaa2_dev_priv *priv = dev->data->dev_private; 2321 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2322 uint16_t max_frame_length; 2323 2324 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id]; 2325 2326 qinfo->mp = rxq->mb_pool; 2327 qinfo->scattered_rx = dev->data->scattered_rx; 2328 qinfo->nb_desc = rxq->nb_desc; 2329 if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 2330 &max_frame_length) == 0) 2331 qinfo->rx_buf_size = max_frame_length; 2332 2333 qinfo->conf.rx_free_thresh = 1; 2334 qinfo->conf.rx_drop_en = 1; 2335 qinfo->conf.rx_deferred_start = 0; 2336 qinfo->conf.offloads = rxq->offloads; 2337 } 2338 2339 static void 2340 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2341 struct rte_eth_txq_info *qinfo) 2342 { 2343 struct dpaa2_queue *txq; 2344 2345 txq = dev->data->tx_queues[queue_id]; 2346 2347 qinfo->nb_desc = txq->nb_desc; 2348 qinfo->conf.tx_thresh.pthresh = 0; 2349 qinfo->conf.tx_thresh.hthresh = 0; 2350 qinfo->conf.tx_thresh.wthresh = 0; 2351 2352 qinfo->conf.tx_free_thresh = 0; 2353 qinfo->conf.tx_rs_thresh = 0; 2354 qinfo->conf.offloads = txq->offloads; 2355 qinfo->conf.tx_deferred_start = 0; 2356 } 2357 2358 static int 2359 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2360 { 2361 *(const void **)ops = &dpaa2_tm_ops; 2362 2363 return 0; 2364 } 2365 2366 void 2367 rte_pmd_dpaa2_thread_init(void) 2368 { 2369 int ret; 2370 2371 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 2372 ret = dpaa2_affine_qbman_swp(); 2373 if (ret) { 2374 DPAA2_PMD_ERR( 2375 "Failed to allocate IO portal, tid: %d\n", 2376 rte_gettid()); 2377 return; 2378 } 2379 } 2380 } 2381 2382 static struct eth_dev_ops dpaa2_ethdev_ops = { 2383 .dev_configure = dpaa2_eth_dev_configure, 2384 .dev_start = dpaa2_dev_start, 2385 .dev_stop = dpaa2_dev_stop, 2386 .dev_close = dpaa2_dev_close, 2387 .promiscuous_enable = dpaa2_dev_promiscuous_enable, 2388 .promiscuous_disable = dpaa2_dev_promiscuous_disable, 2389 .allmulticast_enable = dpaa2_dev_allmulticast_enable, 2390 .allmulticast_disable = dpaa2_dev_allmulticast_disable, 2391 .dev_set_link_up = dpaa2_dev_set_link_up, 2392 .dev_set_link_down = dpaa2_dev_set_link_down, 2393 .link_update = dpaa2_dev_link_update, 2394 .stats_get = dpaa2_dev_stats_get, 2395 .xstats_get = dpaa2_dev_xstats_get, 2396 .xstats_get_by_id = dpaa2_xstats_get_by_id, 2397 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, 2398 .xstats_get_names = dpaa2_xstats_get_names, 2399 .stats_reset = dpaa2_dev_stats_reset, 2400 .xstats_reset = dpaa2_dev_stats_reset, 2401 .fw_version_get = dpaa2_fw_version_get, 2402 .dev_infos_get = dpaa2_dev_info_get, 2403 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, 2404 .mtu_set = dpaa2_dev_mtu_set, 2405 .vlan_filter_set = dpaa2_vlan_filter_set, 2406 .vlan_offload_set = dpaa2_vlan_offload_set, 2407 .vlan_tpid_set = dpaa2_vlan_tpid_set, 2408 .rx_queue_setup = dpaa2_dev_rx_queue_setup, 2409 .rx_queue_release = dpaa2_dev_rx_queue_release, 2410 .tx_queue_setup = dpaa2_dev_tx_queue_setup, 2411 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get, 2412 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get, 2413 .flow_ctrl_get = dpaa2_flow_ctrl_get, 2414 .flow_ctrl_set = dpaa2_flow_ctrl_set, 2415 .mac_addr_add = dpaa2_dev_add_mac_addr, 2416 .mac_addr_remove = dpaa2_dev_remove_mac_addr, 2417 .mac_addr_set = dpaa2_dev_set_mac_addr, 2418 .rss_hash_update = dpaa2_dev_rss_hash_update, 2419 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, 2420 .flow_ops_get = dpaa2_dev_flow_ops_get, 2421 .rxq_info_get = dpaa2_rxq_info_get, 2422 .txq_info_get = dpaa2_txq_info_get, 2423 .tm_ops_get = dpaa2_tm_ops_get, 2424 #if defined(RTE_LIBRTE_IEEE1588) 2425 .timesync_enable = dpaa2_timesync_enable, 2426 .timesync_disable = dpaa2_timesync_disable, 2427 .timesync_read_time = dpaa2_timesync_read_time, 2428 .timesync_write_time = dpaa2_timesync_write_time, 2429 .timesync_adjust_time = dpaa2_timesync_adjust_time, 2430 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp, 2431 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp, 2432 #endif 2433 }; 2434 2435 /* Populate the mac address from physically available (u-boot/firmware) and/or 2436 * one set by higher layers like MC (restool) etc. 2437 * Returns the table of MAC entries (multiple entries) 2438 */ 2439 static int 2440 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv, 2441 struct rte_ether_addr *mac_entry) 2442 { 2443 int ret; 2444 struct rte_ether_addr phy_mac, prime_mac; 2445 2446 memset(&phy_mac, 0, sizeof(struct rte_ether_addr)); 2447 memset(&prime_mac, 0, sizeof(struct rte_ether_addr)); 2448 2449 /* Get the physical device MAC address */ 2450 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2451 phy_mac.addr_bytes); 2452 if (ret) { 2453 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret); 2454 goto cleanup; 2455 } 2456 2457 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2458 prime_mac.addr_bytes); 2459 if (ret) { 2460 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret); 2461 goto cleanup; 2462 } 2463 2464 /* Now that both MAC have been obtained, do: 2465 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy 2466 * and return phy 2467 * If empty_mac(phy), return prime. 2468 * if both are empty, create random MAC, set as prime and return 2469 */ 2470 if (!rte_is_zero_ether_addr(&phy_mac)) { 2471 /* If the addresses are not same, overwrite prime */ 2472 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) { 2473 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2474 priv->token, 2475 phy_mac.addr_bytes); 2476 if (ret) { 2477 DPAA2_PMD_ERR("Unable to set MAC Address: %d", 2478 ret); 2479 goto cleanup; 2480 } 2481 memcpy(&prime_mac, &phy_mac, 2482 sizeof(struct rte_ether_addr)); 2483 } 2484 } else if (rte_is_zero_ether_addr(&prime_mac)) { 2485 /* In case phys and prime, both are zero, create random MAC */ 2486 rte_eth_random_addr(prime_mac.addr_bytes); 2487 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2488 priv->token, 2489 prime_mac.addr_bytes); 2490 if (ret) { 2491 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret); 2492 goto cleanup; 2493 } 2494 } 2495 2496 /* prime_mac the final MAC address */ 2497 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr)); 2498 return 0; 2499 2500 cleanup: 2501 return -1; 2502 } 2503 2504 static int 2505 check_devargs_handler(__rte_unused const char *key, const char *value, 2506 __rte_unused void *opaque) 2507 { 2508 if (strcmp(value, "1")) 2509 return -1; 2510 2511 return 0; 2512 } 2513 2514 static int 2515 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key) 2516 { 2517 struct rte_kvargs *kvlist; 2518 2519 if (!devargs) 2520 return 0; 2521 2522 kvlist = rte_kvargs_parse(devargs->args, NULL); 2523 if (!kvlist) 2524 return 0; 2525 2526 if (!rte_kvargs_count(kvlist, key)) { 2527 rte_kvargs_free(kvlist); 2528 return 0; 2529 } 2530 2531 if (rte_kvargs_process(kvlist, key, 2532 check_devargs_handler, NULL) < 0) { 2533 rte_kvargs_free(kvlist); 2534 return 0; 2535 } 2536 rte_kvargs_free(kvlist); 2537 2538 return 1; 2539 } 2540 2541 static int 2542 dpaa2_dev_init(struct rte_eth_dev *eth_dev) 2543 { 2544 struct rte_device *dev = eth_dev->device; 2545 struct rte_dpaa2_device *dpaa2_dev; 2546 struct fsl_mc_io *dpni_dev; 2547 struct dpni_attr attr; 2548 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2549 struct dpni_buffer_layout layout; 2550 int ret, hw_id, i; 2551 2552 PMD_INIT_FUNC_TRACE(); 2553 2554 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0); 2555 if (!dpni_dev) { 2556 DPAA2_PMD_ERR("Memory allocation failed for dpni device"); 2557 return -1; 2558 } 2559 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX); 2560 eth_dev->process_private = (void *)dpni_dev; 2561 2562 /* For secondary processes, the primary has done all the work */ 2563 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2564 /* In case of secondary, only burst and ops API need to be 2565 * plugged. 2566 */ 2567 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2568 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count; 2569 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) 2570 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2571 else if (dpaa2_get_devargs(dev->devargs, 2572 DRIVER_NO_PREFETCH_MODE)) 2573 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2574 else 2575 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2576 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2577 return 0; 2578 } 2579 2580 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); 2581 2582 hw_id = dpaa2_dev->object_id; 2583 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token); 2584 if (ret) { 2585 DPAA2_PMD_ERR( 2586 "Failure in opening dpni@%d with err code %d", 2587 hw_id, ret); 2588 rte_free(dpni_dev); 2589 return -1; 2590 } 2591 2592 /* Clean the device first */ 2593 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token); 2594 if (ret) { 2595 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d", 2596 hw_id, ret); 2597 goto init_err; 2598 } 2599 2600 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr); 2601 if (ret) { 2602 DPAA2_PMD_ERR( 2603 "Failure in get dpni@%d attribute, err code %d", 2604 hw_id, ret); 2605 goto init_err; 2606 } 2607 2608 priv->num_rx_tc = attr.num_rx_tcs; 2609 priv->qos_entries = attr.qos_entries; 2610 priv->fs_entries = attr.fs_entries; 2611 priv->dist_queues = attr.num_queues; 2612 2613 /* only if the custom CG is enabled */ 2614 if (attr.options & DPNI_OPT_CUSTOM_CG) 2615 priv->max_cgs = attr.num_cgs; 2616 else 2617 priv->max_cgs = 0; 2618 2619 for (i = 0; i < priv->max_cgs; i++) 2620 priv->cgid_in_use[i] = 0; 2621 2622 for (i = 0; i < attr.num_rx_tcs; i++) 2623 priv->nb_rx_queues += attr.num_queues; 2624 2625 /* Using number of TX queues as number of TX TCs */ 2626 priv->nb_tx_queues = attr.num_tx_tcs; 2627 2628 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d", 2629 priv->num_rx_tc, priv->nb_rx_queues, 2630 priv->nb_tx_queues, priv->max_cgs); 2631 2632 priv->hw = dpni_dev; 2633 priv->hw_id = hw_id; 2634 priv->options = attr.options; 2635 priv->max_mac_filters = attr.mac_filter_entries; 2636 priv->max_vlan_filters = attr.vlan_filter_entries; 2637 priv->flags = 0; 2638 #if defined(RTE_LIBRTE_IEEE1588) 2639 printf("DPDK IEEE1588 is enabled\n"); 2640 priv->flags |= DPAA2_TX_CONF_ENABLE; 2641 #endif 2642 /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */ 2643 if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) { 2644 priv->flags |= DPAA2_TX_CONF_ENABLE; 2645 DPAA2_PMD_INFO("TX_CONF Enabled"); 2646 } 2647 2648 if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) { 2649 dpaa2_enable_err_queue = 1; 2650 DPAA2_PMD_INFO("Enable error queue"); 2651 } 2652 2653 /* Allocate memory for hardware structure for queues */ 2654 ret = dpaa2_alloc_rx_tx_queues(eth_dev); 2655 if (ret) { 2656 DPAA2_PMD_ERR("Queue allocation Failed"); 2657 goto init_err; 2658 } 2659 2660 /* Allocate memory for storing MAC addresses. 2661 * Table of mac_filter_entries size is allocated so that RTE ether lib 2662 * can add MAC entries when rte_eth_dev_mac_addr_add is called. 2663 */ 2664 eth_dev->data->mac_addrs = rte_zmalloc("dpni", 2665 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0); 2666 if (eth_dev->data->mac_addrs == NULL) { 2667 DPAA2_PMD_ERR( 2668 "Failed to allocate %d bytes needed to store MAC addresses", 2669 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries); 2670 ret = -ENOMEM; 2671 goto init_err; 2672 } 2673 2674 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]); 2675 if (ret) { 2676 DPAA2_PMD_ERR("Unable to fetch MAC Address for device"); 2677 rte_free(eth_dev->data->mac_addrs); 2678 eth_dev->data->mac_addrs = NULL; 2679 goto init_err; 2680 } 2681 2682 /* ... tx buffer layout ... */ 2683 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2684 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 2685 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2686 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2687 layout.pass_timestamp = true; 2688 } else { 2689 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2690 } 2691 layout.pass_frame_status = 1; 2692 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2693 DPNI_QUEUE_TX, &layout); 2694 if (ret) { 2695 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret); 2696 goto init_err; 2697 } 2698 2699 /* ... tx-conf and error buffer layout ... */ 2700 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2701 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 2702 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2703 layout.pass_timestamp = true; 2704 } 2705 layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2706 layout.pass_frame_status = 1; 2707 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2708 DPNI_QUEUE_TX_CONFIRM, &layout); 2709 if (ret) { 2710 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout", 2711 ret); 2712 goto init_err; 2713 } 2714 2715 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2716 2717 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) { 2718 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2719 DPAA2_PMD_INFO("Loopback mode"); 2720 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) { 2721 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2722 DPAA2_PMD_INFO("No Prefetch mode"); 2723 } else { 2724 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2725 } 2726 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2727 2728 /*Init fields w.r.t. classficaition*/ 2729 memset(&priv->extract.qos_key_extract, 0, 2730 sizeof(struct dpaa2_key_extract)); 2731 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64); 2732 if (!priv->extract.qos_extract_param) { 2733 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow " 2734 " classificaiton ", ret); 2735 goto init_err; 2736 } 2737 priv->extract.qos_key_extract.key_info.ipv4_src_offset = 2738 IP_ADDRESS_OFFSET_INVALID; 2739 priv->extract.qos_key_extract.key_info.ipv4_dst_offset = 2740 IP_ADDRESS_OFFSET_INVALID; 2741 priv->extract.qos_key_extract.key_info.ipv6_src_offset = 2742 IP_ADDRESS_OFFSET_INVALID; 2743 priv->extract.qos_key_extract.key_info.ipv6_dst_offset = 2744 IP_ADDRESS_OFFSET_INVALID; 2745 2746 for (i = 0; i < MAX_TCS; i++) { 2747 memset(&priv->extract.tc_key_extract[i], 0, 2748 sizeof(struct dpaa2_key_extract)); 2749 priv->extract.tc_extract_param[i] = 2750 (size_t)rte_malloc(NULL, 256, 64); 2751 if (!priv->extract.tc_extract_param[i]) { 2752 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton", 2753 ret); 2754 goto init_err; 2755 } 2756 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset = 2757 IP_ADDRESS_OFFSET_INVALID; 2758 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset = 2759 IP_ADDRESS_OFFSET_INVALID; 2760 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset = 2761 IP_ADDRESS_OFFSET_INVALID; 2762 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset = 2763 IP_ADDRESS_OFFSET_INVALID; 2764 } 2765 2766 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token, 2767 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN 2768 + VLAN_TAG_SIZE); 2769 if (ret) { 2770 DPAA2_PMD_ERR("Unable to set mtu. check config"); 2771 goto init_err; 2772 } 2773 2774 /*TODO To enable soft parser support DPAA2 driver needs to integrate 2775 * with external entity to receive byte code for software sequence 2776 * and same will be offload to the H/W using MC interface. 2777 * Currently it is assumed that DPAA2 driver has byte code by some 2778 * mean and same if offloaded to H/W. 2779 */ 2780 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) { 2781 WRIOP_SS_INITIALIZER(priv); 2782 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS); 2783 if (ret < 0) { 2784 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n", 2785 ret); 2786 return ret; 2787 } 2788 2789 ret = dpaa2_eth_enable_wriop_soft_parser(priv, 2790 DPNI_SS_INGRESS); 2791 if (ret < 0) { 2792 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n", 2793 ret); 2794 return ret; 2795 } 2796 } 2797 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name); 2798 return 0; 2799 init_err: 2800 dpaa2_dev_close(eth_dev); 2801 2802 return ret; 2803 } 2804 2805 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev) 2806 { 2807 return dev->device->driver == &rte_dpaa2_pmd.driver; 2808 } 2809 2810 static int 2811 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, 2812 struct rte_dpaa2_device *dpaa2_dev) 2813 { 2814 struct rte_eth_dev *eth_dev; 2815 struct dpaa2_dev_priv *dev_priv; 2816 int diag; 2817 2818 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > 2819 RTE_PKTMBUF_HEADROOM) { 2820 DPAA2_PMD_ERR( 2821 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)", 2822 RTE_PKTMBUF_HEADROOM, 2823 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE); 2824 2825 return -1; 2826 } 2827 2828 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2829 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name); 2830 if (!eth_dev) 2831 return -ENODEV; 2832 dev_priv = rte_zmalloc("ethdev private structure", 2833 sizeof(struct dpaa2_dev_priv), 2834 RTE_CACHE_LINE_SIZE); 2835 if (dev_priv == NULL) { 2836 DPAA2_PMD_CRIT( 2837 "Unable to allocate memory for private data"); 2838 rte_eth_dev_release_port(eth_dev); 2839 return -ENOMEM; 2840 } 2841 eth_dev->data->dev_private = (void *)dev_priv; 2842 /* Store a pointer to eth_dev in dev_private */ 2843 dev_priv->eth_dev = eth_dev; 2844 } else { 2845 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); 2846 if (!eth_dev) { 2847 DPAA2_PMD_DEBUG("returning enodev"); 2848 return -ENODEV; 2849 } 2850 } 2851 2852 eth_dev->device = &dpaa2_dev->device; 2853 2854 dpaa2_dev->eth_dev = eth_dev; 2855 eth_dev->data->rx_mbuf_alloc_failed = 0; 2856 2857 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) 2858 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2859 2860 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2861 2862 /* Invoke PMD device initialization function */ 2863 diag = dpaa2_dev_init(eth_dev); 2864 if (diag == 0) { 2865 rte_eth_dev_probing_finish(eth_dev); 2866 return 0; 2867 } 2868 2869 rte_eth_dev_release_port(eth_dev); 2870 return diag; 2871 } 2872 2873 static int 2874 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev) 2875 { 2876 struct rte_eth_dev *eth_dev; 2877 int ret; 2878 2879 eth_dev = dpaa2_dev->eth_dev; 2880 dpaa2_dev_close(eth_dev); 2881 ret = rte_eth_dev_release_port(eth_dev); 2882 2883 return ret; 2884 } 2885 2886 static struct rte_dpaa2_driver rte_dpaa2_pmd = { 2887 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA, 2888 .drv_type = DPAA2_ETH, 2889 .probe = rte_dpaa2_probe, 2890 .remove = rte_dpaa2_remove, 2891 }; 2892 2893 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd); 2894 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME, 2895 DRIVER_LOOPBACK_MODE "=<int> " 2896 DRIVER_NO_PREFETCH_MODE "=<int>" 2897 DRIVER_TX_CONF "=<int>" 2898 DRIVER_ERROR_QUEUE "=<int>"); 2899 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE); 2900