1*ff9e112dSShreyansh Jain /*- 2*ff9e112dSShreyansh Jain * BSD LICENSE 3*ff9e112dSShreyansh Jain * 4*ff9e112dSShreyansh Jain * Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved. 5*ff9e112dSShreyansh Jain * Copyright 2017 NXP. 6*ff9e112dSShreyansh Jain * 7*ff9e112dSShreyansh Jain * Redistribution and use in source and binary forms, with or without 8*ff9e112dSShreyansh Jain * modification, are permitted provided that the following conditions 9*ff9e112dSShreyansh Jain * are met: 10*ff9e112dSShreyansh Jain * 11*ff9e112dSShreyansh Jain * * Redistributions of source code must retain the above copyright 12*ff9e112dSShreyansh Jain * notice, this list of conditions and the following disclaimer. 13*ff9e112dSShreyansh Jain * * Redistributions in binary form must reproduce the above copyright 14*ff9e112dSShreyansh Jain * notice, this list of conditions and the following disclaimer in 15*ff9e112dSShreyansh Jain * the documentation and/or other materials provided with the 16*ff9e112dSShreyansh Jain * distribution. 17*ff9e112dSShreyansh Jain * * Neither the name of Freescale Semiconductor, Inc nor the names of its 18*ff9e112dSShreyansh Jain * contributors may be used to endorse or promote products derived 19*ff9e112dSShreyansh Jain * from this software without specific prior written permission. 20*ff9e112dSShreyansh Jain * 21*ff9e112dSShreyansh Jain * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22*ff9e112dSShreyansh Jain * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23*ff9e112dSShreyansh Jain * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24*ff9e112dSShreyansh Jain * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25*ff9e112dSShreyansh Jain * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26*ff9e112dSShreyansh Jain * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27*ff9e112dSShreyansh Jain * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28*ff9e112dSShreyansh Jain * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29*ff9e112dSShreyansh Jain * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30*ff9e112dSShreyansh Jain * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31*ff9e112dSShreyansh Jain * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32*ff9e112dSShreyansh Jain */ 33*ff9e112dSShreyansh Jain #ifndef __DPAA_ETHDEV_H__ 34*ff9e112dSShreyansh Jain #define __DPAA_ETHDEV_H__ 35*ff9e112dSShreyansh Jain 36*ff9e112dSShreyansh Jain /* System headers */ 37*ff9e112dSShreyansh Jain #include <stdbool.h> 38*ff9e112dSShreyansh Jain #include <rte_ethdev.h> 39*ff9e112dSShreyansh Jain 40*ff9e112dSShreyansh Jain #include <fsl_usd.h> 41*ff9e112dSShreyansh Jain #include <fsl_qman.h> 42*ff9e112dSShreyansh Jain #include <fsl_bman.h> 43*ff9e112dSShreyansh Jain #include <of.h> 44*ff9e112dSShreyansh Jain #include <netcfg.h> 45*ff9e112dSShreyansh Jain 46*ff9e112dSShreyansh Jain #define DPAA_MBUF_HW_ANNOTATION 64 47*ff9e112dSShreyansh Jain #define DPAA_FD_PTA_SIZE 64 48*ff9e112dSShreyansh Jain 49*ff9e112dSShreyansh Jain #if (DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM 50*ff9e112dSShreyansh Jain #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM" 51*ff9e112dSShreyansh Jain #endif 52*ff9e112dSShreyansh Jain 53*ff9e112dSShreyansh Jain /* we will re-use the HEADROOM for annotation in RX */ 54*ff9e112dSShreyansh Jain #define DPAA_HW_BUF_RESERVE 0 55*ff9e112dSShreyansh Jain #define DPAA_PACKET_LAYOUT_ALIGN 64 56*ff9e112dSShreyansh Jain 57*ff9e112dSShreyansh Jain /* Alignment to use for cpu-local structs to avoid coherency problems. */ 58*ff9e112dSShreyansh Jain #define MAX_CACHELINE 64 59*ff9e112dSShreyansh Jain 60*ff9e112dSShreyansh Jain #define DPAA_MIN_RX_BUF_SIZE 512 61*ff9e112dSShreyansh Jain #define DPAA_MAX_RX_PKT_LEN 10240 62*ff9e112dSShreyansh Jain 63*ff9e112dSShreyansh Jain /* RX queue tail drop threshold 64*ff9e112dSShreyansh Jain * currently considering 32 KB packets. 65*ff9e112dSShreyansh Jain */ 66*ff9e112dSShreyansh Jain #define CONG_THRESHOLD_RX_Q (32 * 1024) 67*ff9e112dSShreyansh Jain 68*ff9e112dSShreyansh Jain /*max mac filter for memac(8) including primary mac addr*/ 69*ff9e112dSShreyansh Jain #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1) 70*ff9e112dSShreyansh Jain 71*ff9e112dSShreyansh Jain /*Maximum number of slots available in TX ring*/ 72*ff9e112dSShreyansh Jain #define MAX_TX_RING_SLOTS 8 73*ff9e112dSShreyansh Jain 74*ff9e112dSShreyansh Jain /* PCD frame queues */ 75*ff9e112dSShreyansh Jain #define DPAA_PCD_FQID_START 0x400 76*ff9e112dSShreyansh Jain #define DPAA_PCD_FQID_MULTIPLIER 0x100 77*ff9e112dSShreyansh Jain #define DPAA_DEFAULT_NUM_PCD_QUEUES 1 78*ff9e112dSShreyansh Jain 79*ff9e112dSShreyansh Jain #define DPAA_IF_TX_PRIORITY 3 80*ff9e112dSShreyansh Jain #define DPAA_IF_RX_PRIORITY 4 81*ff9e112dSShreyansh Jain #define DPAA_IF_DEBUG_PRIORITY 7 82*ff9e112dSShreyansh Jain 83*ff9e112dSShreyansh Jain #define DPAA_IF_RX_ANNOTATION_STASH 1 84*ff9e112dSShreyansh Jain #define DPAA_IF_RX_DATA_STASH 1 85*ff9e112dSShreyansh Jain #define DPAA_IF_RX_CONTEXT_STASH 0 86*ff9e112dSShreyansh Jain 87*ff9e112dSShreyansh Jain /* Each "debug" FQ is represented by one of these */ 88*ff9e112dSShreyansh Jain #define DPAA_DEBUG_FQ_RX_ERROR 0 89*ff9e112dSShreyansh Jain #define DPAA_DEBUG_FQ_TX_ERROR 1 90*ff9e112dSShreyansh Jain 91*ff9e112dSShreyansh Jain #define DPAA_TX_CKSUM_OFFLOAD_MASK ( \ 92*ff9e112dSShreyansh Jain PKT_TX_IP_CKSUM | \ 93*ff9e112dSShreyansh Jain PKT_TX_TCP_CKSUM | \ 94*ff9e112dSShreyansh Jain PKT_TX_UDP_CKSUM) 95*ff9e112dSShreyansh Jain 96*ff9e112dSShreyansh Jain /* DPAA Frame descriptor macros */ 97*ff9e112dSShreyansh Jain 98*ff9e112dSShreyansh Jain #define DPAA_FD_CMD_FCO 0x80000000 99*ff9e112dSShreyansh Jain /**< Frame queue Context Override */ 100*ff9e112dSShreyansh Jain #define DPAA_FD_CMD_RPD 0x40000000 101*ff9e112dSShreyansh Jain /**< Read Prepended Data */ 102*ff9e112dSShreyansh Jain #define DPAA_FD_CMD_UPD 0x20000000 103*ff9e112dSShreyansh Jain /**< Update Prepended Data */ 104*ff9e112dSShreyansh Jain #define DPAA_FD_CMD_DTC 0x10000000 105*ff9e112dSShreyansh Jain /**< Do IP/TCP/UDP Checksum */ 106*ff9e112dSShreyansh Jain #define DPAA_FD_CMD_DCL4C 0x10000000 107*ff9e112dSShreyansh Jain /**< Didn't calculate L4 Checksum */ 108*ff9e112dSShreyansh Jain #define DPAA_FD_CMD_CFQ 0x00ffffff 109*ff9e112dSShreyansh Jain /**< Confirmation Frame Queue */ 110*ff9e112dSShreyansh Jain 111*ff9e112dSShreyansh Jain /* Each network interface is represented by one of these */ 112*ff9e112dSShreyansh Jain struct dpaa_if { 113*ff9e112dSShreyansh Jain int valid; 114*ff9e112dSShreyansh Jain char *name; 115*ff9e112dSShreyansh Jain const struct fm_eth_port_cfg *cfg; 116*ff9e112dSShreyansh Jain struct qman_fq *rx_queues; 117*ff9e112dSShreyansh Jain struct qman_fq *tx_queues; 118*ff9e112dSShreyansh Jain struct qman_fq debug_queues[2]; 119*ff9e112dSShreyansh Jain uint16_t nb_rx_queues; 120*ff9e112dSShreyansh Jain uint16_t nb_tx_queues; 121*ff9e112dSShreyansh Jain uint32_t ifid; 122*ff9e112dSShreyansh Jain struct fman_if *fif; 123*ff9e112dSShreyansh Jain struct dpaa_bp_info *bp_info; 124*ff9e112dSShreyansh Jain struct rte_eth_fc_conf *fc_conf; 125*ff9e112dSShreyansh Jain }; 126*ff9e112dSShreyansh Jain 127*ff9e112dSShreyansh Jain #endif 128