xref: /dpdk/drivers/net/dpaa/dpaa_ethdev.h (revision df96fd0d)
1d81734caSHemant Agrawal /* SPDX-License-Identifier: BSD-3-Clause
2ff9e112dSShreyansh Jain  *
3ff9e112dSShreyansh Jain  *   Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved.
4f513f620SSachin Saxena  *   Copyright 2017-2019 NXP
5ff9e112dSShreyansh Jain  *
6ff9e112dSShreyansh Jain  */
7ff9e112dSShreyansh Jain #ifndef __DPAA_ETHDEV_H__
8ff9e112dSShreyansh Jain #define __DPAA_ETHDEV_H__
9ff9e112dSShreyansh Jain 
10ff9e112dSShreyansh Jain /* System headers */
11ff9e112dSShreyansh Jain #include <stdbool.h>
12*df96fd0dSBruce Richardson #include <ethdev_driver.h>
135e745593SSunil Kumar Kori #include <rte_event_eth_rx_adapter.h>
14ff9e112dSShreyansh Jain 
15ff9e112dSShreyansh Jain #include <fsl_usd.h>
16ff9e112dSShreyansh Jain #include <fsl_qman.h>
17ff9e112dSShreyansh Jain #include <fsl_bman.h>
188c83f28cSHemant Agrawal #include <dpaa_of.h>
19ff9e112dSShreyansh Jain #include <netcfg.h>
20ff9e112dSShreyansh Jain 
21af2828cfSAkhil Goyal #define MAX_DPAA_CORES			4
22ff9e112dSShreyansh Jain #define DPAA_MBUF_HW_ANNOTATION		64
23ff9e112dSShreyansh Jain #define DPAA_FD_PTA_SIZE		64
24ff9e112dSShreyansh Jain 
25ff9e112dSShreyansh Jain /* we will re-use the HEADROOM for annotation in RX */
26ff9e112dSShreyansh Jain #define DPAA_HW_BUF_RESERVE	0
27ff9e112dSShreyansh Jain #define DPAA_PACKET_LAYOUT_ALIGN	64
28ff9e112dSShreyansh Jain 
29ff9e112dSShreyansh Jain /* Alignment to use for cpu-local structs to avoid coherency problems. */
30ff9e112dSShreyansh Jain #define MAX_CACHELINE			64
31ff9e112dSShreyansh Jain 
32ff9e112dSShreyansh Jain #define DPAA_MAX_RX_PKT_LEN  10240
33ff9e112dSShreyansh Jain 
3455576ac2SHemant Agrawal #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
3555576ac2SHemant Agrawal 
3662f53995SHemant Agrawal /* RX queue tail drop threshold (CGR Based) in frame count */
3762f53995SHemant Agrawal #define CGR_RX_PERFQ_THRESH 256
38e35ead33SHemant Agrawal #define CGR_TX_CGR_THRESH 512
39ff9e112dSShreyansh Jain 
40ff9e112dSShreyansh Jain /*max mac filter for memac(8) including primary mac addr*/
41ff9e112dSShreyansh Jain #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1)
42ff9e112dSShreyansh Jain 
43ff9e112dSShreyansh Jain /*Maximum number of slots available in TX ring*/
44b0a87fe2SNipun Gupta #define DPAA_TX_BURST_SIZE	7
45ff9e112dSShreyansh Jain 
462c01a48aSShreyansh Jain /* Optimal burst size for RX and TX as default */
472c01a48aSShreyansh Jain #define DPAA_DEF_RX_BURST_SIZE 7
482c01a48aSShreyansh Jain #define DPAA_DEF_TX_BURST_SIZE DPAA_TX_BURST_SIZE
492c01a48aSShreyansh Jain 
509658ac3aSAshish Jain #ifndef VLAN_TAG_SIZE
519658ac3aSAshish Jain #define VLAN_TAG_SIZE   4 /** < Vlan Header Length */
529658ac3aSAshish Jain #endif
539658ac3aSAshish Jain 
541d57225dSSteve Yang #define DPAA_ETH_MAX_LEN (RTE_ETHER_MTU + \
551d57225dSSteve Yang 			  RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \
561d57225dSSteve Yang 			  VLAN_TAG_SIZE)
571d57225dSSteve Yang 
58ff9e112dSShreyansh Jain /* PCD frame queues */
59ff9e112dSShreyansh Jain #define DPAA_DEFAULT_NUM_PCD_QUEUES	1
60f5fe3eedSJun Yang #define DPAA_VSP_PROFILE_MAX_NUM	8
61f5fe3eedSJun Yang #define DPAA_MAX_NUM_PCD_QUEUES	DPAA_VSP_PROFILE_MAX_NUM
62f5fe3eedSJun Yang /*Same as VSP profile number*/
63ff9e112dSShreyansh Jain 
64ff9e112dSShreyansh Jain #define DPAA_IF_TX_PRIORITY		3
650c504f69SHemant Agrawal #define DPAA_IF_RX_PRIORITY		0
66ff9e112dSShreyansh Jain #define DPAA_IF_DEBUG_PRIORITY		7
67ff9e112dSShreyansh Jain 
68ff9e112dSShreyansh Jain #define DPAA_IF_RX_ANNOTATION_STASH	1
69ff9e112dSShreyansh Jain #define DPAA_IF_RX_DATA_STASH		1
70ff9e112dSShreyansh Jain #define DPAA_IF_RX_CONTEXT_STASH		0
71ff9e112dSShreyansh Jain 
72ff9e112dSShreyansh Jain /* Each "debug" FQ is represented by one of these */
73ff9e112dSShreyansh Jain #define DPAA_DEBUG_FQ_RX_ERROR   0
74ff9e112dSShreyansh Jain #define DPAA_DEBUG_FQ_TX_ERROR   1
75ff9e112dSShreyansh Jain 
764fa5e0bbSShreyansh Jain #define DPAA_RSS_OFFLOAD_ALL ( \
77dce2f7ceSNipun Gupta 	ETH_RSS_L2_PAYLOAD | \
78dce2f7ceSNipun Gupta 	ETH_RSS_IP | \
79dce2f7ceSNipun Gupta 	ETH_RSS_UDP | \
80dce2f7ceSNipun Gupta 	ETH_RSS_TCP | \
81dce2f7ceSNipun Gupta 	ETH_RSS_SCTP)
824fa5e0bbSShreyansh Jain 
83ff9e112dSShreyansh Jain #define DPAA_TX_CKSUM_OFFLOAD_MASK (             \
84ff9e112dSShreyansh Jain 		PKT_TX_IP_CKSUM |                \
85ff9e112dSShreyansh Jain 		PKT_TX_TCP_CKSUM |               \
86ff9e112dSShreyansh Jain 		PKT_TX_UDP_CKSUM)
87ff9e112dSShreyansh Jain 
88ff9e112dSShreyansh Jain /* DPAA Frame descriptor macros */
89ff9e112dSShreyansh Jain 
90ff9e112dSShreyansh Jain #define DPAA_FD_CMD_FCO			0x80000000
91ff9e112dSShreyansh Jain /**< Frame queue Context Override */
92ff9e112dSShreyansh Jain #define DPAA_FD_CMD_RPD			0x40000000
93ff9e112dSShreyansh Jain /**< Read Prepended Data */
94ff9e112dSShreyansh Jain #define DPAA_FD_CMD_UPD			0x20000000
95ff9e112dSShreyansh Jain /**< Update Prepended Data */
96ff9e112dSShreyansh Jain #define DPAA_FD_CMD_DTC			0x10000000
97ff9e112dSShreyansh Jain /**< Do IP/TCP/UDP Checksum */
98ff9e112dSShreyansh Jain #define DPAA_FD_CMD_DCL4C		0x10000000
99ff9e112dSShreyansh Jain /**< Didn't calculate L4 Checksum */
100ff9e112dSShreyansh Jain #define DPAA_FD_CMD_CFQ			0x00ffffff
101ff9e112dSShreyansh Jain /**< Confirmation Frame Queue */
102ff9e112dSShreyansh Jain 
103e4abd4ffSJun Yang #define DPAA_DEFAULT_RXQ_VSP_ID		1
104e4abd4ffSJun Yang 
105f5fe3eedSJun Yang #define FMC_FILE "/tmp/fmc.bin"
106f5fe3eedSJun Yang 
107ff9e112dSShreyansh Jain /* Each network interface is represented by one of these */
108ff9e112dSShreyansh Jain struct dpaa_if {
109ff9e112dSShreyansh Jain 	int valid;
110ff9e112dSShreyansh Jain 	char *name;
111ff9e112dSShreyansh Jain 	const struct fm_eth_port_cfg *cfg;
112ff9e112dSShreyansh Jain 	struct qman_fq *rx_queues;
11362f53995SHemant Agrawal 	struct qman_cgr *cgr_rx;
114ff9e112dSShreyansh Jain 	struct qman_fq *tx_queues;
1159124e65dSGagandeep Singh 	struct qman_cgr *cgr_tx;
116ff9e112dSShreyansh Jain 	struct qman_fq debug_queues[2];
117ff9e112dSShreyansh Jain 	uint16_t nb_rx_queues;
118ff9e112dSShreyansh Jain 	uint16_t nb_tx_queues;
119ff9e112dSShreyansh Jain 	uint32_t ifid;
120ff9e112dSShreyansh Jain 	struct dpaa_bp_info *bp_info;
121ff9e112dSShreyansh Jain 	struct rte_eth_fc_conf *fc_conf;
1224defbc8cSSachin Saxena 	void *port_handle;
1234defbc8cSSachin Saxena 	void *netenv_handle;
1244defbc8cSSachin Saxena 	void *scheme_handle[2];
1254defbc8cSSachin Saxena 	uint32_t scheme_count;
126e4abd4ffSJun Yang 
127e4abd4ffSJun Yang 	void *vsp_handle[DPAA_VSP_PROFILE_MAX_NUM];
128e4abd4ffSJun Yang 	uint32_t vsp_bpid[DPAA_VSP_PROFILE_MAX_NUM];
129ff9e112dSShreyansh Jain };
130ff9e112dSShreyansh Jain 
131b21ed3e2SHemant Agrawal struct dpaa_if_stats {
132b21ed3e2SHemant Agrawal 	/* Rx Statistics Counter */
133b21ed3e2SHemant Agrawal 	uint64_t reoct;		/**<Rx Eth Octets Counter */
134b21ed3e2SHemant Agrawal 	uint64_t roct;		/**<Rx Octet Counters */
135b21ed3e2SHemant Agrawal 	uint64_t raln;		/**<Rx Alignment Error Counter */
136b21ed3e2SHemant Agrawal 	uint64_t rxpf;		/**<Rx valid Pause Frame */
137b21ed3e2SHemant Agrawal 	uint64_t rfrm;		/**<Rx Frame counter */
138b21ed3e2SHemant Agrawal 	uint64_t rfcs;		/**<Rx frame check seq error */
139b21ed3e2SHemant Agrawal 	uint64_t rvlan;		/**<Rx Vlan Frame Counter */
140b21ed3e2SHemant Agrawal 	uint64_t rerr;		/**<Rx Frame error */
141b21ed3e2SHemant Agrawal 	uint64_t ruca;		/**<Rx Unicast */
142b21ed3e2SHemant Agrawal 	uint64_t rmca;		/**<Rx Multicast */
143b21ed3e2SHemant Agrawal 	uint64_t rbca;		/**<Rx Broadcast */
144b21ed3e2SHemant Agrawal 	uint64_t rdrp;		/**<Rx Dropped Packet */
145b21ed3e2SHemant Agrawal 	uint64_t rpkt;		/**<Rx packet */
146b21ed3e2SHemant Agrawal 	uint64_t rund;		/**<Rx undersized packets */
147b21ed3e2SHemant Agrawal 	uint32_t res_x[14];
148b21ed3e2SHemant Agrawal 	uint64_t rovr;		/**<Rx oversized but good */
149b21ed3e2SHemant Agrawal 	uint64_t rjbr;		/**<Rx oversized with bad csum */
150b21ed3e2SHemant Agrawal 	uint64_t rfrg;		/**<Rx fragment Packet */
151b21ed3e2SHemant Agrawal 	uint64_t rcnp;		/**<Rx control packets (0x8808 */
152b21ed3e2SHemant Agrawal 	uint64_t rdrntp;	/**<Rx dropped due to FIFO overflow */
153b21ed3e2SHemant Agrawal 	uint32_t res01d0[12];
154b21ed3e2SHemant Agrawal 	/* Tx Statistics Counter */
155b21ed3e2SHemant Agrawal 	uint64_t teoct;		/**<Tx eth octets */
156b21ed3e2SHemant Agrawal 	uint64_t toct;		/**<Tx Octets */
157b21ed3e2SHemant Agrawal 	uint32_t res0210[2];
158b21ed3e2SHemant Agrawal 	uint64_t txpf;		/**<Tx valid pause frame */
159b21ed3e2SHemant Agrawal 	uint64_t tfrm;		/**<Tx frame counter */
160b21ed3e2SHemant Agrawal 	uint64_t tfcs;		/**<Tx FCS error */
161b21ed3e2SHemant Agrawal 	uint64_t tvlan;		/**<Tx Vlan Frame */
162b21ed3e2SHemant Agrawal 	uint64_t terr;		/**<Tx frame error */
163b21ed3e2SHemant Agrawal 	uint64_t tuca;		/**<Tx Unicast */
164b21ed3e2SHemant Agrawal 	uint64_t tmca;		/**<Tx Multicast */
165b21ed3e2SHemant Agrawal 	uint64_t tbca;		/**<Tx Broadcast */
166b21ed3e2SHemant Agrawal 	uint32_t res0258[2];
167b21ed3e2SHemant Agrawal 	uint64_t tpkt;		/**<Tx Packet */
168b21ed3e2SHemant Agrawal 	uint64_t tund;		/**<Tx Undersized */
169b21ed3e2SHemant Agrawal };
170b21ed3e2SHemant Agrawal 
1716b6ca751SHemant Agrawal __rte_internal
1721e06b6dcSHemant Agrawal int
1731e06b6dcSHemant Agrawal dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
1745e745593SSunil Kumar Kori 		int eth_rx_queue_id,
1755e745593SSunil Kumar Kori 		u16 ch_id,
1765e745593SSunil Kumar Kori 		const struct rte_event_eth_rx_adapter_queue_conf *queue_conf);
1775e745593SSunil Kumar Kori 
1786b6ca751SHemant Agrawal __rte_internal
1791e06b6dcSHemant Agrawal int
1801e06b6dcSHemant Agrawal dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1815e745593SSunil Kumar Kori 			   int eth_rx_queue_id);
1825e745593SSunil Kumar Kori 
1835e745593SSunil Kumar Kori enum qman_cb_dqrr_result
1845e745593SSunil Kumar Kori dpaa_rx_cb_parallel(void *event,
1855e745593SSunil Kumar Kori 		    struct qman_portal *qm __always_unused,
1865e745593SSunil Kumar Kori 		    struct qman_fq *fq,
1875e745593SSunil Kumar Kori 		    const struct qm_dqrr_entry *dqrr,
1885e745593SSunil Kumar Kori 		    void **bufs);
1895e745593SSunil Kumar Kori enum qman_cb_dqrr_result
1905e745593SSunil Kumar Kori dpaa_rx_cb_atomic(void *event,
1915e745593SSunil Kumar Kori 		  struct qman_portal *qm __always_unused,
1925e745593SSunil Kumar Kori 		  struct qman_fq *fq,
1935e745593SSunil Kumar Kori 		  const struct qm_dqrr_entry *dqrr,
1945e745593SSunil Kumar Kori 		  void **bufs);
1955e745593SSunil Kumar Kori 
196df80d4f8SHemant Agrawal /* PMD related logs */
197df80d4f8SHemant Agrawal extern int dpaa_logtype_pmd;
198df80d4f8SHemant Agrawal 
199df80d4f8SHemant Agrawal #define DPAA_PMD_LOG(level, fmt, args...) \
200df80d4f8SHemant Agrawal 	rte_log(RTE_LOG_ ## level, dpaa_logtype_pmd, "%s(): " fmt "\n", \
201df80d4f8SHemant Agrawal 		__func__, ##args)
202df80d4f8SHemant Agrawal 
203df80d4f8SHemant Agrawal #define PMD_INIT_FUNC_TRACE() DPAA_PMD_LOG(DEBUG, " >>")
204df80d4f8SHemant Agrawal 
205df80d4f8SHemant Agrawal #define DPAA_PMD_DEBUG(fmt, args...) \
206df80d4f8SHemant Agrawal 	DPAA_PMD_LOG(DEBUG, fmt, ## args)
207df80d4f8SHemant Agrawal #define DPAA_PMD_ERR(fmt, args...) \
208df80d4f8SHemant Agrawal 	DPAA_PMD_LOG(ERR, fmt, ## args)
209df80d4f8SHemant Agrawal #define DPAA_PMD_INFO(fmt, args...) \
210df80d4f8SHemant Agrawal 	DPAA_PMD_LOG(INFO, fmt, ## args)
211df80d4f8SHemant Agrawal #define DPAA_PMD_WARN(fmt, args...) \
212df80d4f8SHemant Agrawal 	DPAA_PMD_LOG(WARNING, fmt, ## args)
213df80d4f8SHemant Agrawal 
214df80d4f8SHemant Agrawal /* DP Logs, toggled out at compile time if level lower than current level */
215df80d4f8SHemant Agrawal #define DPAA_DP_LOG(level, fmt, args...) \
216df80d4f8SHemant Agrawal 	RTE_LOG_DP(level, PMD, fmt, ## args)
217df80d4f8SHemant Agrawal 
218ff9e112dSShreyansh Jain #endif
219