xref: /dpdk/drivers/net/dpaa/dpaa_ethdev.h (revision 9658ac3a)
1d81734caSHemant Agrawal /* SPDX-License-Identifier: BSD-3-Clause
2ff9e112dSShreyansh Jain  *
3ff9e112dSShreyansh Jain  *   Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved.
4d81734caSHemant Agrawal  *   Copyright 2017 NXP
5ff9e112dSShreyansh Jain  *
6ff9e112dSShreyansh Jain  */
7ff9e112dSShreyansh Jain #ifndef __DPAA_ETHDEV_H__
8ff9e112dSShreyansh Jain #define __DPAA_ETHDEV_H__
9ff9e112dSShreyansh Jain 
10ff9e112dSShreyansh Jain /* System headers */
11ff9e112dSShreyansh Jain #include <stdbool.h>
12ff9e112dSShreyansh Jain #include <rte_ethdev.h>
13ff9e112dSShreyansh Jain 
14ff9e112dSShreyansh Jain #include <fsl_usd.h>
15ff9e112dSShreyansh Jain #include <fsl_qman.h>
16ff9e112dSShreyansh Jain #include <fsl_bman.h>
17ff9e112dSShreyansh Jain #include <of.h>
18ff9e112dSShreyansh Jain #include <netcfg.h>
19ff9e112dSShreyansh Jain 
20ff9e112dSShreyansh Jain #define DPAA_MBUF_HW_ANNOTATION		64
21ff9e112dSShreyansh Jain #define DPAA_FD_PTA_SIZE		64
22ff9e112dSShreyansh Jain 
23ff9e112dSShreyansh Jain #if (DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM
24ff9e112dSShreyansh Jain #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM"
25ff9e112dSShreyansh Jain #endif
26ff9e112dSShreyansh Jain 
27ff9e112dSShreyansh Jain /* we will re-use the HEADROOM for annotation in RX */
28ff9e112dSShreyansh Jain #define DPAA_HW_BUF_RESERVE	0
29ff9e112dSShreyansh Jain #define DPAA_PACKET_LAYOUT_ALIGN	64
30ff9e112dSShreyansh Jain 
31ff9e112dSShreyansh Jain /* Alignment to use for cpu-local structs to avoid coherency problems. */
32ff9e112dSShreyansh Jain #define MAX_CACHELINE			64
33ff9e112dSShreyansh Jain 
34ff9e112dSShreyansh Jain #define DPAA_MIN_RX_BUF_SIZE 512
35ff9e112dSShreyansh Jain #define DPAA_MAX_RX_PKT_LEN  10240
36ff9e112dSShreyansh Jain 
37ff9e112dSShreyansh Jain /* RX queue tail drop threshold
38ff9e112dSShreyansh Jain  * currently considering 32 KB packets.
39ff9e112dSShreyansh Jain  */
40ff9e112dSShreyansh Jain #define CONG_THRESHOLD_RX_Q  (32 * 1024)
41ff9e112dSShreyansh Jain 
42ff9e112dSShreyansh Jain /*max mac filter for memac(8) including primary mac addr*/
43ff9e112dSShreyansh Jain #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1)
44ff9e112dSShreyansh Jain 
45ff9e112dSShreyansh Jain /*Maximum number of slots available in TX ring*/
46ff9e112dSShreyansh Jain #define MAX_TX_RING_SLOTS	8
47ff9e112dSShreyansh Jain 
48*9658ac3aSAshish Jain #ifndef VLAN_TAG_SIZE
49*9658ac3aSAshish Jain #define VLAN_TAG_SIZE   4 /** < Vlan Header Length */
50*9658ac3aSAshish Jain #endif
51*9658ac3aSAshish Jain 
52ff9e112dSShreyansh Jain /* PCD frame queues */
53ff9e112dSShreyansh Jain #define DPAA_PCD_FQID_START		0x400
54ff9e112dSShreyansh Jain #define DPAA_PCD_FQID_MULTIPLIER	0x100
55ff9e112dSShreyansh Jain #define DPAA_DEFAULT_NUM_PCD_QUEUES	1
56ff9e112dSShreyansh Jain 
57ff9e112dSShreyansh Jain #define DPAA_IF_TX_PRIORITY		3
58ff9e112dSShreyansh Jain #define DPAA_IF_RX_PRIORITY		4
59ff9e112dSShreyansh Jain #define DPAA_IF_DEBUG_PRIORITY		7
60ff9e112dSShreyansh Jain 
61ff9e112dSShreyansh Jain #define DPAA_IF_RX_ANNOTATION_STASH	1
62ff9e112dSShreyansh Jain #define DPAA_IF_RX_DATA_STASH		1
63ff9e112dSShreyansh Jain #define DPAA_IF_RX_CONTEXT_STASH		0
64ff9e112dSShreyansh Jain 
65ff9e112dSShreyansh Jain /* Each "debug" FQ is represented by one of these */
66ff9e112dSShreyansh Jain #define DPAA_DEBUG_FQ_RX_ERROR   0
67ff9e112dSShreyansh Jain #define DPAA_DEBUG_FQ_TX_ERROR   1
68ff9e112dSShreyansh Jain 
694fa5e0bbSShreyansh Jain #define DPAA_RSS_OFFLOAD_ALL ( \
704fa5e0bbSShreyansh Jain 	ETH_RSS_FRAG_IPV4 | \
714fa5e0bbSShreyansh Jain 	ETH_RSS_NONFRAG_IPV4_TCP | \
724fa5e0bbSShreyansh Jain 	ETH_RSS_NONFRAG_IPV4_UDP | \
734fa5e0bbSShreyansh Jain 	ETH_RSS_NONFRAG_IPV4_SCTP | \
744fa5e0bbSShreyansh Jain 	ETH_RSS_FRAG_IPV6 | \
754fa5e0bbSShreyansh Jain 	ETH_RSS_NONFRAG_IPV6_TCP | \
764fa5e0bbSShreyansh Jain 	ETH_RSS_NONFRAG_IPV6_UDP | \
774fa5e0bbSShreyansh Jain 	ETH_RSS_NONFRAG_IPV6_SCTP)
784fa5e0bbSShreyansh Jain 
79ff9e112dSShreyansh Jain #define DPAA_TX_CKSUM_OFFLOAD_MASK (             \
80ff9e112dSShreyansh Jain 		PKT_TX_IP_CKSUM |                \
81ff9e112dSShreyansh Jain 		PKT_TX_TCP_CKSUM |               \
82ff9e112dSShreyansh Jain 		PKT_TX_UDP_CKSUM)
83ff9e112dSShreyansh Jain 
84ff9e112dSShreyansh Jain /* DPAA Frame descriptor macros */
85ff9e112dSShreyansh Jain 
86ff9e112dSShreyansh Jain #define DPAA_FD_CMD_FCO			0x80000000
87ff9e112dSShreyansh Jain /**< Frame queue Context Override */
88ff9e112dSShreyansh Jain #define DPAA_FD_CMD_RPD			0x40000000
89ff9e112dSShreyansh Jain /**< Read Prepended Data */
90ff9e112dSShreyansh Jain #define DPAA_FD_CMD_UPD			0x20000000
91ff9e112dSShreyansh Jain /**< Update Prepended Data */
92ff9e112dSShreyansh Jain #define DPAA_FD_CMD_DTC			0x10000000
93ff9e112dSShreyansh Jain /**< Do IP/TCP/UDP Checksum */
94ff9e112dSShreyansh Jain #define DPAA_FD_CMD_DCL4C		0x10000000
95ff9e112dSShreyansh Jain /**< Didn't calculate L4 Checksum */
96ff9e112dSShreyansh Jain #define DPAA_FD_CMD_CFQ			0x00ffffff
97ff9e112dSShreyansh Jain /**< Confirmation Frame Queue */
98ff9e112dSShreyansh Jain 
99ff9e112dSShreyansh Jain /* Each network interface is represented by one of these */
100ff9e112dSShreyansh Jain struct dpaa_if {
101ff9e112dSShreyansh Jain 	int valid;
102ff9e112dSShreyansh Jain 	char *name;
103ff9e112dSShreyansh Jain 	const struct fm_eth_port_cfg *cfg;
104ff9e112dSShreyansh Jain 	struct qman_fq *rx_queues;
105ff9e112dSShreyansh Jain 	struct qman_fq *tx_queues;
106ff9e112dSShreyansh Jain 	struct qman_fq debug_queues[2];
107ff9e112dSShreyansh Jain 	uint16_t nb_rx_queues;
108ff9e112dSShreyansh Jain 	uint16_t nb_tx_queues;
109ff9e112dSShreyansh Jain 	uint32_t ifid;
110ff9e112dSShreyansh Jain 	struct fman_if *fif;
111ff9e112dSShreyansh Jain 	struct dpaa_bp_info *bp_info;
112ff9e112dSShreyansh Jain 	struct rte_eth_fc_conf *fc_conf;
113ff9e112dSShreyansh Jain };
114ff9e112dSShreyansh Jain 
115b21ed3e2SHemant Agrawal struct dpaa_if_stats {
116b21ed3e2SHemant Agrawal 	/* Rx Statistics Counter */
117b21ed3e2SHemant Agrawal 	uint64_t reoct;		/**<Rx Eth Octets Counter */
118b21ed3e2SHemant Agrawal 	uint64_t roct;		/**<Rx Octet Counters */
119b21ed3e2SHemant Agrawal 	uint64_t raln;		/**<Rx Alignment Error Counter */
120b21ed3e2SHemant Agrawal 	uint64_t rxpf;		/**<Rx valid Pause Frame */
121b21ed3e2SHemant Agrawal 	uint64_t rfrm;		/**<Rx Frame counter */
122b21ed3e2SHemant Agrawal 	uint64_t rfcs;		/**<Rx frame check seq error */
123b21ed3e2SHemant Agrawal 	uint64_t rvlan;		/**<Rx Vlan Frame Counter */
124b21ed3e2SHemant Agrawal 	uint64_t rerr;		/**<Rx Frame error */
125b21ed3e2SHemant Agrawal 	uint64_t ruca;		/**<Rx Unicast */
126b21ed3e2SHemant Agrawal 	uint64_t rmca;		/**<Rx Multicast */
127b21ed3e2SHemant Agrawal 	uint64_t rbca;		/**<Rx Broadcast */
128b21ed3e2SHemant Agrawal 	uint64_t rdrp;		/**<Rx Dropped Packet */
129b21ed3e2SHemant Agrawal 	uint64_t rpkt;		/**<Rx packet */
130b21ed3e2SHemant Agrawal 	uint64_t rund;		/**<Rx undersized packets */
131b21ed3e2SHemant Agrawal 	uint32_t res_x[14];
132b21ed3e2SHemant Agrawal 	uint64_t rovr;		/**<Rx oversized but good */
133b21ed3e2SHemant Agrawal 	uint64_t rjbr;		/**<Rx oversized with bad csum */
134b21ed3e2SHemant Agrawal 	uint64_t rfrg;		/**<Rx fragment Packet */
135b21ed3e2SHemant Agrawal 	uint64_t rcnp;		/**<Rx control packets (0x8808 */
136b21ed3e2SHemant Agrawal 	uint64_t rdrntp;	/**<Rx dropped due to FIFO overflow */
137b21ed3e2SHemant Agrawal 	uint32_t res01d0[12];
138b21ed3e2SHemant Agrawal 	/* Tx Statistics Counter */
139b21ed3e2SHemant Agrawal 	uint64_t teoct;		/**<Tx eth octets */
140b21ed3e2SHemant Agrawal 	uint64_t toct;		/**<Tx Octets */
141b21ed3e2SHemant Agrawal 	uint32_t res0210[2];
142b21ed3e2SHemant Agrawal 	uint64_t txpf;		/**<Tx valid pause frame */
143b21ed3e2SHemant Agrawal 	uint64_t tfrm;		/**<Tx frame counter */
144b21ed3e2SHemant Agrawal 	uint64_t tfcs;		/**<Tx FCS error */
145b21ed3e2SHemant Agrawal 	uint64_t tvlan;		/**<Tx Vlan Frame */
146b21ed3e2SHemant Agrawal 	uint64_t terr;		/**<Tx frame error */
147b21ed3e2SHemant Agrawal 	uint64_t tuca;		/**<Tx Unicast */
148b21ed3e2SHemant Agrawal 	uint64_t tmca;		/**<Tx Multicast */
149b21ed3e2SHemant Agrawal 	uint64_t tbca;		/**<Tx Broadcast */
150b21ed3e2SHemant Agrawal 	uint32_t res0258[2];
151b21ed3e2SHemant Agrawal 	uint64_t tpkt;		/**<Tx Packet */
152b21ed3e2SHemant Agrawal 	uint64_t tund;		/**<Tx Undersized */
153b21ed3e2SHemant Agrawal };
154b21ed3e2SHemant Agrawal 
155ff9e112dSShreyansh Jain #endif
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