1ff9e112dSShreyansh Jain /*- 2ff9e112dSShreyansh Jain * BSD LICENSE 3ff9e112dSShreyansh Jain * 4ff9e112dSShreyansh Jain * Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved. 5ff9e112dSShreyansh Jain * Copyright 2017 NXP. 6ff9e112dSShreyansh Jain * 7ff9e112dSShreyansh Jain * Redistribution and use in source and binary forms, with or without 8ff9e112dSShreyansh Jain * modification, are permitted provided that the following conditions 9ff9e112dSShreyansh Jain * are met: 10ff9e112dSShreyansh Jain * 11ff9e112dSShreyansh Jain * * Redistributions of source code must retain the above copyright 12ff9e112dSShreyansh Jain * notice, this list of conditions and the following disclaimer. 13ff9e112dSShreyansh Jain * * Redistributions in binary form must reproduce the above copyright 14ff9e112dSShreyansh Jain * notice, this list of conditions and the following disclaimer in 15ff9e112dSShreyansh Jain * the documentation and/or other materials provided with the 16ff9e112dSShreyansh Jain * distribution. 17ff9e112dSShreyansh Jain * * Neither the name of Freescale Semiconductor, Inc nor the names of its 18ff9e112dSShreyansh Jain * contributors may be used to endorse or promote products derived 19ff9e112dSShreyansh Jain * from this software without specific prior written permission. 20ff9e112dSShreyansh Jain * 21ff9e112dSShreyansh Jain * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22ff9e112dSShreyansh Jain * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23ff9e112dSShreyansh Jain * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24ff9e112dSShreyansh Jain * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25ff9e112dSShreyansh Jain * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26ff9e112dSShreyansh Jain * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27ff9e112dSShreyansh Jain * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28ff9e112dSShreyansh Jain * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29ff9e112dSShreyansh Jain * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30ff9e112dSShreyansh Jain * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31ff9e112dSShreyansh Jain * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32ff9e112dSShreyansh Jain */ 33ff9e112dSShreyansh Jain #ifndef __DPAA_ETHDEV_H__ 34ff9e112dSShreyansh Jain #define __DPAA_ETHDEV_H__ 35ff9e112dSShreyansh Jain 36ff9e112dSShreyansh Jain /* System headers */ 37ff9e112dSShreyansh Jain #include <stdbool.h> 38ff9e112dSShreyansh Jain #include <rte_ethdev.h> 39ff9e112dSShreyansh Jain 40ff9e112dSShreyansh Jain #include <fsl_usd.h> 41ff9e112dSShreyansh Jain #include <fsl_qman.h> 42ff9e112dSShreyansh Jain #include <fsl_bman.h> 43ff9e112dSShreyansh Jain #include <of.h> 44ff9e112dSShreyansh Jain #include <netcfg.h> 45ff9e112dSShreyansh Jain 46ff9e112dSShreyansh Jain #define DPAA_MBUF_HW_ANNOTATION 64 47ff9e112dSShreyansh Jain #define DPAA_FD_PTA_SIZE 64 48ff9e112dSShreyansh Jain 49ff9e112dSShreyansh Jain #if (DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM 50ff9e112dSShreyansh Jain #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM" 51ff9e112dSShreyansh Jain #endif 52ff9e112dSShreyansh Jain 53ff9e112dSShreyansh Jain /* we will re-use the HEADROOM for annotation in RX */ 54ff9e112dSShreyansh Jain #define DPAA_HW_BUF_RESERVE 0 55ff9e112dSShreyansh Jain #define DPAA_PACKET_LAYOUT_ALIGN 64 56ff9e112dSShreyansh Jain 57ff9e112dSShreyansh Jain /* Alignment to use for cpu-local structs to avoid coherency problems. */ 58ff9e112dSShreyansh Jain #define MAX_CACHELINE 64 59ff9e112dSShreyansh Jain 60ff9e112dSShreyansh Jain #define DPAA_MIN_RX_BUF_SIZE 512 61ff9e112dSShreyansh Jain #define DPAA_MAX_RX_PKT_LEN 10240 62ff9e112dSShreyansh Jain 63ff9e112dSShreyansh Jain /* RX queue tail drop threshold 64ff9e112dSShreyansh Jain * currently considering 32 KB packets. 65ff9e112dSShreyansh Jain */ 66ff9e112dSShreyansh Jain #define CONG_THRESHOLD_RX_Q (32 * 1024) 67ff9e112dSShreyansh Jain 68ff9e112dSShreyansh Jain /*max mac filter for memac(8) including primary mac addr*/ 69ff9e112dSShreyansh Jain #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1) 70ff9e112dSShreyansh Jain 71ff9e112dSShreyansh Jain /*Maximum number of slots available in TX ring*/ 72ff9e112dSShreyansh Jain #define MAX_TX_RING_SLOTS 8 73ff9e112dSShreyansh Jain 74ff9e112dSShreyansh Jain /* PCD frame queues */ 75ff9e112dSShreyansh Jain #define DPAA_PCD_FQID_START 0x400 76ff9e112dSShreyansh Jain #define DPAA_PCD_FQID_MULTIPLIER 0x100 77ff9e112dSShreyansh Jain #define DPAA_DEFAULT_NUM_PCD_QUEUES 1 78ff9e112dSShreyansh Jain 79ff9e112dSShreyansh Jain #define DPAA_IF_TX_PRIORITY 3 80ff9e112dSShreyansh Jain #define DPAA_IF_RX_PRIORITY 4 81ff9e112dSShreyansh Jain #define DPAA_IF_DEBUG_PRIORITY 7 82ff9e112dSShreyansh Jain 83ff9e112dSShreyansh Jain #define DPAA_IF_RX_ANNOTATION_STASH 1 84ff9e112dSShreyansh Jain #define DPAA_IF_RX_DATA_STASH 1 85ff9e112dSShreyansh Jain #define DPAA_IF_RX_CONTEXT_STASH 0 86ff9e112dSShreyansh Jain 87ff9e112dSShreyansh Jain /* Each "debug" FQ is represented by one of these */ 88ff9e112dSShreyansh Jain #define DPAA_DEBUG_FQ_RX_ERROR 0 89ff9e112dSShreyansh Jain #define DPAA_DEBUG_FQ_TX_ERROR 1 90ff9e112dSShreyansh Jain 91*4fa5e0bbSShreyansh Jain #define DPAA_RSS_OFFLOAD_ALL ( \ 92*4fa5e0bbSShreyansh Jain ETH_RSS_FRAG_IPV4 | \ 93*4fa5e0bbSShreyansh Jain ETH_RSS_NONFRAG_IPV4_TCP | \ 94*4fa5e0bbSShreyansh Jain ETH_RSS_NONFRAG_IPV4_UDP | \ 95*4fa5e0bbSShreyansh Jain ETH_RSS_NONFRAG_IPV4_SCTP | \ 96*4fa5e0bbSShreyansh Jain ETH_RSS_FRAG_IPV6 | \ 97*4fa5e0bbSShreyansh Jain ETH_RSS_NONFRAG_IPV6_TCP | \ 98*4fa5e0bbSShreyansh Jain ETH_RSS_NONFRAG_IPV6_UDP | \ 99*4fa5e0bbSShreyansh Jain ETH_RSS_NONFRAG_IPV6_SCTP) 100*4fa5e0bbSShreyansh Jain 101ff9e112dSShreyansh Jain #define DPAA_TX_CKSUM_OFFLOAD_MASK ( \ 102ff9e112dSShreyansh Jain PKT_TX_IP_CKSUM | \ 103ff9e112dSShreyansh Jain PKT_TX_TCP_CKSUM | \ 104ff9e112dSShreyansh Jain PKT_TX_UDP_CKSUM) 105ff9e112dSShreyansh Jain 106ff9e112dSShreyansh Jain /* DPAA Frame descriptor macros */ 107ff9e112dSShreyansh Jain 108ff9e112dSShreyansh Jain #define DPAA_FD_CMD_FCO 0x80000000 109ff9e112dSShreyansh Jain /**< Frame queue Context Override */ 110ff9e112dSShreyansh Jain #define DPAA_FD_CMD_RPD 0x40000000 111ff9e112dSShreyansh Jain /**< Read Prepended Data */ 112ff9e112dSShreyansh Jain #define DPAA_FD_CMD_UPD 0x20000000 113ff9e112dSShreyansh Jain /**< Update Prepended Data */ 114ff9e112dSShreyansh Jain #define DPAA_FD_CMD_DTC 0x10000000 115ff9e112dSShreyansh Jain /**< Do IP/TCP/UDP Checksum */ 116ff9e112dSShreyansh Jain #define DPAA_FD_CMD_DCL4C 0x10000000 117ff9e112dSShreyansh Jain /**< Didn't calculate L4 Checksum */ 118ff9e112dSShreyansh Jain #define DPAA_FD_CMD_CFQ 0x00ffffff 119ff9e112dSShreyansh Jain /**< Confirmation Frame Queue */ 120ff9e112dSShreyansh Jain 121ff9e112dSShreyansh Jain /* Each network interface is represented by one of these */ 122ff9e112dSShreyansh Jain struct dpaa_if { 123ff9e112dSShreyansh Jain int valid; 124ff9e112dSShreyansh Jain char *name; 125ff9e112dSShreyansh Jain const struct fm_eth_port_cfg *cfg; 126ff9e112dSShreyansh Jain struct qman_fq *rx_queues; 127ff9e112dSShreyansh Jain struct qman_fq *tx_queues; 128ff9e112dSShreyansh Jain struct qman_fq debug_queues[2]; 129ff9e112dSShreyansh Jain uint16_t nb_rx_queues; 130ff9e112dSShreyansh Jain uint16_t nb_tx_queues; 131ff9e112dSShreyansh Jain uint32_t ifid; 132ff9e112dSShreyansh Jain struct fman_if *fif; 133ff9e112dSShreyansh Jain struct dpaa_bp_info *bp_info; 134ff9e112dSShreyansh Jain struct rte_eth_fc_conf *fc_conf; 135ff9e112dSShreyansh Jain }; 136ff9e112dSShreyansh Jain 137ff9e112dSShreyansh Jain #endif 138