1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 18 #include <rte_string_fns.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_interrupts.h> 22 #include <rte_log.h> 23 #include <rte_debug.h> 24 #include <rte_pci.h> 25 #include <rte_atomic.h> 26 #include <rte_branch_prediction.h> 27 #include <rte_memory.h> 28 #include <rte_tailq.h> 29 #include <rte_eal.h> 30 #include <rte_alarm.h> 31 #include <rte_ether.h> 32 #include <rte_ethdev_driver.h> 33 #include <rte_malloc.h> 34 #include <rte_ring.h> 35 36 #include <rte_dpaa_bus.h> 37 #include <rte_dpaa_logs.h> 38 #include <dpaa_mempool.h> 39 40 #include <dpaa_ethdev.h> 41 #include <dpaa_rxtx.h> 42 #include <rte_pmd_dpaa.h> 43 44 #include <fsl_usd.h> 45 #include <fsl_qman.h> 46 #include <fsl_bman.h> 47 #include <fsl_fman.h> 48 49 /* Supported Rx offloads */ 50 static uint64_t dev_rx_offloads_sup = 51 DEV_RX_OFFLOAD_JUMBO_FRAME | 52 DEV_RX_OFFLOAD_SCATTER; 53 54 /* Rx offloads which cannot be disabled */ 55 static uint64_t dev_rx_offloads_nodis = 56 DEV_RX_OFFLOAD_IPV4_CKSUM | 57 DEV_RX_OFFLOAD_UDP_CKSUM | 58 DEV_RX_OFFLOAD_TCP_CKSUM | 59 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM; 60 61 /* Supported Tx offloads */ 62 static uint64_t dev_tx_offloads_sup; 63 64 /* Tx offloads which cannot be disabled */ 65 static uint64_t dev_tx_offloads_nodis = 66 DEV_TX_OFFLOAD_IPV4_CKSUM | 67 DEV_TX_OFFLOAD_UDP_CKSUM | 68 DEV_TX_OFFLOAD_TCP_CKSUM | 69 DEV_TX_OFFLOAD_SCTP_CKSUM | 70 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 71 DEV_TX_OFFLOAD_MULTI_SEGS | 72 DEV_TX_OFFLOAD_MT_LOCKFREE | 73 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 74 75 /* Keep track of whether QMAN and BMAN have been globally initialized */ 76 static int is_global_init; 77 static int default_q; /* use default queue - FMC is not executed*/ 78 /* At present we only allow up to 4 push mode queues as default - as each of 79 * this queue need dedicated portal and we are short of portals. 80 */ 81 #define DPAA_MAX_PUSH_MODE_QUEUE 8 82 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 83 84 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 85 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 86 87 88 /* Per FQ Taildrop in frame count */ 89 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 90 91 struct rte_dpaa_xstats_name_off { 92 char name[RTE_ETH_XSTATS_NAME_SIZE]; 93 uint32_t offset; 94 }; 95 96 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 97 {"rx_align_err", 98 offsetof(struct dpaa_if_stats, raln)}, 99 {"rx_valid_pause", 100 offsetof(struct dpaa_if_stats, rxpf)}, 101 {"rx_fcs_err", 102 offsetof(struct dpaa_if_stats, rfcs)}, 103 {"rx_vlan_frame", 104 offsetof(struct dpaa_if_stats, rvlan)}, 105 {"rx_frame_err", 106 offsetof(struct dpaa_if_stats, rerr)}, 107 {"rx_drop_err", 108 offsetof(struct dpaa_if_stats, rdrp)}, 109 {"rx_undersized", 110 offsetof(struct dpaa_if_stats, rund)}, 111 {"rx_oversize_err", 112 offsetof(struct dpaa_if_stats, rovr)}, 113 {"rx_fragment_pkt", 114 offsetof(struct dpaa_if_stats, rfrg)}, 115 {"tx_valid_pause", 116 offsetof(struct dpaa_if_stats, txpf)}, 117 {"tx_fcs_err", 118 offsetof(struct dpaa_if_stats, terr)}, 119 {"tx_vlan_frame", 120 offsetof(struct dpaa_if_stats, tvlan)}, 121 {"rx_undersized", 122 offsetof(struct dpaa_if_stats, tund)}, 123 }; 124 125 static struct rte_dpaa_driver rte_dpaa_pmd; 126 127 static int 128 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 129 130 static inline void 131 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 132 { 133 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 134 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 135 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 136 QM_FQCTRL_PREFERINCACHE; 137 opts->fqd.context_a.stashing.exclusive = 0; 138 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 139 opts->fqd.context_a.stashing.annotation_cl = 140 DPAA_IF_RX_ANNOTATION_STASH; 141 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 142 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 143 } 144 145 static int 146 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 147 { 148 struct dpaa_if *dpaa_intf = dev->data->dev_private; 149 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 150 + VLAN_TAG_SIZE; 151 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 152 153 PMD_INIT_FUNC_TRACE(); 154 155 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN) 156 return -EINVAL; 157 /* 158 * Refuse mtu that requires the support of scattered packets 159 * when this feature has not been enabled before. 160 */ 161 if (dev->data->min_rx_buf_size && 162 !dev->data->scattered_rx && frame_size > buffsz) { 163 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 164 return -EINVAL; 165 } 166 167 /* check <seg size> * <max_seg> >= max_frame */ 168 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 169 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 170 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 171 buffsz * DPAA_SGT_MAX_ENTRIES); 172 return -EINVAL; 173 } 174 175 if (frame_size > RTE_ETHER_MAX_LEN) 176 dev->data->dev_conf.rxmode.offloads &= 177 DEV_RX_OFFLOAD_JUMBO_FRAME; 178 else 179 dev->data->dev_conf.rxmode.offloads &= 180 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 181 182 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 183 184 fman_if_set_maxfrm(dpaa_intf->fif, frame_size); 185 186 return 0; 187 } 188 189 static int 190 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 191 { 192 struct dpaa_if *dpaa_intf = dev->data->dev_private; 193 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 194 uint64_t rx_offloads = eth_conf->rxmode.offloads; 195 uint64_t tx_offloads = eth_conf->txmode.offloads; 196 197 PMD_INIT_FUNC_TRACE(); 198 199 /* Rx offloads validation */ 200 if (dev_rx_offloads_nodis & ~rx_offloads) { 201 DPAA_PMD_WARN( 202 "Rx offloads non configurable - requested 0x%" PRIx64 203 " ignored 0x%" PRIx64, 204 rx_offloads, dev_rx_offloads_nodis); 205 } 206 207 /* Tx offloads validation */ 208 if (dev_tx_offloads_nodis & ~tx_offloads) { 209 DPAA_PMD_WARN( 210 "Tx offloads non configurable - requested 0x%" PRIx64 211 " ignored 0x%" PRIx64, 212 tx_offloads, dev_tx_offloads_nodis); 213 } 214 215 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 216 uint32_t max_len; 217 218 DPAA_PMD_DEBUG("enabling jumbo"); 219 220 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= 221 DPAA_MAX_RX_PKT_LEN) 222 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 223 else { 224 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 225 "supported is %d", 226 dev->data->dev_conf.rxmode.max_rx_pkt_len, 227 DPAA_MAX_RX_PKT_LEN); 228 max_len = DPAA_MAX_RX_PKT_LEN; 229 } 230 231 fman_if_set_maxfrm(dpaa_intf->fif, max_len); 232 dev->data->mtu = max_len 233 - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE; 234 } 235 236 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) { 237 DPAA_PMD_DEBUG("enabling scatter mode"); 238 fman_if_set_sg(dpaa_intf->fif, 1); 239 dev->data->scattered_rx = 1; 240 } 241 242 return 0; 243 } 244 245 static const uint32_t * 246 dpaa_supported_ptypes_get(struct rte_eth_dev *dev) 247 { 248 static const uint32_t ptypes[] = { 249 RTE_PTYPE_L2_ETHER, 250 RTE_PTYPE_L2_ETHER_VLAN, 251 RTE_PTYPE_L2_ETHER_ARP, 252 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 253 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 254 RTE_PTYPE_L4_ICMP, 255 RTE_PTYPE_L4_TCP, 256 RTE_PTYPE_L4_UDP, 257 RTE_PTYPE_L4_FRAG, 258 RTE_PTYPE_L4_TCP, 259 RTE_PTYPE_L4_UDP, 260 RTE_PTYPE_L4_SCTP 261 }; 262 263 PMD_INIT_FUNC_TRACE(); 264 265 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) 266 return ptypes; 267 return NULL; 268 } 269 270 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 271 { 272 struct dpaa_if *dpaa_intf = dev->data->dev_private; 273 274 PMD_INIT_FUNC_TRACE(); 275 276 /* Change tx callback to the real one */ 277 dev->tx_pkt_burst = dpaa_eth_queue_tx; 278 fman_if_enable_rx(dpaa_intf->fif); 279 280 return 0; 281 } 282 283 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev) 284 { 285 struct dpaa_if *dpaa_intf = dev->data->dev_private; 286 287 PMD_INIT_FUNC_TRACE(); 288 289 fman_if_disable_rx(dpaa_intf->fif); 290 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 291 } 292 293 static void dpaa_eth_dev_close(struct rte_eth_dev *dev) 294 { 295 PMD_INIT_FUNC_TRACE(); 296 297 dpaa_eth_dev_stop(dev); 298 } 299 300 static int 301 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 302 char *fw_version, 303 size_t fw_size) 304 { 305 int ret; 306 FILE *svr_file = NULL; 307 unsigned int svr_ver = 0; 308 309 PMD_INIT_FUNC_TRACE(); 310 311 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 312 if (!svr_file) { 313 DPAA_PMD_ERR("Unable to open SoC device"); 314 return -ENOTSUP; /* Not supported on this infra */ 315 } 316 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 317 dpaa_svr_family = svr_ver & SVR_MASK; 318 else 319 DPAA_PMD_ERR("Unable to read SoC device"); 320 321 fclose(svr_file); 322 323 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 324 svr_ver, fman_ip_rev); 325 ret += 1; /* add the size of '\0' */ 326 327 if (fw_size < (uint32_t)ret) 328 return ret; 329 else 330 return 0; 331 } 332 333 static int dpaa_eth_dev_info(struct rte_eth_dev *dev, 334 struct rte_eth_dev_info *dev_info) 335 { 336 struct dpaa_if *dpaa_intf = dev->data->dev_private; 337 338 PMD_INIT_FUNC_TRACE(); 339 340 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 341 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 342 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 343 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 344 dev_info->max_hash_mac_addrs = 0; 345 dev_info->max_vfs = 0; 346 dev_info->max_vmdq_pools = ETH_16_POOLS; 347 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 348 349 if (dpaa_intf->fif->mac_type == fman_mac_1g) { 350 dev_info->speed_capa = ETH_LINK_SPEED_1G; 351 } else if (dpaa_intf->fif->mac_type == fman_mac_10g) { 352 dev_info->speed_capa = (ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G); 353 } else { 354 DPAA_PMD_ERR("invalid link_speed: %s, %d", 355 dpaa_intf->name, dpaa_intf->fif->mac_type); 356 return -EINVAL; 357 } 358 359 dev_info->rx_offload_capa = dev_rx_offloads_sup | 360 dev_rx_offloads_nodis; 361 dev_info->tx_offload_capa = dev_tx_offloads_sup | 362 dev_tx_offloads_nodis; 363 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 364 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 365 366 return 0; 367 } 368 369 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 370 int wait_to_complete __rte_unused) 371 { 372 struct dpaa_if *dpaa_intf = dev->data->dev_private; 373 struct rte_eth_link *link = &dev->data->dev_link; 374 375 PMD_INIT_FUNC_TRACE(); 376 377 if (dpaa_intf->fif->mac_type == fman_mac_1g) 378 link->link_speed = ETH_SPEED_NUM_1G; 379 else if (dpaa_intf->fif->mac_type == fman_mac_10g) 380 link->link_speed = ETH_SPEED_NUM_10G; 381 else 382 DPAA_PMD_ERR("invalid link_speed: %s, %d", 383 dpaa_intf->name, dpaa_intf->fif->mac_type); 384 385 link->link_status = dpaa_intf->valid; 386 link->link_duplex = ETH_LINK_FULL_DUPLEX; 387 link->link_autoneg = ETH_LINK_AUTONEG; 388 return 0; 389 } 390 391 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 392 struct rte_eth_stats *stats) 393 { 394 struct dpaa_if *dpaa_intf = dev->data->dev_private; 395 396 PMD_INIT_FUNC_TRACE(); 397 398 fman_if_stats_get(dpaa_intf->fif, stats); 399 return 0; 400 } 401 402 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev) 403 { 404 struct dpaa_if *dpaa_intf = dev->data->dev_private; 405 406 PMD_INIT_FUNC_TRACE(); 407 408 fman_if_stats_reset(dpaa_intf->fif); 409 } 410 411 static int 412 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 413 unsigned int n) 414 { 415 struct dpaa_if *dpaa_intf = dev->data->dev_private; 416 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 417 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 418 419 if (n < num) 420 return num; 421 422 if (xstats == NULL) 423 return 0; 424 425 fman_if_stats_get_all(dpaa_intf->fif, values, 426 sizeof(struct dpaa_if_stats) / 8); 427 428 for (i = 0; i < num; i++) { 429 xstats[i].id = i; 430 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 431 } 432 return i; 433 } 434 435 static int 436 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 437 struct rte_eth_xstat_name *xstats_names, 438 unsigned int limit) 439 { 440 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 441 442 if (limit < stat_cnt) 443 return stat_cnt; 444 445 if (xstats_names != NULL) 446 for (i = 0; i < stat_cnt; i++) 447 strlcpy(xstats_names[i].name, 448 dpaa_xstats_strings[i].name, 449 sizeof(xstats_names[i].name)); 450 451 return stat_cnt; 452 } 453 454 static int 455 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 456 uint64_t *values, unsigned int n) 457 { 458 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 459 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 460 461 if (!ids) { 462 struct dpaa_if *dpaa_intf = dev->data->dev_private; 463 464 if (n < stat_cnt) 465 return stat_cnt; 466 467 if (!values) 468 return 0; 469 470 fman_if_stats_get_all(dpaa_intf->fif, values_copy, 471 sizeof(struct dpaa_if_stats) / 8); 472 473 for (i = 0; i < stat_cnt; i++) 474 values[i] = 475 values_copy[dpaa_xstats_strings[i].offset / 8]; 476 477 return stat_cnt; 478 } 479 480 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 481 482 for (i = 0; i < n; i++) { 483 if (ids[i] >= stat_cnt) { 484 DPAA_PMD_ERR("id value isn't valid"); 485 return -1; 486 } 487 values[i] = values_copy[ids[i]]; 488 } 489 return n; 490 } 491 492 static int 493 dpaa_xstats_get_names_by_id( 494 struct rte_eth_dev *dev, 495 struct rte_eth_xstat_name *xstats_names, 496 const uint64_t *ids, 497 unsigned int limit) 498 { 499 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 500 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 501 502 if (!ids) 503 return dpaa_xstats_get_names(dev, xstats_names, limit); 504 505 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 506 507 for (i = 0; i < limit; i++) { 508 if (ids[i] >= stat_cnt) { 509 DPAA_PMD_ERR("id value isn't valid"); 510 return -1; 511 } 512 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 513 } 514 return limit; 515 } 516 517 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 518 { 519 struct dpaa_if *dpaa_intf = dev->data->dev_private; 520 521 PMD_INIT_FUNC_TRACE(); 522 523 fman_if_promiscuous_enable(dpaa_intf->fif); 524 525 return 0; 526 } 527 528 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 529 { 530 struct dpaa_if *dpaa_intf = dev->data->dev_private; 531 532 PMD_INIT_FUNC_TRACE(); 533 534 fman_if_promiscuous_disable(dpaa_intf->fif); 535 536 return 0; 537 } 538 539 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 540 { 541 struct dpaa_if *dpaa_intf = dev->data->dev_private; 542 543 PMD_INIT_FUNC_TRACE(); 544 545 fman_if_set_mcast_filter_table(dpaa_intf->fif); 546 } 547 548 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 549 { 550 struct dpaa_if *dpaa_intf = dev->data->dev_private; 551 552 PMD_INIT_FUNC_TRACE(); 553 554 fman_if_reset_mcast_filter_table(dpaa_intf->fif); 555 } 556 557 static 558 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 559 uint16_t nb_desc, 560 unsigned int socket_id __rte_unused, 561 const struct rte_eth_rxconf *rx_conf __rte_unused, 562 struct rte_mempool *mp) 563 { 564 struct dpaa_if *dpaa_intf = dev->data->dev_private; 565 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 566 struct qm_mcc_initfq opts = {0}; 567 u32 flags = 0; 568 int ret; 569 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 570 571 PMD_INIT_FUNC_TRACE(); 572 573 if (queue_idx >= dev->data->nb_rx_queues) { 574 rte_errno = EOVERFLOW; 575 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 576 (void *)dev, queue_idx, dev->data->nb_rx_queues); 577 return -rte_errno; 578 } 579 580 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 581 queue_idx, rxq->fqid); 582 583 /* Max packet can fit in single buffer */ 584 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) { 585 ; 586 } else if (dev->data->dev_conf.rxmode.offloads & 587 DEV_RX_OFFLOAD_SCATTER) { 588 if (dev->data->dev_conf.rxmode.max_rx_pkt_len > 589 buffsz * DPAA_SGT_MAX_ENTRIES) { 590 DPAA_PMD_ERR("max RxPkt size %d too big to fit " 591 "MaxSGlist %d", 592 dev->data->dev_conf.rxmode.max_rx_pkt_len, 593 buffsz * DPAA_SGT_MAX_ENTRIES); 594 rte_errno = EOVERFLOW; 595 return -rte_errno; 596 } 597 } else { 598 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 599 " larger than a single mbuf (%u) and scattered" 600 " mode has not been requested", 601 dev->data->dev_conf.rxmode.max_rx_pkt_len, 602 buffsz - RTE_PKTMBUF_HEADROOM); 603 } 604 605 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) { 606 struct fman_if_ic_params icp; 607 uint32_t fd_offset; 608 uint32_t bp_size; 609 610 if (!mp->pool_data) { 611 DPAA_PMD_ERR("Not an offloaded buffer pool!"); 612 return -1; 613 } 614 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 615 616 memset(&icp, 0, sizeof(icp)); 617 /* set ICEOF for to the default value , which is 0*/ 618 icp.iciof = DEFAULT_ICIOF; 619 icp.iceof = DEFAULT_RX_ICEOF; 620 icp.icsz = DEFAULT_ICSZ; 621 fman_if_set_ic_params(dpaa_intf->fif, &icp); 622 623 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 624 fman_if_set_fdoff(dpaa_intf->fif, fd_offset); 625 626 /* Buffer pool size should be equal to Dataroom Size*/ 627 bp_size = rte_pktmbuf_data_room_size(mp); 628 fman_if_set_bp(dpaa_intf->fif, mp->size, 629 dpaa_intf->bp_info->bpid, bp_size); 630 dpaa_intf->valid = 1; 631 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d", 632 dpaa_intf->name, fd_offset, 633 fman_if_get_fdoff(dpaa_intf->fif)); 634 } 635 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 636 fman_if_get_sg_enable(dpaa_intf->fif), 637 dev->data->dev_conf.rxmode.max_rx_pkt_len); 638 /* checking if push mode only, no error check for now */ 639 if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 640 dpaa_push_queue_idx++; 641 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 642 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 643 QM_FQCTRL_CTXASTASHING | 644 QM_FQCTRL_PREFERINCACHE; 645 opts.fqd.context_a.stashing.exclusive = 0; 646 /* In muticore scenario stashing becomes a bottleneck on LS1046. 647 * So do not enable stashing in this case 648 */ 649 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 650 opts.fqd.context_a.stashing.annotation_cl = 651 DPAA_IF_RX_ANNOTATION_STASH; 652 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 653 opts.fqd.context_a.stashing.context_cl = 654 DPAA_IF_RX_CONTEXT_STASH; 655 656 /*Create a channel and associate given queue with the channel*/ 657 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 658 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 659 opts.fqd.dest.channel = rxq->ch_id; 660 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 661 flags = QMAN_INITFQ_FLAG_SCHED; 662 663 /* Configure tail drop */ 664 if (dpaa_intf->cgr_rx) { 665 opts.we_mask |= QM_INITFQ_WE_CGID; 666 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 667 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 668 } 669 ret = qman_init_fq(rxq, flags, &opts); 670 if (ret) { 671 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 672 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 673 return ret; 674 } 675 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 676 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 677 } else { 678 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 679 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 680 } 681 682 rxq->is_static = true; 683 } 684 rxq->bp_array = rte_dpaa_bpid_info; 685 dev->data->rx_queues[queue_idx] = rxq; 686 687 /* configure the CGR size as per the desc size */ 688 if (dpaa_intf->cgr_rx) { 689 struct qm_mcc_initcgr cgr_opts = {0}; 690 691 /* Enable tail drop with cgr on this queue */ 692 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 693 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 694 if (ret) { 695 DPAA_PMD_WARN( 696 "rx taildrop modify fail on fqid %d (ret=%d)", 697 rxq->fqid, ret); 698 } 699 } 700 701 return 0; 702 } 703 704 int 705 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 706 int eth_rx_queue_id, 707 u16 ch_id, 708 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 709 { 710 int ret; 711 u32 flags = 0; 712 struct dpaa_if *dpaa_intf = dev->data->dev_private; 713 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 714 struct qm_mcc_initfq opts = {0}; 715 716 if (dpaa_push_mode_max_queue) 717 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n" 718 "PUSH mode already enabled for first %d queues.\n" 719 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n", 720 dpaa_push_mode_max_queue); 721 722 dpaa_poll_queue_default_config(&opts); 723 724 switch (queue_conf->ev.sched_type) { 725 case RTE_SCHED_TYPE_ATOMIC: 726 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 727 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 728 * configuration with HOLD_ACTIVE setting 729 */ 730 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 731 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 732 break; 733 case RTE_SCHED_TYPE_ORDERED: 734 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n"); 735 return -1; 736 default: 737 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 738 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 739 break; 740 } 741 742 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 743 opts.fqd.dest.channel = ch_id; 744 opts.fqd.dest.wq = queue_conf->ev.priority; 745 746 if (dpaa_intf->cgr_rx) { 747 opts.we_mask |= QM_INITFQ_WE_CGID; 748 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 749 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 750 } 751 752 flags = QMAN_INITFQ_FLAG_SCHED; 753 754 ret = qman_init_fq(rxq, flags, &opts); 755 if (ret) { 756 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 757 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 758 return ret; 759 } 760 761 /* copy configuration which needs to be filled during dequeue */ 762 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 763 dev->data->rx_queues[eth_rx_queue_id] = rxq; 764 765 return ret; 766 } 767 768 int 769 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 770 int eth_rx_queue_id) 771 { 772 struct qm_mcc_initfq opts; 773 int ret; 774 u32 flags = 0; 775 struct dpaa_if *dpaa_intf = dev->data->dev_private; 776 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 777 778 dpaa_poll_queue_default_config(&opts); 779 780 if (dpaa_intf->cgr_rx) { 781 opts.we_mask |= QM_INITFQ_WE_CGID; 782 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 783 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 784 } 785 786 ret = qman_init_fq(rxq, flags, &opts); 787 if (ret) { 788 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", 789 rxq->fqid, ret); 790 } 791 792 rxq->cb.dqrr_dpdk_cb = NULL; 793 dev->data->rx_queues[eth_rx_queue_id] = NULL; 794 795 return 0; 796 } 797 798 static 799 void dpaa_eth_rx_queue_release(void *rxq __rte_unused) 800 { 801 PMD_INIT_FUNC_TRACE(); 802 } 803 804 static 805 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 806 uint16_t nb_desc __rte_unused, 807 unsigned int socket_id __rte_unused, 808 const struct rte_eth_txconf *tx_conf __rte_unused) 809 { 810 struct dpaa_if *dpaa_intf = dev->data->dev_private; 811 812 PMD_INIT_FUNC_TRACE(); 813 814 if (queue_idx >= dev->data->nb_tx_queues) { 815 rte_errno = EOVERFLOW; 816 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 817 (void *)dev, queue_idx, dev->data->nb_tx_queues); 818 return -rte_errno; 819 } 820 821 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 822 queue_idx, dpaa_intf->tx_queues[queue_idx].fqid); 823 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx]; 824 return 0; 825 } 826 827 static void dpaa_eth_tx_queue_release(void *txq __rte_unused) 828 { 829 PMD_INIT_FUNC_TRACE(); 830 } 831 832 static uint32_t 833 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 834 { 835 struct dpaa_if *dpaa_intf = dev->data->dev_private; 836 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id]; 837 u32 frm_cnt = 0; 838 839 PMD_INIT_FUNC_TRACE(); 840 841 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 842 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n", 843 rx_queue_id, frm_cnt); 844 } 845 return frm_cnt; 846 } 847 848 static int dpaa_link_down(struct rte_eth_dev *dev) 849 { 850 PMD_INIT_FUNC_TRACE(); 851 852 dpaa_eth_dev_stop(dev); 853 return 0; 854 } 855 856 static int dpaa_link_up(struct rte_eth_dev *dev) 857 { 858 PMD_INIT_FUNC_TRACE(); 859 860 dpaa_eth_dev_start(dev); 861 return 0; 862 } 863 864 static int 865 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 866 struct rte_eth_fc_conf *fc_conf) 867 { 868 struct dpaa_if *dpaa_intf = dev->data->dev_private; 869 struct rte_eth_fc_conf *net_fc; 870 871 PMD_INIT_FUNC_TRACE(); 872 873 if (!(dpaa_intf->fc_conf)) { 874 dpaa_intf->fc_conf = rte_zmalloc(NULL, 875 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 876 if (!dpaa_intf->fc_conf) { 877 DPAA_PMD_ERR("unable to save flow control info"); 878 return -ENOMEM; 879 } 880 } 881 net_fc = dpaa_intf->fc_conf; 882 883 if (fc_conf->high_water < fc_conf->low_water) { 884 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 885 return -EINVAL; 886 } 887 888 if (fc_conf->mode == RTE_FC_NONE) { 889 return 0; 890 } else if (fc_conf->mode == RTE_FC_TX_PAUSE || 891 fc_conf->mode == RTE_FC_FULL) { 892 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water, 893 fc_conf->low_water, 894 dpaa_intf->bp_info->bpid); 895 if (fc_conf->pause_time) 896 fman_if_set_fc_quanta(dpaa_intf->fif, 897 fc_conf->pause_time); 898 } 899 900 /* Save the information in dpaa device */ 901 net_fc->pause_time = fc_conf->pause_time; 902 net_fc->high_water = fc_conf->high_water; 903 net_fc->low_water = fc_conf->low_water; 904 net_fc->send_xon = fc_conf->send_xon; 905 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 906 net_fc->mode = fc_conf->mode; 907 net_fc->autoneg = fc_conf->autoneg; 908 909 return 0; 910 } 911 912 static int 913 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 914 struct rte_eth_fc_conf *fc_conf) 915 { 916 struct dpaa_if *dpaa_intf = dev->data->dev_private; 917 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 918 int ret; 919 920 PMD_INIT_FUNC_TRACE(); 921 922 if (net_fc) { 923 fc_conf->pause_time = net_fc->pause_time; 924 fc_conf->high_water = net_fc->high_water; 925 fc_conf->low_water = net_fc->low_water; 926 fc_conf->send_xon = net_fc->send_xon; 927 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 928 fc_conf->mode = net_fc->mode; 929 fc_conf->autoneg = net_fc->autoneg; 930 return 0; 931 } 932 ret = fman_if_get_fc_threshold(dpaa_intf->fif); 933 if (ret) { 934 fc_conf->mode = RTE_FC_TX_PAUSE; 935 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif); 936 } else { 937 fc_conf->mode = RTE_FC_NONE; 938 } 939 940 return 0; 941 } 942 943 static int 944 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 945 struct rte_ether_addr *addr, 946 uint32_t index, 947 __rte_unused uint32_t pool) 948 { 949 int ret; 950 struct dpaa_if *dpaa_intf = dev->data->dev_private; 951 952 PMD_INIT_FUNC_TRACE(); 953 954 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index); 955 956 if (ret) 957 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:" 958 " err = %d", ret); 959 return 0; 960 } 961 962 static void 963 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 964 uint32_t index) 965 { 966 struct dpaa_if *dpaa_intf = dev->data->dev_private; 967 968 PMD_INIT_FUNC_TRACE(); 969 970 fman_if_clear_mac_addr(dpaa_intf->fif, index); 971 } 972 973 static int 974 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 975 struct rte_ether_addr *addr) 976 { 977 int ret; 978 struct dpaa_if *dpaa_intf = dev->data->dev_private; 979 980 PMD_INIT_FUNC_TRACE(); 981 982 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0); 983 if (ret) 984 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret); 985 986 return ret; 987 } 988 989 static struct eth_dev_ops dpaa_devops = { 990 .dev_configure = dpaa_eth_dev_configure, 991 .dev_start = dpaa_eth_dev_start, 992 .dev_stop = dpaa_eth_dev_stop, 993 .dev_close = dpaa_eth_dev_close, 994 .dev_infos_get = dpaa_eth_dev_info, 995 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 996 997 .rx_queue_setup = dpaa_eth_rx_queue_setup, 998 .tx_queue_setup = dpaa_eth_tx_queue_setup, 999 .rx_queue_release = dpaa_eth_rx_queue_release, 1000 .tx_queue_release = dpaa_eth_tx_queue_release, 1001 .rx_queue_count = dpaa_dev_rx_queue_count, 1002 1003 .flow_ctrl_get = dpaa_flow_ctrl_get, 1004 .flow_ctrl_set = dpaa_flow_ctrl_set, 1005 1006 .link_update = dpaa_eth_link_update, 1007 .stats_get = dpaa_eth_stats_get, 1008 .xstats_get = dpaa_dev_xstats_get, 1009 .xstats_get_by_id = dpaa_xstats_get_by_id, 1010 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1011 .xstats_get_names = dpaa_xstats_get_names, 1012 .xstats_reset = dpaa_eth_stats_reset, 1013 .stats_reset = dpaa_eth_stats_reset, 1014 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1015 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1016 .allmulticast_enable = dpaa_eth_multicast_enable, 1017 .allmulticast_disable = dpaa_eth_multicast_disable, 1018 .mtu_set = dpaa_mtu_set, 1019 .dev_set_link_down = dpaa_link_down, 1020 .dev_set_link_up = dpaa_link_up, 1021 .mac_addr_add = dpaa_dev_add_mac_addr, 1022 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1023 .mac_addr_set = dpaa_dev_set_mac_addr, 1024 1025 .fw_version_get = dpaa_fw_version_get, 1026 }; 1027 1028 static bool 1029 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1030 { 1031 if (strcmp(dev->device->driver->name, 1032 drv->driver.name)) 1033 return false; 1034 1035 return true; 1036 } 1037 1038 static bool 1039 is_dpaa_supported(struct rte_eth_dev *dev) 1040 { 1041 return is_device_supported(dev, &rte_dpaa_pmd); 1042 } 1043 1044 int 1045 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on) 1046 { 1047 struct rte_eth_dev *dev; 1048 struct dpaa_if *dpaa_intf; 1049 1050 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1051 1052 dev = &rte_eth_devices[port]; 1053 1054 if (!is_dpaa_supported(dev)) 1055 return -ENOTSUP; 1056 1057 dpaa_intf = dev->data->dev_private; 1058 1059 if (on) 1060 fman_if_loopback_enable(dpaa_intf->fif); 1061 else 1062 fman_if_loopback_disable(dpaa_intf->fif); 1063 1064 return 0; 1065 } 1066 1067 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf) 1068 { 1069 struct rte_eth_fc_conf *fc_conf; 1070 int ret; 1071 1072 PMD_INIT_FUNC_TRACE(); 1073 1074 if (!(dpaa_intf->fc_conf)) { 1075 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1076 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1077 if (!dpaa_intf->fc_conf) { 1078 DPAA_PMD_ERR("unable to save flow control info"); 1079 return -ENOMEM; 1080 } 1081 } 1082 fc_conf = dpaa_intf->fc_conf; 1083 ret = fman_if_get_fc_threshold(dpaa_intf->fif); 1084 if (ret) { 1085 fc_conf->mode = RTE_FC_TX_PAUSE; 1086 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif); 1087 } else { 1088 fc_conf->mode = RTE_FC_NONE; 1089 } 1090 1091 return 0; 1092 } 1093 1094 /* Initialise an Rx FQ */ 1095 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1096 uint32_t fqid) 1097 { 1098 struct qm_mcc_initfq opts = {0}; 1099 int ret; 1100 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1101 struct qm_mcc_initcgr cgr_opts = { 1102 .we_mask = QM_CGR_WE_CS_THRES | 1103 QM_CGR_WE_CSTD_EN | 1104 QM_CGR_WE_MODE, 1105 .cgr = { 1106 .cstd_en = QM_CGR_EN, 1107 .mode = QMAN_CGR_MODE_FRAME 1108 } 1109 }; 1110 1111 PMD_INIT_FUNC_TRACE(); 1112 1113 if (fqid) { 1114 ret = qman_reserve_fqid(fqid); 1115 if (ret) { 1116 DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d", 1117 fqid, ret); 1118 return -EINVAL; 1119 } 1120 } else { 1121 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID; 1122 } 1123 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1124 ret = qman_create_fq(fqid, flags, fq); 1125 if (ret) { 1126 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1127 fqid, ret); 1128 return ret; 1129 } 1130 fq->is_static = false; 1131 1132 dpaa_poll_queue_default_config(&opts); 1133 1134 if (cgr_rx) { 1135 /* Enable tail drop with cgr on this queue */ 1136 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1137 cgr_rx->cb = NULL; 1138 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1139 &cgr_opts); 1140 if (ret) { 1141 DPAA_PMD_WARN( 1142 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1143 fq->fqid, ret); 1144 goto without_cgr; 1145 } 1146 opts.we_mask |= QM_INITFQ_WE_CGID; 1147 opts.fqd.cgid = cgr_rx->cgrid; 1148 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1149 } 1150 without_cgr: 1151 ret = qman_init_fq(fq, 0, &opts); 1152 if (ret) 1153 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1154 return ret; 1155 } 1156 1157 /* Initialise a Tx FQ */ 1158 static int dpaa_tx_queue_init(struct qman_fq *fq, 1159 struct fman_if *fman_intf) 1160 { 1161 struct qm_mcc_initfq opts = {0}; 1162 int ret; 1163 1164 PMD_INIT_FUNC_TRACE(); 1165 1166 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1167 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1168 if (ret) { 1169 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1170 return ret; 1171 } 1172 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1173 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1174 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1175 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1176 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1177 opts.fqd.context_b = 0; 1178 /* no tx-confirmation */ 1179 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1180 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1181 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1182 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1183 if (ret) 1184 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 1185 return ret; 1186 } 1187 1188 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1189 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1190 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1191 { 1192 struct qm_mcc_initfq opts = {0}; 1193 int ret; 1194 1195 PMD_INIT_FUNC_TRACE(); 1196 1197 ret = qman_reserve_fqid(fqid); 1198 if (ret) { 1199 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1200 fqid, ret); 1201 return -EINVAL; 1202 } 1203 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1204 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1205 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1206 if (ret) { 1207 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1208 fqid, ret); 1209 return ret; 1210 } 1211 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1212 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1213 ret = qman_init_fq(fq, 0, &opts); 1214 if (ret) 1215 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1216 fqid, ret); 1217 return ret; 1218 } 1219 #endif 1220 1221 /* Initialise a network interface */ 1222 static int 1223 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1224 { 1225 int num_rx_fqs, fqid; 1226 int loop, ret = 0; 1227 int dev_id; 1228 struct rte_dpaa_device *dpaa_device; 1229 struct dpaa_if *dpaa_intf; 1230 struct fm_eth_port_cfg *cfg; 1231 struct fman_if *fman_intf; 1232 struct fman_if_bpool *bp, *tmp_bp; 1233 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1234 1235 PMD_INIT_FUNC_TRACE(); 1236 1237 dpaa_intf = eth_dev->data->dev_private; 1238 /* For secondary processes, the primary has done all the work */ 1239 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1240 eth_dev->dev_ops = &dpaa_devops; 1241 /* Plugging of UCODE burst API not supported in Secondary */ 1242 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1243 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 1244 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 1245 qman_set_fq_lookup_table( 1246 dpaa_intf->rx_queues->qman_fq_lookup_table); 1247 #endif 1248 return 0; 1249 } 1250 1251 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1252 dev_id = dpaa_device->id.dev_id; 1253 dpaa_intf = eth_dev->data->dev_private; 1254 cfg = &dpaa_netcfg->port_cfg[dev_id]; 1255 fman_intf = cfg->fman_if; 1256 1257 dpaa_intf->name = dpaa_device->name; 1258 1259 /* save fman_if & cfg in the interface struture */ 1260 dpaa_intf->fif = fman_intf; 1261 dpaa_intf->ifid = dev_id; 1262 dpaa_intf->cfg = cfg; 1263 1264 /* Initialize Rx FQ's */ 1265 if (default_q) { 1266 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1267 } else { 1268 if (getenv("DPAA_NUM_RX_QUEUES")) 1269 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES")); 1270 else 1271 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1272 } 1273 1274 1275 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1276 * queues. 1277 */ 1278 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1279 DPAA_PMD_ERR("Invalid number of RX queues\n"); 1280 return -EINVAL; 1281 } 1282 1283 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1284 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1285 if (!dpaa_intf->rx_queues) { 1286 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n"); 1287 return -ENOMEM; 1288 } 1289 1290 /* If congestion control is enabled globally*/ 1291 if (td_threshold) { 1292 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1293 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1294 if (!dpaa_intf->cgr_rx) { 1295 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n"); 1296 ret = -ENOMEM; 1297 goto free_rx; 1298 } 1299 1300 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1301 if (ret != num_rx_fqs) { 1302 DPAA_PMD_WARN("insufficient CGRIDs available"); 1303 ret = -EINVAL; 1304 goto free_rx; 1305 } 1306 } else { 1307 dpaa_intf->cgr_rx = NULL; 1308 } 1309 1310 for (loop = 0; loop < num_rx_fqs; loop++) { 1311 if (default_q) 1312 fqid = cfg->rx_def; 1313 else 1314 fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx * 1315 DPAA_PCD_FQID_MULTIPLIER + loop; 1316 1317 if (dpaa_intf->cgr_rx) 1318 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 1319 1320 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 1321 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 1322 fqid); 1323 if (ret) 1324 goto free_rx; 1325 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 1326 } 1327 dpaa_intf->nb_rx_queues = num_rx_fqs; 1328 1329 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 1330 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 1331 MAX_DPAA_CORES, MAX_CACHELINE); 1332 if (!dpaa_intf->tx_queues) { 1333 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n"); 1334 ret = -ENOMEM; 1335 goto free_rx; 1336 } 1337 1338 for (loop = 0; loop < MAX_DPAA_CORES; loop++) { 1339 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 1340 fman_intf); 1341 if (ret) 1342 goto free_tx; 1343 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 1344 } 1345 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES; 1346 1347 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1348 dpaa_debug_queue_init(&dpaa_intf->debug_queues[ 1349 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 1350 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 1351 dpaa_debug_queue_init(&dpaa_intf->debug_queues[ 1352 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 1353 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 1354 #endif 1355 1356 DPAA_PMD_DEBUG("All frame queues created"); 1357 1358 /* Get the initial configuration for flow control */ 1359 dpaa_fc_set_default(dpaa_intf); 1360 1361 /* reset bpool list, initialize bpool dynamically */ 1362 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 1363 list_del(&bp->node); 1364 rte_free(bp); 1365 } 1366 1367 /* Populate ethdev structure */ 1368 eth_dev->dev_ops = &dpaa_devops; 1369 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1370 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 1371 1372 /* Allocate memory for storing MAC addresses */ 1373 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 1374 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 1375 if (eth_dev->data->mac_addrs == NULL) { 1376 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 1377 "store MAC addresses", 1378 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 1379 ret = -ENOMEM; 1380 goto free_tx; 1381 } 1382 1383 /* copy the primary mac address */ 1384 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 1385 1386 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n", 1387 dpaa_device->name, 1388 fman_intf->mac_addr.addr_bytes[0], 1389 fman_intf->mac_addr.addr_bytes[1], 1390 fman_intf->mac_addr.addr_bytes[2], 1391 fman_intf->mac_addr.addr_bytes[3], 1392 fman_intf->mac_addr.addr_bytes[4], 1393 fman_intf->mac_addr.addr_bytes[5]); 1394 1395 /* Disable RX mode */ 1396 fman_if_discard_rx_errors(fman_intf); 1397 fman_if_disable_rx(fman_intf); 1398 /* Disable promiscuous mode */ 1399 fman_if_promiscuous_disable(fman_intf); 1400 /* Disable multicast */ 1401 fman_if_reset_mcast_filter_table(fman_intf); 1402 /* Reset interface statistics */ 1403 fman_if_stats_reset(fman_intf); 1404 /* Disable SG by default */ 1405 fman_if_set_sg(fman_intf, 0); 1406 fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE); 1407 1408 return 0; 1409 1410 free_tx: 1411 rte_free(dpaa_intf->tx_queues); 1412 dpaa_intf->tx_queues = NULL; 1413 dpaa_intf->nb_tx_queues = 0; 1414 1415 free_rx: 1416 rte_free(dpaa_intf->cgr_rx); 1417 rte_free(dpaa_intf->rx_queues); 1418 dpaa_intf->rx_queues = NULL; 1419 dpaa_intf->nb_rx_queues = 0; 1420 return ret; 1421 } 1422 1423 static int 1424 dpaa_dev_uninit(struct rte_eth_dev *dev) 1425 { 1426 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1427 int loop; 1428 1429 PMD_INIT_FUNC_TRACE(); 1430 1431 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1432 return -EPERM; 1433 1434 if (!dpaa_intf) { 1435 DPAA_PMD_WARN("Already closed or not started"); 1436 return -1; 1437 } 1438 1439 dpaa_eth_dev_close(dev); 1440 1441 /* release configuration memory */ 1442 if (dpaa_intf->fc_conf) 1443 rte_free(dpaa_intf->fc_conf); 1444 1445 /* Release RX congestion Groups */ 1446 if (dpaa_intf->cgr_rx) { 1447 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 1448 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 1449 1450 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid, 1451 dpaa_intf->nb_rx_queues); 1452 } 1453 1454 rte_free(dpaa_intf->cgr_rx); 1455 dpaa_intf->cgr_rx = NULL; 1456 1457 rte_free(dpaa_intf->rx_queues); 1458 dpaa_intf->rx_queues = NULL; 1459 1460 rte_free(dpaa_intf->tx_queues); 1461 dpaa_intf->tx_queues = NULL; 1462 1463 dev->dev_ops = NULL; 1464 dev->rx_pkt_burst = NULL; 1465 dev->tx_pkt_burst = NULL; 1466 1467 return 0; 1468 } 1469 1470 static int 1471 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused, 1472 struct rte_dpaa_device *dpaa_dev) 1473 { 1474 int diag; 1475 int ret; 1476 struct rte_eth_dev *eth_dev; 1477 1478 PMD_INIT_FUNC_TRACE(); 1479 1480 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > 1481 RTE_PKTMBUF_HEADROOM) { 1482 DPAA_PMD_ERR( 1483 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)", 1484 RTE_PKTMBUF_HEADROOM, 1485 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE); 1486 1487 return -1; 1488 } 1489 1490 /* In case of secondary process, the device is already configured 1491 * and no further action is required, except portal initialization 1492 * and verifying secondary attachment to port name. 1493 */ 1494 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1495 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 1496 if (!eth_dev) 1497 return -ENOMEM; 1498 eth_dev->device = &dpaa_dev->device; 1499 eth_dev->dev_ops = &dpaa_devops; 1500 rte_eth_dev_probing_finish(eth_dev); 1501 return 0; 1502 } 1503 1504 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) { 1505 /* One time load of Qman/Bman drivers */ 1506 ret = qman_global_init(); 1507 if (ret) { 1508 DPAA_PMD_ERR("QMAN initialization failed: %d", 1509 ret); 1510 return ret; 1511 } 1512 ret = bman_global_init(); 1513 if (ret) { 1514 DPAA_PMD_ERR("BMAN initialization failed: %d", 1515 ret); 1516 return ret; 1517 } 1518 1519 if (access("/tmp/fmc.bin", F_OK) == -1) { 1520 RTE_LOG(INFO, PMD, 1521 "* FMC not configured.Enabling default mode\n"); 1522 default_q = 1; 1523 } 1524 1525 /* disabling the default push mode for LS1043 */ 1526 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 1527 dpaa_push_mode_max_queue = 0; 1528 1529 /* if push mode queues to be enabled. Currenly we are allowing 1530 * only one queue per thread. 1531 */ 1532 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 1533 dpaa_push_mode_max_queue = 1534 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 1535 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 1536 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 1537 } 1538 1539 is_global_init = 1; 1540 } 1541 1542 if (unlikely(!RTE_PER_LCORE(dpaa_io))) { 1543 ret = rte_dpaa_portal_init((void *)1); 1544 if (ret) { 1545 DPAA_PMD_ERR("Unable to initialize portal"); 1546 return ret; 1547 } 1548 } 1549 1550 /* In case of secondary process, the device is already configured 1551 * and no further action is required, except portal initialization 1552 * and verifying secondary attachment to port name. 1553 */ 1554 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1555 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 1556 if (!eth_dev) 1557 return -ENOMEM; 1558 } else { 1559 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 1560 if (eth_dev == NULL) 1561 return -ENOMEM; 1562 1563 eth_dev->data->dev_private = rte_zmalloc( 1564 "ethdev private structure", 1565 sizeof(struct dpaa_if), 1566 RTE_CACHE_LINE_SIZE); 1567 if (!eth_dev->data->dev_private) { 1568 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 1569 rte_eth_dev_release_port(eth_dev); 1570 return -ENOMEM; 1571 } 1572 } 1573 eth_dev->device = &dpaa_dev->device; 1574 dpaa_dev->eth_dev = eth_dev; 1575 1576 /* Invoke PMD device initialization function */ 1577 diag = dpaa_dev_init(eth_dev); 1578 if (diag == 0) { 1579 rte_eth_dev_probing_finish(eth_dev); 1580 return 0; 1581 } 1582 1583 rte_eth_dev_release_port(eth_dev); 1584 return diag; 1585 } 1586 1587 static int 1588 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 1589 { 1590 struct rte_eth_dev *eth_dev; 1591 1592 PMD_INIT_FUNC_TRACE(); 1593 1594 eth_dev = dpaa_dev->eth_dev; 1595 dpaa_dev_uninit(eth_dev); 1596 1597 rte_eth_dev_release_port(eth_dev); 1598 1599 return 0; 1600 } 1601 1602 static struct rte_dpaa_driver rte_dpaa_pmd = { 1603 .drv_type = FSL_DPAA_ETH, 1604 .probe = rte_dpaa_probe, 1605 .remove = rte_dpaa_remove, 1606 }; 1607 1608 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 1609