1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017-2020 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 18 #include <rte_string_fns.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_interrupts.h> 22 #include <rte_log.h> 23 #include <rte_debug.h> 24 #include <rte_pci.h> 25 #include <rte_atomic.h> 26 #include <rte_branch_prediction.h> 27 #include <rte_memory.h> 28 #include <rte_tailq.h> 29 #include <rte_eal.h> 30 #include <rte_alarm.h> 31 #include <rte_ether.h> 32 #include <ethdev_driver.h> 33 #include <rte_malloc.h> 34 #include <rte_ring.h> 35 36 #include <rte_dpaa_bus.h> 37 #include <rte_dpaa_logs.h> 38 #include <dpaa_mempool.h> 39 40 #include <dpaa_ethdev.h> 41 #include <dpaa_rxtx.h> 42 #include <dpaa_flow.h> 43 #include <rte_pmd_dpaa.h> 44 45 #include <fsl_usd.h> 46 #include <fsl_qman.h> 47 #include <fsl_bman.h> 48 #include <fsl_fman.h> 49 #include <process.h> 50 #include <fmlib/fm_ext.h> 51 52 #define CHECK_INTERVAL 100 /* 100ms */ 53 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 54 55 /* Supported Rx offloads */ 56 static uint64_t dev_rx_offloads_sup = 57 DEV_RX_OFFLOAD_JUMBO_FRAME | 58 DEV_RX_OFFLOAD_SCATTER; 59 60 /* Rx offloads which cannot be disabled */ 61 static uint64_t dev_rx_offloads_nodis = 62 DEV_RX_OFFLOAD_IPV4_CKSUM | 63 DEV_RX_OFFLOAD_UDP_CKSUM | 64 DEV_RX_OFFLOAD_TCP_CKSUM | 65 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 66 DEV_RX_OFFLOAD_RSS_HASH; 67 68 /* Supported Tx offloads */ 69 static uint64_t dev_tx_offloads_sup = 70 DEV_TX_OFFLOAD_MT_LOCKFREE | 71 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 72 73 /* Tx offloads which cannot be disabled */ 74 static uint64_t dev_tx_offloads_nodis = 75 DEV_TX_OFFLOAD_IPV4_CKSUM | 76 DEV_TX_OFFLOAD_UDP_CKSUM | 77 DEV_TX_OFFLOAD_TCP_CKSUM | 78 DEV_TX_OFFLOAD_SCTP_CKSUM | 79 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 80 DEV_TX_OFFLOAD_MULTI_SEGS; 81 82 /* Keep track of whether QMAN and BMAN have been globally initialized */ 83 static int is_global_init; 84 static int fmc_q = 1; /* Indicates the use of static fmc for distribution */ 85 static int default_q; /* use default queue - FMC is not executed*/ 86 /* At present we only allow up to 4 push mode queues as default - as each of 87 * this queue need dedicated portal and we are short of portals. 88 */ 89 #define DPAA_MAX_PUSH_MODE_QUEUE 8 90 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 91 92 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 93 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 94 95 96 /* Per RX FQ Taildrop in frame count */ 97 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 98 99 /* Per TX FQ Taildrop in frame count, disabled by default */ 100 static unsigned int td_tx_threshold; 101 102 struct rte_dpaa_xstats_name_off { 103 char name[RTE_ETH_XSTATS_NAME_SIZE]; 104 uint32_t offset; 105 }; 106 107 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 108 {"rx_align_err", 109 offsetof(struct dpaa_if_stats, raln)}, 110 {"rx_valid_pause", 111 offsetof(struct dpaa_if_stats, rxpf)}, 112 {"rx_fcs_err", 113 offsetof(struct dpaa_if_stats, rfcs)}, 114 {"rx_vlan_frame", 115 offsetof(struct dpaa_if_stats, rvlan)}, 116 {"rx_frame_err", 117 offsetof(struct dpaa_if_stats, rerr)}, 118 {"rx_drop_err", 119 offsetof(struct dpaa_if_stats, rdrp)}, 120 {"rx_undersized", 121 offsetof(struct dpaa_if_stats, rund)}, 122 {"rx_oversize_err", 123 offsetof(struct dpaa_if_stats, rovr)}, 124 {"rx_fragment_pkt", 125 offsetof(struct dpaa_if_stats, rfrg)}, 126 {"tx_valid_pause", 127 offsetof(struct dpaa_if_stats, txpf)}, 128 {"tx_fcs_err", 129 offsetof(struct dpaa_if_stats, terr)}, 130 {"tx_vlan_frame", 131 offsetof(struct dpaa_if_stats, tvlan)}, 132 {"rx_undersized", 133 offsetof(struct dpaa_if_stats, tund)}, 134 }; 135 136 static struct rte_dpaa_driver rte_dpaa_pmd; 137 138 static int 139 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 140 141 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 142 int wait_to_complete __rte_unused); 143 144 static void dpaa_interrupt_handler(void *param); 145 146 static inline void 147 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 148 { 149 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 150 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 151 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 152 QM_FQCTRL_PREFERINCACHE; 153 opts->fqd.context_a.stashing.exclusive = 0; 154 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 155 opts->fqd.context_a.stashing.annotation_cl = 156 DPAA_IF_RX_ANNOTATION_STASH; 157 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 158 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 159 } 160 161 static int 162 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 163 { 164 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 165 + VLAN_TAG_SIZE; 166 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 167 168 PMD_INIT_FUNC_TRACE(); 169 170 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN) 171 return -EINVAL; 172 /* 173 * Refuse mtu that requires the support of scattered packets 174 * when this feature has not been enabled before. 175 */ 176 if (dev->data->min_rx_buf_size && 177 !dev->data->scattered_rx && frame_size > buffsz) { 178 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 179 return -EINVAL; 180 } 181 182 /* check <seg size> * <max_seg> >= max_frame */ 183 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 184 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 185 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 186 buffsz * DPAA_SGT_MAX_ENTRIES); 187 return -EINVAL; 188 } 189 190 fman_if_set_maxfrm(dev->process_private, frame_size); 191 192 return 0; 193 } 194 195 static int 196 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 197 { 198 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 199 uint64_t rx_offloads = eth_conf->rxmode.offloads; 200 uint64_t tx_offloads = eth_conf->txmode.offloads; 201 struct rte_device *rdev = dev->device; 202 struct rte_eth_link *link = &dev->data->dev_link; 203 struct rte_dpaa_device *dpaa_dev; 204 struct fman_if *fif = dev->process_private; 205 struct __fman_if *__fif; 206 struct rte_intr_handle *intr_handle; 207 uint32_t max_rx_pktlen; 208 int speed, duplex; 209 int ret; 210 211 PMD_INIT_FUNC_TRACE(); 212 213 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 214 intr_handle = &dpaa_dev->intr_handle; 215 __fif = container_of(fif, struct __fman_if, __if); 216 217 /* Rx offloads which are enabled by default */ 218 if (dev_rx_offloads_nodis & ~rx_offloads) { 219 DPAA_PMD_INFO( 220 "Some of rx offloads enabled by default - requested 0x%" PRIx64 221 " fixed are 0x%" PRIx64, 222 rx_offloads, dev_rx_offloads_nodis); 223 } 224 225 /* Tx offloads which are enabled by default */ 226 if (dev_tx_offloads_nodis & ~tx_offloads) { 227 DPAA_PMD_INFO( 228 "Some of tx offloads enabled by default - requested 0x%" PRIx64 229 " fixed are 0x%" PRIx64, 230 tx_offloads, dev_tx_offloads_nodis); 231 } 232 233 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + 234 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; 235 if (max_rx_pktlen > DPAA_MAX_RX_PKT_LEN) { 236 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 237 "supported is %d", 238 max_rx_pktlen, DPAA_MAX_RX_PKT_LEN); 239 max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 240 } 241 242 fman_if_set_maxfrm(dev->process_private, max_rx_pktlen); 243 244 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) { 245 DPAA_PMD_DEBUG("enabling scatter mode"); 246 fman_if_set_sg(dev->process_private, 1); 247 dev->data->scattered_rx = 1; 248 } 249 250 if (!(default_q || fmc_q)) { 251 if (dpaa_fm_config(dev, 252 eth_conf->rx_adv_conf.rss_conf.rss_hf)) { 253 dpaa_write_fm_config_to_file(); 254 DPAA_PMD_ERR("FM port configuration: Failed\n"); 255 return -1; 256 } 257 dpaa_write_fm_config_to_file(); 258 } 259 260 /* if the interrupts were configured on this devices*/ 261 if (intr_handle && intr_handle->fd) { 262 if (dev->data->dev_conf.intr_conf.lsc != 0) 263 rte_intr_callback_register(intr_handle, 264 dpaa_interrupt_handler, 265 (void *)dev); 266 267 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd); 268 if (ret) { 269 if (dev->data->dev_conf.intr_conf.lsc != 0) { 270 rte_intr_callback_unregister(intr_handle, 271 dpaa_interrupt_handler, 272 (void *)dev); 273 if (ret == EINVAL) 274 printf("Failed to enable interrupt: Not Supported\n"); 275 else 276 printf("Failed to enable interrupt\n"); 277 } 278 dev->data->dev_conf.intr_conf.lsc = 0; 279 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 280 } 281 } 282 283 /* Wait for link status to get updated */ 284 if (!link->link_status) 285 sleep(1); 286 287 /* Configure link only if link is UP*/ 288 if (link->link_status) { 289 if (eth_conf->link_speeds == ETH_LINK_SPEED_AUTONEG) { 290 /* Start autoneg only if link is not in autoneg mode */ 291 if (!link->link_autoneg) 292 dpaa_restart_link_autoneg(__fif->node_name); 293 } else if (eth_conf->link_speeds & ETH_LINK_SPEED_FIXED) { 294 switch (eth_conf->link_speeds & ~ETH_LINK_SPEED_FIXED) { 295 case ETH_LINK_SPEED_10M_HD: 296 speed = ETH_SPEED_NUM_10M; 297 duplex = ETH_LINK_HALF_DUPLEX; 298 break; 299 case ETH_LINK_SPEED_10M: 300 speed = ETH_SPEED_NUM_10M; 301 duplex = ETH_LINK_FULL_DUPLEX; 302 break; 303 case ETH_LINK_SPEED_100M_HD: 304 speed = ETH_SPEED_NUM_100M; 305 duplex = ETH_LINK_HALF_DUPLEX; 306 break; 307 case ETH_LINK_SPEED_100M: 308 speed = ETH_SPEED_NUM_100M; 309 duplex = ETH_LINK_FULL_DUPLEX; 310 break; 311 case ETH_LINK_SPEED_1G: 312 speed = ETH_SPEED_NUM_1G; 313 duplex = ETH_LINK_FULL_DUPLEX; 314 break; 315 case ETH_LINK_SPEED_2_5G: 316 speed = ETH_SPEED_NUM_2_5G; 317 duplex = ETH_LINK_FULL_DUPLEX; 318 break; 319 case ETH_LINK_SPEED_10G: 320 speed = ETH_SPEED_NUM_10G; 321 duplex = ETH_LINK_FULL_DUPLEX; 322 break; 323 default: 324 speed = ETH_SPEED_NUM_NONE; 325 duplex = ETH_LINK_FULL_DUPLEX; 326 break; 327 } 328 /* Set link speed */ 329 dpaa_update_link_speed(__fif->node_name, speed, duplex); 330 } else { 331 /* Manual autoneg - custom advertisement speed. */ 332 printf("Custom Advertisement speeds not supported\n"); 333 } 334 } 335 336 return 0; 337 } 338 339 static const uint32_t * 340 dpaa_supported_ptypes_get(struct rte_eth_dev *dev) 341 { 342 static const uint32_t ptypes[] = { 343 RTE_PTYPE_L2_ETHER, 344 RTE_PTYPE_L2_ETHER_VLAN, 345 RTE_PTYPE_L2_ETHER_ARP, 346 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 347 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 348 RTE_PTYPE_L4_ICMP, 349 RTE_PTYPE_L4_TCP, 350 RTE_PTYPE_L4_UDP, 351 RTE_PTYPE_L4_FRAG, 352 RTE_PTYPE_L4_TCP, 353 RTE_PTYPE_L4_UDP, 354 RTE_PTYPE_L4_SCTP 355 }; 356 357 PMD_INIT_FUNC_TRACE(); 358 359 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) 360 return ptypes; 361 return NULL; 362 } 363 364 static void dpaa_interrupt_handler(void *param) 365 { 366 struct rte_eth_dev *dev = param; 367 struct rte_device *rdev = dev->device; 368 struct rte_dpaa_device *dpaa_dev; 369 struct rte_intr_handle *intr_handle; 370 uint64_t buf; 371 int bytes_read; 372 373 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 374 intr_handle = &dpaa_dev->intr_handle; 375 376 bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t)); 377 if (bytes_read < 0) 378 DPAA_PMD_ERR("Error reading eventfd\n"); 379 dpaa_eth_link_update(dev, 0); 380 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 381 } 382 383 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 384 { 385 struct dpaa_if *dpaa_intf = dev->data->dev_private; 386 387 PMD_INIT_FUNC_TRACE(); 388 389 if (!(default_q || fmc_q)) 390 dpaa_write_fm_config_to_file(); 391 392 /* Change tx callback to the real one */ 393 if (dpaa_intf->cgr_tx) 394 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 395 else 396 dev->tx_pkt_burst = dpaa_eth_queue_tx; 397 398 fman_if_enable_rx(dev->process_private); 399 400 return 0; 401 } 402 403 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev) 404 { 405 struct fman_if *fif = dev->process_private; 406 407 PMD_INIT_FUNC_TRACE(); 408 dev->data->dev_started = 0; 409 410 if (!fif->is_shared_mac) 411 fman_if_disable_rx(fif); 412 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 413 414 return 0; 415 } 416 417 static int dpaa_eth_dev_close(struct rte_eth_dev *dev) 418 { 419 struct fman_if *fif = dev->process_private; 420 struct __fman_if *__fif; 421 struct rte_device *rdev = dev->device; 422 struct rte_dpaa_device *dpaa_dev; 423 struct rte_intr_handle *intr_handle; 424 struct rte_eth_link *link = &dev->data->dev_link; 425 struct dpaa_if *dpaa_intf = dev->data->dev_private; 426 int loop; 427 int ret; 428 429 PMD_INIT_FUNC_TRACE(); 430 431 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 432 return 0; 433 434 if (!dpaa_intf) { 435 DPAA_PMD_WARN("Already closed or not started"); 436 return -1; 437 } 438 439 /* DPAA FM deconfig */ 440 if (!(default_q || fmc_q)) { 441 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private)) 442 DPAA_PMD_WARN("DPAA FM deconfig failed\n"); 443 } 444 445 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 446 intr_handle = &dpaa_dev->intr_handle; 447 __fif = container_of(fif, struct __fman_if, __if); 448 449 ret = dpaa_eth_dev_stop(dev); 450 451 /* Reset link to autoneg */ 452 if (link->link_status && !link->link_autoneg) 453 dpaa_restart_link_autoneg(__fif->node_name); 454 455 if (intr_handle && intr_handle->fd && 456 dev->data->dev_conf.intr_conf.lsc != 0) { 457 dpaa_intr_disable(__fif->node_name); 458 rte_intr_callback_unregister(intr_handle, 459 dpaa_interrupt_handler, 460 (void *)dev); 461 } 462 463 /* release configuration memory */ 464 if (dpaa_intf->fc_conf) 465 rte_free(dpaa_intf->fc_conf); 466 467 /* Release RX congestion Groups */ 468 if (dpaa_intf->cgr_rx) { 469 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 470 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 471 } 472 473 rte_free(dpaa_intf->cgr_rx); 474 dpaa_intf->cgr_rx = NULL; 475 /* Release TX congestion Groups */ 476 if (dpaa_intf->cgr_tx) { 477 for (loop = 0; loop < MAX_DPAA_CORES; loop++) 478 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]); 479 rte_free(dpaa_intf->cgr_tx); 480 dpaa_intf->cgr_tx = NULL; 481 } 482 483 rte_free(dpaa_intf->rx_queues); 484 dpaa_intf->rx_queues = NULL; 485 486 rte_free(dpaa_intf->tx_queues); 487 dpaa_intf->tx_queues = NULL; 488 489 return ret; 490 } 491 492 static int 493 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 494 char *fw_version, 495 size_t fw_size) 496 { 497 int ret; 498 FILE *svr_file = NULL; 499 unsigned int svr_ver = 0; 500 501 PMD_INIT_FUNC_TRACE(); 502 503 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 504 if (!svr_file) { 505 DPAA_PMD_ERR("Unable to open SoC device"); 506 return -ENOTSUP; /* Not supported on this infra */ 507 } 508 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 509 dpaa_svr_family = svr_ver & SVR_MASK; 510 else 511 DPAA_PMD_ERR("Unable to read SoC device"); 512 513 fclose(svr_file); 514 515 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 516 svr_ver, fman_ip_rev); 517 if (ret < 0) 518 return -EINVAL; 519 520 ret += 1; /* add the size of '\0' */ 521 if (fw_size < (size_t)ret) 522 return ret; 523 else 524 return 0; 525 } 526 527 static int dpaa_eth_dev_info(struct rte_eth_dev *dev, 528 struct rte_eth_dev_info *dev_info) 529 { 530 struct dpaa_if *dpaa_intf = dev->data->dev_private; 531 struct fman_if *fif = dev->process_private; 532 533 DPAA_PMD_DEBUG(": %s", dpaa_intf->name); 534 535 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 536 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 537 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 538 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 539 dev_info->max_hash_mac_addrs = 0; 540 dev_info->max_vfs = 0; 541 dev_info->max_vmdq_pools = ETH_16_POOLS; 542 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 543 544 if (fif->mac_type == fman_mac_1g) { 545 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD 546 | ETH_LINK_SPEED_10M 547 | ETH_LINK_SPEED_100M_HD 548 | ETH_LINK_SPEED_100M 549 | ETH_LINK_SPEED_1G; 550 } else if (fif->mac_type == fman_mac_2_5g) { 551 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD 552 | ETH_LINK_SPEED_10M 553 | ETH_LINK_SPEED_100M_HD 554 | ETH_LINK_SPEED_100M 555 | ETH_LINK_SPEED_1G 556 | ETH_LINK_SPEED_2_5G; 557 } else if (fif->mac_type == fman_mac_10g) { 558 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD 559 | ETH_LINK_SPEED_10M 560 | ETH_LINK_SPEED_100M_HD 561 | ETH_LINK_SPEED_100M 562 | ETH_LINK_SPEED_1G 563 | ETH_LINK_SPEED_2_5G 564 | ETH_LINK_SPEED_10G; 565 } else { 566 DPAA_PMD_ERR("invalid link_speed: %s, %d", 567 dpaa_intf->name, fif->mac_type); 568 return -EINVAL; 569 } 570 571 dev_info->rx_offload_capa = dev_rx_offloads_sup | 572 dev_rx_offloads_nodis; 573 dev_info->tx_offload_capa = dev_tx_offloads_sup | 574 dev_tx_offloads_nodis; 575 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 576 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 577 dev_info->default_rxportconf.nb_queues = 1; 578 dev_info->default_txportconf.nb_queues = 1; 579 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH; 580 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH; 581 582 return 0; 583 } 584 585 static int 586 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 587 __rte_unused uint16_t queue_id, 588 struct rte_eth_burst_mode *mode) 589 { 590 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 591 int ret = -EINVAL; 592 unsigned int i; 593 const struct burst_info { 594 uint64_t flags; 595 const char *output; 596 } rx_offload_map[] = { 597 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"}, 598 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}, 599 {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 600 {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 601 {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 602 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 603 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"} 604 }; 605 606 /* Update Rx offload info */ 607 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 608 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 609 snprintf(mode->info, sizeof(mode->info), "%s", 610 rx_offload_map[i].output); 611 ret = 0; 612 break; 613 } 614 } 615 return ret; 616 } 617 618 static int 619 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 620 __rte_unused uint16_t queue_id, 621 struct rte_eth_burst_mode *mode) 622 { 623 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 624 int ret = -EINVAL; 625 unsigned int i; 626 const struct burst_info { 627 uint64_t flags; 628 const char *output; 629 } tx_offload_map[] = { 630 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 631 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 632 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 633 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 634 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 635 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 636 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 637 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 638 }; 639 640 /* Update Tx offload info */ 641 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 642 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 643 snprintf(mode->info, sizeof(mode->info), "%s", 644 tx_offload_map[i].output); 645 ret = 0; 646 break; 647 } 648 } 649 return ret; 650 } 651 652 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 653 int wait_to_complete) 654 { 655 struct dpaa_if *dpaa_intf = dev->data->dev_private; 656 struct rte_eth_link *link = &dev->data->dev_link; 657 struct fman_if *fif = dev->process_private; 658 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if); 659 int ret, ioctl_version; 660 uint8_t count; 661 662 PMD_INIT_FUNC_TRACE(); 663 664 ioctl_version = dpaa_get_ioctl_version_number(); 665 666 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) { 667 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 668 ret = dpaa_get_link_status(__fif->node_name, link); 669 if (ret) 670 return ret; 671 if (link->link_status == ETH_LINK_DOWN && 672 wait_to_complete) 673 rte_delay_ms(CHECK_INTERVAL); 674 else 675 break; 676 } 677 } else { 678 link->link_status = dpaa_intf->valid; 679 } 680 681 if (ioctl_version < 2) { 682 link->link_duplex = ETH_LINK_FULL_DUPLEX; 683 link->link_autoneg = ETH_LINK_AUTONEG; 684 685 if (fif->mac_type == fman_mac_1g) 686 link->link_speed = ETH_SPEED_NUM_1G; 687 else if (fif->mac_type == fman_mac_2_5g) 688 link->link_speed = ETH_SPEED_NUM_2_5G; 689 else if (fif->mac_type == fman_mac_10g) 690 link->link_speed = ETH_SPEED_NUM_10G; 691 else 692 DPAA_PMD_ERR("invalid link_speed: %s, %d", 693 dpaa_intf->name, fif->mac_type); 694 } 695 696 DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 697 link->link_status ? "Up" : "Down"); 698 return 0; 699 } 700 701 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 702 struct rte_eth_stats *stats) 703 { 704 PMD_INIT_FUNC_TRACE(); 705 706 fman_if_stats_get(dev->process_private, stats); 707 return 0; 708 } 709 710 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev) 711 { 712 PMD_INIT_FUNC_TRACE(); 713 714 fman_if_stats_reset(dev->process_private); 715 716 return 0; 717 } 718 719 static int 720 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 721 unsigned int n) 722 { 723 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 724 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 725 726 if (n < num) 727 return num; 728 729 if (xstats == NULL) 730 return 0; 731 732 fman_if_stats_get_all(dev->process_private, values, 733 sizeof(struct dpaa_if_stats) / 8); 734 735 for (i = 0; i < num; i++) { 736 xstats[i].id = i; 737 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 738 } 739 return i; 740 } 741 742 static int 743 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 744 struct rte_eth_xstat_name *xstats_names, 745 unsigned int limit) 746 { 747 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 748 749 if (limit < stat_cnt) 750 return stat_cnt; 751 752 if (xstats_names != NULL) 753 for (i = 0; i < stat_cnt; i++) 754 strlcpy(xstats_names[i].name, 755 dpaa_xstats_strings[i].name, 756 sizeof(xstats_names[i].name)); 757 758 return stat_cnt; 759 } 760 761 static int 762 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 763 uint64_t *values, unsigned int n) 764 { 765 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 766 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 767 768 if (!ids) { 769 if (n < stat_cnt) 770 return stat_cnt; 771 772 if (!values) 773 return 0; 774 775 fman_if_stats_get_all(dev->process_private, values_copy, 776 sizeof(struct dpaa_if_stats) / 8); 777 778 for (i = 0; i < stat_cnt; i++) 779 values[i] = 780 values_copy[dpaa_xstats_strings[i].offset / 8]; 781 782 return stat_cnt; 783 } 784 785 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 786 787 for (i = 0; i < n; i++) { 788 if (ids[i] >= stat_cnt) { 789 DPAA_PMD_ERR("id value isn't valid"); 790 return -1; 791 } 792 values[i] = values_copy[ids[i]]; 793 } 794 return n; 795 } 796 797 static int 798 dpaa_xstats_get_names_by_id( 799 struct rte_eth_dev *dev, 800 const uint64_t *ids, 801 struct rte_eth_xstat_name *xstats_names, 802 unsigned int limit) 803 { 804 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 805 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 806 807 if (!ids) 808 return dpaa_xstats_get_names(dev, xstats_names, limit); 809 810 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 811 812 for (i = 0; i < limit; i++) { 813 if (ids[i] >= stat_cnt) { 814 DPAA_PMD_ERR("id value isn't valid"); 815 return -1; 816 } 817 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 818 } 819 return limit; 820 } 821 822 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 823 { 824 PMD_INIT_FUNC_TRACE(); 825 826 fman_if_promiscuous_enable(dev->process_private); 827 828 return 0; 829 } 830 831 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 832 { 833 PMD_INIT_FUNC_TRACE(); 834 835 fman_if_promiscuous_disable(dev->process_private); 836 837 return 0; 838 } 839 840 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 841 { 842 PMD_INIT_FUNC_TRACE(); 843 844 fman_if_set_mcast_filter_table(dev->process_private); 845 846 return 0; 847 } 848 849 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 850 { 851 PMD_INIT_FUNC_TRACE(); 852 853 fman_if_reset_mcast_filter_table(dev->process_private); 854 855 return 0; 856 } 857 858 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev) 859 { 860 struct dpaa_if *dpaa_intf = dev->data->dev_private; 861 struct fman_if_ic_params icp; 862 uint32_t fd_offset; 863 uint32_t bp_size; 864 865 memset(&icp, 0, sizeof(icp)); 866 /* set ICEOF for to the default value , which is 0*/ 867 icp.iciof = DEFAULT_ICIOF; 868 icp.iceof = DEFAULT_RX_ICEOF; 869 icp.icsz = DEFAULT_ICSZ; 870 fman_if_set_ic_params(dev->process_private, &icp); 871 872 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 873 fman_if_set_fdoff(dev->process_private, fd_offset); 874 875 /* Buffer pool size should be equal to Dataroom Size*/ 876 bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp); 877 878 fman_if_set_bp(dev->process_private, 879 dpaa_intf->bp_info->mp->size, 880 dpaa_intf->bp_info->bpid, bp_size); 881 } 882 883 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev, 884 int8_t vsp_id, uint32_t bpid) 885 { 886 struct dpaa_if *dpaa_intf = dev->data->dev_private; 887 struct fman_if *fif = dev->process_private; 888 889 if (fif->num_profiles) { 890 if (vsp_id < 0) 891 vsp_id = fif->base_profile_id; 892 } else { 893 if (vsp_id < 0) 894 vsp_id = 0; 895 } 896 897 if (dpaa_intf->vsp_bpid[vsp_id] && 898 bpid != dpaa_intf->vsp_bpid[vsp_id]) { 899 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP"); 900 901 return -1; 902 } 903 904 return 0; 905 } 906 907 static 908 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 909 uint16_t nb_desc, 910 unsigned int socket_id __rte_unused, 911 const struct rte_eth_rxconf *rx_conf, 912 struct rte_mempool *mp) 913 { 914 struct dpaa_if *dpaa_intf = dev->data->dev_private; 915 struct fman_if *fif = dev->process_private; 916 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 917 struct qm_mcc_initfq opts = {0}; 918 u32 flags = 0; 919 int ret; 920 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 921 uint32_t max_rx_pktlen; 922 923 PMD_INIT_FUNC_TRACE(); 924 925 if (queue_idx >= dev->data->nb_rx_queues) { 926 rte_errno = EOVERFLOW; 927 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 928 (void *)dev, queue_idx, dev->data->nb_rx_queues); 929 return -rte_errno; 930 } 931 932 /* Rx deferred start is not supported */ 933 if (rx_conf->rx_deferred_start) { 934 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev); 935 return -EINVAL; 936 } 937 rxq->nb_desc = UINT16_MAX; 938 rxq->offloads = rx_conf->offloads; 939 940 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 941 queue_idx, rxq->fqid); 942 943 if (!fif->num_profiles) { 944 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 945 dpaa_intf->bp_info->mp != mp) { 946 DPAA_PMD_WARN("Multiple pools on same interface not" 947 " supported"); 948 return -EINVAL; 949 } 950 } else { 951 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id, 952 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) { 953 return -EINVAL; 954 } 955 } 956 957 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 958 dpaa_intf->bp_info->mp != mp) { 959 DPAA_PMD_WARN("Multiple pools on same interface not supported"); 960 return -EINVAL; 961 } 962 963 max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 964 VLAN_TAG_SIZE; 965 /* Max packet can fit in single buffer */ 966 if (max_rx_pktlen <= buffsz) { 967 ; 968 } else if (dev->data->dev_conf.rxmode.offloads & 969 DEV_RX_OFFLOAD_SCATTER) { 970 if (max_rx_pktlen > buffsz * DPAA_SGT_MAX_ENTRIES) { 971 DPAA_PMD_ERR("Maximum Rx packet size %d too big to fit " 972 "MaxSGlist %d", 973 max_rx_pktlen, buffsz * DPAA_SGT_MAX_ENTRIES); 974 rte_errno = EOVERFLOW; 975 return -rte_errno; 976 } 977 } else { 978 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 979 " larger than a single mbuf (%u) and scattered" 980 " mode has not been requested", 981 max_rx_pktlen, buffsz - RTE_PKTMBUF_HEADROOM); 982 } 983 984 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 985 986 /* For shared interface, it's done in kernel, skip.*/ 987 if (!fif->is_shared_mac) 988 dpaa_fman_if_pool_setup(dev); 989 990 if (fif->num_profiles) { 991 int8_t vsp_id = rxq->vsp_id; 992 993 if (vsp_id >= 0) { 994 ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id, 995 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid, 996 fif); 997 if (ret) { 998 DPAA_PMD_ERR("dpaa_port_vsp_update failed"); 999 return ret; 1000 } 1001 } else { 1002 DPAA_PMD_INFO("Base profile is associated to" 1003 " RXQ fqid:%d\r\n", rxq->fqid); 1004 if (fif->is_shared_mac) { 1005 DPAA_PMD_ERR("Fatal: Base profile is associated" 1006 " to shared interface on DPDK."); 1007 return -EINVAL; 1008 } 1009 dpaa_intf->vsp_bpid[fif->base_profile_id] = 1010 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1011 } 1012 } else { 1013 dpaa_intf->vsp_bpid[0] = 1014 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1015 } 1016 1017 dpaa_intf->valid = 1; 1018 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 1019 fman_if_get_sg_enable(fif), max_rx_pktlen); 1020 /* checking if push mode only, no error check for now */ 1021 if (!rxq->is_static && 1022 dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 1023 struct qman_portal *qp; 1024 int q_fd; 1025 1026 dpaa_push_queue_idx++; 1027 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 1028 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 1029 QM_FQCTRL_CTXASTASHING | 1030 QM_FQCTRL_PREFERINCACHE; 1031 opts.fqd.context_a.stashing.exclusive = 0; 1032 /* In muticore scenario stashing becomes a bottleneck on LS1046. 1033 * So do not enable stashing in this case 1034 */ 1035 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 1036 opts.fqd.context_a.stashing.annotation_cl = 1037 DPAA_IF_RX_ANNOTATION_STASH; 1038 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 1039 opts.fqd.context_a.stashing.context_cl = 1040 DPAA_IF_RX_CONTEXT_STASH; 1041 1042 /*Create a channel and associate given queue with the channel*/ 1043 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 1044 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1045 opts.fqd.dest.channel = rxq->ch_id; 1046 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 1047 flags = QMAN_INITFQ_FLAG_SCHED; 1048 1049 /* Configure tail drop */ 1050 if (dpaa_intf->cgr_rx) { 1051 opts.we_mask |= QM_INITFQ_WE_CGID; 1052 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 1053 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1054 } 1055 ret = qman_init_fq(rxq, flags, &opts); 1056 if (ret) { 1057 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 1058 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1059 return ret; 1060 } 1061 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 1062 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 1063 } else { 1064 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 1065 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 1066 } 1067 1068 rxq->is_static = true; 1069 1070 /* Allocate qman specific portals */ 1071 qp = fsl_qman_fq_portal_create(&q_fd); 1072 if (!qp) { 1073 DPAA_PMD_ERR("Unable to alloc fq portal"); 1074 return -1; 1075 } 1076 rxq->qp = qp; 1077 1078 /* Set up the device interrupt handler */ 1079 if (!dev->intr_handle) { 1080 struct rte_dpaa_device *dpaa_dev; 1081 struct rte_device *rdev = dev->device; 1082 1083 dpaa_dev = container_of(rdev, struct rte_dpaa_device, 1084 device); 1085 dev->intr_handle = &dpaa_dev->intr_handle; 1086 dev->intr_handle->intr_vec = rte_zmalloc(NULL, 1087 dpaa_push_mode_max_queue, 0); 1088 if (!dev->intr_handle->intr_vec) { 1089 DPAA_PMD_ERR("intr_vec alloc failed"); 1090 return -ENOMEM; 1091 } 1092 dev->intr_handle->nb_efd = dpaa_push_mode_max_queue; 1093 dev->intr_handle->max_intr = dpaa_push_mode_max_queue; 1094 } 1095 1096 dev->intr_handle->type = RTE_INTR_HANDLE_EXT; 1097 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1; 1098 dev->intr_handle->efds[queue_idx] = q_fd; 1099 rxq->q_fd = q_fd; 1100 } 1101 rxq->bp_array = rte_dpaa_bpid_info; 1102 dev->data->rx_queues[queue_idx] = rxq; 1103 1104 /* configure the CGR size as per the desc size */ 1105 if (dpaa_intf->cgr_rx) { 1106 struct qm_mcc_initcgr cgr_opts = {0}; 1107 1108 rxq->nb_desc = nb_desc; 1109 /* Enable tail drop with cgr on this queue */ 1110 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 1111 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 1112 if (ret) { 1113 DPAA_PMD_WARN( 1114 "rx taildrop modify fail on fqid %d (ret=%d)", 1115 rxq->fqid, ret); 1116 } 1117 } 1118 /* Enable main queue to receive error packets also by default */ 1119 fman_if_set_err_fqid(fif, rxq->fqid); 1120 return 0; 1121 } 1122 1123 int 1124 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 1125 int eth_rx_queue_id, 1126 u16 ch_id, 1127 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 1128 { 1129 int ret; 1130 u32 flags = 0; 1131 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1132 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1133 struct qm_mcc_initfq opts = {0}; 1134 1135 if (dpaa_push_mode_max_queue) 1136 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n" 1137 "PUSH mode already enabled for first %d queues.\n" 1138 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n", 1139 dpaa_push_mode_max_queue); 1140 1141 dpaa_poll_queue_default_config(&opts); 1142 1143 switch (queue_conf->ev.sched_type) { 1144 case RTE_SCHED_TYPE_ATOMIC: 1145 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 1146 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 1147 * configuration with HOLD_ACTIVE setting 1148 */ 1149 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 1150 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 1151 break; 1152 case RTE_SCHED_TYPE_ORDERED: 1153 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n"); 1154 return -1; 1155 default: 1156 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 1157 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 1158 break; 1159 } 1160 1161 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1162 opts.fqd.dest.channel = ch_id; 1163 opts.fqd.dest.wq = queue_conf->ev.priority; 1164 1165 if (dpaa_intf->cgr_rx) { 1166 opts.we_mask |= QM_INITFQ_WE_CGID; 1167 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1168 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1169 } 1170 1171 flags = QMAN_INITFQ_FLAG_SCHED; 1172 1173 ret = qman_init_fq(rxq, flags, &opts); 1174 if (ret) { 1175 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 1176 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1177 return ret; 1178 } 1179 1180 /* copy configuration which needs to be filled during dequeue */ 1181 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 1182 dev->data->rx_queues[eth_rx_queue_id] = rxq; 1183 1184 return ret; 1185 } 1186 1187 int 1188 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 1189 int eth_rx_queue_id) 1190 { 1191 struct qm_mcc_initfq opts; 1192 int ret; 1193 u32 flags = 0; 1194 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1195 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1196 1197 dpaa_poll_queue_default_config(&opts); 1198 1199 if (dpaa_intf->cgr_rx) { 1200 opts.we_mask |= QM_INITFQ_WE_CGID; 1201 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1202 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1203 } 1204 1205 ret = qman_init_fq(rxq, flags, &opts); 1206 if (ret) { 1207 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", 1208 rxq->fqid, ret); 1209 } 1210 1211 rxq->cb.dqrr_dpdk_cb = NULL; 1212 dev->data->rx_queues[eth_rx_queue_id] = NULL; 1213 1214 return 0; 1215 } 1216 1217 static 1218 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 1219 uint16_t nb_desc __rte_unused, 1220 unsigned int socket_id __rte_unused, 1221 const struct rte_eth_txconf *tx_conf) 1222 { 1223 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1224 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx]; 1225 1226 PMD_INIT_FUNC_TRACE(); 1227 1228 /* Tx deferred start is not supported */ 1229 if (tx_conf->tx_deferred_start) { 1230 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev); 1231 return -EINVAL; 1232 } 1233 txq->nb_desc = UINT16_MAX; 1234 txq->offloads = tx_conf->offloads; 1235 1236 if (queue_idx >= dev->data->nb_tx_queues) { 1237 rte_errno = EOVERFLOW; 1238 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 1239 (void *)dev, queue_idx, dev->data->nb_tx_queues); 1240 return -rte_errno; 1241 } 1242 1243 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 1244 queue_idx, txq->fqid); 1245 dev->data->tx_queues[queue_idx] = txq; 1246 1247 return 0; 1248 } 1249 1250 static uint32_t 1251 dpaa_dev_rx_queue_count(void *rx_queue) 1252 { 1253 struct qman_fq *rxq = rx_queue; 1254 u32 frm_cnt = 0; 1255 1256 PMD_INIT_FUNC_TRACE(); 1257 1258 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 1259 DPAA_PMD_DEBUG("RX frame count for q(%p) is %u", 1260 rx_queue, frm_cnt); 1261 } 1262 return frm_cnt; 1263 } 1264 1265 static int dpaa_link_down(struct rte_eth_dev *dev) 1266 { 1267 struct fman_if *fif = dev->process_private; 1268 struct __fman_if *__fif; 1269 1270 PMD_INIT_FUNC_TRACE(); 1271 1272 __fif = container_of(fif, struct __fman_if, __if); 1273 1274 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1275 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN); 1276 else 1277 return dpaa_eth_dev_stop(dev); 1278 return 0; 1279 } 1280 1281 static int dpaa_link_up(struct rte_eth_dev *dev) 1282 { 1283 struct fman_if *fif = dev->process_private; 1284 struct __fman_if *__fif; 1285 1286 PMD_INIT_FUNC_TRACE(); 1287 1288 __fif = container_of(fif, struct __fman_if, __if); 1289 1290 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1291 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP); 1292 else 1293 dpaa_eth_dev_start(dev); 1294 return 0; 1295 } 1296 1297 static int 1298 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 1299 struct rte_eth_fc_conf *fc_conf) 1300 { 1301 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1302 struct rte_eth_fc_conf *net_fc; 1303 1304 PMD_INIT_FUNC_TRACE(); 1305 1306 if (!(dpaa_intf->fc_conf)) { 1307 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1308 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1309 if (!dpaa_intf->fc_conf) { 1310 DPAA_PMD_ERR("unable to save flow control info"); 1311 return -ENOMEM; 1312 } 1313 } 1314 net_fc = dpaa_intf->fc_conf; 1315 1316 if (fc_conf->high_water < fc_conf->low_water) { 1317 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 1318 return -EINVAL; 1319 } 1320 1321 if (fc_conf->mode == RTE_FC_NONE) { 1322 return 0; 1323 } else if (fc_conf->mode == RTE_FC_TX_PAUSE || 1324 fc_conf->mode == RTE_FC_FULL) { 1325 fman_if_set_fc_threshold(dev->process_private, 1326 fc_conf->high_water, 1327 fc_conf->low_water, 1328 dpaa_intf->bp_info->bpid); 1329 if (fc_conf->pause_time) 1330 fman_if_set_fc_quanta(dev->process_private, 1331 fc_conf->pause_time); 1332 } 1333 1334 /* Save the information in dpaa device */ 1335 net_fc->pause_time = fc_conf->pause_time; 1336 net_fc->high_water = fc_conf->high_water; 1337 net_fc->low_water = fc_conf->low_water; 1338 net_fc->send_xon = fc_conf->send_xon; 1339 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 1340 net_fc->mode = fc_conf->mode; 1341 net_fc->autoneg = fc_conf->autoneg; 1342 1343 return 0; 1344 } 1345 1346 static int 1347 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 1348 struct rte_eth_fc_conf *fc_conf) 1349 { 1350 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1351 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 1352 int ret; 1353 1354 PMD_INIT_FUNC_TRACE(); 1355 1356 if (net_fc) { 1357 fc_conf->pause_time = net_fc->pause_time; 1358 fc_conf->high_water = net_fc->high_water; 1359 fc_conf->low_water = net_fc->low_water; 1360 fc_conf->send_xon = net_fc->send_xon; 1361 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 1362 fc_conf->mode = net_fc->mode; 1363 fc_conf->autoneg = net_fc->autoneg; 1364 return 0; 1365 } 1366 ret = fman_if_get_fc_threshold(dev->process_private); 1367 if (ret) { 1368 fc_conf->mode = RTE_FC_TX_PAUSE; 1369 fc_conf->pause_time = 1370 fman_if_get_fc_quanta(dev->process_private); 1371 } else { 1372 fc_conf->mode = RTE_FC_NONE; 1373 } 1374 1375 return 0; 1376 } 1377 1378 static int 1379 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 1380 struct rte_ether_addr *addr, 1381 uint32_t index, 1382 __rte_unused uint32_t pool) 1383 { 1384 int ret; 1385 1386 PMD_INIT_FUNC_TRACE(); 1387 1388 ret = fman_if_add_mac_addr(dev->process_private, 1389 addr->addr_bytes, index); 1390 1391 if (ret) 1392 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret); 1393 return 0; 1394 } 1395 1396 static void 1397 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 1398 uint32_t index) 1399 { 1400 PMD_INIT_FUNC_TRACE(); 1401 1402 fman_if_clear_mac_addr(dev->process_private, index); 1403 } 1404 1405 static int 1406 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 1407 struct rte_ether_addr *addr) 1408 { 1409 int ret; 1410 1411 PMD_INIT_FUNC_TRACE(); 1412 1413 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0); 1414 if (ret) 1415 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret); 1416 1417 return ret; 1418 } 1419 1420 static int 1421 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev, 1422 struct rte_eth_rss_conf *rss_conf) 1423 { 1424 struct rte_eth_dev_data *data = dev->data; 1425 struct rte_eth_conf *eth_conf = &data->dev_conf; 1426 1427 PMD_INIT_FUNC_TRACE(); 1428 1429 if (!(default_q || fmc_q)) { 1430 if (dpaa_fm_config(dev, rss_conf->rss_hf)) { 1431 DPAA_PMD_ERR("FM port configuration: Failed\n"); 1432 return -1; 1433 } 1434 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 1435 } else { 1436 DPAA_PMD_ERR("Function not supported\n"); 1437 return -ENOTSUP; 1438 } 1439 return 0; 1440 } 1441 1442 static int 1443 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1444 struct rte_eth_rss_conf *rss_conf) 1445 { 1446 struct rte_eth_dev_data *data = dev->data; 1447 struct rte_eth_conf *eth_conf = &data->dev_conf; 1448 1449 /* dpaa does not support rss_key, so length should be 0*/ 1450 rss_conf->rss_key_len = 0; 1451 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 1452 return 0; 1453 } 1454 1455 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev, 1456 uint16_t queue_id) 1457 { 1458 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1459 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1460 1461 if (!rxq->is_static) 1462 return -EINVAL; 1463 1464 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI); 1465 } 1466 1467 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev, 1468 uint16_t queue_id) 1469 { 1470 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1471 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1472 uint32_t temp; 1473 ssize_t temp1; 1474 1475 if (!rxq->is_static) 1476 return -EINVAL; 1477 1478 qman_fq_portal_irqsource_remove(rxq->qp, ~0); 1479 1480 temp1 = read(rxq->q_fd, &temp, sizeof(temp)); 1481 if (temp1 != sizeof(temp)) 1482 DPAA_PMD_ERR("irq read error"); 1483 1484 qman_fq_portal_thread_irq(rxq->qp); 1485 1486 return 0; 1487 } 1488 1489 static void 1490 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1491 struct rte_eth_rxq_info *qinfo) 1492 { 1493 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1494 struct qman_fq *rxq; 1495 int ret; 1496 1497 rxq = dev->data->rx_queues[queue_id]; 1498 1499 qinfo->mp = dpaa_intf->bp_info->mp; 1500 qinfo->scattered_rx = dev->data->scattered_rx; 1501 qinfo->nb_desc = rxq->nb_desc; 1502 1503 /* Report the HW Rx buffer length to user */ 1504 ret = fman_if_get_maxfrm(dev->process_private); 1505 if (ret > 0) 1506 qinfo->rx_buf_size = ret; 1507 1508 qinfo->conf.rx_free_thresh = 1; 1509 qinfo->conf.rx_drop_en = 1; 1510 qinfo->conf.rx_deferred_start = 0; 1511 qinfo->conf.offloads = rxq->offloads; 1512 } 1513 1514 static void 1515 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1516 struct rte_eth_txq_info *qinfo) 1517 { 1518 struct qman_fq *txq; 1519 1520 txq = dev->data->tx_queues[queue_id]; 1521 1522 qinfo->nb_desc = txq->nb_desc; 1523 qinfo->conf.tx_thresh.pthresh = 0; 1524 qinfo->conf.tx_thresh.hthresh = 0; 1525 qinfo->conf.tx_thresh.wthresh = 0; 1526 1527 qinfo->conf.tx_free_thresh = 0; 1528 qinfo->conf.tx_rs_thresh = 0; 1529 qinfo->conf.offloads = txq->offloads; 1530 qinfo->conf.tx_deferred_start = 0; 1531 } 1532 1533 static struct eth_dev_ops dpaa_devops = { 1534 .dev_configure = dpaa_eth_dev_configure, 1535 .dev_start = dpaa_eth_dev_start, 1536 .dev_stop = dpaa_eth_dev_stop, 1537 .dev_close = dpaa_eth_dev_close, 1538 .dev_infos_get = dpaa_eth_dev_info, 1539 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 1540 1541 .rx_queue_setup = dpaa_eth_rx_queue_setup, 1542 .tx_queue_setup = dpaa_eth_tx_queue_setup, 1543 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get, 1544 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get, 1545 .rxq_info_get = dpaa_rxq_info_get, 1546 .txq_info_get = dpaa_txq_info_get, 1547 1548 .flow_ctrl_get = dpaa_flow_ctrl_get, 1549 .flow_ctrl_set = dpaa_flow_ctrl_set, 1550 1551 .link_update = dpaa_eth_link_update, 1552 .stats_get = dpaa_eth_stats_get, 1553 .xstats_get = dpaa_dev_xstats_get, 1554 .xstats_get_by_id = dpaa_xstats_get_by_id, 1555 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1556 .xstats_get_names = dpaa_xstats_get_names, 1557 .xstats_reset = dpaa_eth_stats_reset, 1558 .stats_reset = dpaa_eth_stats_reset, 1559 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1560 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1561 .allmulticast_enable = dpaa_eth_multicast_enable, 1562 .allmulticast_disable = dpaa_eth_multicast_disable, 1563 .mtu_set = dpaa_mtu_set, 1564 .dev_set_link_down = dpaa_link_down, 1565 .dev_set_link_up = dpaa_link_up, 1566 .mac_addr_add = dpaa_dev_add_mac_addr, 1567 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1568 .mac_addr_set = dpaa_dev_set_mac_addr, 1569 1570 .fw_version_get = dpaa_fw_version_get, 1571 1572 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable, 1573 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable, 1574 .rss_hash_update = dpaa_dev_rss_hash_update, 1575 .rss_hash_conf_get = dpaa_dev_rss_hash_conf_get, 1576 }; 1577 1578 static bool 1579 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1580 { 1581 if (strcmp(dev->device->driver->name, 1582 drv->driver.name)) 1583 return false; 1584 1585 return true; 1586 } 1587 1588 static bool 1589 is_dpaa_supported(struct rte_eth_dev *dev) 1590 { 1591 return is_device_supported(dev, &rte_dpaa_pmd); 1592 } 1593 1594 int 1595 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on) 1596 { 1597 struct rte_eth_dev *dev; 1598 1599 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1600 1601 dev = &rte_eth_devices[port]; 1602 1603 if (!is_dpaa_supported(dev)) 1604 return -ENOTSUP; 1605 1606 if (on) 1607 fman_if_loopback_enable(dev->process_private); 1608 else 1609 fman_if_loopback_disable(dev->process_private); 1610 1611 return 0; 1612 } 1613 1614 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf, 1615 struct fman_if *fman_intf) 1616 { 1617 struct rte_eth_fc_conf *fc_conf; 1618 int ret; 1619 1620 PMD_INIT_FUNC_TRACE(); 1621 1622 if (!(dpaa_intf->fc_conf)) { 1623 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1624 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1625 if (!dpaa_intf->fc_conf) { 1626 DPAA_PMD_ERR("unable to save flow control info"); 1627 return -ENOMEM; 1628 } 1629 } 1630 fc_conf = dpaa_intf->fc_conf; 1631 ret = fman_if_get_fc_threshold(fman_intf); 1632 if (ret) { 1633 fc_conf->mode = RTE_FC_TX_PAUSE; 1634 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf); 1635 } else { 1636 fc_conf->mode = RTE_FC_NONE; 1637 } 1638 1639 return 0; 1640 } 1641 1642 /* Initialise an Rx FQ */ 1643 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1644 uint32_t fqid) 1645 { 1646 struct qm_mcc_initfq opts = {0}; 1647 int ret; 1648 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1649 struct qm_mcc_initcgr cgr_opts = { 1650 .we_mask = QM_CGR_WE_CS_THRES | 1651 QM_CGR_WE_CSTD_EN | 1652 QM_CGR_WE_MODE, 1653 .cgr = { 1654 .cstd_en = QM_CGR_EN, 1655 .mode = QMAN_CGR_MODE_FRAME 1656 } 1657 }; 1658 1659 if (fmc_q || default_q) { 1660 ret = qman_reserve_fqid(fqid); 1661 if (ret) { 1662 DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d", 1663 fqid, ret); 1664 return -EINVAL; 1665 } 1666 } 1667 1668 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1669 ret = qman_create_fq(fqid, flags, fq); 1670 if (ret) { 1671 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1672 fqid, ret); 1673 return ret; 1674 } 1675 fq->is_static = false; 1676 1677 dpaa_poll_queue_default_config(&opts); 1678 1679 if (cgr_rx) { 1680 /* Enable tail drop with cgr on this queue */ 1681 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1682 cgr_rx->cb = NULL; 1683 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1684 &cgr_opts); 1685 if (ret) { 1686 DPAA_PMD_WARN( 1687 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1688 fq->fqid, ret); 1689 goto without_cgr; 1690 } 1691 opts.we_mask |= QM_INITFQ_WE_CGID; 1692 opts.fqd.cgid = cgr_rx->cgrid; 1693 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1694 } 1695 without_cgr: 1696 ret = qman_init_fq(fq, 0, &opts); 1697 if (ret) 1698 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1699 return ret; 1700 } 1701 1702 /* Initialise a Tx FQ */ 1703 static int dpaa_tx_queue_init(struct qman_fq *fq, 1704 struct fman_if *fman_intf, 1705 struct qman_cgr *cgr_tx) 1706 { 1707 struct qm_mcc_initfq opts = {0}; 1708 struct qm_mcc_initcgr cgr_opts = { 1709 .we_mask = QM_CGR_WE_CS_THRES | 1710 QM_CGR_WE_CSTD_EN | 1711 QM_CGR_WE_MODE, 1712 .cgr = { 1713 .cstd_en = QM_CGR_EN, 1714 .mode = QMAN_CGR_MODE_FRAME 1715 } 1716 }; 1717 int ret; 1718 1719 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1720 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1721 if (ret) { 1722 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1723 return ret; 1724 } 1725 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1726 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1727 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1728 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1729 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1730 opts.fqd.context_b = 0; 1731 /* no tx-confirmation */ 1732 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1733 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1734 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1735 1736 if (cgr_tx) { 1737 /* Enable tail drop with cgr on this queue */ 1738 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, 1739 td_tx_threshold, 0); 1740 cgr_tx->cb = NULL; 1741 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT, 1742 &cgr_opts); 1743 if (ret) { 1744 DPAA_PMD_WARN( 1745 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1746 fq->fqid, ret); 1747 goto without_cgr; 1748 } 1749 opts.we_mask |= QM_INITFQ_WE_CGID; 1750 opts.fqd.cgid = cgr_tx->cgrid; 1751 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1752 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n", 1753 td_tx_threshold); 1754 } 1755 without_cgr: 1756 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1757 if (ret) 1758 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 1759 return ret; 1760 } 1761 1762 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1763 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1764 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1765 { 1766 struct qm_mcc_initfq opts = {0}; 1767 int ret; 1768 1769 PMD_INIT_FUNC_TRACE(); 1770 1771 ret = qman_reserve_fqid(fqid); 1772 if (ret) { 1773 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1774 fqid, ret); 1775 return -EINVAL; 1776 } 1777 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1778 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1779 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1780 if (ret) { 1781 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1782 fqid, ret); 1783 return ret; 1784 } 1785 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1786 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1787 ret = qman_init_fq(fq, 0, &opts); 1788 if (ret) 1789 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1790 fqid, ret); 1791 return ret; 1792 } 1793 #endif 1794 1795 /* Initialise a network interface */ 1796 static int 1797 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev) 1798 { 1799 struct rte_dpaa_device *dpaa_device; 1800 struct fm_eth_port_cfg *cfg; 1801 struct dpaa_if *dpaa_intf; 1802 struct fman_if *fman_intf; 1803 int dev_id; 1804 1805 PMD_INIT_FUNC_TRACE(); 1806 1807 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1808 dev_id = dpaa_device->id.dev_id; 1809 cfg = dpaa_get_eth_port_cfg(dev_id); 1810 fman_intf = cfg->fman_if; 1811 eth_dev->process_private = fman_intf; 1812 1813 /* Plugging of UCODE burst API not supported in Secondary */ 1814 dpaa_intf = eth_dev->data->dev_private; 1815 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1816 if (dpaa_intf->cgr_tx) 1817 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 1818 else 1819 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 1820 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 1821 qman_set_fq_lookup_table( 1822 dpaa_intf->rx_queues->qman_fq_lookup_table); 1823 #endif 1824 1825 return 0; 1826 } 1827 1828 /* Initialise a network interface */ 1829 static int 1830 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1831 { 1832 int num_rx_fqs, fqid; 1833 int loop, ret = 0; 1834 int dev_id; 1835 struct rte_dpaa_device *dpaa_device; 1836 struct dpaa_if *dpaa_intf; 1837 struct fm_eth_port_cfg *cfg; 1838 struct fman_if *fman_intf; 1839 struct fman_if_bpool *bp, *tmp_bp; 1840 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1841 uint32_t cgrid_tx[MAX_DPAA_CORES]; 1842 uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES]; 1843 int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES]; 1844 int8_t vsp_id = -1; 1845 1846 PMD_INIT_FUNC_TRACE(); 1847 1848 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1849 dev_id = dpaa_device->id.dev_id; 1850 dpaa_intf = eth_dev->data->dev_private; 1851 cfg = dpaa_get_eth_port_cfg(dev_id); 1852 fman_intf = cfg->fman_if; 1853 1854 dpaa_intf->name = dpaa_device->name; 1855 1856 /* save fman_if & cfg in the interface struture */ 1857 eth_dev->process_private = fman_intf; 1858 dpaa_intf->ifid = dev_id; 1859 dpaa_intf->cfg = cfg; 1860 1861 memset((char *)dev_rx_fqids, 0, 1862 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES); 1863 1864 memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES); 1865 1866 /* Initialize Rx FQ's */ 1867 if (default_q) { 1868 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1869 } else if (fmc_q) { 1870 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids, 1871 dev_vspids, 1872 DPAA_MAX_NUM_PCD_QUEUES); 1873 if (num_rx_fqs < 0) { 1874 DPAA_PMD_ERR("%s FMC initializes failed!", 1875 dpaa_intf->name); 1876 goto free_rx; 1877 } 1878 if (!num_rx_fqs) { 1879 DPAA_PMD_WARN("%s is not configured by FMC.", 1880 dpaa_intf->name); 1881 } 1882 } else { 1883 /* FMCLESS mode, load balance to multiple cores.*/ 1884 num_rx_fqs = rte_lcore_count(); 1885 } 1886 1887 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1888 * queues. 1889 */ 1890 if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1891 DPAA_PMD_ERR("Invalid number of RX queues\n"); 1892 return -EINVAL; 1893 } 1894 1895 if (num_rx_fqs > 0) { 1896 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1897 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1898 if (!dpaa_intf->rx_queues) { 1899 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n"); 1900 return -ENOMEM; 1901 } 1902 } else { 1903 dpaa_intf->rx_queues = NULL; 1904 } 1905 1906 memset(cgrid, 0, sizeof(cgrid)); 1907 memset(cgrid_tx, 0, sizeof(cgrid_tx)); 1908 1909 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means 1910 * Tx tail drop is disabled. 1911 */ 1912 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) { 1913 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD")); 1914 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u", 1915 td_tx_threshold); 1916 /* if a very large value is being configured */ 1917 if (td_tx_threshold > UINT16_MAX) 1918 td_tx_threshold = CGR_RX_PERFQ_THRESH; 1919 } 1920 1921 /* If congestion control is enabled globally*/ 1922 if (num_rx_fqs > 0 && td_threshold) { 1923 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1924 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1925 if (!dpaa_intf->cgr_rx) { 1926 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n"); 1927 ret = -ENOMEM; 1928 goto free_rx; 1929 } 1930 1931 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1932 if (ret != num_rx_fqs) { 1933 DPAA_PMD_WARN("insufficient CGRIDs available"); 1934 ret = -EINVAL; 1935 goto free_rx; 1936 } 1937 } else { 1938 dpaa_intf->cgr_rx = NULL; 1939 } 1940 1941 if (!fmc_q && !default_q) { 1942 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs, 1943 num_rx_fqs, 0); 1944 if (ret < 0) { 1945 DPAA_PMD_ERR("Failed to alloc rx fqid's\n"); 1946 goto free_rx; 1947 } 1948 } 1949 1950 for (loop = 0; loop < num_rx_fqs; loop++) { 1951 if (default_q) 1952 fqid = cfg->rx_def; 1953 else 1954 fqid = dev_rx_fqids[loop]; 1955 1956 vsp_id = dev_vspids[loop]; 1957 1958 if (dpaa_intf->cgr_rx) 1959 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 1960 1961 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 1962 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 1963 fqid); 1964 if (ret) 1965 goto free_rx; 1966 dpaa_intf->rx_queues[loop].vsp_id = vsp_id; 1967 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 1968 } 1969 dpaa_intf->nb_rx_queues = num_rx_fqs; 1970 1971 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 1972 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 1973 MAX_DPAA_CORES, MAX_CACHELINE); 1974 if (!dpaa_intf->tx_queues) { 1975 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n"); 1976 ret = -ENOMEM; 1977 goto free_rx; 1978 } 1979 1980 /* If congestion control is enabled globally*/ 1981 if (td_tx_threshold) { 1982 dpaa_intf->cgr_tx = rte_zmalloc(NULL, 1983 sizeof(struct qman_cgr) * MAX_DPAA_CORES, 1984 MAX_CACHELINE); 1985 if (!dpaa_intf->cgr_tx) { 1986 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n"); 1987 ret = -ENOMEM; 1988 goto free_rx; 1989 } 1990 1991 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES, 1992 1, 0); 1993 if (ret != MAX_DPAA_CORES) { 1994 DPAA_PMD_WARN("insufficient CGRIDs available"); 1995 ret = -EINVAL; 1996 goto free_rx; 1997 } 1998 } else { 1999 dpaa_intf->cgr_tx = NULL; 2000 } 2001 2002 2003 for (loop = 0; loop < MAX_DPAA_CORES; loop++) { 2004 if (dpaa_intf->cgr_tx) 2005 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop]; 2006 2007 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 2008 fman_intf, 2009 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL); 2010 if (ret) 2011 goto free_tx; 2012 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 2013 } 2014 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES; 2015 2016 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 2017 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2018 [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 2019 if (ret) { 2020 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!"); 2021 goto free_tx; 2022 } 2023 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 2024 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2025 [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 2026 if (ret) { 2027 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!"); 2028 goto free_tx; 2029 } 2030 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 2031 #endif 2032 2033 DPAA_PMD_DEBUG("All frame queues created"); 2034 2035 /* Get the initial configuration for flow control */ 2036 dpaa_fc_set_default(dpaa_intf, fman_intf); 2037 2038 /* reset bpool list, initialize bpool dynamically */ 2039 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 2040 list_del(&bp->node); 2041 rte_free(bp); 2042 } 2043 2044 /* Populate ethdev structure */ 2045 eth_dev->dev_ops = &dpaa_devops; 2046 eth_dev->rx_queue_count = dpaa_dev_rx_queue_count; 2047 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 2048 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 2049 2050 /* Allocate memory for storing MAC addresses */ 2051 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 2052 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 2053 if (eth_dev->data->mac_addrs == NULL) { 2054 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 2055 "store MAC addresses", 2056 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 2057 ret = -ENOMEM; 2058 goto free_tx; 2059 } 2060 2061 /* copy the primary mac address */ 2062 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 2063 2064 RTE_LOG(INFO, PMD, "net: dpaa: %s: " RTE_ETHER_ADDR_PRT_FMT "\n", 2065 dpaa_device->name, RTE_ETHER_ADDR_BYTES(&fman_intf->mac_addr)); 2066 2067 if (!fman_intf->is_shared_mac) { 2068 /* Configure error packet handling */ 2069 fman_if_receive_rx_errors(fman_intf, 2070 FM_FD_RX_STATUS_ERR_MASK); 2071 /* Disable RX mode */ 2072 fman_if_disable_rx(fman_intf); 2073 /* Disable promiscuous mode */ 2074 fman_if_promiscuous_disable(fman_intf); 2075 /* Disable multicast */ 2076 fman_if_reset_mcast_filter_table(fman_intf); 2077 /* Reset interface statistics */ 2078 fman_if_stats_reset(fman_intf); 2079 /* Disable SG by default */ 2080 fman_if_set_sg(fman_intf, 0); 2081 fman_if_set_maxfrm(fman_intf, 2082 RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE); 2083 } 2084 2085 return 0; 2086 2087 free_tx: 2088 rte_free(dpaa_intf->tx_queues); 2089 dpaa_intf->tx_queues = NULL; 2090 dpaa_intf->nb_tx_queues = 0; 2091 2092 free_rx: 2093 rte_free(dpaa_intf->cgr_rx); 2094 rte_free(dpaa_intf->cgr_tx); 2095 rte_free(dpaa_intf->rx_queues); 2096 dpaa_intf->rx_queues = NULL; 2097 dpaa_intf->nb_rx_queues = 0; 2098 return ret; 2099 } 2100 2101 static int 2102 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv, 2103 struct rte_dpaa_device *dpaa_dev) 2104 { 2105 int diag; 2106 int ret; 2107 struct rte_eth_dev *eth_dev; 2108 2109 PMD_INIT_FUNC_TRACE(); 2110 2111 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > 2112 RTE_PKTMBUF_HEADROOM) { 2113 DPAA_PMD_ERR( 2114 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)", 2115 RTE_PKTMBUF_HEADROOM, 2116 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE); 2117 2118 return -1; 2119 } 2120 2121 /* In case of secondary process, the device is already configured 2122 * and no further action is required, except portal initialization 2123 * and verifying secondary attachment to port name. 2124 */ 2125 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2126 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 2127 if (!eth_dev) 2128 return -ENOMEM; 2129 eth_dev->device = &dpaa_dev->device; 2130 eth_dev->dev_ops = &dpaa_devops; 2131 2132 ret = dpaa_dev_init_secondary(eth_dev); 2133 if (ret != 0) { 2134 RTE_LOG(ERR, PMD, "secondary dev init failed\n"); 2135 return ret; 2136 } 2137 2138 rte_eth_dev_probing_finish(eth_dev); 2139 return 0; 2140 } 2141 2142 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) { 2143 if (access("/tmp/fmc.bin", F_OK) == -1) { 2144 DPAA_PMD_INFO("* FMC not configured.Enabling default mode"); 2145 default_q = 1; 2146 } 2147 2148 if (!(default_q || fmc_q)) { 2149 if (dpaa_fm_init()) { 2150 DPAA_PMD_ERR("FM init failed\n"); 2151 return -1; 2152 } 2153 } 2154 2155 /* disabling the default push mode for LS1043 */ 2156 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 2157 dpaa_push_mode_max_queue = 0; 2158 2159 /* if push mode queues to be enabled. Currenly we are allowing 2160 * only one queue per thread. 2161 */ 2162 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 2163 dpaa_push_mode_max_queue = 2164 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 2165 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 2166 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 2167 } 2168 2169 is_global_init = 1; 2170 } 2171 2172 if (unlikely(!DPAA_PER_LCORE_PORTAL)) { 2173 ret = rte_dpaa_portal_init((void *)1); 2174 if (ret) { 2175 DPAA_PMD_ERR("Unable to initialize portal"); 2176 return ret; 2177 } 2178 } 2179 2180 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 2181 if (!eth_dev) 2182 return -ENOMEM; 2183 2184 eth_dev->data->dev_private = 2185 rte_zmalloc("ethdev private structure", 2186 sizeof(struct dpaa_if), 2187 RTE_CACHE_LINE_SIZE); 2188 if (!eth_dev->data->dev_private) { 2189 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 2190 rte_eth_dev_release_port(eth_dev); 2191 return -ENOMEM; 2192 } 2193 2194 eth_dev->device = &dpaa_dev->device; 2195 dpaa_dev->eth_dev = eth_dev; 2196 2197 qman_ern_register_cb(dpaa_free_mbuf); 2198 2199 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC) 2200 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2201 2202 /* Invoke PMD device initialization function */ 2203 diag = dpaa_dev_init(eth_dev); 2204 if (diag == 0) { 2205 rte_eth_dev_probing_finish(eth_dev); 2206 return 0; 2207 } 2208 2209 rte_eth_dev_release_port(eth_dev); 2210 return diag; 2211 } 2212 2213 static int 2214 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 2215 { 2216 struct rte_eth_dev *eth_dev; 2217 int ret; 2218 2219 PMD_INIT_FUNC_TRACE(); 2220 2221 eth_dev = dpaa_dev->eth_dev; 2222 dpaa_eth_dev_close(eth_dev); 2223 ret = rte_eth_dev_release_port(eth_dev); 2224 2225 return ret; 2226 } 2227 2228 static void __attribute__((destructor(102))) dpaa_finish(void) 2229 { 2230 /* For secondary, primary will do all the cleanup */ 2231 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2232 return; 2233 2234 if (!(default_q || fmc_q)) { 2235 unsigned int i; 2236 2237 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 2238 if (rte_eth_devices[i].dev_ops == &dpaa_devops) { 2239 struct rte_eth_dev *dev = &rte_eth_devices[i]; 2240 struct dpaa_if *dpaa_intf = 2241 dev->data->dev_private; 2242 struct fman_if *fif = 2243 dev->process_private; 2244 if (dpaa_intf->port_handle) 2245 if (dpaa_fm_deconfig(dpaa_intf, fif)) 2246 DPAA_PMD_WARN("DPAA FM " 2247 "deconfig failed\n"); 2248 if (fif->num_profiles) { 2249 if (dpaa_port_vsp_cleanup(dpaa_intf, 2250 fif)) 2251 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n"); 2252 } 2253 } 2254 } 2255 if (is_global_init) 2256 if (dpaa_fm_term()) 2257 DPAA_PMD_WARN("DPAA FM term failed\n"); 2258 2259 is_global_init = 0; 2260 2261 DPAA_PMD_INFO("DPAA fman cleaned up"); 2262 } 2263 } 2264 2265 static struct rte_dpaa_driver rte_dpaa_pmd = { 2266 .drv_flags = RTE_DPAA_DRV_INTR_LSC, 2267 .drv_type = FSL_DPAA_ETH, 2268 .probe = rte_dpaa_probe, 2269 .remove = rte_dpaa_remove, 2270 }; 2271 2272 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 2273 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE); 2274