1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_atomic.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_memory.h> 27 #include <rte_tailq.h> 28 #include <rte_eal.h> 29 #include <rte_alarm.h> 30 #include <rte_ether.h> 31 #include <rte_ethdev_driver.h> 32 #include <rte_ethdev_pci.h> 33 #include <rte_malloc.h> 34 #include <rte_random.h> 35 #include <rte_dev.h> 36 37 #include "cxgbe.h" 38 #include "cxgbe_pfvf.h" 39 #include "cxgbe_flow.h" 40 41 int cxgbe_logtype; 42 43 /* 44 * Macros needed to support the PCI Device ID Table ... 45 */ 46 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 47 static const struct rte_pci_id cxgb4_pci_tbl[] = { 48 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 49 50 #define PCI_VENDOR_ID_CHELSIO 0x1425 51 52 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 54 55 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 56 { .vendor_id = 0, } \ 57 } 58 59 /* 60 *... and the PCI ID Table itself ... 61 */ 62 #include "base/t4_pci_id_tbl.h" 63 64 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 65 uint16_t nb_pkts) 66 { 67 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 68 uint16_t pkts_sent, pkts_remain; 69 uint16_t total_sent = 0; 70 int ret = 0; 71 72 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n", 73 __func__, txq, tx_pkts, nb_pkts); 74 75 t4_os_lock(&txq->txq_lock); 76 /* free up desc from already completed tx */ 77 reclaim_completed_tx(&txq->q); 78 while (total_sent < nb_pkts) { 79 pkts_remain = nb_pkts - total_sent; 80 81 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 82 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent], 83 nb_pkts); 84 if (ret < 0) 85 break; 86 } 87 if (!pkts_sent) 88 break; 89 total_sent += pkts_sent; 90 /* reclaim as much as possible */ 91 reclaim_completed_tx(&txq->q); 92 } 93 94 t4_os_unlock(&txq->txq_lock); 95 return total_sent; 96 } 97 98 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 99 uint16_t nb_pkts) 100 { 101 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 102 unsigned int work_done; 103 104 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n", 105 __func__, rxq->rspq.cntxt_id, nb_pkts); 106 107 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 108 dev_err(adapter, "error in cxgbe poll\n"); 109 110 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done); 111 return work_done; 112 } 113 114 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 115 struct rte_eth_dev_info *device_info) 116 { 117 struct port_info *pi = eth_dev->data->dev_private; 118 struct adapter *adapter = pi->adapter; 119 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports; 120 121 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 122 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 123 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 124 .nb_align = 1, 125 }; 126 127 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 128 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 129 device_info->max_rx_queues = max_queues; 130 device_info->max_tx_queues = max_queues; 131 device_info->max_mac_addrs = 1; 132 /* XXX: For now we support one MAC/port */ 133 device_info->max_vfs = adapter->params.arch.vfcount; 134 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 135 136 device_info->rx_queue_offload_capa = 0UL; 137 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 138 139 device_info->tx_queue_offload_capa = 0UL; 140 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 141 142 device_info->reta_size = pi->rss_size; 143 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 144 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 145 146 device_info->rx_desc_lim = cxgbe_desc_lim; 147 device_info->tx_desc_lim = cxgbe_desc_lim; 148 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 149 } 150 151 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 152 { 153 struct port_info *pi = eth_dev->data->dev_private; 154 struct adapter *adapter = pi->adapter; 155 156 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 157 1, -1, 1, -1, false); 158 } 159 160 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 161 { 162 struct port_info *pi = eth_dev->data->dev_private; 163 struct adapter *adapter = pi->adapter; 164 165 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 166 0, -1, 1, -1, false); 167 } 168 169 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 170 { 171 struct port_info *pi = eth_dev->data->dev_private; 172 struct adapter *adapter = pi->adapter; 173 174 /* TODO: address filters ?? */ 175 176 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 177 -1, 1, 1, -1, false); 178 } 179 180 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 181 { 182 struct port_info *pi = eth_dev->data->dev_private; 183 struct adapter *adapter = pi->adapter; 184 185 /* TODO: address filters ?? */ 186 187 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 188 -1, 0, 1, -1, false); 189 } 190 191 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 192 int wait_to_complete) 193 { 194 struct port_info *pi = eth_dev->data->dev_private; 195 struct adapter *adapter = pi->adapter; 196 struct sge *s = &adapter->sge; 197 struct rte_eth_link new_link = { 0 }; 198 unsigned int i, work_done, budget = 32; 199 u8 old_link = pi->link_cfg.link_ok; 200 201 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { 202 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 203 204 /* Exit if link status changed or always forced up */ 205 if (pi->link_cfg.link_ok != old_link || 206 cxgbe_force_linkup(adapter)) 207 break; 208 209 if (!wait_to_complete) 210 break; 211 212 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); 213 } 214 215 new_link.link_status = cxgbe_force_linkup(adapter) ? 216 ETH_LINK_UP : pi->link_cfg.link_ok; 217 new_link.link_autoneg = pi->link_cfg.autoneg; 218 new_link.link_duplex = ETH_LINK_FULL_DUPLEX; 219 new_link.link_speed = pi->link_cfg.speed; 220 221 return rte_eth_linkstatus_set(eth_dev, &new_link); 222 } 223 224 /** 225 * Set device link up. 226 */ 227 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) 228 { 229 struct port_info *pi = dev->data->dev_private; 230 struct adapter *adapter = pi->adapter; 231 unsigned int work_done, budget = 32; 232 struct sge *s = &adapter->sge; 233 int ret; 234 235 /* Flush all link events */ 236 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 237 238 /* If link already up, nothing to do */ 239 if (pi->link_cfg.link_ok) 240 return 0; 241 242 ret = cxgbe_set_link_status(pi, true); 243 if (ret) 244 return ret; 245 246 cxgbe_dev_link_update(dev, 1); 247 return 0; 248 } 249 250 /** 251 * Set device link down. 252 */ 253 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) 254 { 255 struct port_info *pi = dev->data->dev_private; 256 struct adapter *adapter = pi->adapter; 257 unsigned int work_done, budget = 32; 258 struct sge *s = &adapter->sge; 259 int ret; 260 261 /* Flush all link events */ 262 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 263 264 /* If link already down, nothing to do */ 265 if (!pi->link_cfg.link_ok) 266 return 0; 267 268 ret = cxgbe_set_link_status(pi, false); 269 if (ret) 270 return ret; 271 272 cxgbe_dev_link_update(dev, 0); 273 return 0; 274 } 275 276 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 277 { 278 struct port_info *pi = eth_dev->data->dev_private; 279 struct adapter *adapter = pi->adapter; 280 struct rte_eth_dev_info dev_info; 281 int err; 282 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 283 284 cxgbe_dev_info_get(eth_dev, &dev_info); 285 286 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 287 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen) 288 return -EINVAL; 289 290 /* set to jumbo mode if needed */ 291 if (new_mtu > RTE_ETHER_MAX_LEN) 292 eth_dev->data->dev_conf.rxmode.offloads |= 293 DEV_RX_OFFLOAD_JUMBO_FRAME; 294 else 295 eth_dev->data->dev_conf.rxmode.offloads &= 296 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 297 298 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 299 -1, -1, true); 300 if (!err) 301 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu; 302 303 return err; 304 } 305 306 /* 307 * Stop device. 308 */ 309 void cxgbe_dev_close(struct rte_eth_dev *eth_dev) 310 { 311 struct port_info *pi = eth_dev->data->dev_private; 312 struct adapter *adapter = pi->adapter; 313 314 CXGBE_FUNC_TRACE(); 315 316 if (!(adapter->flags & FULL_INIT_DONE)) 317 return; 318 319 cxgbe_down(pi); 320 321 /* 322 * We clear queues only if both tx and rx path of the port 323 * have been disabled 324 */ 325 t4_sge_eth_clear_queues(pi); 326 } 327 328 /* Start the device. 329 * It returns 0 on success. 330 */ 331 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 332 { 333 struct port_info *pi = eth_dev->data->dev_private; 334 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; 335 struct adapter *adapter = pi->adapter; 336 int err = 0, i; 337 338 CXGBE_FUNC_TRACE(); 339 340 /* 341 * If we don't have a connection to the firmware there's nothing we 342 * can do. 343 */ 344 if (!(adapter->flags & FW_OK)) { 345 err = -ENXIO; 346 goto out; 347 } 348 349 if (!(adapter->flags & FULL_INIT_DONE)) { 350 err = cxgbe_up(adapter); 351 if (err < 0) 352 goto out; 353 } 354 355 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) 356 eth_dev->data->scattered_rx = 1; 357 else 358 eth_dev->data->scattered_rx = 0; 359 360 cxgbe_enable_rx_queues(pi); 361 362 err = cxgbe_setup_rss(pi); 363 if (err) 364 goto out; 365 366 for (i = 0; i < pi->n_tx_qsets; i++) { 367 err = cxgbe_dev_tx_queue_start(eth_dev, i); 368 if (err) 369 goto out; 370 } 371 372 for (i = 0; i < pi->n_rx_qsets; i++) { 373 err = cxgbe_dev_rx_queue_start(eth_dev, i); 374 if (err) 375 goto out; 376 } 377 378 err = cxgbe_link_start(pi); 379 if (err) 380 goto out; 381 382 out: 383 return err; 384 } 385 386 /* 387 * Stop device: disable rx and tx functions to allow for reconfiguring. 388 */ 389 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 390 { 391 struct port_info *pi = eth_dev->data->dev_private; 392 struct adapter *adapter = pi->adapter; 393 394 CXGBE_FUNC_TRACE(); 395 396 if (!(adapter->flags & FULL_INIT_DONE)) 397 return; 398 399 cxgbe_down(pi); 400 401 /* 402 * We clear queues only if both tx and rx path of the port 403 * have been disabled 404 */ 405 t4_sge_eth_clear_queues(pi); 406 eth_dev->data->scattered_rx = 0; 407 } 408 409 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 410 { 411 struct port_info *pi = eth_dev->data->dev_private; 412 struct adapter *adapter = pi->adapter; 413 int err; 414 415 CXGBE_FUNC_TRACE(); 416 417 if (!(adapter->flags & FW_QUEUE_BOUND)) { 418 err = cxgbe_setup_sge_fwevtq(adapter); 419 if (err) 420 return err; 421 adapter->flags |= FW_QUEUE_BOUND; 422 if (is_pf4(adapter)) { 423 err = cxgbe_setup_sge_ctrl_txq(adapter); 424 if (err) 425 return err; 426 } 427 } 428 429 err = cxgbe_cfg_queue_count(eth_dev); 430 if (err) 431 return err; 432 433 return 0; 434 } 435 436 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 437 { 438 int ret; 439 struct sge_eth_txq *txq = (struct sge_eth_txq *) 440 (eth_dev->data->tx_queues[tx_queue_id]); 441 442 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 443 444 ret = t4_sge_eth_txq_start(txq); 445 if (ret == 0) 446 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 447 448 return ret; 449 } 450 451 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 452 { 453 int ret; 454 struct sge_eth_txq *txq = (struct sge_eth_txq *) 455 (eth_dev->data->tx_queues[tx_queue_id]); 456 457 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 458 459 ret = t4_sge_eth_txq_stop(txq); 460 if (ret == 0) 461 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 462 463 return ret; 464 } 465 466 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 467 uint16_t queue_idx, uint16_t nb_desc, 468 unsigned int socket_id, 469 const struct rte_eth_txconf *tx_conf __rte_unused) 470 { 471 struct port_info *pi = eth_dev->data->dev_private; 472 struct adapter *adapter = pi->adapter; 473 struct sge *s = &adapter->sge; 474 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx]; 475 int err = 0; 476 unsigned int temp_nb_desc; 477 478 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 479 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 480 socket_id, pi->first_qset); 481 482 /* Free up the existing queue */ 483 if (eth_dev->data->tx_queues[queue_idx]) { 484 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]); 485 eth_dev->data->tx_queues[queue_idx] = NULL; 486 } 487 488 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 489 490 /* Sanity Checking 491 * 492 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 493 */ 494 temp_nb_desc = nb_desc; 495 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 496 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 497 __func__, CXGBE_MIN_RING_DESC_SIZE, 498 CXGBE_DEFAULT_TX_DESC_SIZE); 499 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 500 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 501 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 502 __func__, CXGBE_MIN_RING_DESC_SIZE, 503 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 504 return -(EINVAL); 505 } 506 507 txq->q.size = temp_nb_desc; 508 509 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 510 s->fw_evtq.cntxt_id, socket_id); 511 512 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 513 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 514 return err; 515 } 516 517 void cxgbe_dev_tx_queue_release(void *q) 518 { 519 struct sge_eth_txq *txq = (struct sge_eth_txq *)q; 520 521 if (txq) { 522 struct port_info *pi = (struct port_info *) 523 (txq->eth_dev->data->dev_private); 524 struct adapter *adap = pi->adapter; 525 526 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 527 __func__, pi->port_id, txq->q.cntxt_id); 528 529 t4_sge_eth_txq_release(adap, txq); 530 } 531 } 532 533 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 534 { 535 int ret; 536 struct port_info *pi = eth_dev->data->dev_private; 537 struct adapter *adap = pi->adapter; 538 struct sge_rspq *q; 539 540 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 541 __func__, pi->port_id, rx_queue_id); 542 543 q = eth_dev->data->rx_queues[rx_queue_id]; 544 545 ret = t4_sge_eth_rxq_start(adap, q); 546 if (ret == 0) 547 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 548 549 return ret; 550 } 551 552 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 553 { 554 int ret; 555 struct port_info *pi = eth_dev->data->dev_private; 556 struct adapter *adap = pi->adapter; 557 struct sge_rspq *q; 558 559 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 560 __func__, pi->port_id, rx_queue_id); 561 562 q = eth_dev->data->rx_queues[rx_queue_id]; 563 ret = t4_sge_eth_rxq_stop(adap, q); 564 if (ret == 0) 565 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 566 567 return ret; 568 } 569 570 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 571 uint16_t queue_idx, uint16_t nb_desc, 572 unsigned int socket_id, 573 const struct rte_eth_rxconf *rx_conf __rte_unused, 574 struct rte_mempool *mp) 575 { 576 struct port_info *pi = eth_dev->data->dev_private; 577 struct adapter *adapter = pi->adapter; 578 struct sge *s = &adapter->sge; 579 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx]; 580 int err = 0; 581 int msi_idx = 0; 582 unsigned int temp_nb_desc; 583 struct rte_eth_dev_info dev_info; 584 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 585 586 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 587 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 588 socket_id, mp); 589 590 cxgbe_dev_info_get(eth_dev, &dev_info); 591 592 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 593 if ((pkt_len < dev_info.min_rx_bufsize) || 594 (pkt_len > dev_info.max_rx_pktlen)) { 595 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 596 __func__, dev_info.min_rx_bufsize, 597 dev_info.max_rx_pktlen); 598 return -EINVAL; 599 } 600 601 /* Free up the existing queue */ 602 if (eth_dev->data->rx_queues[queue_idx]) { 603 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]); 604 eth_dev->data->rx_queues[queue_idx] = NULL; 605 } 606 607 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 608 609 /* Sanity Checking 610 * 611 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 612 */ 613 temp_nb_desc = nb_desc; 614 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 615 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 616 __func__, CXGBE_MIN_RING_DESC_SIZE, 617 CXGBE_DEFAULT_RX_DESC_SIZE); 618 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 619 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 620 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 621 __func__, CXGBE_MIN_RING_DESC_SIZE, 622 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 623 return -(EINVAL); 624 } 625 626 rxq->rspq.size = temp_nb_desc; 627 if ((&rxq->fl) != NULL) 628 rxq->fl.size = temp_nb_desc; 629 630 /* Set to jumbo mode if necessary */ 631 if (pkt_len > RTE_ETHER_MAX_LEN) 632 eth_dev->data->dev_conf.rxmode.offloads |= 633 DEV_RX_OFFLOAD_JUMBO_FRAME; 634 else 635 eth_dev->data->dev_conf.rxmode.offloads &= 636 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 637 638 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 639 &rxq->fl, NULL, 640 is_pf4(adapter) ? 641 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 642 queue_idx, socket_id); 643 644 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 645 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 646 rxq->rspq.abs_id); 647 return err; 648 } 649 650 void cxgbe_dev_rx_queue_release(void *q) 651 { 652 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q; 653 struct sge_rspq *rq = &rxq->rspq; 654 655 if (rq) { 656 struct port_info *pi = (struct port_info *) 657 (rq->eth_dev->data->dev_private); 658 struct adapter *adap = pi->adapter; 659 660 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 661 __func__, pi->port_id, rxq->rspq.cntxt_id); 662 663 t4_sge_eth_rxq_release(adap, rxq); 664 } 665 } 666 667 /* 668 * Get port statistics. 669 */ 670 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 671 struct rte_eth_stats *eth_stats) 672 { 673 struct port_info *pi = eth_dev->data->dev_private; 674 struct adapter *adapter = pi->adapter; 675 struct sge *s = &adapter->sge; 676 struct port_stats ps; 677 unsigned int i; 678 679 cxgbe_stats_get(pi, &ps); 680 681 /* RX Stats */ 682 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 683 ps.rx_ovflow2 + ps.rx_ovflow3 + 684 ps.rx_trunc0 + ps.rx_trunc1 + 685 ps.rx_trunc2 + ps.rx_trunc3; 686 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 687 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 688 ps.rx_len_err; 689 690 /* TX Stats */ 691 eth_stats->opackets = ps.tx_frames; 692 eth_stats->obytes = ps.tx_octets; 693 eth_stats->oerrors = ps.tx_error_frames; 694 695 for (i = 0; i < pi->n_rx_qsets; i++) { 696 struct sge_eth_rxq *rxq = 697 &s->ethrxq[pi->first_qset + i]; 698 699 eth_stats->q_ipackets[i] = rxq->stats.pkts; 700 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes; 701 eth_stats->ipackets += eth_stats->q_ipackets[i]; 702 eth_stats->ibytes += eth_stats->q_ibytes[i]; 703 } 704 705 for (i = 0; i < pi->n_tx_qsets; i++) { 706 struct sge_eth_txq *txq = 707 &s->ethtxq[pi->first_qset + i]; 708 709 eth_stats->q_opackets[i] = txq->stats.pkts; 710 eth_stats->q_obytes[i] = txq->stats.tx_bytes; 711 } 712 return 0; 713 } 714 715 /* 716 * Reset port statistics. 717 */ 718 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 719 { 720 struct port_info *pi = eth_dev->data->dev_private; 721 struct adapter *adapter = pi->adapter; 722 struct sge *s = &adapter->sge; 723 unsigned int i; 724 725 cxgbe_stats_reset(pi); 726 for (i = 0; i < pi->n_rx_qsets; i++) { 727 struct sge_eth_rxq *rxq = 728 &s->ethrxq[pi->first_qset + i]; 729 730 rxq->stats.pkts = 0; 731 rxq->stats.rx_bytes = 0; 732 } 733 for (i = 0; i < pi->n_tx_qsets; i++) { 734 struct sge_eth_txq *txq = 735 &s->ethtxq[pi->first_qset + i]; 736 737 txq->stats.pkts = 0; 738 txq->stats.tx_bytes = 0; 739 txq->stats.mapping_err = 0; 740 } 741 } 742 743 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 744 struct rte_eth_fc_conf *fc_conf) 745 { 746 struct port_info *pi = eth_dev->data->dev_private; 747 struct link_config *lc = &pi->link_cfg; 748 int rx_pause, tx_pause; 749 750 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG; 751 rx_pause = lc->fc & PAUSE_RX; 752 tx_pause = lc->fc & PAUSE_TX; 753 754 if (rx_pause && tx_pause) 755 fc_conf->mode = RTE_FC_FULL; 756 else if (rx_pause) 757 fc_conf->mode = RTE_FC_RX_PAUSE; 758 else if (tx_pause) 759 fc_conf->mode = RTE_FC_TX_PAUSE; 760 else 761 fc_conf->mode = RTE_FC_NONE; 762 return 0; 763 } 764 765 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 766 struct rte_eth_fc_conf *fc_conf) 767 { 768 struct port_info *pi = eth_dev->data->dev_private; 769 struct adapter *adapter = pi->adapter; 770 struct link_config *lc = &pi->link_cfg; 771 772 if (lc->pcaps & FW_PORT_CAP32_ANEG) { 773 if (fc_conf->autoneg) 774 lc->requested_fc |= PAUSE_AUTONEG; 775 else 776 lc->requested_fc &= ~PAUSE_AUTONEG; 777 } 778 779 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 780 (fc_conf->mode & RTE_FC_RX_PAUSE)) 781 lc->requested_fc |= PAUSE_RX; 782 else 783 lc->requested_fc &= ~PAUSE_RX; 784 785 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 786 (fc_conf->mode & RTE_FC_TX_PAUSE)) 787 lc->requested_fc |= PAUSE_TX; 788 else 789 lc->requested_fc &= ~PAUSE_TX; 790 791 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 792 &pi->link_cfg); 793 } 794 795 const uint32_t * 796 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 797 { 798 static const uint32_t ptypes[] = { 799 RTE_PTYPE_L3_IPV4, 800 RTE_PTYPE_L3_IPV6, 801 RTE_PTYPE_UNKNOWN 802 }; 803 804 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 805 return ptypes; 806 return NULL; 807 } 808 809 /* Update RSS hash configuration 810 */ 811 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 812 struct rte_eth_rss_conf *rss_conf) 813 { 814 struct port_info *pi = dev->data->dev_private; 815 struct adapter *adapter = pi->adapter; 816 int err; 817 818 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 819 if (err) 820 return err; 821 822 pi->rss_hf = rss_conf->rss_hf; 823 824 if (rss_conf->rss_key) { 825 u32 key[10], mod_key[10]; 826 int i, j; 827 828 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 829 830 for (i = 9, j = 0; i >= 0; i--, j++) 831 mod_key[j] = cpu_to_be32(key[i]); 832 833 t4_write_rss_key(adapter, mod_key, -1); 834 } 835 836 return 0; 837 } 838 839 /* Get RSS hash configuration 840 */ 841 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 842 struct rte_eth_rss_conf *rss_conf) 843 { 844 struct port_info *pi = dev->data->dev_private; 845 struct adapter *adapter = pi->adapter; 846 u64 rss_hf = 0; 847 u64 flags = 0; 848 int err; 849 850 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 851 &flags, NULL); 852 853 if (err) 854 return err; 855 856 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 857 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; 858 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 859 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; 860 } 861 862 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 863 rss_hf |= CXGBE_RSS_HF_IPV6_MASK; 864 865 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 866 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 867 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 868 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 869 } 870 871 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 872 rss_hf |= CXGBE_RSS_HF_IPV4_MASK; 873 874 rss_conf->rss_hf = rss_hf; 875 876 if (rss_conf->rss_key) { 877 u32 key[10], mod_key[10]; 878 int i, j; 879 880 t4_read_rss_key(adapter, key); 881 882 for (i = 9, j = 0; i >= 0; i--, j++) 883 mod_key[j] = be32_to_cpu(key[i]); 884 885 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 886 } 887 888 return 0; 889 } 890 891 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 892 { 893 RTE_SET_USED(dev); 894 return EEPROMSIZE; 895 } 896 897 /** 898 * eeprom_ptov - translate a physical EEPROM address to virtual 899 * @phys_addr: the physical EEPROM address 900 * @fn: the PCI function number 901 * @sz: size of function-specific area 902 * 903 * Translate a physical EEPROM address to virtual. The first 1K is 904 * accessed through virtual addresses starting at 31K, the rest is 905 * accessed through virtual addresses starting at 0. 906 * 907 * The mapping is as follows: 908 * [0..1K) -> [31K..32K) 909 * [1K..1K+A) -> [31K-A..31K) 910 * [1K+A..ES) -> [0..ES-A-1K) 911 * 912 * where A = @fn * @sz, and ES = EEPROM size. 913 */ 914 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 915 { 916 fn *= sz; 917 if (phys_addr < 1024) 918 return phys_addr + (31 << 10); 919 if (phys_addr < 1024 + fn) 920 return fn + phys_addr - 1024; 921 if (phys_addr < EEPROMSIZE) 922 return phys_addr - 1024 - fn; 923 if (phys_addr < EEPROMVSIZE) 924 return phys_addr - 1024; 925 return -EINVAL; 926 } 927 928 /* The next two routines implement eeprom read/write from physical addresses. 929 */ 930 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 931 { 932 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 933 934 if (vaddr >= 0) 935 vaddr = t4_seeprom_read(adap, vaddr, v); 936 return vaddr < 0 ? vaddr : 0; 937 } 938 939 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 940 { 941 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 942 943 if (vaddr >= 0) 944 vaddr = t4_seeprom_write(adap, vaddr, v); 945 return vaddr < 0 ? vaddr : 0; 946 } 947 948 #define EEPROM_MAGIC 0x38E2F10C 949 950 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 951 struct rte_dev_eeprom_info *e) 952 { 953 struct port_info *pi = dev->data->dev_private; 954 struct adapter *adapter = pi->adapter; 955 u32 i, err = 0; 956 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 957 958 if (!buf) 959 return -ENOMEM; 960 961 e->magic = EEPROM_MAGIC; 962 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 963 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 964 965 if (!err) 966 rte_memcpy(e->data, buf + e->offset, e->length); 967 rte_free(buf); 968 return err; 969 } 970 971 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 972 struct rte_dev_eeprom_info *eeprom) 973 { 974 struct port_info *pi = dev->data->dev_private; 975 struct adapter *adapter = pi->adapter; 976 u8 *buf; 977 int err = 0; 978 u32 aligned_offset, aligned_len, *p; 979 980 if (eeprom->magic != EEPROM_MAGIC) 981 return -EINVAL; 982 983 aligned_offset = eeprom->offset & ~3; 984 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 985 986 if (adapter->pf > 0) { 987 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 988 989 if (aligned_offset < start || 990 aligned_offset + aligned_len > start + EEPROMPFSIZE) 991 return -EPERM; 992 } 993 994 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 995 /* RMW possibly needed for first or last words. 996 */ 997 buf = rte_zmalloc(NULL, aligned_len, 0); 998 if (!buf) 999 return -ENOMEM; 1000 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1001 if (!err && aligned_len > 4) 1002 err = eeprom_rd_phys(adapter, 1003 aligned_offset + aligned_len - 4, 1004 (u32 *)&buf[aligned_len - 4]); 1005 if (err) 1006 goto out; 1007 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1008 eeprom->length); 1009 } else { 1010 buf = eeprom->data; 1011 } 1012 1013 err = t4_seeprom_wp(adapter, false); 1014 if (err) 1015 goto out; 1016 1017 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1018 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1019 aligned_offset += 4; 1020 } 1021 1022 if (!err) 1023 err = t4_seeprom_wp(adapter, true); 1024 out: 1025 if (buf != eeprom->data) 1026 rte_free(buf); 1027 return err; 1028 } 1029 1030 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1031 { 1032 struct port_info *pi = eth_dev->data->dev_private; 1033 struct adapter *adapter = pi->adapter; 1034 1035 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1036 } 1037 1038 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1039 struct rte_dev_reg_info *regs) 1040 { 1041 struct port_info *pi = eth_dev->data->dev_private; 1042 struct adapter *adapter = pi->adapter; 1043 1044 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1045 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1046 (1 << 16); 1047 1048 if (regs->data == NULL) { 1049 regs->length = cxgbe_get_regs_len(eth_dev); 1050 regs->width = sizeof(uint32_t); 1051 1052 return 0; 1053 } 1054 1055 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1056 1057 return 0; 1058 } 1059 1060 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 1061 { 1062 struct port_info *pi = dev->data->dev_private; 1063 int ret; 1064 1065 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); 1066 if (ret < 0) { 1067 dev_err(adapter, "failed to set mac addr; err = %d\n", 1068 ret); 1069 return ret; 1070 } 1071 pi->xact_addr_filt = ret; 1072 return 0; 1073 } 1074 1075 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1076 .dev_start = cxgbe_dev_start, 1077 .dev_stop = cxgbe_dev_stop, 1078 .dev_close = cxgbe_dev_close, 1079 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1080 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1081 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1082 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1083 .dev_configure = cxgbe_dev_configure, 1084 .dev_infos_get = cxgbe_dev_info_get, 1085 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1086 .link_update = cxgbe_dev_link_update, 1087 .dev_set_link_up = cxgbe_dev_set_link_up, 1088 .dev_set_link_down = cxgbe_dev_set_link_down, 1089 .mtu_set = cxgbe_dev_mtu_set, 1090 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1091 .tx_queue_start = cxgbe_dev_tx_queue_start, 1092 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1093 .tx_queue_release = cxgbe_dev_tx_queue_release, 1094 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1095 .rx_queue_start = cxgbe_dev_rx_queue_start, 1096 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1097 .rx_queue_release = cxgbe_dev_rx_queue_release, 1098 .filter_ctrl = cxgbe_dev_filter_ctrl, 1099 .stats_get = cxgbe_dev_stats_get, 1100 .stats_reset = cxgbe_dev_stats_reset, 1101 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1102 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1103 .get_eeprom_length = cxgbe_get_eeprom_length, 1104 .get_eeprom = cxgbe_get_eeprom, 1105 .set_eeprom = cxgbe_set_eeprom, 1106 .get_reg = cxgbe_get_regs, 1107 .rss_hash_update = cxgbe_dev_rss_hash_update, 1108 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1109 .mac_addr_set = cxgbe_mac_addr_set, 1110 }; 1111 1112 /* 1113 * Initialize driver 1114 * It returns 0 on success. 1115 */ 1116 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1117 { 1118 struct rte_pci_device *pci_dev; 1119 struct port_info *pi = eth_dev->data->dev_private; 1120 struct adapter *adapter = NULL; 1121 char name[RTE_ETH_NAME_MAX_LEN]; 1122 int err = 0; 1123 1124 CXGBE_FUNC_TRACE(); 1125 1126 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1127 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1128 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1129 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1130 1131 /* for secondary processes, we attach to ethdevs allocated by primary 1132 * and do minimal initialization. 1133 */ 1134 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1135 int i; 1136 1137 for (i = 1; i < MAX_NPORTS; i++) { 1138 struct rte_eth_dev *rest_eth_dev; 1139 char namei[RTE_ETH_NAME_MAX_LEN]; 1140 1141 snprintf(namei, sizeof(namei), "%s_%d", 1142 pci_dev->device.name, i); 1143 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1144 if (rest_eth_dev) { 1145 rest_eth_dev->device = &pci_dev->device; 1146 rest_eth_dev->dev_ops = 1147 eth_dev->dev_ops; 1148 rest_eth_dev->rx_pkt_burst = 1149 eth_dev->rx_pkt_burst; 1150 rest_eth_dev->tx_pkt_burst = 1151 eth_dev->tx_pkt_burst; 1152 rte_eth_dev_probing_finish(rest_eth_dev); 1153 } 1154 } 1155 return 0; 1156 } 1157 1158 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1159 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1160 if (!adapter) 1161 return -1; 1162 1163 adapter->use_unpacked_mode = 1; 1164 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1165 if (!adapter->regs) { 1166 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1167 err = -ENOMEM; 1168 goto out_free_adapter; 1169 } 1170 adapter->pdev = pci_dev; 1171 adapter->eth_dev = eth_dev; 1172 pi->adapter = adapter; 1173 1174 err = cxgbe_probe(adapter); 1175 if (err) { 1176 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1177 __func__, err); 1178 goto out_free_adapter; 1179 } 1180 1181 return 0; 1182 1183 out_free_adapter: 1184 rte_free(adapter); 1185 return err; 1186 } 1187 1188 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1189 { 1190 struct port_info *pi = eth_dev->data->dev_private; 1191 struct adapter *adap = pi->adapter; 1192 1193 /* Free up other ports and all resources */ 1194 cxgbe_close(adap); 1195 return 0; 1196 } 1197 1198 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1199 struct rte_pci_device *pci_dev) 1200 { 1201 return rte_eth_dev_pci_generic_probe(pci_dev, 1202 sizeof(struct port_info), eth_cxgbe_dev_init); 1203 } 1204 1205 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1206 { 1207 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1208 } 1209 1210 static struct rte_pci_driver rte_cxgbe_pmd = { 1211 .id_table = cxgb4_pci_tbl, 1212 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1213 .probe = eth_cxgbe_pci_probe, 1214 .remove = eth_cxgbe_pci_remove, 1215 }; 1216 1217 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1218 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1219 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1220 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1221 CXGBE_DEVARG_KEEP_OVLAN "=<0|1> " 1222 CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> "); 1223 1224 RTE_INIT(cxgbe_init_log) 1225 { 1226 cxgbe_logtype = rte_log_register("pmd.net.cxgbe"); 1227 if (cxgbe_logtype >= 0) 1228 rte_log_set_level(cxgbe_logtype, RTE_LOG_NOTICE); 1229 } 1230