1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_atomic.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_memory.h> 27 #include <rte_tailq.h> 28 #include <rte_eal.h> 29 #include <rte_alarm.h> 30 #include <rte_ether.h> 31 #include <rte_ethdev_driver.h> 32 #include <rte_ethdev_pci.h> 33 #include <rte_malloc.h> 34 #include <rte_random.h> 35 #include <rte_dev.h> 36 37 #include "cxgbe.h" 38 #include "cxgbe_pfvf.h" 39 40 /* 41 * Macros needed to support the PCI Device ID Table ... 42 */ 43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 44 static const struct rte_pci_id cxgb4_pci_tbl[] = { 45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 46 47 #define PCI_VENDOR_ID_CHELSIO 0x1425 48 49 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 51 52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 53 { .vendor_id = 0, } \ 54 } 55 56 /* 57 *... and the PCI ID Table itself ... 58 */ 59 #include "t4_pci_id_tbl.h" 60 61 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\ 62 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 63 DEV_TX_OFFLOAD_UDP_CKSUM |\ 64 DEV_TX_OFFLOAD_TCP_CKSUM |\ 65 DEV_TX_OFFLOAD_TCP_TSO) 66 67 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\ 68 DEV_RX_OFFLOAD_CRC_STRIP |\ 69 DEV_RX_OFFLOAD_IPV4_CKSUM |\ 70 DEV_RX_OFFLOAD_JUMBO_FRAME |\ 71 DEV_RX_OFFLOAD_UDP_CKSUM |\ 72 DEV_RX_OFFLOAD_TCP_CKSUM) 73 74 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 75 uint16_t nb_pkts) 76 { 77 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 78 uint16_t pkts_sent, pkts_remain; 79 uint16_t total_sent = 0; 80 int ret = 0; 81 82 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n", 83 __func__, txq, tx_pkts, nb_pkts); 84 85 t4_os_lock(&txq->txq_lock); 86 /* free up desc from already completed tx */ 87 reclaim_completed_tx(&txq->q); 88 while (total_sent < nb_pkts) { 89 pkts_remain = nb_pkts - total_sent; 90 91 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 92 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent], 93 nb_pkts); 94 if (ret < 0) 95 break; 96 } 97 if (!pkts_sent) 98 break; 99 total_sent += pkts_sent; 100 /* reclaim as much as possible */ 101 reclaim_completed_tx(&txq->q); 102 } 103 104 t4_os_unlock(&txq->txq_lock); 105 return total_sent; 106 } 107 108 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 109 uint16_t nb_pkts) 110 { 111 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 112 unsigned int work_done; 113 114 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n", 115 __func__, rxq->rspq.cntxt_id, nb_pkts); 116 117 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 118 dev_err(adapter, "error in cxgbe poll\n"); 119 120 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done); 121 return work_done; 122 } 123 124 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 125 struct rte_eth_dev_info *device_info) 126 { 127 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 128 struct adapter *adapter = pi->adapter; 129 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports; 130 131 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 132 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 133 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 134 .nb_align = 1, 135 }; 136 137 device_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 138 139 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 140 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 141 device_info->max_rx_queues = max_queues; 142 device_info->max_tx_queues = max_queues; 143 device_info->max_mac_addrs = 1; 144 /* XXX: For now we support one MAC/port */ 145 device_info->max_vfs = adapter->params.arch.vfcount; 146 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 147 148 device_info->rx_queue_offload_capa = 0UL; 149 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 150 151 device_info->tx_queue_offload_capa = 0UL; 152 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 153 154 device_info->reta_size = pi->rss_size; 155 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 156 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 157 158 device_info->rx_desc_lim = cxgbe_desc_lim; 159 device_info->tx_desc_lim = cxgbe_desc_lim; 160 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 161 } 162 163 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 164 { 165 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 166 struct adapter *adapter = pi->adapter; 167 168 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 169 1, -1, 1, -1, false); 170 } 171 172 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 173 { 174 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 175 struct adapter *adapter = pi->adapter; 176 177 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 178 0, -1, 1, -1, false); 179 } 180 181 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 182 { 183 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 184 struct adapter *adapter = pi->adapter; 185 186 /* TODO: address filters ?? */ 187 188 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 189 -1, 1, 1, -1, false); 190 } 191 192 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 193 { 194 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 195 struct adapter *adapter = pi->adapter; 196 197 /* TODO: address filters ?? */ 198 199 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 200 -1, 0, 1, -1, false); 201 } 202 203 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 204 __rte_unused int wait_to_complete) 205 { 206 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 207 struct adapter *adapter = pi->adapter; 208 struct sge *s = &adapter->sge; 209 struct rte_eth_link *old_link = ð_dev->data->dev_link; 210 unsigned int work_done, budget = 4; 211 212 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 213 if (old_link->link_status == pi->link_cfg.link_ok) 214 return -1; /* link not changed */ 215 216 eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok; 217 eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX; 218 eth_dev->data->dev_link.link_speed = pi->link_cfg.speed; 219 220 /* link has changed */ 221 return 0; 222 } 223 224 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 225 { 226 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 227 struct adapter *adapter = pi->adapter; 228 struct rte_eth_dev_info dev_info; 229 int err; 230 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 231 232 cxgbe_dev_info_get(eth_dev, &dev_info); 233 234 /* Must accommodate at least ETHER_MIN_MTU */ 235 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen)) 236 return -EINVAL; 237 238 /* set to jumbo mode if needed */ 239 if (new_mtu > ETHER_MAX_LEN) 240 eth_dev->data->dev_conf.rxmode.offloads |= 241 DEV_RX_OFFLOAD_JUMBO_FRAME; 242 else 243 eth_dev->data->dev_conf.rxmode.offloads &= 244 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 245 246 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 247 -1, -1, true); 248 if (!err) 249 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu; 250 251 return err; 252 } 253 254 /* 255 * Stop device. 256 */ 257 void cxgbe_dev_close(struct rte_eth_dev *eth_dev) 258 { 259 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 260 struct adapter *adapter = pi->adapter; 261 int i, dev_down = 0; 262 263 CXGBE_FUNC_TRACE(); 264 265 if (!(adapter->flags & FULL_INIT_DONE)) 266 return; 267 268 cxgbe_down(pi); 269 270 /* 271 * We clear queues only if both tx and rx path of the port 272 * have been disabled 273 */ 274 t4_sge_eth_clear_queues(pi); 275 276 /* See if all ports are down */ 277 for_each_port(adapter, i) { 278 pi = adap2pinfo(adapter, i); 279 /* 280 * Skip first port of the adapter since it will be closed 281 * by DPDK 282 */ 283 if (i == 0) 284 continue; 285 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0; 286 } 287 288 /* If rest of the ports are stopped, then free up resources */ 289 if (dev_down == (adapter->params.nports - 1)) 290 cxgbe_close(adapter); 291 } 292 293 /* Start the device. 294 * It returns 0 on success. 295 */ 296 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 297 { 298 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 299 struct adapter *adapter = pi->adapter; 300 int err = 0, i; 301 302 CXGBE_FUNC_TRACE(); 303 304 /* 305 * If we don't have a connection to the firmware there's nothing we 306 * can do. 307 */ 308 if (!(adapter->flags & FW_OK)) { 309 err = -ENXIO; 310 goto out; 311 } 312 313 if (!(adapter->flags & FULL_INIT_DONE)) { 314 err = cxgbe_up(adapter); 315 if (err < 0) 316 goto out; 317 } 318 319 cxgbe_enable_rx_queues(pi); 320 321 err = setup_rss(pi); 322 if (err) 323 goto out; 324 325 for (i = 0; i < pi->n_tx_qsets; i++) { 326 err = cxgbe_dev_tx_queue_start(eth_dev, i); 327 if (err) 328 goto out; 329 } 330 331 for (i = 0; i < pi->n_rx_qsets; i++) { 332 err = cxgbe_dev_rx_queue_start(eth_dev, i); 333 if (err) 334 goto out; 335 } 336 337 err = link_start(pi); 338 if (err) 339 goto out; 340 341 out: 342 return err; 343 } 344 345 /* 346 * Stop device: disable rx and tx functions to allow for reconfiguring. 347 */ 348 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 349 { 350 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 351 struct adapter *adapter = pi->adapter; 352 353 CXGBE_FUNC_TRACE(); 354 355 if (!(adapter->flags & FULL_INIT_DONE)) 356 return; 357 358 cxgbe_down(pi); 359 360 /* 361 * We clear queues only if both tx and rx path of the port 362 * have been disabled 363 */ 364 t4_sge_eth_clear_queues(pi); 365 } 366 367 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 368 { 369 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 370 struct adapter *adapter = pi->adapter; 371 uint64_t unsupported_offloads, configured_offloads; 372 int err; 373 374 CXGBE_FUNC_TRACE(); 375 configured_offloads = eth_dev->data->dev_conf.rxmode.offloads; 376 if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) { 377 dev_info(adapter, "can't disable hw crc strip\n"); 378 configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP; 379 } 380 381 unsupported_offloads = configured_offloads & ~CXGBE_RX_OFFLOADS; 382 if (unsupported_offloads) { 383 dev_err(adapter, "Rx offloads 0x%" PRIx64 " are not supported. " 384 "Supported:0x%" PRIx64 "\n", 385 unsupported_offloads, (uint64_t)CXGBE_RX_OFFLOADS); 386 return -ENOTSUP; 387 } 388 389 configured_offloads = eth_dev->data->dev_conf.txmode.offloads; 390 unsupported_offloads = configured_offloads & ~CXGBE_TX_OFFLOADS; 391 if (unsupported_offloads) { 392 dev_err(adapter, "Tx offloads 0x%" PRIx64 " are not supported. " 393 "Supported:0x%" PRIx64 "\n", 394 unsupported_offloads, (uint64_t)CXGBE_TX_OFFLOADS); 395 return -ENOTSUP; 396 } 397 398 if (!(adapter->flags & FW_QUEUE_BOUND)) { 399 err = setup_sge_fwevtq(adapter); 400 if (err) 401 return err; 402 adapter->flags |= FW_QUEUE_BOUND; 403 } 404 405 err = cfg_queue_count(eth_dev); 406 if (err) 407 return err; 408 409 return 0; 410 } 411 412 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 413 { 414 int ret; 415 struct sge_eth_txq *txq = (struct sge_eth_txq *) 416 (eth_dev->data->tx_queues[tx_queue_id]); 417 418 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 419 420 ret = t4_sge_eth_txq_start(txq); 421 if (ret == 0) 422 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 423 424 return ret; 425 } 426 427 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 428 { 429 int ret; 430 struct sge_eth_txq *txq = (struct sge_eth_txq *) 431 (eth_dev->data->tx_queues[tx_queue_id]); 432 433 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 434 435 ret = t4_sge_eth_txq_stop(txq); 436 if (ret == 0) 437 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 438 439 return ret; 440 } 441 442 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 443 uint16_t queue_idx, uint16_t nb_desc, 444 unsigned int socket_id, 445 const struct rte_eth_txconf *tx_conf) 446 { 447 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 448 struct adapter *adapter = pi->adapter; 449 struct sge *s = &adapter->sge; 450 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx]; 451 int err = 0; 452 unsigned int temp_nb_desc; 453 uint64_t unsupported_offloads; 454 455 unsupported_offloads = tx_conf->offloads & ~CXGBE_TX_OFFLOADS; 456 if (unsupported_offloads) { 457 dev_err(adapter, "Tx offloads 0x%" PRIx64 " are not supported. " 458 "Supported:0x%" PRIx64 "\n", 459 unsupported_offloads, (uint64_t)CXGBE_TX_OFFLOADS); 460 return -ENOTSUP; 461 } 462 463 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 464 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 465 socket_id, pi->first_qset); 466 467 /* Free up the existing queue */ 468 if (eth_dev->data->tx_queues[queue_idx]) { 469 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]); 470 eth_dev->data->tx_queues[queue_idx] = NULL; 471 } 472 473 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 474 475 /* Sanity Checking 476 * 477 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 478 */ 479 temp_nb_desc = nb_desc; 480 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 481 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 482 __func__, CXGBE_MIN_RING_DESC_SIZE, 483 CXGBE_DEFAULT_TX_DESC_SIZE); 484 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 485 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 486 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 487 __func__, CXGBE_MIN_RING_DESC_SIZE, 488 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 489 return -(EINVAL); 490 } 491 492 txq->q.size = temp_nb_desc; 493 494 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 495 s->fw_evtq.cntxt_id, socket_id); 496 497 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 498 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 499 return err; 500 } 501 502 void cxgbe_dev_tx_queue_release(void *q) 503 { 504 struct sge_eth_txq *txq = (struct sge_eth_txq *)q; 505 506 if (txq) { 507 struct port_info *pi = (struct port_info *) 508 (txq->eth_dev->data->dev_private); 509 struct adapter *adap = pi->adapter; 510 511 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 512 __func__, pi->port_id, txq->q.cntxt_id); 513 514 t4_sge_eth_txq_release(adap, txq); 515 } 516 } 517 518 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 519 { 520 int ret; 521 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 522 struct adapter *adap = pi->adapter; 523 struct sge_rspq *q; 524 525 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 526 __func__, pi->port_id, rx_queue_id); 527 528 q = eth_dev->data->rx_queues[rx_queue_id]; 529 530 ret = t4_sge_eth_rxq_start(adap, q); 531 if (ret == 0) 532 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 533 534 return ret; 535 } 536 537 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 538 { 539 int ret; 540 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 541 struct adapter *adap = pi->adapter; 542 struct sge_rspq *q; 543 544 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 545 __func__, pi->port_id, rx_queue_id); 546 547 q = eth_dev->data->rx_queues[rx_queue_id]; 548 ret = t4_sge_eth_rxq_stop(adap, q); 549 if (ret == 0) 550 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 551 552 return ret; 553 } 554 555 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 556 uint16_t queue_idx, uint16_t nb_desc, 557 unsigned int socket_id, 558 const struct rte_eth_rxconf *rx_conf, 559 struct rte_mempool *mp) 560 { 561 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 562 struct adapter *adapter = pi->adapter; 563 struct sge *s = &adapter->sge; 564 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx]; 565 int err = 0; 566 int msi_idx = 0; 567 unsigned int temp_nb_desc; 568 struct rte_eth_dev_info dev_info; 569 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 570 uint64_t unsupported_offloads, configured_offloads; 571 572 configured_offloads = rx_conf->offloads; 573 if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) { 574 dev_info(adapter, "can't disable hw crc strip\n"); 575 configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP; 576 } 577 578 unsupported_offloads = configured_offloads & ~CXGBE_RX_OFFLOADS; 579 if (unsupported_offloads) { 580 dev_err(adapter, "Rx offloads 0x%" PRIx64 " are not supported. " 581 "Supported:0x%" PRIx64 "\n", 582 unsupported_offloads, (uint64_t)CXGBE_RX_OFFLOADS); 583 return -ENOTSUP; 584 } 585 586 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 587 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 588 socket_id, mp); 589 590 cxgbe_dev_info_get(eth_dev, &dev_info); 591 592 /* Must accommodate at least ETHER_MIN_MTU */ 593 if ((pkt_len < dev_info.min_rx_bufsize) || 594 (pkt_len > dev_info.max_rx_pktlen)) { 595 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 596 __func__, dev_info.min_rx_bufsize, 597 dev_info.max_rx_pktlen); 598 return -EINVAL; 599 } 600 601 /* Free up the existing queue */ 602 if (eth_dev->data->rx_queues[queue_idx]) { 603 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]); 604 eth_dev->data->rx_queues[queue_idx] = NULL; 605 } 606 607 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 608 609 /* Sanity Checking 610 * 611 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 612 */ 613 temp_nb_desc = nb_desc; 614 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 615 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 616 __func__, CXGBE_MIN_RING_DESC_SIZE, 617 CXGBE_DEFAULT_RX_DESC_SIZE); 618 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 619 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 620 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 621 __func__, CXGBE_MIN_RING_DESC_SIZE, 622 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 623 return -(EINVAL); 624 } 625 626 rxq->rspq.size = temp_nb_desc; 627 if ((&rxq->fl) != NULL) 628 rxq->fl.size = temp_nb_desc; 629 630 /* Set to jumbo mode if necessary */ 631 if (pkt_len > ETHER_MAX_LEN) 632 eth_dev->data->dev_conf.rxmode.offloads |= 633 DEV_RX_OFFLOAD_JUMBO_FRAME; 634 else 635 eth_dev->data->dev_conf.rxmode.offloads &= 636 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 637 638 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 639 &rxq->fl, t4_ethrx_handler, 640 is_pf4(adapter) ? 641 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 642 queue_idx, socket_id); 643 644 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 645 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 646 rxq->rspq.abs_id); 647 return err; 648 } 649 650 void cxgbe_dev_rx_queue_release(void *q) 651 { 652 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q; 653 struct sge_rspq *rq = &rxq->rspq; 654 655 if (rq) { 656 struct port_info *pi = (struct port_info *) 657 (rq->eth_dev->data->dev_private); 658 struct adapter *adap = pi->adapter; 659 660 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 661 __func__, pi->port_id, rxq->rspq.cntxt_id); 662 663 t4_sge_eth_rxq_release(adap, rxq); 664 } 665 } 666 667 /* 668 * Get port statistics. 669 */ 670 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 671 struct rte_eth_stats *eth_stats) 672 { 673 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 674 struct adapter *adapter = pi->adapter; 675 struct sge *s = &adapter->sge; 676 struct port_stats ps; 677 unsigned int i; 678 679 cxgbe_stats_get(pi, &ps); 680 681 /* RX Stats */ 682 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 683 ps.rx_ovflow2 + ps.rx_ovflow3 + 684 ps.rx_trunc0 + ps.rx_trunc1 + 685 ps.rx_trunc2 + ps.rx_trunc3; 686 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 687 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 688 ps.rx_len_err; 689 690 /* TX Stats */ 691 eth_stats->opackets = ps.tx_frames; 692 eth_stats->obytes = ps.tx_octets; 693 eth_stats->oerrors = ps.tx_error_frames; 694 695 for (i = 0; i < pi->n_rx_qsets; i++) { 696 struct sge_eth_rxq *rxq = 697 &s->ethrxq[pi->first_qset + i]; 698 699 eth_stats->q_ipackets[i] = rxq->stats.pkts; 700 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes; 701 eth_stats->ipackets += eth_stats->q_ipackets[i]; 702 eth_stats->ibytes += eth_stats->q_ibytes[i]; 703 } 704 705 for (i = 0; i < pi->n_tx_qsets; i++) { 706 struct sge_eth_txq *txq = 707 &s->ethtxq[pi->first_qset + i]; 708 709 eth_stats->q_opackets[i] = txq->stats.pkts; 710 eth_stats->q_obytes[i] = txq->stats.tx_bytes; 711 eth_stats->q_errors[i] = txq->stats.mapping_err; 712 } 713 return 0; 714 } 715 716 /* 717 * Reset port statistics. 718 */ 719 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 720 { 721 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 722 struct adapter *adapter = pi->adapter; 723 struct sge *s = &adapter->sge; 724 unsigned int i; 725 726 cxgbe_stats_reset(pi); 727 for (i = 0; i < pi->n_rx_qsets; i++) { 728 struct sge_eth_rxq *rxq = 729 &s->ethrxq[pi->first_qset + i]; 730 731 rxq->stats.pkts = 0; 732 rxq->stats.rx_bytes = 0; 733 } 734 for (i = 0; i < pi->n_tx_qsets; i++) { 735 struct sge_eth_txq *txq = 736 &s->ethtxq[pi->first_qset + i]; 737 738 txq->stats.pkts = 0; 739 txq->stats.tx_bytes = 0; 740 txq->stats.mapping_err = 0; 741 } 742 } 743 744 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 745 struct rte_eth_fc_conf *fc_conf) 746 { 747 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 748 struct link_config *lc = &pi->link_cfg; 749 int rx_pause, tx_pause; 750 751 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG; 752 rx_pause = lc->fc & PAUSE_RX; 753 tx_pause = lc->fc & PAUSE_TX; 754 755 if (rx_pause && tx_pause) 756 fc_conf->mode = RTE_FC_FULL; 757 else if (rx_pause) 758 fc_conf->mode = RTE_FC_RX_PAUSE; 759 else if (tx_pause) 760 fc_conf->mode = RTE_FC_TX_PAUSE; 761 else 762 fc_conf->mode = RTE_FC_NONE; 763 return 0; 764 } 765 766 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 767 struct rte_eth_fc_conf *fc_conf) 768 { 769 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 770 struct adapter *adapter = pi->adapter; 771 struct link_config *lc = &pi->link_cfg; 772 773 if (lc->pcaps & FW_PORT_CAP32_ANEG) { 774 if (fc_conf->autoneg) 775 lc->requested_fc |= PAUSE_AUTONEG; 776 else 777 lc->requested_fc &= ~PAUSE_AUTONEG; 778 } 779 780 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 781 (fc_conf->mode & RTE_FC_RX_PAUSE)) 782 lc->requested_fc |= PAUSE_RX; 783 else 784 lc->requested_fc &= ~PAUSE_RX; 785 786 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 787 (fc_conf->mode & RTE_FC_TX_PAUSE)) 788 lc->requested_fc |= PAUSE_TX; 789 else 790 lc->requested_fc &= ~PAUSE_TX; 791 792 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 793 &pi->link_cfg); 794 } 795 796 const uint32_t * 797 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 798 { 799 static const uint32_t ptypes[] = { 800 RTE_PTYPE_L3_IPV4, 801 RTE_PTYPE_L3_IPV6, 802 RTE_PTYPE_UNKNOWN 803 }; 804 805 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 806 return ptypes; 807 return NULL; 808 } 809 810 /* Update RSS hash configuration 811 */ 812 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 813 struct rte_eth_rss_conf *rss_conf) 814 { 815 struct port_info *pi = (struct port_info *)(dev->data->dev_private); 816 struct adapter *adapter = pi->adapter; 817 int err; 818 819 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 820 if (err) 821 return err; 822 823 pi->rss_hf = rss_conf->rss_hf; 824 825 if (rss_conf->rss_key) { 826 u32 key[10], mod_key[10]; 827 int i, j; 828 829 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 830 831 for (i = 9, j = 0; i >= 0; i--, j++) 832 mod_key[j] = cpu_to_be32(key[i]); 833 834 t4_write_rss_key(adapter, mod_key, -1); 835 } 836 837 return 0; 838 } 839 840 /* Get RSS hash configuration 841 */ 842 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 843 struct rte_eth_rss_conf *rss_conf) 844 { 845 struct port_info *pi = (struct port_info *)(dev->data->dev_private); 846 struct adapter *adapter = pi->adapter; 847 u64 rss_hf = 0; 848 u64 flags = 0; 849 int err; 850 851 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 852 &flags, NULL); 853 854 if (err) 855 return err; 856 857 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 858 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 859 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 860 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 861 } 862 863 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 864 rss_hf |= ETH_RSS_IPV6; 865 866 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 867 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 868 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 869 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 870 } 871 872 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 873 rss_hf |= ETH_RSS_IPV4; 874 875 rss_conf->rss_hf = rss_hf; 876 877 if (rss_conf->rss_key) { 878 u32 key[10], mod_key[10]; 879 int i, j; 880 881 t4_read_rss_key(adapter, key); 882 883 for (i = 9, j = 0; i >= 0; i--, j++) 884 mod_key[j] = be32_to_cpu(key[i]); 885 886 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 887 } 888 889 return 0; 890 } 891 892 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 893 { 894 RTE_SET_USED(dev); 895 return EEPROMSIZE; 896 } 897 898 /** 899 * eeprom_ptov - translate a physical EEPROM address to virtual 900 * @phys_addr: the physical EEPROM address 901 * @fn: the PCI function number 902 * @sz: size of function-specific area 903 * 904 * Translate a physical EEPROM address to virtual. The first 1K is 905 * accessed through virtual addresses starting at 31K, the rest is 906 * accessed through virtual addresses starting at 0. 907 * 908 * The mapping is as follows: 909 * [0..1K) -> [31K..32K) 910 * [1K..1K+A) -> [31K-A..31K) 911 * [1K+A..ES) -> [0..ES-A-1K) 912 * 913 * where A = @fn * @sz, and ES = EEPROM size. 914 */ 915 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 916 { 917 fn *= sz; 918 if (phys_addr < 1024) 919 return phys_addr + (31 << 10); 920 if (phys_addr < 1024 + fn) 921 return fn + phys_addr - 1024; 922 if (phys_addr < EEPROMSIZE) 923 return phys_addr - 1024 - fn; 924 if (phys_addr < EEPROMVSIZE) 925 return phys_addr - 1024; 926 return -EINVAL; 927 } 928 929 /* The next two routines implement eeprom read/write from physical addresses. 930 */ 931 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 932 { 933 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 934 935 if (vaddr >= 0) 936 vaddr = t4_seeprom_read(adap, vaddr, v); 937 return vaddr < 0 ? vaddr : 0; 938 } 939 940 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 941 { 942 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 943 944 if (vaddr >= 0) 945 vaddr = t4_seeprom_write(adap, vaddr, v); 946 return vaddr < 0 ? vaddr : 0; 947 } 948 949 #define EEPROM_MAGIC 0x38E2F10C 950 951 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 952 struct rte_dev_eeprom_info *e) 953 { 954 struct port_info *pi = (struct port_info *)(dev->data->dev_private); 955 struct adapter *adapter = pi->adapter; 956 u32 i, err = 0; 957 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 958 959 if (!buf) 960 return -ENOMEM; 961 962 e->magic = EEPROM_MAGIC; 963 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 964 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 965 966 if (!err) 967 rte_memcpy(e->data, buf + e->offset, e->length); 968 rte_free(buf); 969 return err; 970 } 971 972 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 973 struct rte_dev_eeprom_info *eeprom) 974 { 975 struct port_info *pi = (struct port_info *)(dev->data->dev_private); 976 struct adapter *adapter = pi->adapter; 977 u8 *buf; 978 int err = 0; 979 u32 aligned_offset, aligned_len, *p; 980 981 if (eeprom->magic != EEPROM_MAGIC) 982 return -EINVAL; 983 984 aligned_offset = eeprom->offset & ~3; 985 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 986 987 if (adapter->pf > 0) { 988 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 989 990 if (aligned_offset < start || 991 aligned_offset + aligned_len > start + EEPROMPFSIZE) 992 return -EPERM; 993 } 994 995 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 996 /* RMW possibly needed for first or last words. 997 */ 998 buf = rte_zmalloc(NULL, aligned_len, 0); 999 if (!buf) 1000 return -ENOMEM; 1001 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1002 if (!err && aligned_len > 4) 1003 err = eeprom_rd_phys(adapter, 1004 aligned_offset + aligned_len - 4, 1005 (u32 *)&buf[aligned_len - 4]); 1006 if (err) 1007 goto out; 1008 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1009 eeprom->length); 1010 } else { 1011 buf = eeprom->data; 1012 } 1013 1014 err = t4_seeprom_wp(adapter, false); 1015 if (err) 1016 goto out; 1017 1018 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1019 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1020 aligned_offset += 4; 1021 } 1022 1023 if (!err) 1024 err = t4_seeprom_wp(adapter, true); 1025 out: 1026 if (buf != eeprom->data) 1027 rte_free(buf); 1028 return err; 1029 } 1030 1031 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1032 { 1033 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 1034 struct adapter *adapter = pi->adapter; 1035 1036 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1037 } 1038 1039 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1040 struct rte_dev_reg_info *regs) 1041 { 1042 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 1043 struct adapter *adapter = pi->adapter; 1044 1045 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1046 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1047 (1 << 16); 1048 1049 if (regs->data == NULL) { 1050 regs->length = cxgbe_get_regs_len(eth_dev); 1051 regs->width = sizeof(uint32_t); 1052 1053 return 0; 1054 } 1055 1056 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1057 1058 return 0; 1059 } 1060 1061 void cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr) 1062 { 1063 struct port_info *pi = (struct port_info *)(dev->data->dev_private); 1064 struct adapter *adapter = pi->adapter; 1065 int ret; 1066 1067 ret = t4_change_mac(adapter, adapter->mbox, pi->viid, 1068 pi->xact_addr_filt, (u8 *)addr, true, true); 1069 if (ret < 0) { 1070 dev_err(adapter, "failed to set mac addr; err = %d\n", 1071 ret); 1072 return; 1073 } 1074 pi->xact_addr_filt = ret; 1075 } 1076 1077 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1078 .dev_start = cxgbe_dev_start, 1079 .dev_stop = cxgbe_dev_stop, 1080 .dev_close = cxgbe_dev_close, 1081 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1082 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1083 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1084 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1085 .dev_configure = cxgbe_dev_configure, 1086 .dev_infos_get = cxgbe_dev_info_get, 1087 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1088 .link_update = cxgbe_dev_link_update, 1089 .mtu_set = cxgbe_dev_mtu_set, 1090 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1091 .tx_queue_start = cxgbe_dev_tx_queue_start, 1092 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1093 .tx_queue_release = cxgbe_dev_tx_queue_release, 1094 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1095 .rx_queue_start = cxgbe_dev_rx_queue_start, 1096 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1097 .rx_queue_release = cxgbe_dev_rx_queue_release, 1098 .stats_get = cxgbe_dev_stats_get, 1099 .stats_reset = cxgbe_dev_stats_reset, 1100 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1101 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1102 .get_eeprom_length = cxgbe_get_eeprom_length, 1103 .get_eeprom = cxgbe_get_eeprom, 1104 .set_eeprom = cxgbe_set_eeprom, 1105 .get_reg = cxgbe_get_regs, 1106 .rss_hash_update = cxgbe_dev_rss_hash_update, 1107 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1108 .mac_addr_set = cxgbe_mac_addr_set, 1109 }; 1110 1111 /* 1112 * Initialize driver 1113 * It returns 0 on success. 1114 */ 1115 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1116 { 1117 struct rte_pci_device *pci_dev; 1118 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 1119 struct adapter *adapter = NULL; 1120 char name[RTE_ETH_NAME_MAX_LEN]; 1121 int err = 0; 1122 1123 CXGBE_FUNC_TRACE(); 1124 1125 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1126 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1127 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1128 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1129 1130 /* for secondary processes, we attach to ethdevs allocated by primary 1131 * and do minimal initialization. 1132 */ 1133 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1134 int i; 1135 1136 for (i = 1; i < MAX_NPORTS; i++) { 1137 struct rte_eth_dev *rest_eth_dev; 1138 char namei[RTE_ETH_NAME_MAX_LEN]; 1139 1140 snprintf(namei, sizeof(namei), "%s_%d", 1141 pci_dev->device.name, i); 1142 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1143 if (rest_eth_dev) { 1144 rest_eth_dev->device = &pci_dev->device; 1145 rest_eth_dev->dev_ops = 1146 eth_dev->dev_ops; 1147 rest_eth_dev->rx_pkt_burst = 1148 eth_dev->rx_pkt_burst; 1149 rest_eth_dev->tx_pkt_burst = 1150 eth_dev->tx_pkt_burst; 1151 } 1152 } 1153 return 0; 1154 } 1155 1156 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1157 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1158 if (!adapter) 1159 return -1; 1160 1161 adapter->use_unpacked_mode = 1; 1162 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1163 if (!adapter->regs) { 1164 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1165 err = -ENOMEM; 1166 goto out_free_adapter; 1167 } 1168 adapter->pdev = pci_dev; 1169 adapter->eth_dev = eth_dev; 1170 pi->adapter = adapter; 1171 1172 err = cxgbe_probe(adapter); 1173 if (err) { 1174 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1175 __func__, err); 1176 goto out_free_adapter; 1177 } 1178 1179 return 0; 1180 1181 out_free_adapter: 1182 rte_free(adapter); 1183 return err; 1184 } 1185 1186 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1187 struct rte_pci_device *pci_dev) 1188 { 1189 return rte_eth_dev_pci_generic_probe(pci_dev, 1190 sizeof(struct port_info), eth_cxgbe_dev_init); 1191 } 1192 1193 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1194 { 1195 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 1196 } 1197 1198 static struct rte_pci_driver rte_cxgbe_pmd = { 1199 .id_table = cxgb4_pci_tbl, 1200 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1201 .probe = eth_cxgbe_pci_probe, 1202 .remove = eth_cxgbe_pci_remove, 1203 }; 1204 1205 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1206 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1207 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1208