1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #ifndef T4_MSG_H 7 #define T4_MSG_H 8 9 enum { 10 CPL_SGE_EGR_UPDATE = 0xA5, 11 CPL_FW4_MSG = 0xC0, 12 CPL_FW6_MSG = 0xE0, 13 CPL_TX_PKT_LSO = 0xED, 14 CPL_TX_PKT_XT = 0xEE, 15 }; 16 17 enum { /* TX_PKT_XT checksum types */ 18 TX_CSUM_TCPIP = 8, 19 TX_CSUM_UDPIP = 9, 20 TX_CSUM_TCPIP6 = 10, 21 }; 22 23 union opcode_tid { 24 __be32 opcode_tid; 25 __u8 opcode; 26 }; 27 28 struct rss_header { 29 __u8 opcode; 30 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 31 __u8 channel:2; 32 __u8 filter_hit:1; 33 __u8 filter_tid:1; 34 __u8 hash_type:2; 35 __u8 ipv6:1; 36 __u8 send2fw:1; 37 #else 38 __u8 send2fw:1; 39 __u8 ipv6:1; 40 __u8 hash_type:2; 41 __u8 filter_tid:1; 42 __u8 filter_hit:1; 43 __u8 channel:2; 44 #endif 45 __be16 qid; 46 __be32 hash_val; 47 }; 48 49 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW) 50 #define RSS_HDR struct rss_header rss_hdr 51 #else 52 #define RSS_HDR 53 #endif 54 55 #ifndef CHELSIO_FW 56 struct work_request_hdr { 57 __be32 wr_hi; 58 __be32 wr_mid; 59 __be64 wr_lo; 60 }; 61 62 #define WR_HDR struct work_request_hdr wr 63 #define WR_HDR_SIZE sizeof(struct work_request_hdr) 64 #else 65 #define WR_HDR 66 #define WR_HDR_SIZE 0 67 #endif 68 69 struct cpl_tx_data { 70 union opcode_tid ot; 71 __be32 len; 72 __be32 rsvd; 73 __be32 flags; 74 }; 75 76 struct cpl_tx_pkt_core { 77 __be32 ctrl0; 78 __be16 pack; 79 __be16 len; 80 __be64 ctrl1; 81 }; 82 83 struct cpl_tx_pkt { 84 WR_HDR; 85 struct cpl_tx_pkt_core c; 86 }; 87 88 /* cpl_tx_pkt_core.ctrl0 fields */ 89 #define S_TXPKT_PF 8 90 #define M_TXPKT_PF 0x7 91 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 92 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 93 94 #define S_TXPKT_INTF 16 95 #define M_TXPKT_INTF 0xF 96 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 97 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 98 99 #define S_TXPKT_OPCODE 24 100 #define M_TXPKT_OPCODE 0xFF 101 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 102 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 103 104 /* cpl_tx_pkt_core.ctrl1 fields */ 105 #define S_TXPKT_IPHDR_LEN 20 106 #define M_TXPKT_IPHDR_LEN 0x3FFF 107 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 108 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 109 110 #define S_TXPKT_ETHHDR_LEN 34 111 #define M_TXPKT_ETHHDR_LEN 0x3F 112 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 113 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 114 115 #define S_T6_TXPKT_ETHHDR_LEN 32 116 #define M_T6_TXPKT_ETHHDR_LEN 0xFF 117 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN) 118 #define G_T6_TXPKT_ETHHDR_LEN(x) \ 119 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN) 120 121 #define S_TXPKT_CSUM_TYPE 40 122 #define M_TXPKT_CSUM_TYPE 0xF 123 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 124 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 125 126 #define S_TXPKT_VLAN 44 127 #define M_TXPKT_VLAN 0xFFFF 128 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 129 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 130 131 #define S_TXPKT_VLAN_VLD 60 132 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 133 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 134 135 #define S_TXPKT_IPCSUM_DIS 62 136 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 137 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 138 139 #define S_TXPKT_L4CSUM_DIS 63 140 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 141 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 142 143 struct cpl_tx_pkt_lso_core { 144 __be32 lso_ctrl; 145 __be16 ipid_ofst; 146 __be16 mss; 147 __be32 seqno_offset; 148 __be32 len; 149 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 150 }; 151 152 struct cpl_tx_pkt_lso { 153 WR_HDR; 154 struct cpl_tx_pkt_lso_core c; 155 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 156 }; 157 158 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 159 #define S_LSO_TCPHDR_LEN 0 160 #define M_LSO_TCPHDR_LEN 0xF 161 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 162 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 163 164 #define S_LSO_IPHDR_LEN 4 165 #define M_LSO_IPHDR_LEN 0xFFF 166 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 167 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 168 169 #define S_LSO_ETHHDR_LEN 16 170 #define M_LSO_ETHHDR_LEN 0xF 171 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 172 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 173 174 #define S_LSO_IPV6 20 175 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 176 #define F_LSO_IPV6 V_LSO_IPV6(1U) 177 178 #define S_LSO_LAST_SLICE 22 179 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 180 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 181 182 #define S_LSO_FIRST_SLICE 23 183 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 184 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 185 186 #define S_LSO_OPCODE 24 187 #define M_LSO_OPCODE 0xFF 188 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 189 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 190 191 #define S_LSO_T5_XFER_SIZE 0 192 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF 193 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 194 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 195 196 struct cpl_rx_pkt { 197 RSS_HDR; 198 __u8 opcode; 199 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 200 __u8 iff:4; 201 __u8 csum_calc:1; 202 __u8 ipmi_pkt:1; 203 __u8 vlan_ex:1; 204 __u8 ip_frag:1; 205 #else 206 __u8 ip_frag:1; 207 __u8 vlan_ex:1; 208 __u8 ipmi_pkt:1; 209 __u8 csum_calc:1; 210 __u8 iff:4; 211 #endif 212 __be16 csum; 213 __be16 vlan; 214 __be16 len; 215 __be32 l2info; 216 __be16 hdr_len; 217 __be16 err_vec; 218 }; 219 220 /* rx_pkt.l2info fields */ 221 #define S_RXF_UDP 22 222 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 223 #define F_RXF_UDP V_RXF_UDP(1U) 224 225 #define S_RXF_TCP 23 226 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 227 #define F_RXF_TCP V_RXF_TCP(1U) 228 229 #define S_RXF_IP 24 230 #define V_RXF_IP(x) ((x) << S_RXF_IP) 231 #define F_RXF_IP V_RXF_IP(1U) 232 233 #define S_RXF_IP6 25 234 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 235 #define F_RXF_IP6 V_RXF_IP6(1U) 236 237 /* rx_pkt.err_vec fields */ 238 /* In T6, rx_pkt.err_vec indicates 239 * RxError Error vector (16b) or 240 * Encapsulating header length (8b), 241 * Outer encapsulation type (2b) and 242 * compressed error vector (6b) if CRxPktEnc is 243 * enabled in TP_OUT_CONFIG 244 */ 245 #define S_T6_COMPR_RXERR_VEC 0 246 #define M_T6_COMPR_RXERR_VEC 0x3F 247 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC) 248 #define G_T6_COMPR_RXERR_VEC(x) \ 249 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC) 250 251 /* cpl_fw*.type values */ 252 enum { 253 FW_TYPE_RSSCPL = 4, 254 }; 255 256 struct cpl_fw4_msg { 257 RSS_HDR; 258 u8 opcode; 259 u8 type; 260 __be16 rsvd0; 261 __be32 rsvd1; 262 __be64 data[2]; 263 }; 264 265 struct cpl_fw6_msg { 266 RSS_HDR; 267 u8 opcode; 268 u8 type; 269 __be16 rsvd0; 270 __be32 rsvd1; 271 __be64 data[4]; 272 }; 273 274 enum { 275 ULP_TX_SC_IMM = 0x81, 276 ULP_TX_SC_DSGL = 0x82, 277 ULP_TX_SC_ISGL = 0x83 278 }; 279 280 #define S_ULPTX_CMD 24 281 #define M_ULPTX_CMD 0xFF 282 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 283 284 #define S_ULP_TX_SC_MORE 23 285 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 286 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 287 288 struct ulptx_sge_pair { 289 __be32 len[2]; 290 __be64 addr[2]; 291 }; 292 293 struct ulptx_sgl { 294 __be32 cmd_nsge; 295 __be32 len0; 296 __be64 addr0; 297 298 #if !(defined C99_NOT_SUPPORTED) 299 struct ulptx_sge_pair sge[0]; 300 #endif 301 302 }; 303 304 struct ulptx_idata { 305 __be32 cmd_more; 306 __be32 len; 307 }; 308 309 #define S_ULPTX_NSGE 0 310 #define M_ULPTX_NSGE 0xFFFF 311 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 312 313 struct ulp_txpkt { 314 __be32 cmd_dest; 315 __be32 len; 316 }; 317 318 /* ulp_txpkt.cmd_dest fields */ 319 #define S_ULP_TXPKT_DEST 16 320 #define M_ULP_TXPKT_DEST 0x3 321 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 322 323 #define S_ULP_TXPKT_FID 4 324 #define M_ULP_TXPKT_FID 0x7ff 325 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 326 327 #define S_ULP_TXPKT_RO 3 328 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 329 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 330 331 #endif /* T4_MSG_H */ 332