1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 /* This file should not be included directly. Include common.h instead. */ 7 8 #ifndef __T4_ADAPTER_H__ 9 #define __T4_ADAPTER_H__ 10 11 #include <rte_bus_pci.h> 12 #include <rte_mbuf.h> 13 #include <rte_io.h> 14 #include <rte_rwlock.h> 15 #include <ethdev_driver.h> 16 17 #include "../cxgbe_compat.h" 18 #include "../cxgbe_ofld.h" 19 #include "t4_regs_values.h" 20 21 enum { 22 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */ 23 }; 24 25 struct adapter; 26 struct sge_rspq; 27 28 enum { 29 PORT_RSS_DONE = (1 << 0), 30 }; 31 32 struct port_info { 33 struct adapter *adapter; /* adapter that this port belongs to */ 34 struct rte_eth_dev *eth_dev; /* associated rte eth device */ 35 struct port_stats stats_base; /* port statistics base */ 36 struct link_config link_cfg; /* link configuration info */ 37 38 unsigned long flags; /* port related flags */ 39 short int xact_addr_filt; /* index of exact MAC address filter */ 40 41 u16 viid; /* associated virtual interface id */ 42 u8 port_id; /* physical port ID */ 43 u8 pidx; /* port index for this PF */ 44 u8 tx_chan; /* associated channel */ 45 46 u16 n_rx_qsets; /* # of rx qsets */ 47 u16 n_tx_qsets; /* # of tx qsets */ 48 u16 first_rxqset; /* index of first rxqset */ 49 u16 first_txqset; /* index of first txqset */ 50 51 u16 *rss; /* rss table */ 52 u8 rss_mode; /* rss mode */ 53 u16 rss_size; /* size of VI's RSS table slice */ 54 u64 rss_hf; /* RSS Hash Function */ 55 56 /* viid fields either returned by fw 57 * or decoded by parsing viid by driver. 58 */ 59 u8 vin; 60 u8 vivld; 61 62 u8 vi_en_rx; /* Enable/disable VI Rx */ 63 u8 vi_en_tx; /* Enable/disable VI Tx */ 64 }; 65 66 enum { /* adapter flags */ 67 FULL_INIT_DONE = (1 << 0), 68 USING_MSI = (1 << 1), 69 USING_MSIX = (1 << 2), 70 FW_QUEUE_BOUND = (1 << 3), 71 FW_OK = (1 << 4), 72 CFG_QUEUES = (1 << 5), 73 MASTER_PF = (1 << 6), 74 }; 75 76 struct rx_sw_desc { /* SW state per Rx descriptor */ 77 void *buf; /* struct page or mbuf */ 78 dma_addr_t dma_addr; 79 }; 80 81 struct sge_fl { /* SGE free-buffer queue state */ 82 /* RO fields */ 83 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */ 84 85 dma_addr_t addr; /* bus address of HW ring start */ 86 __be64 *desc; /* address of HW Rx descriptor ring */ 87 88 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 89 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 90 91 unsigned int cntxt_id; /* SGE relative QID for the free list */ 92 unsigned int size; /* capacity of free list */ 93 94 unsigned int avail; /* # of available Rx buffers */ 95 unsigned int pend_cred; /* new buffers since last FL DB ring */ 96 unsigned int cidx; /* consumer index */ 97 unsigned int pidx; /* producer index */ 98 99 unsigned long alloc_failed; /* # of times buffer allocation failed */ 100 unsigned long low; /* # of times momentarily starving */ 101 }; 102 103 #define MAX_MBUF_FRAGS (16384 / 512 + 2) 104 105 /* A packet gather list */ 106 struct pkt_gl { 107 union { 108 struct rte_mbuf *mbufs[MAX_MBUF_FRAGS]; 109 } /* UNNAMED */; 110 void *va; /* virtual address of first byte */ 111 unsigned int nfrags; /* # of fragments */ 112 unsigned int tot_len; /* total length of fragments */ 113 bool usembufs; /* use mbufs for fragments */ 114 }; 115 116 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp, 117 const struct pkt_gl *gl); 118 119 struct sge_rspq { /* state for an SGE response queue */ 120 struct adapter *adapter; /* adapter that this queue belongs to */ 121 struct rte_eth_dev *eth_dev; /* associated rte eth device */ 122 struct rte_mempool *mb_pool; /* associated mempool */ 123 124 dma_addr_t phys_addr; /* physical address of the ring */ 125 __be64 *desc; /* address of HW response ring */ 126 const __be64 *cur_desc; /* current descriptor in queue */ 127 128 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 129 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 130 struct sge_qstat *stat; 131 132 unsigned int cidx; /* consumer index */ 133 unsigned int gts_idx; /* last gts write sent */ 134 unsigned int iqe_len; /* entry size */ 135 unsigned int size; /* capacity of response queue */ 136 int offset; /* offset into current Rx buffer */ 137 138 u8 gen; /* current generation bit */ 139 u8 intr_params; /* interrupt holdoff parameters */ 140 u8 next_intr_params; /* holdoff params for next interrupt */ 141 u8 pktcnt_idx; /* interrupt packet threshold */ 142 u8 port_id; /* associated port-id */ 143 u8 idx; /* queue index within its group */ 144 u16 cntxt_id; /* SGE relative QID for the response Q */ 145 u16 abs_id; /* absolute SGE id for the response q */ 146 147 rspq_handler_t handler; /* associated handler for this response q */ 148 }; 149 150 struct sge_eth_rx_stats { /* Ethernet rx queue statistics */ 151 u64 pkts; /* # of ethernet packets */ 152 u64 rx_bytes; /* # of ethernet bytes */ 153 u64 rx_cso; /* # of Rx checksum offloads */ 154 u64 vlan_ex; /* # of Rx VLAN extractions */ 155 u64 rx_drops; /* # of packets dropped due to no mem */ 156 }; 157 158 struct sge_eth_rxq { /* a SW Ethernet Rx queue */ 159 unsigned int flags; /* flags for state of the queue */ 160 struct sge_rspq rspq; 161 struct sge_fl fl; 162 struct sge_eth_rx_stats stats; 163 bool usembufs; /* one ingress packet per mbuf FL buffer */ 164 } __rte_cache_aligned; 165 166 /* 167 * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per 168 * packet (if one sgl is present) and type 1 needs 32 bytes. This means 169 * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit 170 * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR 171 * to be able to free those mbufs when we get completions back from the FW. 172 * Allocating the maximum number of pointers in every tx desc is a waste 173 * of memory resources so we only store 2 pointers per tx desc which should 174 * be enough since a tx desc can only fit 2 packets in the best case 175 * scenario where a packet needs 32 bytes. 176 */ 177 #define ETH_COALESCE_PKT_NUM 15 178 #define ETH_COALESCE_VF_PKT_NUM 7 179 #define ETH_COALESCE_PKT_PER_DESC 2 180 181 struct tx_eth_coal_desc { 182 struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC]; 183 struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC]; 184 int idx; 185 }; 186 187 struct tx_desc { 188 __be64 flit[8]; 189 }; 190 191 struct tx_sw_desc { /* SW state per Tx descriptor */ 192 struct rte_mbuf *mbuf; 193 struct ulptx_sgl *sgl; 194 struct tx_eth_coal_desc coalesce; 195 }; 196 197 enum cxgbe_txq_state { 198 EQ_STOPPED = (1 << 0), 199 }; 200 201 enum cxgbe_rxq_state { 202 IQ_STOPPED = (1 << 0), 203 }; 204 205 struct eth_coalesce { 206 unsigned char *ptr; 207 unsigned char type; 208 unsigned int idx; 209 unsigned int len; 210 unsigned int flits; 211 unsigned int max; 212 __u8 ethmacdst[ETHER_ADDR_LEN]; 213 __u8 ethmacsrc[ETHER_ADDR_LEN]; 214 __be16 ethtype; 215 __be16 vlantci; 216 }; 217 218 struct sge_txq { 219 struct tx_desc *desc; /* address of HW Tx descriptor ring */ 220 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */ 221 struct sge_qstat *stat; /* queue status entry */ 222 struct eth_coalesce coalesce; /* coalesce info */ 223 224 uint64_t phys_addr; /* physical address of the ring */ 225 226 void __iomem *bar2_addr; /* address of BAR2 Queue registers */ 227 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */ 228 229 unsigned int cntxt_id; /* SGE relative QID for the Tx Q */ 230 unsigned int in_use; /* # of in-use Tx descriptors */ 231 unsigned int size; /* # of descriptors */ 232 unsigned int cidx; /* SW consumer index */ 233 unsigned int pidx; /* producer index */ 234 unsigned int dbidx; /* last idx when db ring was done */ 235 unsigned int equeidx; /* last sent credit request */ 236 unsigned int last_pidx; /* last pidx recorded by tx monitor */ 237 unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */ 238 unsigned int abs_id; 239 240 int db_disabled; /* doorbell state */ 241 unsigned short db_pidx; /* doorbell producer index */ 242 unsigned short db_pidx_inc; /* doorbell producer increment */ 243 }; 244 245 struct sge_eth_tx_stats { /* Ethernet tx queue statistics */ 246 u64 pkts; /* # of ethernet packets */ 247 u64 tx_bytes; /* # of ethernet bytes */ 248 u64 tso; /* # of TSO requests */ 249 u64 tx_cso; /* # of Tx checksum offloads */ 250 u64 vlan_ins; /* # of Tx VLAN insertions */ 251 u64 mapping_err; /* # of I/O MMU packet mapping errors */ 252 u64 coal_wr; /* # of coalesced wr */ 253 u64 coal_pkts; /* # of coalesced packets */ 254 }; 255 256 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ 257 struct sge_txq q; 258 struct rte_eth_dev *eth_dev; /* port that this queue belongs to */ 259 struct rte_eth_dev_data *data; 260 struct sge_eth_tx_stats stats; /* queue statistics */ 261 rte_spinlock_t txq_lock; 262 263 unsigned int flags; /* flags for state of the queue */ 264 } __rte_cache_aligned; 265 266 struct sge_ctrl_txq { /* State for an SGE control Tx queue */ 267 struct sge_txq q; /* txq */ 268 struct adapter *adapter; /* adapter associated with this queue */ 269 rte_spinlock_t ctrlq_lock; /* control queue lock */ 270 u8 full; /* the Tx ring is full */ 271 u64 txp; /* number of transmits */ 272 struct rte_mempool *mb_pool; /* mempool to generate ctrl pkts */ 273 } __rte_cache_aligned; 274 275 struct sge { 276 struct sge_eth_txq *ethtxq; 277 struct sge_eth_rxq *ethrxq; 278 struct sge_rspq fw_evtq __rte_cache_aligned; 279 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES]; 280 281 u16 max_ethqsets; /* # of available Ethernet queue sets */ 282 u32 stat_len; /* length of status page at ring end */ 283 u32 pktshift; /* padding between CPL & packet data */ 284 285 /* response queue interrupt parameters */ 286 u16 timer_val[SGE_NTIMERS]; 287 u8 counter_val[SGE_NCOUNTERS]; 288 289 u32 fl_align; /* response queue message alignment */ 290 u32 fl_pg_order; /* large page allocation size */ 291 u32 fl_starve_thres; /* Free List starvation threshold */ 292 }; 293 294 /* 295 * OS Lock/List primitives for those interfaces in the Common Code which 296 * need this. 297 */ 298 299 struct mbox_entry { 300 TAILQ_ENTRY(mbox_entry) next; 301 }; 302 303 TAILQ_HEAD(mbox_list, mbox_entry); 304 305 struct adapter_devargs { 306 bool keep_ovlan; 307 bool force_link_up; 308 bool tx_mode_latency; 309 u32 filtermode; 310 u32 filtermask; 311 }; 312 313 struct adapter { 314 struct rte_pci_device *pdev; /* associated rte pci device */ 315 struct rte_eth_dev *eth_dev; /* first port's rte eth device */ 316 struct adapter_params params; /* adapter parameters */ 317 struct port_info *port[MAX_NPORTS];/* ports belonging to this adapter */ 318 struct sge sge; /* associated SGE */ 319 320 /* support for single-threading access to adapter mailbox registers */ 321 struct mbox_list mbox_list; 322 rte_spinlock_t mbox_lock; 323 324 u8 *regs; /* pointer to registers region */ 325 u8 *bar2; /* pointer to bar2 region */ 326 unsigned long flags; /* adapter flags */ 327 unsigned int mbox; /* associated mailbox */ 328 unsigned int pf; /* associated physical function id */ 329 330 unsigned int vpd_busy; 331 unsigned int vpd_flag; 332 333 int use_unpacked_mode; /* unpacked rx mode state */ 334 rte_spinlock_t win0_lock; 335 336 rte_spinlock_t flow_lock; /* Serialize access for rte_flow ops */ 337 338 unsigned int clipt_start; /* CLIP table start */ 339 unsigned int clipt_end; /* CLIP table end */ 340 unsigned int l2t_start; /* Layer 2 table start */ 341 unsigned int l2t_end; /* Layer 2 table end */ 342 struct clip_tbl *clipt; /* CLIP table */ 343 struct l2t_data *l2t; /* Layer 2 table */ 344 struct smt_data *smt; /* Source mac table */ 345 struct mpstcam_table *mpstcam; 346 347 struct tid_info tids; /* Info used to access TID related tables */ 348 349 struct adapter_devargs devargs; 350 }; 351 352 /** 353 * t4_os_rwlock_init - initialize rwlock 354 * @lock: the rwlock 355 */ 356 static inline void t4_os_rwlock_init(rte_rwlock_t *lock) 357 { 358 rte_rwlock_init(lock); 359 } 360 361 /** 362 * t4_os_write_lock - get a write lock 363 * @lock: the rwlock 364 */ 365 static inline void t4_os_write_lock(rte_rwlock_t *lock) 366 { 367 rte_rwlock_write_lock(lock); 368 } 369 370 /** 371 * t4_os_write_unlock - unlock a write lock 372 * @lock: the rwlock 373 */ 374 static inline void t4_os_write_unlock(rte_rwlock_t *lock) 375 { 376 rte_rwlock_write_unlock(lock); 377 } 378 379 /** 380 * ethdev2pinfo - return the port_info structure associated with a rte_eth_dev 381 * @dev: the rte_eth_dev 382 * 383 * Return the struct port_info associated with a rte_eth_dev 384 */ 385 static inline struct port_info *ethdev2pinfo(const struct rte_eth_dev *dev) 386 { 387 return dev->data->dev_private; 388 } 389 390 /** 391 * adap2pinfo - return the port_info of a port 392 * @adap: the adapter 393 * @idx: the port index 394 * 395 * Return the port_info structure for the port of the given index. 396 */ 397 static inline struct port_info *adap2pinfo(const struct adapter *adap, int idx) 398 { 399 return adap->port[idx]; 400 } 401 402 /** 403 * ethdev2adap - return the adapter structure associated with a rte_eth_dev 404 * @dev: the rte_eth_dev 405 * 406 * Return the struct adapter associated with a rte_eth_dev 407 */ 408 static inline struct adapter *ethdev2adap(const struct rte_eth_dev *dev) 409 { 410 return ethdev2pinfo(dev)->adapter; 411 } 412 413 #define CXGBE_PCI_REG(reg) rte_read32(reg) 414 415 static inline uint64_t cxgbe_read_addr64(volatile void *addr) 416 { 417 uint64_t val = CXGBE_PCI_REG(addr); 418 uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4)); 419 420 val2 = (uint64_t)(val2 << 32); 421 val += val2; 422 return val; 423 } 424 425 static inline uint32_t cxgbe_read_addr(volatile void *addr) 426 { 427 return CXGBE_PCI_REG(addr); 428 } 429 430 #define CXGBE_PCI_REG_ADDR(adap, reg) \ 431 ((volatile uint32_t *)((char *)(adap)->regs + (reg))) 432 433 #define CXGBE_READ_REG(adap, reg) \ 434 cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg))) 435 436 #define CXGBE_READ_REG64(adap, reg) \ 437 cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg))) 438 439 #define CXGBE_PCI_REG_WRITE(reg, value) rte_write32((value), (reg)) 440 441 #define CXGBE_PCI_REG_WRITE_RELAXED(reg, value) \ 442 rte_write32_relaxed((value), (reg)) 443 444 #define CXGBE_WRITE_REG(adap, reg, value) \ 445 CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value)) 446 447 #define CXGBE_WRITE_REG_RELAXED(adap, reg, value) \ 448 CXGBE_PCI_REG_WRITE_RELAXED(CXGBE_PCI_REG_ADDR((adap), (reg)), (value)) 449 450 static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val) 451 { 452 CXGBE_PCI_REG_WRITE(addr, val); 453 CXGBE_PCI_REG_WRITE(((volatile uint8_t *)(addr) + 4), (val >> 32)); 454 return val; 455 } 456 457 #define CXGBE_WRITE_REG64(adap, reg, value) \ 458 cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value)) 459 460 /** 461 * t4_read_reg - read a HW register 462 * @adapter: the adapter 463 * @reg_addr: the register address 464 * 465 * Returns the 32-bit value of the given HW register. 466 */ 467 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr) 468 { 469 return CXGBE_READ_REG(adapter, reg_addr); 470 } 471 472 /** 473 * t4_write_reg - write a HW register with barrier 474 * @adapter: the adapter 475 * @reg_addr: the register address 476 * @val: the value to write 477 * 478 * Write a 32-bit value into the given HW register. 479 */ 480 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) 481 { 482 CXGBE_WRITE_REG(adapter, reg_addr, val); 483 } 484 485 /** 486 * t4_write_reg_relaxed - write a HW register with no barrier 487 * @adapter: the adapter 488 * @reg_addr: the register address 489 * @val: the value to write 490 * 491 * Write a 32-bit value into the given HW register. 492 */ 493 static inline void t4_write_reg_relaxed(struct adapter *adapter, u32 reg_addr, 494 u32 val) 495 { 496 CXGBE_WRITE_REG_RELAXED(adapter, reg_addr, val); 497 } 498 499 /** 500 * t4_read_reg64 - read a 64-bit HW register 501 * @adapter: the adapter 502 * @reg_addr: the register address 503 * 504 * Returns the 64-bit value of the given HW register. 505 */ 506 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr) 507 { 508 return CXGBE_READ_REG64(adapter, reg_addr); 509 } 510 511 /** 512 * t4_write_reg64 - write a 64-bit HW register 513 * @adapter: the adapter 514 * @reg_addr: the register address 515 * @val: the value to write 516 * 517 * Write a 64-bit value into the given HW register. 518 */ 519 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr, 520 u64 val) 521 { 522 CXGBE_WRITE_REG64(adapter, reg_addr, val); 523 } 524 525 #define PCI_STATUS 0x06 /* 16 bits */ 526 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 527 #define PCI_CAPABILITY_LIST 0x34 528 /* Offset of first capability list entry */ 529 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 530 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 531 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 532 #define PCI_EXP_DEVCTL 0x0008 /* Device control */ 533 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ 534 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ 535 #define PCI_EXP_DEVCTL_PAYLOAD 0x00E0 /* Max payload */ 536 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 537 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ 538 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ 539 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */ 540 541 /** 542 * t4_os_pci_write_cfg4 - 32-bit write to PCI config space 543 * @adapter: the adapter 544 * @addr: the register address 545 * @val: the value to write 546 * 547 * Write a 32-bit value into the given register in PCI config space. 548 */ 549 static inline void t4_os_pci_write_cfg4(struct adapter *adapter, size_t addr, 550 off_t val) 551 { 552 u32 val32 = val; 553 554 if (rte_pci_write_config(adapter->pdev, &val32, sizeof(val32), 555 addr) < 0) 556 dev_err(adapter, "Can't write to PCI config space\n"); 557 } 558 559 /** 560 * t4_os_pci_read_cfg4 - read a 32-bit value from PCI config space 561 * @adapter: the adapter 562 * @addr: the register address 563 * @val: where to store the value read 564 * 565 * Read a 32-bit value from the given register in PCI config space. 566 */ 567 static inline void t4_os_pci_read_cfg4(struct adapter *adapter, size_t addr, 568 u32 *val) 569 { 570 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val), 571 addr) < 0) 572 dev_err(adapter, "Can't read from PCI config space\n"); 573 } 574 575 /** 576 * t4_os_pci_write_cfg2 - 16-bit write to PCI config space 577 * @adapter: the adapter 578 * @addr: the register address 579 * @val: the value to write 580 * 581 * Write a 16-bit value into the given register in PCI config space. 582 */ 583 static inline void t4_os_pci_write_cfg2(struct adapter *adapter, size_t addr, 584 off_t val) 585 { 586 u16 val16 = val; 587 588 if (rte_pci_write_config(adapter->pdev, &val16, sizeof(val16), 589 addr) < 0) 590 dev_err(adapter, "Can't write to PCI config space\n"); 591 } 592 593 /** 594 * t4_os_pci_read_cfg2 - read a 16-bit value from PCI config space 595 * @adapter: the adapter 596 * @addr: the register address 597 * @val: where to store the value read 598 * 599 * Read a 16-bit value from the given register in PCI config space. 600 */ 601 static inline void t4_os_pci_read_cfg2(struct adapter *adapter, size_t addr, 602 u16 *val) 603 { 604 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val), 605 addr) < 0) 606 dev_err(adapter, "Can't read from PCI config space\n"); 607 } 608 609 /** 610 * t4_os_pci_read_cfg - read a 8-bit value from PCI config space 611 * @adapter: the adapter 612 * @addr: the register address 613 * @val: where to store the value read 614 * 615 * Read a 8-bit value from the given register in PCI config space. 616 */ 617 static inline void t4_os_pci_read_cfg(struct adapter *adapter, size_t addr, 618 u8 *val) 619 { 620 if (rte_pci_read_config(adapter->pdev, val, sizeof(*val), 621 addr) < 0) 622 dev_err(adapter, "Can't read from PCI config space\n"); 623 } 624 625 /** 626 * t4_os_find_pci_capability - lookup a capability in the PCI capability list 627 * @adapter: the adapter 628 * @cap: the capability 629 * 630 * Return the address of the given capability within the PCI capability list. 631 */ 632 static inline int t4_os_find_pci_capability(struct adapter *adapter, int cap) 633 { 634 u16 status; 635 int ttl = 48; 636 u8 pos = 0; 637 u8 id = 0; 638 639 t4_os_pci_read_cfg2(adapter, PCI_STATUS, &status); 640 if (!(status & PCI_STATUS_CAP_LIST)) { 641 dev_err(adapter, "PCIe capability reading failed\n"); 642 return -1; 643 } 644 645 t4_os_pci_read_cfg(adapter, PCI_CAPABILITY_LIST, &pos); 646 while (ttl-- && pos >= 0x40) { 647 pos &= ~3; 648 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_ID), &id); 649 650 if (id == 0xff) 651 break; 652 653 if (id == cap) 654 return (int)pos; 655 656 t4_os_pci_read_cfg(adapter, (pos + PCI_CAP_LIST_NEXT), &pos); 657 } 658 return 0; 659 } 660 661 /** 662 * t4_os_set_hw_addr - store a port's MAC address in SW 663 * @adapter: the adapter 664 * @port_idx: the port index 665 * @hw_addr: the Ethernet address 666 * 667 * Store the Ethernet address of the given port in SW. Called by the 668 * common code when it retrieves a port's Ethernet address from EEPROM. 669 */ 670 static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx, 671 u8 hw_addr[]) 672 { 673 struct port_info *pi = adap2pinfo(adapter, port_idx); 674 675 rte_ether_addr_copy((struct rte_ether_addr *)hw_addr, 676 &pi->eth_dev->data->mac_addrs[0]); 677 } 678 679 /** 680 * t4_os_lock_init - initialize spinlock 681 * @lock: the spinlock 682 */ 683 static inline void t4_os_lock_init(rte_spinlock_t *lock) 684 { 685 rte_spinlock_init(lock); 686 } 687 688 /** 689 * t4_os_lock - spin until lock is acquired 690 * @lock: the spinlock 691 */ 692 static inline void t4_os_lock(rte_spinlock_t *lock) 693 { 694 rte_spinlock_lock(lock); 695 } 696 697 /** 698 * t4_os_unlock - unlock a spinlock 699 * @lock: the spinlock 700 */ 701 static inline void t4_os_unlock(rte_spinlock_t *lock) 702 { 703 rte_spinlock_unlock(lock); 704 } 705 706 /** 707 * t4_os_trylock - try to get a lock 708 * @lock: the spinlock 709 */ 710 static inline int t4_os_trylock(rte_spinlock_t *lock) 711 { 712 return rte_spinlock_trylock(lock); 713 } 714 715 /** 716 * t4_os_init_list_head - initialize 717 * @head: head of list to initialize [to empty] 718 */ 719 static inline void t4_os_init_list_head(struct mbox_list *head) 720 { 721 TAILQ_INIT(head); 722 } 723 724 static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head) 725 { 726 return TAILQ_FIRST(head); 727 } 728 729 /** 730 * t4_os_atomic_add_tail - Enqueue list element atomically onto list 731 * @new: the entry to be addded to the queue 732 * @head: current head of the linked list 733 * @lock: lock to use to guarantee atomicity 734 */ 735 static inline void t4_os_atomic_add_tail(struct mbox_entry *entry, 736 struct mbox_list *head, 737 rte_spinlock_t *lock) 738 { 739 t4_os_lock(lock); 740 TAILQ_INSERT_TAIL(head, entry, next); 741 t4_os_unlock(lock); 742 } 743 744 /** 745 * t4_os_atomic_list_del - Dequeue list element atomically from list 746 * @entry: the entry to be remove/dequeued from the list. 747 * @lock: the spinlock 748 */ 749 static inline void t4_os_atomic_list_del(struct mbox_entry *entry, 750 struct mbox_list *head, 751 rte_spinlock_t *lock) 752 { 753 t4_os_lock(lock); 754 TAILQ_REMOVE(head, entry, next); 755 t4_os_unlock(lock); 756 } 757 758 /** 759 * t4_init_completion - initialize completion 760 * @c: the completion context 761 */ 762 static inline void t4_init_completion(struct t4_completion *c) 763 { 764 c->done = 0; 765 t4_os_lock_init(&c->lock); 766 } 767 768 /** 769 * t4_complete - set completion as done 770 * @c: the completion context 771 */ 772 static inline void t4_complete(struct t4_completion *c) 773 { 774 t4_os_lock(&c->lock); 775 c->done = 1; 776 t4_os_unlock(&c->lock); 777 } 778 779 /** 780 * cxgbe_port_viid - get the VI id of a port 781 * @dev: the device for the port 782 * 783 * Return the VI id of the given port. 784 */ 785 static inline unsigned int cxgbe_port_viid(const struct rte_eth_dev *dev) 786 { 787 return ethdev2pinfo(dev)->viid; 788 } 789 790 void *t4_alloc_mem(size_t size); 791 void t4_free_mem(void *addr); 792 #define t4_os_alloc(_size) t4_alloc_mem((_size)) 793 #define t4_os_free(_ptr) t4_free_mem((_ptr)) 794 795 void t4_os_portmod_changed(const struct adapter *adap, int port_id); 796 void t4_os_link_changed(struct adapter *adap, int port_id); 797 798 void reclaim_completed_tx(struct sge_txq *q); 799 void t4_free_sge_resources(struct adapter *adap); 800 void t4_sge_tx_monitor_start(struct adapter *adap); 801 void t4_sge_tx_monitor_stop(struct adapter *adap); 802 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf, 803 uint16_t nb_pkts); 804 int t4_mgmt_tx(struct sge_ctrl_txq *txq, struct rte_mbuf *mbuf); 805 int t4_sge_init(struct adapter *adap); 806 int t4vf_sge_init(struct adapter *adap); 807 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, 808 struct rte_eth_dev *eth_dev, uint16_t queue_id, 809 unsigned int iqid, int socket_id); 810 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, 811 struct rte_eth_dev *eth_dev, uint16_t queue_id, 812 unsigned int iqid, int socket_id); 813 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq, 814 struct rte_eth_dev *eth_dev, int intr_idx, 815 struct sge_fl *fl, rspq_handler_t handler, 816 int cong, struct rte_mempool *mp, int queue_id, 817 int socket_id); 818 int t4_sge_eth_txq_start(struct sge_eth_txq *txq); 819 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq); 820 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq); 821 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_eth_rxq *rxq); 822 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_eth_rxq *rxq); 823 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq); 824 void t4_sge_eth_clear_queues(struct port_info *pi); 825 void t4_sge_eth_release_queues(struct port_info *pi); 826 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 827 unsigned int cnt); 828 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts, 829 unsigned int budget, unsigned int *work_done); 830 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues); 831 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t flags); 832 833 #endif /* __T4_ADAPTER_H__ */ 834