1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #include <cnxk_ethdev.h> 6 7 int 8 cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) 9 { 10 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 11 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 12 int max_rx_pktlen; 13 14 max_rx_pktlen = (roc_nix_max_pkt_len(&dev->nix) + RTE_ETHER_CRC_LEN - 15 CNXK_NIX_MAX_VTAG_ACT_SIZE); 16 17 devinfo->min_rx_bufsize = NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN; 18 devinfo->max_rx_pktlen = max_rx_pktlen; 19 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT; 20 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT; 21 devinfo->max_mac_addrs = dev->max_mac_entries; 22 devinfo->max_vfs = pci_dev->max_vfs; 23 devinfo->max_mtu = devinfo->max_rx_pktlen - 24 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN); 25 devinfo->min_mtu = devinfo->min_rx_bufsize - CNXK_NIX_L2_OVERHEAD; 26 27 devinfo->rx_offload_capa = dev->rx_offload_capa; 28 devinfo->tx_offload_capa = dev->tx_offload_capa; 29 devinfo->rx_queue_offload_capa = 0; 30 devinfo->tx_queue_offload_capa = 0; 31 32 devinfo->reta_size = dev->nix.reta_sz; 33 devinfo->hash_key_size = ROC_NIX_RSS_KEY_LEN; 34 devinfo->flow_type_rss_offloads = CNXK_NIX_RSS_OFFLOAD; 35 36 devinfo->default_rxconf = (struct rte_eth_rxconf){ 37 .rx_drop_en = 0, 38 .offloads = 0, 39 }; 40 41 devinfo->default_txconf = (struct rte_eth_txconf){ 42 .offloads = 0, 43 }; 44 45 devinfo->default_rxportconf = (struct rte_eth_dev_portconf){ 46 .ring_size = CNXK_NIX_RX_DEFAULT_RING_SZ, 47 }; 48 49 devinfo->rx_desc_lim = (struct rte_eth_desc_lim){ 50 .nb_max = UINT16_MAX, 51 .nb_min = CNXK_NIX_RX_MIN_DESC, 52 .nb_align = CNXK_NIX_RX_MIN_DESC_ALIGN, 53 .nb_seg_max = CNXK_NIX_RX_NB_SEG_MAX, 54 .nb_mtu_seg_max = CNXK_NIX_RX_NB_SEG_MAX, 55 }; 56 devinfo->rx_desc_lim.nb_max = 57 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max, 58 CNXK_NIX_RX_MIN_DESC_ALIGN); 59 60 devinfo->tx_desc_lim = (struct rte_eth_desc_lim){ 61 .nb_max = UINT16_MAX, 62 .nb_min = 1, 63 .nb_align = 1, 64 .nb_seg_max = CNXK_NIX_TX_NB_SEG_MAX, 65 .nb_mtu_seg_max = CNXK_NIX_TX_NB_SEG_MAX, 66 }; 67 68 devinfo->speed_capa = dev->speed_capa; 69 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 70 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 71 devinfo->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 72 return 0; 73 } 74 75 int 76 cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id, 77 struct rte_eth_burst_mode *mode) 78 { 79 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc; 80 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 81 const struct burst_info { 82 uint64_t flags; 83 const char *output; 84 } rx_offload_map[] = { 85 {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN Strip,"}, 86 {RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " Inner IPv4 Checksum,"}, 87 {RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP Checksum,"}, 88 {RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP Checksum,"}, 89 {RTE_ETH_RX_OFFLOAD_TCP_LRO, " TCP LRO,"}, 90 {RTE_ETH_RX_OFFLOAD_QINQ_STRIP, " QinQ VLAN Strip,"}, 91 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPv4 Checksum,"}, 92 {RTE_ETH_RX_OFFLOAD_MACSEC_STRIP, " MACsec Strip,"}, 93 {RTE_ETH_RX_OFFLOAD_HEADER_SPLIT, " Header Split,"}, 94 {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN Filter,"}, 95 {RTE_ETH_RX_OFFLOAD_VLAN_EXTEND, " VLAN Extend,"}, 96 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}, 97 {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"}, 98 {RTE_ETH_RX_OFFLOAD_SECURITY, " Security,"}, 99 {RTE_ETH_RX_OFFLOAD_KEEP_CRC, " Keep CRC,"}, 100 {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP,"}, 101 {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP Checksum,"}, 102 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"} 103 }; 104 static const char *const burst_mode[] = {"Vector Neon, Rx Offloads:", 105 "Scalar, Rx Offloads:" 106 }; 107 uint32_t i; 108 109 PLT_SET_USED(queue_id); 110 111 /* Update burst mode info */ 112 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena], 113 str_size - bytes); 114 if (rc < 0) 115 goto done; 116 117 bytes += rc; 118 119 /* Update Rx offload info */ 120 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 121 if (dev->rx_offloads & rx_offload_map[i].flags) { 122 rc = rte_strscpy(mode->info + bytes, 123 rx_offload_map[i].output, 124 str_size - bytes); 125 if (rc < 0) 126 goto done; 127 128 bytes += rc; 129 } 130 } 131 132 done: 133 return 0; 134 } 135 136 int 137 cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id, 138 struct rte_eth_burst_mode *mode) 139 { 140 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc; 141 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 142 const struct burst_info { 143 uint64_t flags; 144 const char *output; 145 } tx_offload_map[] = { 146 {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"}, 147 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " Inner IPv4 Checksum,"}, 148 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP Checksum,"}, 149 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP Checksum,"}, 150 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP Checksum,"}, 151 {RTE_ETH_TX_OFFLOAD_TCP_TSO, " TCP TSO,"}, 152 {RTE_ETH_TX_OFFLOAD_UDP_TSO, " UDP TSO,"}, 153 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPv4 Checksum,"}, 154 {RTE_ETH_TX_OFFLOAD_QINQ_INSERT, " QinQ VLAN Insert,"}, 155 {RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO, " VXLAN Tunnel TSO,"}, 156 {RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO, " GRE Tunnel TSO,"}, 157 {RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO, " IP-in-IP Tunnel TSO,"}, 158 {RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO, " Geneve Tunnel TSO,"}, 159 {RTE_ETH_TX_OFFLOAD_MACSEC_INSERT, " MACsec Insert,"}, 160 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " Multi Thread Lockless Tx,"}, 161 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}, 162 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " H/W MBUF Free,"}, 163 {RTE_ETH_TX_OFFLOAD_SECURITY, " Security,"}, 164 {RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO, " UDP Tunnel TSO,"}, 165 {RTE_ETH_TX_OFFLOAD_IP_TNL_TSO, " IP Tunnel TSO,"}, 166 {RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP Checksum,"}, 167 {RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP, " Timestamp,"} 168 }; 169 static const char *const burst_mode[] = {"Vector Neon, Tx Offloads:", 170 "Scalar, Tx Offloads:" 171 }; 172 uint32_t i; 173 174 PLT_SET_USED(queue_id); 175 176 /* Update burst mode info */ 177 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena], 178 str_size - bytes); 179 if (rc < 0) 180 goto done; 181 182 bytes += rc; 183 184 /* Update Tx offload info */ 185 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 186 if (dev->tx_offloads & tx_offload_map[i].flags) { 187 rc = rte_strscpy(mode->info + bytes, 188 tx_offload_map[i].output, 189 str_size - bytes); 190 if (rc < 0) 191 goto done; 192 193 bytes += rc; 194 } 195 } 196 197 done: 198 return 0; 199 } 200 201 int 202 cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev, 203 struct rte_eth_fc_conf *fc_conf) 204 { 205 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 206 enum rte_eth_fc_mode mode_map[] = { 207 RTE_ETH_FC_NONE, RTE_ETH_FC_RX_PAUSE, 208 RTE_ETH_FC_TX_PAUSE, RTE_ETH_FC_FULL 209 }; 210 struct roc_nix *nix = &dev->nix; 211 int mode; 212 213 mode = roc_nix_fc_mode_get(nix); 214 if (mode < 0) 215 return mode; 216 217 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 218 fc_conf->mode = mode_map[mode]; 219 return 0; 220 } 221 222 static int 223 nix_fc_cq_config_set(struct cnxk_eth_dev *dev, uint16_t qid, bool enable) 224 { 225 struct roc_nix *nix = &dev->nix; 226 struct roc_nix_fc_cfg fc_cfg; 227 struct roc_nix_cq *cq; 228 229 memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg)); 230 cq = &dev->cqs[qid]; 231 fc_cfg.type = ROC_NIX_FC_CQ_CFG; 232 fc_cfg.cq_cfg.enable = enable; 233 fc_cfg.cq_cfg.rq = qid; 234 fc_cfg.cq_cfg.cq_drop = cq->drop_thresh; 235 236 return roc_nix_fc_config_set(nix, &fc_cfg); 237 } 238 239 int 240 cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev, 241 struct rte_eth_fc_conf *fc_conf) 242 { 243 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 244 enum roc_nix_fc_mode mode_map[] = { 245 ROC_NIX_FC_NONE, ROC_NIX_FC_RX, 246 ROC_NIX_FC_TX, ROC_NIX_FC_FULL 247 }; 248 struct rte_eth_dev_data *data = eth_dev->data; 249 struct cnxk_fc_cfg *fc = &dev->fc_cfg; 250 struct roc_nix *nix = &dev->nix; 251 uint8_t rx_pause, tx_pause; 252 int rc, i; 253 254 if (roc_nix_is_vf_or_sdp(nix) && !roc_nix_is_lbk(nix)) { 255 plt_err("Flow control configuration is not allowed on VFs"); 256 return -ENOTSUP; 257 } 258 259 if (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time || 260 fc_conf->mac_ctrl_frame_fwd || fc_conf->autoneg) { 261 plt_info("Only MODE configuration is supported"); 262 return -EINVAL; 263 } 264 265 if (fc_conf->mode == fc->mode) 266 return 0; 267 268 rx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) || 269 (fc_conf->mode == RTE_ETH_FC_RX_PAUSE); 270 tx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) || 271 (fc_conf->mode == RTE_ETH_FC_TX_PAUSE); 272 273 /* Check if TX pause frame is already enabled or not */ 274 if (fc->tx_pause ^ tx_pause) { 275 if (roc_model_is_cn96_ax() && data->dev_started) { 276 /* On Ax, CQ should be in disabled state 277 * while setting flow control configuration. 278 */ 279 plt_info("Stop the port=%d for setting flow control", 280 data->port_id); 281 return 0; 282 } 283 284 for (i = 0; i < data->nb_rx_queues; i++) { 285 rc = nix_fc_cq_config_set(dev, i, tx_pause); 286 if (rc) 287 return rc; 288 } 289 } 290 291 /* Check if RX pause frame is enabled or not */ 292 if (fc->rx_pause ^ rx_pause) { 293 struct roc_nix_fc_cfg fc_cfg; 294 295 memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg)); 296 fc_cfg.type = ROC_NIX_FC_TM_CFG; 297 fc_cfg.tm_cfg.enable = !!rx_pause; 298 rc = roc_nix_fc_config_set(nix, &fc_cfg); 299 if (rc) 300 return rc; 301 } 302 303 rc = roc_nix_fc_mode_set(nix, mode_map[fc_conf->mode]); 304 if (rc) 305 return rc; 306 307 fc->rx_pause = rx_pause; 308 fc->tx_pause = tx_pause; 309 fc->mode = fc_conf->mode; 310 311 return rc; 312 } 313 314 int 315 cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev, 316 const struct rte_flow_ops **ops) 317 { 318 RTE_SET_USED(eth_dev); 319 320 *ops = &cnxk_flow_ops; 321 return 0; 322 } 323 324 int 325 cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr) 326 { 327 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 328 struct roc_nix *nix = &dev->nix; 329 int rc; 330 331 /* Update mac address at NPC */ 332 rc = roc_nix_npc_mac_addr_set(nix, addr->addr_bytes); 333 if (rc) 334 goto exit; 335 336 /* Update mac address at CGX for PFs only */ 337 if (!roc_nix_is_vf_or_sdp(nix)) { 338 rc = roc_nix_mac_addr_set(nix, addr->addr_bytes); 339 if (rc) { 340 /* Rollback to previous mac address */ 341 roc_nix_npc_mac_addr_set(nix, dev->mac_addr); 342 goto exit; 343 } 344 } 345 346 /* Update mac address to cnxk ethernet device */ 347 rte_memcpy(dev->mac_addr, addr->addr_bytes, RTE_ETHER_ADDR_LEN); 348 349 exit: 350 return rc; 351 } 352 353 int 354 cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr, 355 uint32_t index, uint32_t pool) 356 { 357 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 358 struct roc_nix *nix = &dev->nix; 359 int rc; 360 361 PLT_SET_USED(index); 362 PLT_SET_USED(pool); 363 364 rc = roc_nix_mac_addr_add(nix, addr->addr_bytes); 365 if (rc < 0) { 366 plt_err("Failed to add mac address, rc=%d", rc); 367 return rc; 368 } 369 370 /* Enable promiscuous mode at NIX level */ 371 roc_nix_npc_promisc_ena_dis(nix, true); 372 dev->dmac_filter_enable = true; 373 eth_dev->data->promiscuous = false; 374 dev->dmac_filter_count++; 375 376 return 0; 377 } 378 379 void 380 cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index) 381 { 382 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 383 struct roc_nix *nix = &dev->nix; 384 int rc; 385 386 rc = roc_nix_mac_addr_del(nix, index); 387 if (rc) 388 plt_err("Failed to delete mac address, rc=%d", rc); 389 390 dev->dmac_filter_count--; 391 } 392 393 int 394 cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 395 { 396 uint32_t old_frame_size, frame_size = mtu + CNXK_NIX_L2_OVERHEAD; 397 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 398 struct rte_eth_dev_data *data = eth_dev->data; 399 struct roc_nix *nix = &dev->nix; 400 int rc = -EINVAL; 401 uint32_t buffsz; 402 403 frame_size += CNXK_NIX_TIMESYNC_RX_OFFSET * dev->ptp_en; 404 405 /* Check if MTU is within the allowed range */ 406 if ((frame_size - RTE_ETHER_CRC_LEN) < NIX_MIN_HW_FRS) { 407 plt_err("MTU is lesser than minimum"); 408 goto exit; 409 } 410 411 if ((frame_size - RTE_ETHER_CRC_LEN) > 412 ((uint32_t)roc_nix_max_pkt_len(nix))) { 413 plt_err("MTU is greater than maximum"); 414 goto exit; 415 } 416 417 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 418 old_frame_size = data->mtu + CNXK_NIX_L2_OVERHEAD; 419 420 /* Refuse MTU that requires the support of scattered packets 421 * when this feature has not been enabled before. 422 */ 423 if (data->dev_started && frame_size > buffsz && 424 !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)) { 425 plt_err("Scatter offload is not enabled for mtu"); 426 goto exit; 427 } 428 429 /* Check <seg size> * <max_seg> >= max_frame */ 430 if ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) && 431 frame_size > (buffsz * CNXK_NIX_RX_NB_SEG_MAX)) { 432 plt_err("Greater than maximum supported packet length"); 433 goto exit; 434 } 435 436 frame_size -= RTE_ETHER_CRC_LEN; 437 438 /* Update mtu on Tx */ 439 rc = roc_nix_mac_mtu_set(nix, frame_size); 440 if (rc) { 441 plt_err("Failed to set MTU, rc=%d", rc); 442 goto exit; 443 } 444 445 /* Sync same frame size on Rx */ 446 rc = roc_nix_mac_max_rx_len_set(nix, frame_size); 447 if (rc) { 448 /* Rollback to older mtu */ 449 roc_nix_mac_mtu_set(nix, 450 old_frame_size - RTE_ETHER_CRC_LEN); 451 plt_err("Failed to max Rx frame length, rc=%d", rc); 452 goto exit; 453 } 454 exit: 455 return rc; 456 } 457 458 int 459 cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev) 460 { 461 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 462 struct roc_nix *nix = &dev->nix; 463 int rc = 0; 464 465 if (roc_nix_is_vf_or_sdp(nix)) 466 return rc; 467 468 rc = roc_nix_npc_promisc_ena_dis(nix, true); 469 if (rc) { 470 plt_err("Failed to setup promisc mode in npc, rc=%d(%s)", rc, 471 roc_error_msg_get(rc)); 472 return rc; 473 } 474 475 rc = roc_nix_mac_promisc_mode_enable(nix, true); 476 if (rc) { 477 plt_err("Failed to setup promisc mode in mac, rc=%d(%s)", rc, 478 roc_error_msg_get(rc)); 479 roc_nix_npc_promisc_ena_dis(nix, false); 480 return rc; 481 } 482 483 return 0; 484 } 485 486 int 487 cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev) 488 { 489 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 490 struct roc_nix *nix = &dev->nix; 491 int rc = 0; 492 493 if (roc_nix_is_vf_or_sdp(nix)) 494 return rc; 495 496 rc = roc_nix_npc_promisc_ena_dis(nix, dev->dmac_filter_enable); 497 if (rc) { 498 plt_err("Failed to setup promisc mode in npc, rc=%d(%s)", rc, 499 roc_error_msg_get(rc)); 500 return rc; 501 } 502 503 rc = roc_nix_mac_promisc_mode_enable(nix, false); 504 if (rc) { 505 plt_err("Failed to setup promisc mode in mac, rc=%d(%s)", rc, 506 roc_error_msg_get(rc)); 507 roc_nix_npc_promisc_ena_dis(nix, !dev->dmac_filter_enable); 508 return rc; 509 } 510 511 dev->dmac_filter_enable = false; 512 return 0; 513 } 514 515 int 516 cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev) 517 { 518 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 519 520 return roc_nix_npc_mcast_config(&dev->nix, true, false); 521 } 522 523 int 524 cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev) 525 { 526 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 527 528 return roc_nix_npc_mcast_config(&dev->nix, false, 529 eth_dev->data->promiscuous); 530 } 531 532 int 533 cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev) 534 { 535 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 536 struct roc_nix *nix = &dev->nix; 537 int rc, i; 538 539 if (roc_nix_is_vf_or_sdp(nix)) 540 return -ENOTSUP; 541 542 rc = roc_nix_mac_link_state_set(nix, true); 543 if (rc) 544 goto exit; 545 546 /* Start tx queues */ 547 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) { 548 rc = cnxk_nix_tx_queue_start(eth_dev, i); 549 if (rc) 550 goto exit; 551 } 552 553 exit: 554 return rc; 555 } 556 557 int 558 cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev) 559 { 560 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 561 struct roc_nix *nix = &dev->nix; 562 int rc, i; 563 564 if (roc_nix_is_vf_or_sdp(nix)) 565 return -ENOTSUP; 566 567 /* Stop tx queues */ 568 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) { 569 rc = cnxk_nix_tx_queue_stop(eth_dev, i); 570 if (rc) 571 goto exit; 572 } 573 574 rc = roc_nix_mac_link_state_set(nix, false); 575 exit: 576 return rc; 577 } 578 579 int 580 cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev, 581 struct rte_eth_dev_module_info *modinfo) 582 { 583 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 584 struct roc_nix_eeprom_info eeprom_info = {0}; 585 struct roc_nix *nix = &dev->nix; 586 int rc; 587 588 rc = roc_nix_eeprom_info_get(nix, &eeprom_info); 589 if (rc) 590 return rc; 591 592 modinfo->type = eeprom_info.sff_id; 593 modinfo->eeprom_len = ROC_NIX_EEPROM_SIZE; 594 return 0; 595 } 596 597 int 598 cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev, 599 struct rte_dev_eeprom_info *info) 600 { 601 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 602 struct roc_nix_eeprom_info eeprom_info = {0}; 603 struct roc_nix *nix = &dev->nix; 604 int rc = -EINVAL; 605 606 if (!info->data || !info->length || 607 (info->offset + info->length > ROC_NIX_EEPROM_SIZE)) 608 return rc; 609 610 rc = roc_nix_eeprom_info_get(nix, &eeprom_info); 611 if (rc) 612 return rc; 613 614 rte_memcpy(info->data, eeprom_info.buf + info->offset, info->length); 615 return 0; 616 } 617 618 int 619 cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 620 { 621 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 622 623 roc_nix_rx_queue_intr_enable(&dev->nix, rx_queue_id); 624 return 0; 625 } 626 627 int 628 cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 629 uint16_t rx_queue_id) 630 { 631 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 632 633 roc_nix_rx_queue_intr_disable(&dev->nix, rx_queue_id); 634 return 0; 635 } 636 637 int 638 cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool) 639 { 640 RTE_SET_USED(eth_dev); 641 642 if (!strcmp(pool, rte_mbuf_platform_mempool_ops())) 643 return 0; 644 645 return -ENOTSUP; 646 } 647 648 int 649 cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 650 size_t fw_size) 651 { 652 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 653 const char *str = roc_npc_profile_name_get(&dev->npc); 654 uint32_t size = strlen(str) + 1; 655 656 if (fw_size > size) 657 fw_size = size; 658 659 rte_strlcpy(fw_version, str, fw_size); 660 661 if (fw_size < size) 662 return size; 663 664 return 0; 665 } 666 667 void 668 cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid, 669 struct rte_eth_rxq_info *qinfo) 670 { 671 void *rxq = eth_dev->data->rx_queues[qid]; 672 struct cnxk_eth_rxq_sp *rxq_sp = cnxk_eth_rxq_to_sp(rxq); 673 674 memset(qinfo, 0, sizeof(*qinfo)); 675 676 qinfo->mp = rxq_sp->qconf.mp; 677 qinfo->scattered_rx = eth_dev->data->scattered_rx; 678 qinfo->nb_desc = rxq_sp->qconf.nb_desc; 679 680 memcpy(&qinfo->conf, &rxq_sp->qconf.conf.rx, sizeof(qinfo->conf)); 681 } 682 683 void 684 cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid, 685 struct rte_eth_txq_info *qinfo) 686 { 687 void *txq = eth_dev->data->tx_queues[qid]; 688 struct cnxk_eth_txq_sp *txq_sp = cnxk_eth_txq_to_sp(txq); 689 690 memset(qinfo, 0, sizeof(*qinfo)); 691 692 qinfo->nb_desc = txq_sp->qconf.nb_desc; 693 694 memcpy(&qinfo->conf, &txq_sp->qconf.conf.tx, sizeof(qinfo->conf)); 695 } 696 697 /* It is a NOP for cnxk as HW frees the buffer on xmit */ 698 int 699 cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt) 700 { 701 RTE_SET_USED(txq); 702 RTE_SET_USED(free_cnt); 703 704 return 0; 705 } 706 707 int 708 cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) 709 { 710 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 711 struct roc_nix *nix = &dev->nix; 712 uint64_t *data = regs->data; 713 int rc = -ENOTSUP; 714 715 if (data == NULL) { 716 rc = roc_nix_lf_get_reg_count(nix); 717 if (rc > 0) { 718 regs->length = rc; 719 regs->width = 8; 720 rc = 0; 721 } 722 return rc; 723 } 724 725 if (!regs->length || 726 regs->length == (uint32_t)roc_nix_lf_get_reg_count(nix)) 727 return roc_nix_lf_reg_dump(nix, data); 728 729 return rc; 730 } 731 732 int 733 cnxk_nix_reta_update(struct rte_eth_dev *eth_dev, 734 struct rte_eth_rss_reta_entry64 *reta_conf, 735 uint16_t reta_size) 736 { 737 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 738 uint16_t reta[ROC_NIX_RSS_RETA_MAX]; 739 struct roc_nix *nix = &dev->nix; 740 int i, j, rc = -EINVAL, idx = 0; 741 742 if (reta_size != dev->nix.reta_sz) { 743 plt_err("Size of hash lookup table configured (%d) does not " 744 "match the number hardware can supported (%d)", 745 reta_size, dev->nix.reta_sz); 746 goto fail; 747 } 748 749 /* Copy RETA table */ 750 for (i = 0; i < (int)(dev->nix.reta_sz / RTE_ETH_RETA_GROUP_SIZE); i++) { 751 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) { 752 if ((reta_conf[i].mask >> j) & 0x01) 753 reta[idx] = reta_conf[i].reta[j]; 754 idx++; 755 } 756 } 757 758 return roc_nix_rss_reta_set(nix, 0, reta); 759 760 fail: 761 return rc; 762 } 763 764 int 765 cnxk_nix_reta_query(struct rte_eth_dev *eth_dev, 766 struct rte_eth_rss_reta_entry64 *reta_conf, 767 uint16_t reta_size) 768 { 769 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 770 uint16_t reta[ROC_NIX_RSS_RETA_MAX]; 771 struct roc_nix *nix = &dev->nix; 772 int rc = -EINVAL, i, j, idx = 0; 773 774 if (reta_size != dev->nix.reta_sz) { 775 plt_err("Size of hash lookup table configured (%d) does not " 776 "match the number hardware can supported (%d)", 777 reta_size, dev->nix.reta_sz); 778 goto fail; 779 } 780 781 rc = roc_nix_rss_reta_get(nix, 0, reta); 782 if (rc) 783 goto fail; 784 785 /* Copy RETA table */ 786 for (i = 0; i < (int)(dev->nix.reta_sz / RTE_ETH_RETA_GROUP_SIZE); i++) { 787 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) { 788 if ((reta_conf[i].mask >> j) & 0x01) 789 reta_conf[i].reta[j] = reta[idx]; 790 idx++; 791 } 792 } 793 794 return 0; 795 796 fail: 797 return rc; 798 } 799 800 int 801 cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev, 802 struct rte_eth_rss_conf *rss_conf) 803 { 804 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 805 struct roc_nix *nix = &dev->nix; 806 uint8_t rss_hash_level; 807 uint32_t flowkey_cfg; 808 int rc = -EINVAL; 809 uint8_t alg_idx; 810 811 if (rss_conf->rss_key && rss_conf->rss_key_len != ROC_NIX_RSS_KEY_LEN) { 812 plt_err("Hash key size mismatch %d vs %d", 813 rss_conf->rss_key_len, ROC_NIX_RSS_KEY_LEN); 814 goto fail; 815 } 816 817 if (rss_conf->rss_key) 818 roc_nix_rss_key_set(nix, rss_conf->rss_key); 819 820 rss_hash_level = RTE_ETH_RSS_LEVEL(rss_conf->rss_hf); 821 if (rss_hash_level) 822 rss_hash_level -= 1; 823 flowkey_cfg = 824 cnxk_rss_ethdev_to_nix(dev, rss_conf->rss_hf, rss_hash_level); 825 826 rc = roc_nix_rss_flowkey_set(nix, &alg_idx, flowkey_cfg, 827 ROC_NIX_RSS_GROUP_DEFAULT, 828 ROC_NIX_RSS_MCAM_IDX_DEFAULT); 829 if (rc) { 830 plt_err("Failed to set RSS hash function rc=%d", rc); 831 return rc; 832 } 833 834 fail: 835 return rc; 836 } 837 838 int 839 cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 840 struct rte_eth_rss_conf *rss_conf) 841 { 842 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 843 844 if (rss_conf->rss_key) 845 roc_nix_rss_key_get(&dev->nix, rss_conf->rss_key); 846 847 rss_conf->rss_key_len = ROC_NIX_RSS_KEY_LEN; 848 rss_conf->rss_hf = dev->ethdev_rss_hf; 849 850 return 0; 851 } 852 853 int 854 cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev, 855 struct rte_ether_addr *mc_addr_set, 856 uint32_t nb_mc_addr) 857 { 858 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 859 struct rte_eth_dev_data *data = eth_dev->data; 860 struct rte_ether_addr null_mac_addr; 861 struct roc_nix *nix = &dev->nix; 862 int rc, index; 863 uint32_t i; 864 865 memset(&null_mac_addr, 0, sizeof(null_mac_addr)); 866 867 /* All configured multicast filters should be flushed first */ 868 for (i = 0; i < dev->max_mac_entries; i++) { 869 if (rte_is_multicast_ether_addr(&data->mac_addrs[i])) { 870 rc = roc_nix_mac_addr_del(nix, i); 871 if (rc) { 872 plt_err("Failed to flush mcast address, rc=%d", 873 rc); 874 return rc; 875 } 876 877 dev->dmac_filter_count--; 878 /* Update address in NIC data structure */ 879 rte_ether_addr_copy(&null_mac_addr, 880 &data->mac_addrs[i]); 881 } 882 } 883 884 if (!mc_addr_set || !nb_mc_addr) 885 return 0; 886 887 /* Check for available space */ 888 if (nb_mc_addr > 889 ((uint32_t)(dev->max_mac_entries - dev->dmac_filter_count))) { 890 plt_err("No space is available to add multicast filters"); 891 return -ENOSPC; 892 } 893 894 /* Multicast addresses are to be installed */ 895 for (i = 0; i < nb_mc_addr; i++) { 896 index = roc_nix_mac_addr_add(nix, mc_addr_set[i].addr_bytes); 897 if (index < 0) { 898 plt_err("Failed to add mcast mac address, rc=%d", 899 index); 900 return index; 901 } 902 903 dev->dmac_filter_count++; 904 /* Update address in NIC data structure */ 905 rte_ether_addr_copy(&mc_addr_set[i], &data->mac_addrs[index]); 906 } 907 908 roc_nix_npc_promisc_ena_dis(nix, true); 909 dev->dmac_filter_enable = true; 910 eth_dev->data->promiscuous = false; 911 912 return 0; 913 } 914