1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #include <cnxk_ethdev.h> 6 7 int 8 cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) 9 { 10 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 11 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 12 int max_rx_pktlen; 13 14 max_rx_pktlen = (roc_nix_max_pkt_len(&dev->nix) + RTE_ETHER_CRC_LEN - 15 CNXK_NIX_MAX_VTAG_ACT_SIZE); 16 17 devinfo->min_rx_bufsize = NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN; 18 devinfo->max_rx_pktlen = max_rx_pktlen; 19 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT; 20 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT; 21 devinfo->max_mac_addrs = dev->max_mac_entries; 22 devinfo->max_vfs = pci_dev->max_vfs; 23 devinfo->max_mtu = devinfo->max_rx_pktlen - 24 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN); 25 devinfo->min_mtu = devinfo->min_rx_bufsize - CNXK_NIX_L2_OVERHEAD; 26 27 devinfo->rx_offload_capa = dev->rx_offload_capa; 28 devinfo->tx_offload_capa = dev->tx_offload_capa; 29 devinfo->rx_queue_offload_capa = 0; 30 devinfo->tx_queue_offload_capa = 0; 31 32 devinfo->reta_size = dev->nix.reta_sz; 33 devinfo->hash_key_size = ROC_NIX_RSS_KEY_LEN; 34 devinfo->flow_type_rss_offloads = CNXK_NIX_RSS_OFFLOAD; 35 36 devinfo->default_rxconf = (struct rte_eth_rxconf){ 37 .rx_drop_en = 0, 38 .offloads = 0, 39 }; 40 41 devinfo->default_txconf = (struct rte_eth_txconf){ 42 .offloads = 0, 43 }; 44 45 devinfo->default_rxportconf = (struct rte_eth_dev_portconf){ 46 .ring_size = CNXK_NIX_RX_DEFAULT_RING_SZ, 47 }; 48 49 devinfo->rx_desc_lim = (struct rte_eth_desc_lim){ 50 .nb_max = UINT16_MAX, 51 .nb_min = CNXK_NIX_RX_MIN_DESC, 52 .nb_align = CNXK_NIX_RX_MIN_DESC_ALIGN, 53 .nb_seg_max = CNXK_NIX_RX_NB_SEG_MAX, 54 .nb_mtu_seg_max = CNXK_NIX_RX_NB_SEG_MAX, 55 }; 56 devinfo->rx_desc_lim.nb_max = 57 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max, 58 CNXK_NIX_RX_MIN_DESC_ALIGN); 59 60 devinfo->tx_desc_lim = (struct rte_eth_desc_lim){ 61 .nb_max = UINT16_MAX, 62 .nb_min = 1, 63 .nb_align = 1, 64 .nb_seg_max = CNXK_NIX_TX_NB_SEG_MAX, 65 .nb_mtu_seg_max = CNXK_NIX_TX_NB_SEG_MAX, 66 }; 67 68 devinfo->speed_capa = dev->speed_capa; 69 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 70 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 71 return 0; 72 } 73 74 int 75 cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id, 76 struct rte_eth_burst_mode *mode) 77 { 78 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc; 79 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 80 const struct burst_info { 81 uint64_t flags; 82 const char *output; 83 } rx_offload_map[] = { 84 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN Strip,"}, 85 {DEV_RX_OFFLOAD_IPV4_CKSUM, " Inner IPv4 Checksum,"}, 86 {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP Checksum,"}, 87 {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP Checksum,"}, 88 {DEV_RX_OFFLOAD_TCP_LRO, " TCP LRO,"}, 89 {DEV_RX_OFFLOAD_QINQ_STRIP, " QinQ VLAN Strip,"}, 90 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPv4 Checksum,"}, 91 {DEV_RX_OFFLOAD_MACSEC_STRIP, " MACsec Strip,"}, 92 {DEV_RX_OFFLOAD_HEADER_SPLIT, " Header Split,"}, 93 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN Filter,"}, 94 {DEV_RX_OFFLOAD_VLAN_EXTEND, " VLAN Extend,"}, 95 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo Frame,"}, 96 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}, 97 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"}, 98 {DEV_RX_OFFLOAD_SECURITY, " Security,"}, 99 {DEV_RX_OFFLOAD_KEEP_CRC, " Keep CRC,"}, 100 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP,"}, 101 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP Checksum,"}, 102 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"} 103 }; 104 static const char *const burst_mode[] = {"Vector Neon, Rx Offloads:", 105 "Scalar, Rx Offloads:" 106 }; 107 uint32_t i; 108 109 PLT_SET_USED(queue_id); 110 111 /* Update burst mode info */ 112 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena], 113 str_size - bytes); 114 if (rc < 0) 115 goto done; 116 117 bytes += rc; 118 119 /* Update Rx offload info */ 120 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 121 if (dev->rx_offloads & rx_offload_map[i].flags) { 122 rc = rte_strscpy(mode->info + bytes, 123 rx_offload_map[i].output, 124 str_size - bytes); 125 if (rc < 0) 126 goto done; 127 128 bytes += rc; 129 } 130 } 131 132 done: 133 return 0; 134 } 135 136 int 137 cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id, 138 struct rte_eth_burst_mode *mode) 139 { 140 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc; 141 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 142 const struct burst_info { 143 uint64_t flags; 144 const char *output; 145 } tx_offload_map[] = { 146 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"}, 147 {DEV_TX_OFFLOAD_IPV4_CKSUM, " Inner IPv4 Checksum,"}, 148 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP Checksum,"}, 149 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP Checksum,"}, 150 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP Checksum,"}, 151 {DEV_TX_OFFLOAD_TCP_TSO, " TCP TSO,"}, 152 {DEV_TX_OFFLOAD_UDP_TSO, " UDP TSO,"}, 153 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPv4 Checksum,"}, 154 {DEV_TX_OFFLOAD_QINQ_INSERT, " QinQ VLAN Insert,"}, 155 {DEV_TX_OFFLOAD_VXLAN_TNL_TSO, " VXLAN Tunnel TSO,"}, 156 {DEV_TX_OFFLOAD_GRE_TNL_TSO, " GRE Tunnel TSO,"}, 157 {DEV_TX_OFFLOAD_IPIP_TNL_TSO, " IP-in-IP Tunnel TSO,"}, 158 {DEV_TX_OFFLOAD_GENEVE_TNL_TSO, " Geneve Tunnel TSO,"}, 159 {DEV_TX_OFFLOAD_MACSEC_INSERT, " MACsec Insert,"}, 160 {DEV_TX_OFFLOAD_MT_LOCKFREE, " Multi Thread Lockless Tx,"}, 161 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}, 162 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " H/W MBUF Free,"}, 163 {DEV_TX_OFFLOAD_SECURITY, " Security,"}, 164 {DEV_TX_OFFLOAD_UDP_TNL_TSO, " UDP Tunnel TSO,"}, 165 {DEV_TX_OFFLOAD_IP_TNL_TSO, " IP Tunnel TSO,"}, 166 {DEV_TX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP Checksum,"}, 167 {DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP, " Timestamp,"} 168 }; 169 static const char *const burst_mode[] = {"Vector Neon, Tx Offloads:", 170 "Scalar, Tx Offloads:" 171 }; 172 uint32_t i; 173 174 PLT_SET_USED(queue_id); 175 176 /* Update burst mode info */ 177 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena], 178 str_size - bytes); 179 if (rc < 0) 180 goto done; 181 182 bytes += rc; 183 184 /* Update Tx offload info */ 185 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 186 if (dev->tx_offloads & tx_offload_map[i].flags) { 187 rc = rte_strscpy(mode->info + bytes, 188 tx_offload_map[i].output, 189 str_size - bytes); 190 if (rc < 0) 191 goto done; 192 193 bytes += rc; 194 } 195 } 196 197 done: 198 return 0; 199 } 200 201 int 202 cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev, 203 struct rte_eth_fc_conf *fc_conf) 204 { 205 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 206 enum rte_eth_fc_mode mode_map[] = { 207 RTE_FC_NONE, RTE_FC_RX_PAUSE, 208 RTE_FC_TX_PAUSE, RTE_FC_FULL 209 }; 210 struct roc_nix *nix = &dev->nix; 211 int mode; 212 213 mode = roc_nix_fc_mode_get(nix); 214 if (mode < 0) 215 return mode; 216 217 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 218 fc_conf->mode = mode_map[mode]; 219 return 0; 220 } 221 222 static int 223 nix_fc_cq_config_set(struct cnxk_eth_dev *dev, uint16_t qid, bool enable) 224 { 225 struct roc_nix *nix = &dev->nix; 226 struct roc_nix_fc_cfg fc_cfg; 227 struct roc_nix_cq *cq; 228 229 memset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg)); 230 cq = &dev->cqs[qid]; 231 fc_cfg.cq_cfg_valid = true; 232 fc_cfg.cq_cfg.enable = enable; 233 fc_cfg.cq_cfg.rq = qid; 234 fc_cfg.cq_cfg.cq_drop = cq->drop_thresh; 235 236 return roc_nix_fc_config_set(nix, &fc_cfg); 237 } 238 239 int 240 cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev, 241 struct rte_eth_fc_conf *fc_conf) 242 { 243 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 244 enum roc_nix_fc_mode mode_map[] = { 245 ROC_NIX_FC_NONE, ROC_NIX_FC_RX, 246 ROC_NIX_FC_TX, ROC_NIX_FC_FULL 247 }; 248 struct rte_eth_dev_data *data = eth_dev->data; 249 struct cnxk_fc_cfg *fc = &dev->fc_cfg; 250 struct roc_nix *nix = &dev->nix; 251 uint8_t rx_pause, tx_pause; 252 int rc, i; 253 254 if (roc_nix_is_vf_or_sdp(nix)) { 255 plt_err("Flow control configuration is not allowed on VFs"); 256 return -ENOTSUP; 257 } 258 259 if (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time || 260 fc_conf->mac_ctrl_frame_fwd || fc_conf->autoneg) { 261 plt_info("Only MODE configuration is supported"); 262 return -EINVAL; 263 } 264 265 if (fc_conf->mode == fc->mode) 266 return 0; 267 268 rx_pause = (fc_conf->mode == RTE_FC_FULL) || 269 (fc_conf->mode == RTE_FC_RX_PAUSE); 270 tx_pause = (fc_conf->mode == RTE_FC_FULL) || 271 (fc_conf->mode == RTE_FC_TX_PAUSE); 272 273 /* Check if TX pause frame is already enabled or not */ 274 if (fc->tx_pause ^ tx_pause) { 275 if (roc_model_is_cn96_ax() && data->dev_started) { 276 /* On Ax, CQ should be in disabled state 277 * while setting flow control configuration. 278 */ 279 plt_info("Stop the port=%d for setting flow control", 280 data->port_id); 281 return 0; 282 } 283 284 for (i = 0; i < data->nb_rx_queues; i++) { 285 rc = nix_fc_cq_config_set(dev, i, tx_pause); 286 if (rc) 287 return rc; 288 } 289 } 290 291 rc = roc_nix_fc_mode_set(nix, mode_map[fc_conf->mode]); 292 if (rc) 293 return rc; 294 295 fc->rx_pause = rx_pause; 296 fc->tx_pause = tx_pause; 297 fc->mode = fc_conf->mode; 298 299 return rc; 300 } 301 302 int 303 cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev, 304 const struct rte_flow_ops **ops) 305 { 306 RTE_SET_USED(eth_dev); 307 308 *ops = &cnxk_flow_ops; 309 return 0; 310 } 311 312 int 313 cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr) 314 { 315 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 316 struct roc_nix *nix = &dev->nix; 317 int rc; 318 319 /* Update mac address at NPC */ 320 rc = roc_nix_npc_mac_addr_set(nix, addr->addr_bytes); 321 if (rc) 322 goto exit; 323 324 /* Update mac address at CGX for PFs only */ 325 if (!roc_nix_is_vf_or_sdp(nix)) { 326 rc = roc_nix_mac_addr_set(nix, addr->addr_bytes); 327 if (rc) { 328 /* Rollback to previous mac address */ 329 roc_nix_npc_mac_addr_set(nix, dev->mac_addr); 330 goto exit; 331 } 332 } 333 334 /* Update mac address to cnxk ethernet device */ 335 rte_memcpy(dev->mac_addr, addr->addr_bytes, RTE_ETHER_ADDR_LEN); 336 337 exit: 338 return rc; 339 } 340 341 int 342 cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr, 343 uint32_t index, uint32_t pool) 344 { 345 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 346 struct roc_nix *nix = &dev->nix; 347 int rc; 348 349 PLT_SET_USED(index); 350 PLT_SET_USED(pool); 351 352 rc = roc_nix_mac_addr_add(nix, addr->addr_bytes); 353 if (rc < 0) { 354 plt_err("Failed to add mac address, rc=%d", rc); 355 return rc; 356 } 357 358 /* Enable promiscuous mode at NIX level */ 359 roc_nix_npc_promisc_ena_dis(nix, true); 360 dev->dmac_filter_enable = true; 361 eth_dev->data->promiscuous = false; 362 dev->dmac_filter_count++; 363 364 return 0; 365 } 366 367 void 368 cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index) 369 { 370 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 371 struct roc_nix *nix = &dev->nix; 372 int rc; 373 374 rc = roc_nix_mac_addr_del(nix, index); 375 if (rc) 376 plt_err("Failed to delete mac address, rc=%d", rc); 377 378 dev->dmac_filter_count--; 379 } 380 381 int 382 cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 383 { 384 uint32_t old_frame_size, frame_size = mtu + CNXK_NIX_L2_OVERHEAD; 385 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 386 struct rte_eth_dev_data *data = eth_dev->data; 387 struct roc_nix *nix = &dev->nix; 388 int rc = -EINVAL; 389 uint32_t buffsz; 390 391 frame_size += CNXK_NIX_TIMESYNC_RX_OFFSET * dev->ptp_en; 392 393 /* Check if MTU is within the allowed range */ 394 if ((frame_size - RTE_ETHER_CRC_LEN) < NIX_MIN_HW_FRS) { 395 plt_err("MTU is lesser than minimum"); 396 goto exit; 397 } 398 399 if ((frame_size - RTE_ETHER_CRC_LEN) > 400 ((uint32_t)roc_nix_max_pkt_len(nix))) { 401 plt_err("MTU is greater than maximum"); 402 goto exit; 403 } 404 405 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 406 old_frame_size = data->mtu + CNXK_NIX_L2_OVERHEAD; 407 408 /* Refuse MTU that requires the support of scattered packets 409 * when this feature has not been enabled before. 410 */ 411 if (data->dev_started && frame_size > buffsz && 412 !(dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)) { 413 plt_err("Scatter offload is not enabled for mtu"); 414 goto exit; 415 } 416 417 /* Check <seg size> * <max_seg> >= max_frame */ 418 if ((dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER) && 419 frame_size > (buffsz * CNXK_NIX_RX_NB_SEG_MAX)) { 420 plt_err("Greater than maximum supported packet length"); 421 goto exit; 422 } 423 424 frame_size -= RTE_ETHER_CRC_LEN; 425 426 /* Update mtu on Tx */ 427 rc = roc_nix_mac_mtu_set(nix, frame_size); 428 if (rc) { 429 plt_err("Failed to set MTU, rc=%d", rc); 430 goto exit; 431 } 432 433 /* Sync same frame size on Rx */ 434 rc = roc_nix_mac_max_rx_len_set(nix, frame_size); 435 if (rc) { 436 /* Rollback to older mtu */ 437 roc_nix_mac_mtu_set(nix, 438 old_frame_size - RTE_ETHER_CRC_LEN); 439 plt_err("Failed to max Rx frame length, rc=%d", rc); 440 goto exit; 441 } 442 443 frame_size += RTE_ETHER_CRC_LEN; 444 445 if (frame_size > RTE_ETHER_MAX_LEN) 446 dev->rx_offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; 447 else 448 dev->rx_offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; 449 450 /* Update max_rx_pkt_len */ 451 data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 452 453 exit: 454 return rc; 455 } 456 457 int 458 cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev) 459 { 460 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 461 struct roc_nix *nix = &dev->nix; 462 int rc = 0; 463 464 if (roc_nix_is_vf_or_sdp(nix)) 465 return rc; 466 467 rc = roc_nix_npc_promisc_ena_dis(nix, true); 468 if (rc) { 469 plt_err("Failed to setup promisc mode in npc, rc=%d(%s)", rc, 470 roc_error_msg_get(rc)); 471 return rc; 472 } 473 474 rc = roc_nix_mac_promisc_mode_enable(nix, true); 475 if (rc) { 476 plt_err("Failed to setup promisc mode in mac, rc=%d(%s)", rc, 477 roc_error_msg_get(rc)); 478 roc_nix_npc_promisc_ena_dis(nix, false); 479 return rc; 480 } 481 482 return 0; 483 } 484 485 int 486 cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev) 487 { 488 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 489 struct roc_nix *nix = &dev->nix; 490 int rc = 0; 491 492 if (roc_nix_is_vf_or_sdp(nix)) 493 return rc; 494 495 rc = roc_nix_npc_promisc_ena_dis(nix, dev->dmac_filter_enable); 496 if (rc) { 497 plt_err("Failed to setup promisc mode in npc, rc=%d(%s)", rc, 498 roc_error_msg_get(rc)); 499 return rc; 500 } 501 502 rc = roc_nix_mac_promisc_mode_enable(nix, false); 503 if (rc) { 504 plt_err("Failed to setup promisc mode in mac, rc=%d(%s)", rc, 505 roc_error_msg_get(rc)); 506 roc_nix_npc_promisc_ena_dis(nix, !dev->dmac_filter_enable); 507 return rc; 508 } 509 510 dev->dmac_filter_enable = false; 511 return 0; 512 } 513 514 int 515 cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev) 516 { 517 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 518 519 return roc_nix_npc_mcast_config(&dev->nix, true, false); 520 } 521 522 int 523 cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev) 524 { 525 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 526 527 return roc_nix_npc_mcast_config(&dev->nix, false, 528 eth_dev->data->promiscuous); 529 } 530 531 int 532 cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev) 533 { 534 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 535 struct roc_nix *nix = &dev->nix; 536 int rc, i; 537 538 if (roc_nix_is_vf_or_sdp(nix)) 539 return -ENOTSUP; 540 541 rc = roc_nix_mac_link_state_set(nix, true); 542 if (rc) 543 goto exit; 544 545 /* Start tx queues */ 546 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) { 547 rc = cnxk_nix_tx_queue_start(eth_dev, i); 548 if (rc) 549 goto exit; 550 } 551 552 exit: 553 return rc; 554 } 555 556 int 557 cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev) 558 { 559 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 560 struct roc_nix *nix = &dev->nix; 561 int rc, i; 562 563 if (roc_nix_is_vf_or_sdp(nix)) 564 return -ENOTSUP; 565 566 /* Stop tx queues */ 567 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) { 568 rc = cnxk_nix_tx_queue_stop(eth_dev, i); 569 if (rc) 570 goto exit; 571 } 572 573 rc = roc_nix_mac_link_state_set(nix, false); 574 exit: 575 return rc; 576 } 577 578 int 579 cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev, 580 struct rte_eth_dev_module_info *modinfo) 581 { 582 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 583 struct roc_nix_eeprom_info eeprom_info = {0}; 584 struct roc_nix *nix = &dev->nix; 585 int rc; 586 587 rc = roc_nix_eeprom_info_get(nix, &eeprom_info); 588 if (rc) 589 return rc; 590 591 modinfo->type = eeprom_info.sff_id; 592 modinfo->eeprom_len = ROC_NIX_EEPROM_SIZE; 593 return 0; 594 } 595 596 int 597 cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev, 598 struct rte_dev_eeprom_info *info) 599 { 600 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 601 struct roc_nix_eeprom_info eeprom_info = {0}; 602 struct roc_nix *nix = &dev->nix; 603 int rc = -EINVAL; 604 605 if (!info->data || !info->length || 606 (info->offset + info->length > ROC_NIX_EEPROM_SIZE)) 607 return rc; 608 609 rc = roc_nix_eeprom_info_get(nix, &eeprom_info); 610 if (rc) 611 return rc; 612 613 rte_memcpy(info->data, eeprom_info.buf + info->offset, info->length); 614 return 0; 615 } 616 617 int 618 cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 619 { 620 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 621 622 roc_nix_rx_queue_intr_enable(&dev->nix, rx_queue_id); 623 return 0; 624 } 625 626 int 627 cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 628 uint16_t rx_queue_id) 629 { 630 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 631 632 roc_nix_rx_queue_intr_disable(&dev->nix, rx_queue_id); 633 return 0; 634 } 635 636 int 637 cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool) 638 { 639 RTE_SET_USED(eth_dev); 640 641 if (!strcmp(pool, rte_mbuf_platform_mempool_ops())) 642 return 0; 643 644 return -ENOTSUP; 645 } 646 647 int 648 cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 649 size_t fw_size) 650 { 651 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 652 const char *str = roc_npc_profile_name_get(&dev->npc); 653 uint32_t size = strlen(str) + 1; 654 655 if (fw_size > size) 656 fw_size = size; 657 658 rte_strlcpy(fw_version, str, fw_size); 659 660 if (fw_size < size) 661 return size; 662 663 return 0; 664 } 665 666 void 667 cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid, 668 struct rte_eth_rxq_info *qinfo) 669 { 670 void *rxq = eth_dev->data->rx_queues[qid]; 671 struct cnxk_eth_rxq_sp *rxq_sp = cnxk_eth_rxq_to_sp(rxq); 672 673 memset(qinfo, 0, sizeof(*qinfo)); 674 675 qinfo->mp = rxq_sp->qconf.mp; 676 qinfo->scattered_rx = eth_dev->data->scattered_rx; 677 qinfo->nb_desc = rxq_sp->qconf.nb_desc; 678 679 memcpy(&qinfo->conf, &rxq_sp->qconf.conf.rx, sizeof(qinfo->conf)); 680 } 681 682 void 683 cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid, 684 struct rte_eth_txq_info *qinfo) 685 { 686 void *txq = eth_dev->data->tx_queues[qid]; 687 struct cnxk_eth_txq_sp *txq_sp = cnxk_eth_txq_to_sp(txq); 688 689 memset(qinfo, 0, sizeof(*qinfo)); 690 691 qinfo->nb_desc = txq_sp->qconf.nb_desc; 692 693 memcpy(&qinfo->conf, &txq_sp->qconf.conf.tx, sizeof(qinfo->conf)); 694 } 695 696 /* It is a NOP for cnxk as HW frees the buffer on xmit */ 697 int 698 cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt) 699 { 700 RTE_SET_USED(txq); 701 RTE_SET_USED(free_cnt); 702 703 return 0; 704 } 705 706 int 707 cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) 708 { 709 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 710 struct roc_nix *nix = &dev->nix; 711 uint64_t *data = regs->data; 712 int rc = -ENOTSUP; 713 714 if (data == NULL) { 715 rc = roc_nix_lf_get_reg_count(nix); 716 if (rc > 0) { 717 regs->length = rc; 718 regs->width = 8; 719 rc = 0; 720 } 721 return rc; 722 } 723 724 if (!regs->length || 725 regs->length == (uint32_t)roc_nix_lf_get_reg_count(nix)) 726 return roc_nix_lf_reg_dump(nix, data); 727 728 return rc; 729 } 730 731 int 732 cnxk_nix_reta_update(struct rte_eth_dev *eth_dev, 733 struct rte_eth_rss_reta_entry64 *reta_conf, 734 uint16_t reta_size) 735 { 736 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 737 uint16_t reta[ROC_NIX_RSS_RETA_MAX]; 738 struct roc_nix *nix = &dev->nix; 739 int i, j, rc = -EINVAL, idx = 0; 740 741 if (reta_size != dev->nix.reta_sz) { 742 plt_err("Size of hash lookup table configured (%d) does not " 743 "match the number hardware can supported (%d)", 744 reta_size, dev->nix.reta_sz); 745 goto fail; 746 } 747 748 /* Copy RETA table */ 749 for (i = 0; i < (int)(dev->nix.reta_sz / RTE_RETA_GROUP_SIZE); i++) { 750 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { 751 if ((reta_conf[i].mask >> j) & 0x01) 752 reta[idx] = reta_conf[i].reta[j]; 753 idx++; 754 } 755 } 756 757 return roc_nix_rss_reta_set(nix, 0, reta); 758 759 fail: 760 return rc; 761 } 762 763 int 764 cnxk_nix_reta_query(struct rte_eth_dev *eth_dev, 765 struct rte_eth_rss_reta_entry64 *reta_conf, 766 uint16_t reta_size) 767 { 768 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 769 uint16_t reta[ROC_NIX_RSS_RETA_MAX]; 770 struct roc_nix *nix = &dev->nix; 771 int rc = -EINVAL, i, j, idx = 0; 772 773 if (reta_size != dev->nix.reta_sz) { 774 plt_err("Size of hash lookup table configured (%d) does not " 775 "match the number hardware can supported (%d)", 776 reta_size, dev->nix.reta_sz); 777 goto fail; 778 } 779 780 rc = roc_nix_rss_reta_get(nix, 0, reta); 781 if (rc) 782 goto fail; 783 784 /* Copy RETA table */ 785 for (i = 0; i < (int)(dev->nix.reta_sz / RTE_RETA_GROUP_SIZE); i++) { 786 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { 787 if ((reta_conf[i].mask >> j) & 0x01) 788 reta_conf[i].reta[j] = reta[idx]; 789 idx++; 790 } 791 } 792 793 return 0; 794 795 fail: 796 return rc; 797 } 798 799 int 800 cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev, 801 struct rte_eth_rss_conf *rss_conf) 802 { 803 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 804 struct roc_nix *nix = &dev->nix; 805 uint8_t rss_hash_level; 806 uint32_t flowkey_cfg; 807 int rc = -EINVAL; 808 uint8_t alg_idx; 809 810 if (rss_conf->rss_key && rss_conf->rss_key_len != ROC_NIX_RSS_KEY_LEN) { 811 plt_err("Hash key size mismatch %d vs %d", 812 rss_conf->rss_key_len, ROC_NIX_RSS_KEY_LEN); 813 goto fail; 814 } 815 816 if (rss_conf->rss_key) 817 roc_nix_rss_key_set(nix, rss_conf->rss_key); 818 819 rss_hash_level = ETH_RSS_LEVEL(rss_conf->rss_hf); 820 if (rss_hash_level) 821 rss_hash_level -= 1; 822 flowkey_cfg = 823 cnxk_rss_ethdev_to_nix(dev, rss_conf->rss_hf, rss_hash_level); 824 825 rc = roc_nix_rss_flowkey_set(nix, &alg_idx, flowkey_cfg, 826 ROC_NIX_RSS_GROUP_DEFAULT, 827 ROC_NIX_RSS_MCAM_IDX_DEFAULT); 828 if (rc) { 829 plt_err("Failed to set RSS hash function rc=%d", rc); 830 return rc; 831 } 832 833 fail: 834 return rc; 835 } 836 837 int 838 cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 839 struct rte_eth_rss_conf *rss_conf) 840 { 841 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 842 843 if (rss_conf->rss_key) 844 roc_nix_rss_key_get(&dev->nix, rss_conf->rss_key); 845 846 rss_conf->rss_key_len = ROC_NIX_RSS_KEY_LEN; 847 rss_conf->rss_hf = dev->ethdev_rss_hf; 848 849 return 0; 850 } 851 852 int 853 cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev, 854 struct rte_ether_addr *mc_addr_set, 855 uint32_t nb_mc_addr) 856 { 857 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 858 struct rte_eth_dev_data *data = eth_dev->data; 859 struct rte_ether_addr null_mac_addr; 860 struct roc_nix *nix = &dev->nix; 861 int rc, index; 862 uint32_t i; 863 864 memset(&null_mac_addr, 0, sizeof(null_mac_addr)); 865 866 /* All configured multicast filters should be flushed first */ 867 for (i = 0; i < dev->max_mac_entries; i++) { 868 if (rte_is_multicast_ether_addr(&data->mac_addrs[i])) { 869 rc = roc_nix_mac_addr_del(nix, i); 870 if (rc) { 871 plt_err("Failed to flush mcast address, rc=%d", 872 rc); 873 return rc; 874 } 875 876 dev->dmac_filter_count--; 877 /* Update address in NIC data structure */ 878 rte_ether_addr_copy(&null_mac_addr, 879 &data->mac_addrs[i]); 880 } 881 } 882 883 if (!mc_addr_set || !nb_mc_addr) 884 return 0; 885 886 /* Check for available space */ 887 if (nb_mc_addr > 888 ((uint32_t)(dev->max_mac_entries - dev->dmac_filter_count))) { 889 plt_err("No space is available to add multicast filters"); 890 return -ENOSPC; 891 } 892 893 /* Multicast addresses are to be installed */ 894 for (i = 0; i < nb_mc_addr; i++) { 895 index = roc_nix_mac_addr_add(nix, mc_addr_set[i].addr_bytes); 896 if (index < 0) { 897 plt_err("Failed to add mcast mac address, rc=%d", 898 index); 899 return index; 900 } 901 902 dev->dmac_filter_count++; 903 /* Update address in NIC data structure */ 904 rte_ether_addr_copy(&mc_addr_set[i], &data->mac_addrs[index]); 905 } 906 907 roc_nix_npc_promisc_ena_dis(nix, true); 908 dev->dmac_filter_enable = true; 909 eth_dev->data->promiscuous = false; 910 911 return 0; 912 } 913