1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #include <inttypes.h> 6 #include <math.h> 7 8 #include "cnxk_ethdev.h" 9 10 static int 11 parse_outb_nb_desc(const char *key, const char *value, void *extra_args) 12 { 13 RTE_SET_USED(key); 14 uint32_t val; 15 16 val = atoi(value); 17 18 *(uint16_t *)extra_args = val; 19 20 return 0; 21 } 22 23 static int 24 parse_outb_nb_crypto_qs(const char *key, const char *value, void *extra_args) 25 { 26 RTE_SET_USED(key); 27 uint32_t val; 28 29 val = atoi(value); 30 31 if (val < 1 || val > 64) 32 return -EINVAL; 33 34 *(uint16_t *)extra_args = val; 35 36 return 0; 37 } 38 39 static int 40 parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args) 41 { 42 RTE_SET_USED(key); 43 uint32_t val; 44 45 val = atoi(value); 46 47 *(uint16_t *)extra_args = val; 48 49 return 0; 50 } 51 52 static int 53 parse_ipsec_out_max_sa(const char *key, const char *value, void *extra_args) 54 { 55 RTE_SET_USED(key); 56 uint32_t val; 57 58 val = atoi(value); 59 60 *(uint16_t *)extra_args = val; 61 62 return 0; 63 } 64 65 static int 66 parse_flow_max_priority(const char *key, const char *value, void *extra_args) 67 { 68 RTE_SET_USED(key); 69 uint16_t val; 70 71 val = atoi(value); 72 73 /* Limit the max priority to 32 */ 74 if (val < 1 || val > 32) 75 return -EINVAL; 76 77 *(uint16_t *)extra_args = val; 78 79 return 0; 80 } 81 82 static int 83 parse_flow_prealloc_size(const char *key, const char *value, void *extra_args) 84 { 85 RTE_SET_USED(key); 86 uint16_t val; 87 88 val = atoi(value); 89 90 /* Limit the prealloc size to 32 */ 91 if (val < 1 || val > 32) 92 return -EINVAL; 93 94 *(uint16_t *)extra_args = val; 95 96 return 0; 97 } 98 99 static int 100 parse_reta_size(const char *key, const char *value, void *extra_args) 101 { 102 RTE_SET_USED(key); 103 uint32_t val; 104 105 val = atoi(value); 106 107 if (val <= RTE_ETH_RSS_RETA_SIZE_64) 108 val = ROC_NIX_RSS_RETA_SZ_64; 109 else if (val > RTE_ETH_RSS_RETA_SIZE_64 && val <= RTE_ETH_RSS_RETA_SIZE_128) 110 val = ROC_NIX_RSS_RETA_SZ_128; 111 else if (val > RTE_ETH_RSS_RETA_SIZE_128 && val <= RTE_ETH_RSS_RETA_SIZE_256) 112 val = ROC_NIX_RSS_RETA_SZ_256; 113 else 114 val = ROC_NIX_RSS_RETA_SZ_64; 115 116 *(uint16_t *)extra_args = val; 117 118 return 0; 119 } 120 121 static int 122 parse_flag(const char *key, const char *value, void *extra_args) 123 { 124 RTE_SET_USED(key); 125 126 *(uint16_t *)extra_args = atoi(value); 127 128 return 0; 129 } 130 131 static int 132 parse_sqb_count(const char *key, const char *value, void *extra_args) 133 { 134 RTE_SET_USED(key); 135 uint32_t val; 136 137 val = atoi(value); 138 139 *(uint16_t *)extra_args = val; 140 141 return 0; 142 } 143 144 static int 145 parse_switch_header_type(const char *key, const char *value, void *extra_args) 146 { 147 RTE_SET_USED(key); 148 149 if (strcmp(value, "higig2") == 0) 150 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_HIGIG; 151 152 if (strcmp(value, "dsa") == 0) 153 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_EDSA; 154 155 if (strcmp(value, "chlen90b") == 0) 156 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_LEN_90B; 157 158 if (strcmp(value, "exdsa") == 0) 159 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_EXDSA; 160 161 if (strcmp(value, "vlan_exdsa") == 0) 162 *(uint16_t *)extra_args = ROC_PRIV_FLAGS_VLAN_EXDSA; 163 164 return 0; 165 } 166 167 #define CNXK_RSS_RETA_SIZE "reta_size" 168 #define CNXK_SCL_ENABLE "scalar_enable" 169 #define CNXK_MAX_SQB_COUNT "max_sqb_count" 170 #define CNXK_FLOW_PREALLOC_SIZE "flow_prealloc_size" 171 #define CNXK_FLOW_MAX_PRIORITY "flow_max_priority" 172 #define CNXK_SWITCH_HEADER_TYPE "switch_header" 173 #define CNXK_RSS_TAG_AS_XOR "tag_as_xor" 174 #define CNXK_LOCK_RX_CTX "lock_rx_ctx" 175 #define CNXK_IPSEC_IN_MAX_SPI "ipsec_in_max_spi" 176 #define CNXK_IPSEC_OUT_MAX_SA "ipsec_out_max_sa" 177 #define CNXK_OUTB_NB_DESC "outb_nb_desc" 178 #define CNXK_FORCE_INB_INL_DEV "force_inb_inl_dev" 179 #define CNXK_OUTB_NB_CRYPTO_QS "outb_nb_crypto_qs" 180 181 int 182 cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) 183 { 184 uint16_t reta_sz = ROC_NIX_RSS_RETA_SZ_64; 185 uint16_t sqb_count = CNXK_NIX_TX_MAX_SQB; 186 uint16_t ipsec_in_max_spi = BIT(8) - 1; 187 uint16_t ipsec_out_max_sa = BIT(12); 188 uint16_t flow_prealloc_size = 1; 189 uint16_t switch_header_type = 0; 190 uint16_t flow_max_priority = 3; 191 uint16_t force_inb_inl_dev = 0; 192 uint16_t outb_nb_crypto_qs = 1; 193 uint16_t outb_nb_desc = 8200; 194 uint16_t rss_tag_as_xor = 0; 195 uint16_t scalar_enable = 0; 196 uint8_t lock_rx_ctx = 0; 197 struct rte_kvargs *kvlist; 198 199 if (devargs == NULL) 200 goto null_devargs; 201 202 kvlist = rte_kvargs_parse(devargs->args, NULL); 203 if (kvlist == NULL) 204 goto exit; 205 206 rte_kvargs_process(kvlist, CNXK_RSS_RETA_SIZE, &parse_reta_size, 207 &reta_sz); 208 rte_kvargs_process(kvlist, CNXK_SCL_ENABLE, &parse_flag, 209 &scalar_enable); 210 rte_kvargs_process(kvlist, CNXK_MAX_SQB_COUNT, &parse_sqb_count, 211 &sqb_count); 212 rte_kvargs_process(kvlist, CNXK_FLOW_PREALLOC_SIZE, 213 &parse_flow_prealloc_size, &flow_prealloc_size); 214 rte_kvargs_process(kvlist, CNXK_FLOW_MAX_PRIORITY, 215 &parse_flow_max_priority, &flow_max_priority); 216 rte_kvargs_process(kvlist, CNXK_SWITCH_HEADER_TYPE, 217 &parse_switch_header_type, &switch_header_type); 218 rte_kvargs_process(kvlist, CNXK_RSS_TAG_AS_XOR, &parse_flag, 219 &rss_tag_as_xor); 220 rte_kvargs_process(kvlist, CNXK_LOCK_RX_CTX, &parse_flag, &lock_rx_ctx); 221 rte_kvargs_process(kvlist, CNXK_IPSEC_IN_MAX_SPI, 222 &parse_ipsec_in_max_spi, &ipsec_in_max_spi); 223 rte_kvargs_process(kvlist, CNXK_IPSEC_OUT_MAX_SA, 224 &parse_ipsec_out_max_sa, &ipsec_out_max_sa); 225 rte_kvargs_process(kvlist, CNXK_OUTB_NB_DESC, &parse_outb_nb_desc, 226 &outb_nb_desc); 227 rte_kvargs_process(kvlist, CNXK_OUTB_NB_CRYPTO_QS, 228 &parse_outb_nb_crypto_qs, &outb_nb_crypto_qs); 229 rte_kvargs_process(kvlist, CNXK_FORCE_INB_INL_DEV, &parse_flag, 230 &force_inb_inl_dev); 231 rte_kvargs_free(kvlist); 232 233 null_devargs: 234 dev->scalar_ena = !!scalar_enable; 235 dev->inb.force_inl_dev = !!force_inb_inl_dev; 236 dev->inb.max_spi = ipsec_in_max_spi; 237 dev->outb.max_sa = ipsec_out_max_sa; 238 dev->outb.nb_desc = outb_nb_desc; 239 dev->outb.nb_crypto_qs = outb_nb_crypto_qs; 240 dev->nix.ipsec_in_max_spi = ipsec_in_max_spi; 241 dev->nix.ipsec_out_max_sa = ipsec_out_max_sa; 242 dev->nix.rss_tag_as_xor = !!rss_tag_as_xor; 243 dev->nix.max_sqb_count = sqb_count; 244 dev->nix.reta_sz = reta_sz; 245 dev->nix.lock_rx_ctx = lock_rx_ctx; 246 dev->npc.flow_prealloc_size = flow_prealloc_size; 247 dev->npc.flow_max_priority = flow_max_priority; 248 dev->npc.switch_header_type = switch_header_type; 249 return 0; 250 251 exit: 252 return -EINVAL; 253 } 254 255 RTE_PMD_REGISTER_PARAM_STRING(net_cnxk, 256 CNXK_RSS_RETA_SIZE "=<64|128|256>" 257 CNXK_SCL_ENABLE "=1" 258 CNXK_MAX_SQB_COUNT "=<8-512>" 259 CNXK_FLOW_PREALLOC_SIZE "=<1-32>" 260 CNXK_FLOW_MAX_PRIORITY "=<1-32>" 261 CNXK_SWITCH_HEADER_TYPE "=<higig2|dsa|chlen90b>" 262 CNXK_RSS_TAG_AS_XOR "=1" 263 CNXK_IPSEC_IN_MAX_SPI "=<1-65535>" 264 CNXK_OUTB_NB_DESC "=<1-65535>" 265 CNXK_OUTB_NB_CRYPTO_QS "=<1-64>" 266 CNXK_FORCE_INB_INL_DEV "=1"); 267