1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 #ifndef __CNXK_ETHDEV_H__ 5 #define __CNXK_ETHDEV_H__ 6 7 #include <math.h> 8 #include <stdint.h> 9 10 #include <ethdev_driver.h> 11 #include <ethdev_pci.h> 12 #include <rte_kvargs.h> 13 #include <rte_mbuf.h> 14 #include <rte_mbuf_pool_ops.h> 15 #include <rte_mempool.h> 16 #include <rte_mtr_driver.h> 17 #include <rte_security.h> 18 #include <rte_security_driver.h> 19 #include <rte_tailq.h> 20 #include <rte_time.h> 21 22 #include "roc_api.h" 23 24 #define CNXK_ETH_DEV_PMD_VERSION "1.0" 25 26 /* Used for struct cnxk_eth_dev::flags */ 27 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0) 28 29 /* VLAN tag inserted by NIX_TX_VTAG_ACTION. 30 * In Tx space is always reserved for this in FRS. 31 */ 32 #define CNXK_NIX_MAX_VTAG_INS 2 33 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS) 34 35 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */ 36 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \ 37 RTE_ETHER_CRC_LEN + \ 38 CNXK_NIX_MAX_VTAG_ACT_SIZE) 39 40 #define CNXK_NIX_RX_MIN_DESC 16 41 #define CNXK_NIX_RX_MIN_DESC_ALIGN 16 42 #define CNXK_NIX_RX_NB_SEG_MAX 6 43 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096 44 /* Max supported SQB count */ 45 #define CNXK_NIX_TX_MAX_SQB 512 46 47 /* If PTP is enabled additional SEND MEM DESC is required which 48 * takes 2 words, hence max 7 iova address are possible 49 */ 50 #if defined(RTE_LIBRTE_IEEE1588) 51 #define CNXK_NIX_TX_NB_SEG_MAX 7 52 #else 53 #define CNXK_NIX_TX_NB_SEG_MAX 9 54 #endif 55 56 #define CNXK_NIX_TX_MSEG_SG_DWORDS \ 57 ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) + \ 58 CNXK_NIX_TX_NB_SEG_MAX) 59 60 #define CNXK_NIX_RSS_L3_L4_SRC_DST \ 61 (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY | \ 62 RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY) 63 64 #define CNXK_NIX_RSS_OFFLOAD \ 65 (RTE_ETH_RSS_PORT | RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP | \ 66 RTE_ETH_RSS_TCP | RTE_ETH_RSS_SCTP | RTE_ETH_RSS_TUNNEL | \ 67 RTE_ETH_RSS_L2_PAYLOAD | CNXK_NIX_RSS_L3_L4_SRC_DST | \ 68 RTE_ETH_RSS_LEVEL_MASK | RTE_ETH_RSS_C_VLAN) 69 70 #define CNXK_NIX_TX_OFFLOAD_CAPA \ 71 (RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | \ 72 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | RTE_ETH_TX_OFFLOAD_QINQ_INSERT | \ 73 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | \ 74 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \ 75 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_TSO | \ 76 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | \ 77 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | RTE_ETH_TX_OFFLOAD_MULTI_SEGS | \ 78 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_SECURITY) 79 80 #define CNXK_NIX_RX_OFFLOAD_CAPA \ 81 (RTE_ETH_RX_OFFLOAD_CHECKSUM | RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | \ 82 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_SCATTER | \ 83 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_RSS_HASH | \ 84 RTE_ETH_RX_OFFLOAD_TIMESTAMP | RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \ 85 RTE_ETH_RX_OFFLOAD_SECURITY) 86 87 #define RSS_IPV4_ENABLE \ 88 (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \ 89 RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ 90 RTE_ETH_RSS_NONFRAG_IPV4_SCTP) 91 92 #define RSS_IPV6_ENABLE \ 93 (RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | \ 94 RTE_ETH_RSS_NONFRAG_IPV6_UDP | RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ 95 RTE_ETH_RSS_NONFRAG_IPV6_SCTP) 96 97 #define RSS_IPV6_EX_ENABLE \ 98 (RTE_ETH_RSS_IPV6_EX | RTE_ETH_RSS_IPV6_TCP_EX | RTE_ETH_RSS_IPV6_UDP_EX) 99 100 #define RSS_MAX_LEVELS 3 101 102 #define RSS_IPV4_INDEX 0 103 #define RSS_IPV6_INDEX 1 104 #define RSS_TCP_INDEX 2 105 #define RSS_UDP_INDEX 3 106 #define RSS_SCTP_INDEX 4 107 #define RSS_DMAC_INDEX 5 108 109 /* Default mark value used when none is provided. */ 110 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff 111 112 /* Default cycle counter mask */ 113 #define CNXK_CYCLECOUNTER_MASK 0xffffffffffffffffULL 114 #define CNXK_NIX_TIMESYNC_RX_OFFSET 8 115 116 #define PTYPE_NON_TUNNEL_WIDTH 16 117 #define PTYPE_TUNNEL_WIDTH 12 118 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH) 119 #define PTYPE_TUNNEL_ARRAY_SZ BIT(PTYPE_TUNNEL_WIDTH) 120 #define PTYPE_ARRAY_SZ \ 121 ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t)) 122 123 /* NIX_RX_PARSE_S's ERRCODE + ERRLEV (12 bits) */ 124 #define ERRCODE_ERRLEN_WIDTH 12 125 #define ERR_ARRAY_SZ ((BIT(ERRCODE_ERRLEN_WIDTH)) * sizeof(uint32_t)) 126 127 /* Fastpath lookup */ 128 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem" 129 130 #define CNXK_NIX_UDP_TUN_BITMASK \ 131 ((1ull << (RTE_MBUF_F_TX_TUNNEL_VXLAN >> 45)) | \ 132 (1ull << (RTE_MBUF_F_TX_TUNNEL_GENEVE >> 45))) 133 134 /* Subtype from inline outbound error event */ 135 #define CNXK_ETHDEV_SEC_OUTB_EV_SUB 0xFFUL 136 137 /* SPI will be in 20 bits of tag */ 138 #define CNXK_ETHDEV_SPI_TAG_MASK 0xFFFFFUL 139 140 struct cnxk_fc_cfg { 141 enum rte_eth_fc_mode mode; 142 uint8_t rx_pause; 143 uint8_t tx_pause; 144 }; 145 146 struct cnxk_eth_qconf { 147 union { 148 struct rte_eth_txconf tx; 149 struct rte_eth_rxconf rx; 150 } conf; 151 struct rte_mempool *mp; 152 uint16_t nb_desc; 153 uint8_t valid; 154 }; 155 156 struct cnxk_timesync_info { 157 uint8_t rx_ready; 158 uint64_t rx_tstamp; 159 uint64_t rx_tstamp_dynflag; 160 int tstamp_dynfield_offset; 161 rte_iova_t tx_tstamp_iova; 162 uint64_t *tx_tstamp; 163 } __plt_cache_aligned; 164 165 struct cnxk_meter_node { 166 #define MAX_PRV_MTR_NODES 10 167 TAILQ_ENTRY(cnxk_meter_node) next; 168 /**< Pointer to the next flow meter structure. */ 169 uint32_t id; /**< Usr mtr id. */ 170 struct cnxk_mtr_profile_node *profile; 171 struct cnxk_mtr_policy_node *policy; 172 uint32_t bpf_id; /**< Hw mtr id. */ 173 uint32_t rq_num; 174 uint32_t *rq_id; 175 uint16_t level; 176 uint32_t prev_id[MAX_PRV_MTR_NODES]; /**< Prev mtr id for chaining */ 177 uint32_t prev_cnt; 178 uint32_t next_id; /**< Next mtr id for chaining */ 179 bool is_prev; 180 bool is_next; 181 struct rte_mtr_params params; 182 struct roc_nix_bpf_objs profs; 183 bool is_used; 184 uint32_t ref_cnt; 185 }; 186 187 struct action_rss { 188 enum rte_eth_hash_function func; 189 uint32_t level; 190 uint64_t types; 191 uint32_t key_len; 192 uint32_t queue_num; 193 uint8_t *key; 194 uint16_t *queue; 195 }; 196 197 struct policy_actions { 198 uint32_t action_fate; 199 union { 200 uint16_t queue; 201 uint32_t mtr_id; 202 struct action_rss *rss_desc; 203 }; 204 }; 205 206 struct cnxk_mtr_policy_node { 207 TAILQ_ENTRY(cnxk_mtr_policy_node) next; 208 /**< Pointer to the next flow meter structure. */ 209 uint32_t id; /**< Policy id */ 210 uint32_t mtr_id; /** Meter id */ 211 struct rte_mtr_meter_policy_params policy; 212 struct policy_actions actions[RTE_COLORS]; 213 uint32_t ref_cnt; 214 }; 215 216 struct cnxk_mtr_profile_node { 217 TAILQ_ENTRY(cnxk_mtr_profile_node) next; 218 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 219 uint32_t ref_cnt; /**< Use count. */ 220 uint32_t id; /**< Profile id. */ 221 }; 222 223 TAILQ_HEAD(cnxk_mtr_profiles, cnxk_mtr_profile_node); 224 TAILQ_HEAD(cnxk_mtr_policy, cnxk_mtr_policy_node); 225 TAILQ_HEAD(cnxk_mtr, cnxk_meter_node); 226 227 /* Security session private data */ 228 struct cnxk_eth_sec_sess { 229 /* List entry */ 230 TAILQ_ENTRY(cnxk_eth_sec_sess) entry; 231 232 /* Inbound SA is from NIX_RX_IPSEC_SA_BASE or 233 * Outbound SA from roc_nix_inl_outb_sa_base_get() 234 */ 235 void *sa; 236 237 /* SA index */ 238 uint32_t sa_idx; 239 240 /* SPI */ 241 uint32_t spi; 242 243 /* Back pointer to session */ 244 struct rte_security_session *sess; 245 246 /* Inbound */ 247 bool inb; 248 249 /* Inbound session on inl dev */ 250 bool inl_dev; 251 }; 252 253 TAILQ_HEAD(cnxk_eth_sec_sess_list, cnxk_eth_sec_sess); 254 255 /* Inbound security data */ 256 struct cnxk_eth_dev_sec_inb { 257 /* IPSec inbound max SPI */ 258 uint16_t max_spi; 259 260 /* Using inbound with inline device */ 261 bool inl_dev; 262 263 /* Device argument to force inline device for inb */ 264 bool force_inl_dev; 265 266 /* Active sessions */ 267 uint16_t nb_sess; 268 269 /* List of sessions */ 270 struct cnxk_eth_sec_sess_list list; 271 272 /* DPTR for WRITE_SA microcode op */ 273 void *sa_dptr; 274 }; 275 276 /* Outbound security data */ 277 struct cnxk_eth_dev_sec_outb { 278 /* IPSec outbound max SA */ 279 uint16_t max_sa; 280 281 /* Per CPT LF descriptor count */ 282 uint32_t nb_desc; 283 284 /* SA Bitmap */ 285 struct plt_bitmap *sa_bmap; 286 287 /* SA bitmap memory */ 288 void *sa_bmap_mem; 289 290 /* SA base */ 291 uint64_t sa_base; 292 293 /* CPT LF base */ 294 struct roc_cpt_lf *lf_base; 295 296 /* Crypto queues => CPT lf count */ 297 uint16_t nb_crypto_qs; 298 299 /* Active sessions */ 300 uint16_t nb_sess; 301 302 /* List of sessions */ 303 struct cnxk_eth_sec_sess_list list; 304 305 /* DPTR for WRITE_SA microcode op */ 306 void *sa_dptr; 307 }; 308 309 struct cnxk_eth_dev { 310 /* ROC NIX */ 311 struct roc_nix nix; 312 313 /* ROC NPC */ 314 struct roc_npc npc; 315 316 /* ROC RQs, SQs and CQs */ 317 struct roc_nix_rq *rqs; 318 struct roc_nix_sq *sqs; 319 struct roc_nix_cq *cqs; 320 321 /* Configured queue count */ 322 uint16_t nb_rxq; 323 uint16_t nb_txq; 324 uint16_t nb_rxq_sso; 325 uint8_t configured; 326 327 /* Max macfilter entries */ 328 uint8_t dmac_filter_count; 329 uint8_t max_mac_entries; 330 bool dmac_filter_enable; 331 332 uint16_t flags; 333 uint8_t ptype_disable; 334 bool scalar_ena; 335 bool ptp_en; 336 337 /* Pointer back to rte */ 338 struct rte_eth_dev *eth_dev; 339 340 /* HW capabilities / Limitations */ 341 union { 342 struct { 343 uint64_t cq_min_4k : 1; 344 uint64_t ipsecd_drop_re_dis : 1; 345 uint64_t vec_drop_re_dis : 1; 346 }; 347 uint64_t hwcap; 348 }; 349 350 /* Rx and Tx offload capabilities */ 351 uint64_t rx_offload_capa; 352 uint64_t tx_offload_capa; 353 uint32_t speed_capa; 354 /* Configured Rx and Tx offloads */ 355 uint64_t rx_offloads; 356 uint64_t tx_offloads; 357 /* Platform specific offload flags */ 358 uint16_t rx_offload_flags; 359 uint16_t tx_offload_flags; 360 361 /* ETHDEV RSS HF bitmask */ 362 uint64_t ethdev_rss_hf; 363 364 /* Saved qconf before lf realloc */ 365 struct cnxk_eth_qconf *tx_qconf; 366 struct cnxk_eth_qconf *rx_qconf; 367 368 /* Flow control configuration */ 369 struct cnxk_fc_cfg fc_cfg; 370 371 /* PTP Counters */ 372 struct cnxk_timesync_info tstamp; 373 struct rte_timecounter systime_tc; 374 struct rte_timecounter rx_tstamp_tc; 375 struct rte_timecounter tx_tstamp_tc; 376 double clk_freq_mult; 377 uint64_t clk_delta; 378 379 /* Ingress policer */ 380 enum roc_nix_bpf_color precolor_tbl[ROC_NIX_BPF_PRE_COLOR_MAX]; 381 struct cnxk_mtr_profiles mtr_profiles; 382 struct cnxk_mtr_policy mtr_policy; 383 struct cnxk_mtr mtr; 384 385 /* Rx burst for cleanup(Only Primary) */ 386 eth_rx_burst_t rx_pkt_burst_no_offload; 387 388 /* Default mac address */ 389 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 390 391 /* LSO Tunnel format indices */ 392 uint64_t lso_tun_fmt; 393 394 /* Per queue statistics counters */ 395 uint32_t txq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS]; 396 uint32_t rxq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS]; 397 398 /* Security data */ 399 struct cnxk_eth_dev_sec_inb inb; 400 struct cnxk_eth_dev_sec_outb outb; 401 }; 402 403 struct cnxk_eth_rxq_sp { 404 struct cnxk_eth_dev *dev; 405 struct cnxk_eth_qconf qconf; 406 uint16_t qid; 407 } __plt_cache_aligned; 408 409 struct cnxk_eth_txq_sp { 410 struct cnxk_eth_dev *dev; 411 struct cnxk_eth_qconf qconf; 412 uint16_t qid; 413 } __plt_cache_aligned; 414 415 static inline struct cnxk_eth_dev * 416 cnxk_eth_pmd_priv(const struct rte_eth_dev *eth_dev) 417 { 418 return eth_dev->data->dev_private; 419 } 420 421 static inline struct cnxk_eth_rxq_sp * 422 cnxk_eth_rxq_to_sp(void *__rxq) 423 { 424 return ((struct cnxk_eth_rxq_sp *)__rxq) - 1; 425 } 426 427 static inline struct cnxk_eth_txq_sp * 428 cnxk_eth_txq_to_sp(void *__txq) 429 { 430 return ((struct cnxk_eth_txq_sp *)__txq) - 1; 431 } 432 433 /* Common ethdev ops */ 434 extern struct eth_dev_ops cnxk_eth_dev_ops; 435 436 /* Common flow ops */ 437 extern struct rte_flow_ops cnxk_flow_ops; 438 439 /* Common security ops */ 440 extern struct rte_security_ops cnxk_eth_sec_ops; 441 442 /* Ops */ 443 int cnxk_nix_probe(struct rte_pci_driver *pci_drv, 444 struct rte_pci_device *pci_dev); 445 int cnxk_nix_remove(struct rte_pci_device *pci_dev); 446 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu); 447 int cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev, 448 struct rte_ether_addr *mc_addr_set, 449 uint32_t nb_mc_addr); 450 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev, 451 struct rte_ether_addr *addr, uint32_t index, 452 uint32_t pool); 453 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index); 454 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev, 455 struct rte_ether_addr *addr); 456 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev); 457 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev); 458 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev); 459 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev); 460 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev, 461 struct rte_eth_dev_info *dev_info); 462 int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id, 463 struct rte_eth_burst_mode *mode); 464 int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id, 465 struct rte_eth_burst_mode *mode); 466 int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev, 467 struct rte_eth_fc_conf *fc_conf); 468 int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev, 469 struct rte_eth_fc_conf *fc_conf); 470 int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev); 471 int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev); 472 int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev, 473 struct rte_eth_dev_module_info *modinfo); 474 int cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev, 475 struct rte_dev_eeprom_info *info); 476 int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 477 uint16_t rx_queue_id); 478 int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 479 uint16_t rx_queue_id); 480 int cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool); 481 int cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt); 482 int cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev, 483 const struct rte_flow_ops **ops); 484 int cnxk_nix_configure(struct rte_eth_dev *eth_dev); 485 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, 486 uint16_t nb_desc, uint16_t fp_tx_q_sz, 487 const struct rte_eth_txconf *tx_conf); 488 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, 489 uint16_t nb_desc, uint16_t fp_rx_q_sz, 490 const struct rte_eth_rxconf *rx_conf, 491 struct rte_mempool *mp); 492 int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid); 493 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid); 494 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev); 495 int cnxk_nix_timesync_enable(struct rte_eth_dev *eth_dev); 496 int cnxk_nix_timesync_disable(struct rte_eth_dev *eth_dev); 497 int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev, 498 struct timespec *timestamp, 499 uint32_t flags); 500 int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev, 501 struct timespec *timestamp); 502 int cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev, 503 struct timespec *ts); 504 int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev, 505 const struct timespec *ts); 506 int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta); 507 int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev); 508 int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock); 509 510 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev); 511 int cnxk_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops); 512 int cnxk_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev, 513 uint16_t queue_idx, uint16_t tx_rate); 514 515 /* MTR */ 516 int cnxk_nix_mtr_ops_get(struct rte_eth_dev *dev, void *ops); 517 518 /* RSS */ 519 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss, 520 uint8_t rss_level); 521 int cnxk_nix_reta_update(struct rte_eth_dev *eth_dev, 522 struct rte_eth_rss_reta_entry64 *reta_conf, 523 uint16_t reta_size); 524 int cnxk_nix_reta_query(struct rte_eth_dev *eth_dev, 525 struct rte_eth_rss_reta_entry64 *reta_conf, 526 uint16_t reta_size); 527 int cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev, 528 struct rte_eth_rss_conf *rss_conf); 529 int cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 530 struct rte_eth_rss_conf *rss_conf); 531 532 /* Link */ 533 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set); 534 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix, 535 struct roc_nix_link_info *link); 536 void cnxk_eth_dev_link_status_get_cb(struct roc_nix *nix, 537 struct roc_nix_link_info *link); 538 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete); 539 int cnxk_nix_queue_stats_mapping(struct rte_eth_dev *dev, uint16_t queue_id, 540 uint8_t stat_idx, uint8_t is_rx); 541 int cnxk_nix_stats_reset(struct rte_eth_dev *dev); 542 int cnxk_nix_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 543 int cnxk_nix_xstats_get(struct rte_eth_dev *eth_dev, 544 struct rte_eth_xstat *xstats, unsigned int n); 545 int cnxk_nix_xstats_get_names(struct rte_eth_dev *eth_dev, 546 struct rte_eth_xstat_name *xstats_names, 547 unsigned int limit); 548 int cnxk_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 549 const uint64_t *ids, 550 struct rte_eth_xstat_name *xstats_names, 551 unsigned int limit); 552 int cnxk_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 553 uint64_t *values, unsigned int n); 554 int cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev); 555 int cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 556 size_t fw_size); 557 void cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid, 558 struct rte_eth_rxq_info *qinfo); 559 void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid, 560 struct rte_eth_txq_info *qinfo); 561 562 /* Lookup configuration */ 563 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev); 564 void *cnxk_nix_fastpath_lookup_mem_get(void); 565 566 /* Devargs */ 567 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, 568 struct cnxk_eth_dev *dev); 569 570 /* Debug */ 571 int cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev, 572 struct rte_dev_reg_info *regs); 573 /* Security */ 574 int cnxk_eth_outb_sa_idx_get(struct cnxk_eth_dev *dev, uint32_t *idx_p); 575 int cnxk_eth_outb_sa_idx_put(struct cnxk_eth_dev *dev, uint32_t idx); 576 int cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev *dev); 577 int cnxk_nix_lookup_mem_sa_base_clear(struct cnxk_eth_dev *dev); 578 __rte_internal 579 int cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev); 580 struct cnxk_eth_sec_sess *cnxk_eth_sec_sess_get_by_spi(struct cnxk_eth_dev *dev, 581 uint32_t spi, bool inb); 582 struct cnxk_eth_sec_sess * 583 cnxk_eth_sec_sess_get_by_sess(struct cnxk_eth_dev *dev, 584 struct rte_security_session *sess); 585 586 /* Other private functions */ 587 int nix_recalc_mtu(struct rte_eth_dev *eth_dev); 588 int nix_mtr_validate(struct rte_eth_dev *dev, uint32_t id); 589 int nix_mtr_policy_act_get(struct rte_eth_dev *eth_dev, uint32_t id, 590 struct cnxk_mtr_policy_node **policy); 591 int nix_mtr_rq_update(struct rte_eth_dev *eth_dev, uint32_t id, 592 uint32_t queue_num, const uint16_t *queue); 593 int nix_mtr_chain_update(struct rte_eth_dev *eth_dev, uint32_t cur_id, 594 uint32_t prev_id, uint32_t next_id); 595 int nix_mtr_chain_reset(struct rte_eth_dev *eth_dev, uint32_t cur_id); 596 struct cnxk_meter_node *nix_get_mtr(struct rte_eth_dev *eth_dev, 597 uint32_t cur_id); 598 int nix_mtr_level_update(struct rte_eth_dev *eth_dev, uint32_t id, 599 uint32_t level); 600 int nix_mtr_capabilities_init(struct rte_eth_dev *eth_dev); 601 int nix_mtr_configure(struct rte_eth_dev *eth_dev, uint32_t id); 602 int nix_mtr_connect(struct rte_eth_dev *eth_dev, uint32_t id); 603 int nix_mtr_destroy(struct rte_eth_dev *eth_dev, uint32_t id, 604 struct rte_mtr_error *error); 605 int nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id, 606 uint32_t *prev_id, uint32_t *next_id, 607 struct cnxk_mtr_policy_node *policy, 608 int *tree_level); 609 610 /* Inlines */ 611 static __rte_always_inline uint64_t 612 cnxk_pktmbuf_detach(struct rte_mbuf *m) 613 { 614 struct rte_mempool *mp = m->pool; 615 uint32_t mbuf_size, buf_len; 616 struct rte_mbuf *md; 617 uint16_t priv_size; 618 uint16_t refcount; 619 620 /* Update refcount of direct mbuf */ 621 md = rte_mbuf_from_indirect(m); 622 refcount = rte_mbuf_refcnt_update(md, -1); 623 624 priv_size = rte_pktmbuf_priv_size(mp); 625 mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size); 626 buf_len = rte_pktmbuf_data_room_size(mp); 627 628 m->priv_size = priv_size; 629 m->buf_addr = (char *)m + mbuf_size; 630 m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size; 631 m->buf_len = (uint16_t)buf_len; 632 rte_pktmbuf_reset_headroom(m); 633 m->data_len = 0; 634 m->ol_flags = 0; 635 m->next = NULL; 636 m->nb_segs = 1; 637 638 /* Now indirect mbuf is safe to free */ 639 rte_pktmbuf_free(m); 640 641 if (refcount == 0) { 642 rte_mbuf_refcnt_set(md, 1); 643 md->data_len = 0; 644 md->ol_flags = 0; 645 md->next = NULL; 646 md->nb_segs = 1; 647 return 0; 648 } else { 649 return 1; 650 } 651 } 652 653 static __rte_always_inline uint64_t 654 cnxk_nix_prefree_seg(struct rte_mbuf *m) 655 { 656 if (likely(rte_mbuf_refcnt_read(m) == 1)) { 657 if (!RTE_MBUF_DIRECT(m)) 658 return cnxk_pktmbuf_detach(m); 659 660 m->next = NULL; 661 m->nb_segs = 1; 662 return 0; 663 } else if (rte_mbuf_refcnt_update(m, -1) == 0) { 664 if (!RTE_MBUF_DIRECT(m)) 665 return cnxk_pktmbuf_detach(m); 666 667 rte_mbuf_refcnt_set(m, 1); 668 m->next = NULL; 669 m->nb_segs = 1; 670 return 0; 671 } 672 673 /* Mbuf is having refcount more than 1 so need not to be freed */ 674 return 1; 675 } 676 677 static inline rte_mbuf_timestamp_t * 678 cnxk_nix_timestamp_dynfield(struct rte_mbuf *mbuf, 679 struct cnxk_timesync_info *info) 680 { 681 return RTE_MBUF_DYNFIELD(mbuf, info->tstamp_dynfield_offset, 682 rte_mbuf_timestamp_t *); 683 } 684 685 static __rte_always_inline void 686 cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf, 687 struct cnxk_timesync_info *tstamp, 688 const uint8_t ts_enable, const uint8_t mseg_enable, 689 uint64_t *tstamp_ptr) 690 { 691 if (ts_enable) { 692 if (!mseg_enable) { 693 mbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET; 694 mbuf->data_len -= CNXK_NIX_TIMESYNC_RX_OFFSET; 695 } 696 697 /* Reading the rx timestamp inserted by CGX, viz at 698 * starting of the packet data. 699 */ 700 *cnxk_nix_timestamp_dynfield(mbuf, tstamp) = 701 rte_be_to_cpu_64(*tstamp_ptr); 702 /* RTE_MBUF_F_RX_IEEE1588_TMST flag needs to be set only in case 703 * PTP packets are received. 704 */ 705 if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) { 706 tstamp->rx_tstamp = 707 *cnxk_nix_timestamp_dynfield(mbuf, tstamp); 708 tstamp->rx_ready = 1; 709 mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP | 710 RTE_MBUF_F_RX_IEEE1588_TMST | 711 tstamp->rx_tstamp_dynflag; 712 } 713 } 714 } 715 716 static __rte_always_inline uintptr_t 717 cnxk_nix_sa_base_get(uint16_t port, const void *lookup_mem) 718 { 719 uintptr_t sa_base_tbl; 720 721 sa_base_tbl = (uintptr_t)lookup_mem; 722 sa_base_tbl += PTYPE_ARRAY_SZ + ERR_ARRAY_SZ; 723 return *((const uintptr_t *)sa_base_tbl + port); 724 } 725 726 #endif /* __CNXK_ETHDEV_H__ */ 727