1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 #ifndef __CNXK_ETHDEV_H__ 5 #define __CNXK_ETHDEV_H__ 6 7 #include <math.h> 8 #include <stdint.h> 9 10 #include <ethdev_driver.h> 11 #include <ethdev_pci.h> 12 #include <rte_kvargs.h> 13 #include <rte_mbuf.h> 14 #include <rte_mbuf_pool_ops.h> 15 #include <rte_mempool.h> 16 #include <rte_time.h> 17 18 #include "roc_api.h" 19 20 #define CNXK_ETH_DEV_PMD_VERSION "1.0" 21 22 /* Used for struct cnxk_eth_dev::flags */ 23 #define CNXK_LINK_CFG_IN_PROGRESS_F BIT_ULL(0) 24 25 /* VLAN tag inserted by NIX_TX_VTAG_ACTION. 26 * In Tx space is always reserved for this in FRS. 27 */ 28 #define CNXK_NIX_MAX_VTAG_INS 2 29 #define CNXK_NIX_MAX_VTAG_ACT_SIZE (4 * CNXK_NIX_MAX_VTAG_INS) 30 31 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */ 32 #define CNXK_NIX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + \ 33 RTE_ETHER_CRC_LEN + \ 34 CNXK_NIX_MAX_VTAG_ACT_SIZE) 35 36 #define CNXK_NIX_RX_MIN_DESC 16 37 #define CNXK_NIX_RX_MIN_DESC_ALIGN 16 38 #define CNXK_NIX_RX_NB_SEG_MAX 6 39 #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096 40 /* Max supported SQB count */ 41 #define CNXK_NIX_TX_MAX_SQB 512 42 43 /* If PTP is enabled additional SEND MEM DESC is required which 44 * takes 2 words, hence max 7 iova address are possible 45 */ 46 #if defined(RTE_LIBRTE_IEEE1588) 47 #define CNXK_NIX_TX_NB_SEG_MAX 7 48 #else 49 #define CNXK_NIX_TX_NB_SEG_MAX 9 50 #endif 51 52 #define CNXK_NIX_TX_MSEG_SG_DWORDS \ 53 ((RTE_ALIGN_MUL_CEIL(CNXK_NIX_TX_NB_SEG_MAX, 3) / 3) + \ 54 CNXK_NIX_TX_NB_SEG_MAX) 55 56 #define CNXK_NIX_RSS_L3_L4_SRC_DST \ 57 (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | ETH_RSS_L4_SRC_ONLY | \ 58 ETH_RSS_L4_DST_ONLY) 59 60 #define CNXK_NIX_RSS_OFFLOAD \ 61 (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \ 62 ETH_RSS_SCTP | ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \ 63 CNXK_NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | ETH_RSS_C_VLAN) 64 65 #define CNXK_NIX_TX_OFFLOAD_CAPA \ 66 (DEV_TX_OFFLOAD_MBUF_FAST_FREE | DEV_TX_OFFLOAD_MT_LOCKFREE | \ 67 DEV_TX_OFFLOAD_VLAN_INSERT | DEV_TX_OFFLOAD_QINQ_INSERT | \ 68 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \ 69 DEV_TX_OFFLOAD_TCP_CKSUM | DEV_TX_OFFLOAD_UDP_CKSUM | \ 70 DEV_TX_OFFLOAD_SCTP_CKSUM | DEV_TX_OFFLOAD_TCP_TSO | \ 71 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 72 DEV_TX_OFFLOAD_GRE_TNL_TSO | DEV_TX_OFFLOAD_MULTI_SEGS | \ 73 DEV_TX_OFFLOAD_IPV4_CKSUM) 74 75 #define CNXK_NIX_RX_OFFLOAD_CAPA \ 76 (DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_SCTP_CKSUM | \ 77 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | DEV_RX_OFFLOAD_SCATTER | \ 78 DEV_RX_OFFLOAD_JUMBO_FRAME | DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \ 79 DEV_RX_OFFLOAD_RSS_HASH | DEV_RX_OFFLOAD_TIMESTAMP | \ 80 DEV_RX_OFFLOAD_VLAN_STRIP) 81 82 #define RSS_IPV4_ENABLE \ 83 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_UDP | \ 84 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_SCTP) 85 86 #define RSS_IPV6_ENABLE \ 87 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_UDP | \ 88 ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_NONFRAG_IPV6_SCTP) 89 90 #define RSS_IPV6_EX_ENABLE \ 91 (ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | ETH_RSS_IPV6_UDP_EX) 92 93 #define RSS_MAX_LEVELS 3 94 95 #define RSS_IPV4_INDEX 0 96 #define RSS_IPV6_INDEX 1 97 #define RSS_TCP_INDEX 2 98 #define RSS_UDP_INDEX 3 99 #define RSS_SCTP_INDEX 4 100 #define RSS_DMAC_INDEX 5 101 102 /* Default mark value used when none is provided. */ 103 #define CNXK_FLOW_ACTION_FLAG_DEFAULT 0xffff 104 105 /* Default cycle counter mask */ 106 #define CNXK_CYCLECOUNTER_MASK 0xffffffffffffffffULL 107 #define CNXK_NIX_TIMESYNC_RX_OFFSET 8 108 109 #define PTYPE_NON_TUNNEL_WIDTH 16 110 #define PTYPE_TUNNEL_WIDTH 12 111 #define PTYPE_NON_TUNNEL_ARRAY_SZ BIT(PTYPE_NON_TUNNEL_WIDTH) 112 #define PTYPE_TUNNEL_ARRAY_SZ BIT(PTYPE_TUNNEL_WIDTH) 113 #define PTYPE_ARRAY_SZ \ 114 ((PTYPE_NON_TUNNEL_ARRAY_SZ + PTYPE_TUNNEL_ARRAY_SZ) * sizeof(uint16_t)) 115 /* Fastpath lookup */ 116 #define CNXK_NIX_FASTPATH_LOOKUP_MEM "cnxk_nix_fastpath_lookup_mem" 117 118 #define CNXK_NIX_UDP_TUN_BITMASK \ 119 ((1ull << (PKT_TX_TUNNEL_VXLAN >> 45)) | \ 120 (1ull << (PKT_TX_TUNNEL_GENEVE >> 45))) 121 122 struct cnxk_fc_cfg { 123 enum rte_eth_fc_mode mode; 124 uint8_t rx_pause; 125 uint8_t tx_pause; 126 }; 127 128 struct cnxk_eth_qconf { 129 union { 130 struct rte_eth_txconf tx; 131 struct rte_eth_rxconf rx; 132 } conf; 133 struct rte_mempool *mp; 134 uint16_t nb_desc; 135 uint8_t valid; 136 }; 137 138 struct cnxk_timesync_info { 139 uint8_t rx_ready; 140 uint64_t rx_tstamp; 141 uint64_t rx_tstamp_dynflag; 142 int tstamp_dynfield_offset; 143 rte_iova_t tx_tstamp_iova; 144 uint64_t *tx_tstamp; 145 } __plt_cache_aligned; 146 147 struct cnxk_eth_dev { 148 /* ROC NIX */ 149 struct roc_nix nix; 150 151 /* ROC NPC */ 152 struct roc_npc npc; 153 154 /* ROC RQs, SQs and CQs */ 155 struct roc_nix_rq *rqs; 156 struct roc_nix_sq *sqs; 157 struct roc_nix_cq *cqs; 158 159 /* Configured queue count */ 160 uint16_t nb_rxq; 161 uint16_t nb_txq; 162 uint8_t configured; 163 164 /* Max macfilter entries */ 165 uint8_t dmac_filter_count; 166 uint8_t max_mac_entries; 167 bool dmac_filter_enable; 168 169 uint16_t flags; 170 uint8_t ptype_disable; 171 bool scalar_ena; 172 bool ptp_en; 173 174 /* Pointer back to rte */ 175 struct rte_eth_dev *eth_dev; 176 177 /* HW capabilities / Limitations */ 178 union { 179 struct { 180 uint64_t cq_min_4k : 1; 181 }; 182 uint64_t hwcap; 183 }; 184 185 /* Rx and Tx offload capabilities */ 186 uint64_t rx_offload_capa; 187 uint64_t tx_offload_capa; 188 uint32_t speed_capa; 189 /* Configured Rx and Tx offloads */ 190 uint64_t rx_offloads; 191 uint64_t tx_offloads; 192 /* Platform specific offload flags */ 193 uint16_t rx_offload_flags; 194 uint16_t tx_offload_flags; 195 196 /* ETHDEV RSS HF bitmask */ 197 uint64_t ethdev_rss_hf; 198 199 /* Saved qconf before lf realloc */ 200 struct cnxk_eth_qconf *tx_qconf; 201 struct cnxk_eth_qconf *rx_qconf; 202 203 /* Flow control configuration */ 204 struct cnxk_fc_cfg fc_cfg; 205 206 /* PTP Counters */ 207 struct cnxk_timesync_info tstamp; 208 struct rte_timecounter systime_tc; 209 struct rte_timecounter rx_tstamp_tc; 210 struct rte_timecounter tx_tstamp_tc; 211 double clk_freq_mult; 212 uint64_t clk_delta; 213 214 /* Rx burst for cleanup(Only Primary) */ 215 eth_rx_burst_t rx_pkt_burst_no_offload; 216 217 /* Default mac address */ 218 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 219 220 /* LSO Tunnel format indices */ 221 uint64_t lso_tun_fmt; 222 223 /* Per queue statistics counters */ 224 uint32_t txq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS]; 225 uint32_t rxq_stat_map[RTE_ETHDEV_QUEUE_STAT_CNTRS]; 226 }; 227 228 struct cnxk_eth_rxq_sp { 229 struct cnxk_eth_dev *dev; 230 struct cnxk_eth_qconf qconf; 231 uint16_t qid; 232 } __plt_cache_aligned; 233 234 struct cnxk_eth_txq_sp { 235 struct cnxk_eth_dev *dev; 236 struct cnxk_eth_qconf qconf; 237 uint16_t qid; 238 } __plt_cache_aligned; 239 240 static inline struct cnxk_eth_dev * 241 cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev) 242 { 243 return eth_dev->data->dev_private; 244 } 245 246 static inline struct cnxk_eth_rxq_sp * 247 cnxk_eth_rxq_to_sp(void *__rxq) 248 { 249 return ((struct cnxk_eth_rxq_sp *)__rxq) - 1; 250 } 251 252 static inline struct cnxk_eth_txq_sp * 253 cnxk_eth_txq_to_sp(void *__txq) 254 { 255 return ((struct cnxk_eth_txq_sp *)__txq) - 1; 256 } 257 258 /* Common ethdev ops */ 259 extern struct eth_dev_ops cnxk_eth_dev_ops; 260 261 /* Common flow ops */ 262 extern struct rte_flow_ops cnxk_flow_ops; 263 264 /* Ops */ 265 int cnxk_nix_probe(struct rte_pci_driver *pci_drv, 266 struct rte_pci_device *pci_dev); 267 int cnxk_nix_remove(struct rte_pci_device *pci_dev); 268 int cnxk_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu); 269 int cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev, 270 struct rte_ether_addr *mc_addr_set, 271 uint32_t nb_mc_addr); 272 int cnxk_nix_mac_addr_add(struct rte_eth_dev *eth_dev, 273 struct rte_ether_addr *addr, uint32_t index, 274 uint32_t pool); 275 void cnxk_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index); 276 int cnxk_nix_mac_addr_set(struct rte_eth_dev *eth_dev, 277 struct rte_ether_addr *addr); 278 int cnxk_nix_promisc_enable(struct rte_eth_dev *eth_dev); 279 int cnxk_nix_promisc_disable(struct rte_eth_dev *eth_dev); 280 int cnxk_nix_allmulticast_enable(struct rte_eth_dev *eth_dev); 281 int cnxk_nix_allmulticast_disable(struct rte_eth_dev *eth_dev); 282 int cnxk_nix_info_get(struct rte_eth_dev *eth_dev, 283 struct rte_eth_dev_info *dev_info); 284 int cnxk_nix_rx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id, 285 struct rte_eth_burst_mode *mode); 286 int cnxk_nix_tx_burst_mode_get(struct rte_eth_dev *eth_dev, uint16_t queue_id, 287 struct rte_eth_burst_mode *mode); 288 int cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev, 289 struct rte_eth_fc_conf *fc_conf); 290 int cnxk_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev, 291 struct rte_eth_fc_conf *fc_conf); 292 int cnxk_nix_set_link_up(struct rte_eth_dev *eth_dev); 293 int cnxk_nix_set_link_down(struct rte_eth_dev *eth_dev); 294 int cnxk_nix_get_module_info(struct rte_eth_dev *eth_dev, 295 struct rte_eth_dev_module_info *modinfo); 296 int cnxk_nix_get_module_eeprom(struct rte_eth_dev *eth_dev, 297 struct rte_dev_eeprom_info *info); 298 int cnxk_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev, 299 uint16_t rx_queue_id); 300 int cnxk_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev, 301 uint16_t rx_queue_id); 302 int cnxk_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool); 303 int cnxk_nix_tx_done_cleanup(void *txq, uint32_t free_cnt); 304 int cnxk_nix_flow_ops_get(struct rte_eth_dev *eth_dev, 305 const struct rte_flow_ops **ops); 306 int cnxk_nix_configure(struct rte_eth_dev *eth_dev); 307 int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, 308 uint16_t nb_desc, uint16_t fp_tx_q_sz, 309 const struct rte_eth_txconf *tx_conf); 310 int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, 311 uint16_t nb_desc, uint16_t fp_rx_q_sz, 312 const struct rte_eth_rxconf *rx_conf, 313 struct rte_mempool *mp); 314 int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid); 315 int cnxk_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qid); 316 int cnxk_nix_dev_start(struct rte_eth_dev *eth_dev); 317 int cnxk_nix_timesync_enable(struct rte_eth_dev *eth_dev); 318 int cnxk_nix_timesync_disable(struct rte_eth_dev *eth_dev); 319 int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev, 320 struct timespec *timestamp, 321 uint32_t flags); 322 int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev, 323 struct timespec *timestamp); 324 int cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev, 325 struct timespec *ts); 326 int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev, 327 const struct timespec *ts); 328 int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta); 329 int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev); 330 int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock); 331 332 uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev); 333 334 /* RSS */ 335 uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss, 336 uint8_t rss_level); 337 int cnxk_nix_reta_update(struct rte_eth_dev *eth_dev, 338 struct rte_eth_rss_reta_entry64 *reta_conf, 339 uint16_t reta_size); 340 int cnxk_nix_reta_query(struct rte_eth_dev *eth_dev, 341 struct rte_eth_rss_reta_entry64 *reta_conf, 342 uint16_t reta_size); 343 int cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev, 344 struct rte_eth_rss_conf *rss_conf); 345 int cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 346 struct rte_eth_rss_conf *rss_conf); 347 348 /* Link */ 349 void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set); 350 void cnxk_eth_dev_link_status_cb(struct roc_nix *nix, 351 struct roc_nix_link_info *link); 352 int cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete); 353 int cnxk_nix_queue_stats_mapping(struct rte_eth_dev *dev, uint16_t queue_id, 354 uint8_t stat_idx, uint8_t is_rx); 355 int cnxk_nix_stats_reset(struct rte_eth_dev *dev); 356 int cnxk_nix_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 357 int cnxk_nix_xstats_get(struct rte_eth_dev *eth_dev, 358 struct rte_eth_xstat *xstats, unsigned int n); 359 int cnxk_nix_xstats_get_names(struct rte_eth_dev *eth_dev, 360 struct rte_eth_xstat_name *xstats_names, 361 unsigned int limit); 362 int cnxk_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 363 struct rte_eth_xstat_name *xstats_names, 364 const uint64_t *ids, unsigned int limit); 365 int cnxk_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 366 uint64_t *values, unsigned int n); 367 int cnxk_nix_xstats_reset(struct rte_eth_dev *eth_dev); 368 int cnxk_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version, 369 size_t fw_size); 370 void cnxk_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid, 371 struct rte_eth_rxq_info *qinfo); 372 void cnxk_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t qid, 373 struct rte_eth_txq_info *qinfo); 374 375 /* Lookup configuration */ 376 const uint32_t *cnxk_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev); 377 void *cnxk_nix_fastpath_lookup_mem_get(void); 378 379 /* Devargs */ 380 int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, 381 struct cnxk_eth_dev *dev); 382 383 /* Debug */ 384 int cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev, 385 struct rte_dev_reg_info *regs); 386 387 /* Other private functions */ 388 int nix_recalc_mtu(struct rte_eth_dev *eth_dev); 389 390 /* Inlines */ 391 static __rte_always_inline uint64_t 392 cnxk_pktmbuf_detach(struct rte_mbuf *m) 393 { 394 struct rte_mempool *mp = m->pool; 395 uint32_t mbuf_size, buf_len; 396 struct rte_mbuf *md; 397 uint16_t priv_size; 398 uint16_t refcount; 399 400 /* Update refcount of direct mbuf */ 401 md = rte_mbuf_from_indirect(m); 402 refcount = rte_mbuf_refcnt_update(md, -1); 403 404 priv_size = rte_pktmbuf_priv_size(mp); 405 mbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size); 406 buf_len = rte_pktmbuf_data_room_size(mp); 407 408 m->priv_size = priv_size; 409 m->buf_addr = (char *)m + mbuf_size; 410 m->buf_iova = rte_mempool_virt2iova(m) + mbuf_size; 411 m->buf_len = (uint16_t)buf_len; 412 rte_pktmbuf_reset_headroom(m); 413 m->data_len = 0; 414 m->ol_flags = 0; 415 m->next = NULL; 416 m->nb_segs = 1; 417 418 /* Now indirect mbuf is safe to free */ 419 rte_pktmbuf_free(m); 420 421 if (refcount == 0) { 422 rte_mbuf_refcnt_set(md, 1); 423 md->data_len = 0; 424 md->ol_flags = 0; 425 md->next = NULL; 426 md->nb_segs = 1; 427 return 0; 428 } else { 429 return 1; 430 } 431 } 432 433 static __rte_always_inline uint64_t 434 cnxk_nix_prefree_seg(struct rte_mbuf *m) 435 { 436 if (likely(rte_mbuf_refcnt_read(m) == 1)) { 437 if (!RTE_MBUF_DIRECT(m)) 438 return cnxk_pktmbuf_detach(m); 439 440 m->next = NULL; 441 m->nb_segs = 1; 442 return 0; 443 } else if (rte_mbuf_refcnt_update(m, -1) == 0) { 444 if (!RTE_MBUF_DIRECT(m)) 445 return cnxk_pktmbuf_detach(m); 446 447 rte_mbuf_refcnt_set(m, 1); 448 m->next = NULL; 449 m->nb_segs = 1; 450 return 0; 451 } 452 453 /* Mbuf is having refcount more than 1 so need not to be freed */ 454 return 1; 455 } 456 457 static inline rte_mbuf_timestamp_t * 458 cnxk_nix_timestamp_dynfield(struct rte_mbuf *mbuf, 459 struct cnxk_timesync_info *info) 460 { 461 return RTE_MBUF_DYNFIELD(mbuf, info->tstamp_dynfield_offset, 462 rte_mbuf_timestamp_t *); 463 } 464 465 static __rte_always_inline void 466 cnxk_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf, 467 struct cnxk_timesync_info *tstamp, 468 const uint8_t ts_enable, const uint8_t mseg_enable, 469 uint64_t *tstamp_ptr) 470 { 471 if (ts_enable) { 472 if (!mseg_enable) { 473 mbuf->pkt_len -= CNXK_NIX_TIMESYNC_RX_OFFSET; 474 mbuf->data_len -= CNXK_NIX_TIMESYNC_RX_OFFSET; 475 } 476 477 /* Reading the rx timestamp inserted by CGX, viz at 478 * starting of the packet data. 479 */ 480 *cnxk_nix_timestamp_dynfield(mbuf, tstamp) = 481 rte_be_to_cpu_64(*tstamp_ptr); 482 /* PKT_RX_IEEE1588_TMST flag needs to be set only in case 483 * PTP packets are received. 484 */ 485 if (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) { 486 tstamp->rx_tstamp = 487 *cnxk_nix_timestamp_dynfield(mbuf, tstamp); 488 tstamp->rx_ready = 1; 489 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP | 490 PKT_RX_IEEE1588_TMST | 491 tstamp->rx_tstamp_dynflag; 492 } 493 } 494 } 495 496 #endif /* __CNXK_ETHDEV_H__ */ 497