1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 #include "cn10k_ethdev.h" 5 #include "cn10k_rte_flow.h" 6 #include "cn10k_rx.h" 7 #include "cn10k_tx.h" 8 9 static uint16_t 10 nix_rx_offload_flags(struct rte_eth_dev *eth_dev) 11 { 12 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 13 struct rte_eth_dev_data *data = eth_dev->data; 14 struct rte_eth_conf *conf = &data->dev_conf; 15 struct rte_eth_rxmode *rxmode = &conf->rxmode; 16 uint16_t flags = 0; 17 18 if (rxmode->mq_mode == ETH_MQ_RX_RSS && 19 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH)) 20 flags |= NIX_RX_OFFLOAD_RSS_F; 21 22 if (dev->rx_offloads & 23 (DEV_RX_OFFLOAD_TCP_CKSUM | DEV_RX_OFFLOAD_UDP_CKSUM)) 24 flags |= NIX_RX_OFFLOAD_CHECKSUM_F; 25 26 if (dev->rx_offloads & 27 (DEV_RX_OFFLOAD_IPV4_CKSUM | DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM)) 28 flags |= NIX_RX_OFFLOAD_CHECKSUM_F; 29 30 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER) 31 flags |= NIX_RX_MULTI_SEG_F; 32 33 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)) 34 flags |= NIX_RX_OFFLOAD_TSTAMP_F; 35 36 if (!dev->ptype_disable) 37 flags |= NIX_RX_OFFLOAD_PTYPE_F; 38 39 return flags; 40 } 41 42 static uint16_t 43 nix_tx_offload_flags(struct rte_eth_dev *eth_dev) 44 { 45 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 46 uint64_t conf = dev->tx_offloads; 47 uint16_t flags = 0; 48 49 /* Fastpath is dependent on these enums */ 50 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52)); 51 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52)); 52 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52)); 53 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54)); 54 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55)); 55 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58)); 56 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59)); 57 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60)); 58 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41)); 59 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7); 60 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9); 61 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7); 62 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9); 63 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) != 64 offsetof(struct rte_mbuf, buf_iova) + 8); 65 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) != 66 offsetof(struct rte_mbuf, buf_iova) + 16); 67 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) != 68 offsetof(struct rte_mbuf, ol_flags) + 12); 69 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) != 70 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *)); 71 72 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT || 73 conf & DEV_TX_OFFLOAD_QINQ_INSERT) 74 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F; 75 76 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM || 77 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM) 78 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F; 79 80 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM || 81 conf & DEV_TX_OFFLOAD_TCP_CKSUM || 82 conf & DEV_TX_OFFLOAD_UDP_CKSUM || conf & DEV_TX_OFFLOAD_SCTP_CKSUM) 83 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F; 84 85 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE)) 86 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F; 87 88 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS) 89 flags |= NIX_TX_MULTI_SEG_F; 90 91 /* Enable Inner checksum for TSO */ 92 if (conf & DEV_TX_OFFLOAD_TCP_TSO) 93 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_L3_L4_CSUM_F); 94 95 /* Enable Inner and Outer checksum for Tunnel TSO */ 96 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 97 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | DEV_TX_OFFLOAD_GRE_TNL_TSO)) 98 flags |= (NIX_TX_OFFLOAD_TSO_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F | 99 NIX_TX_OFFLOAD_L3_L4_CSUM_F); 100 101 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)) 102 flags |= NIX_TX_OFFLOAD_TSTAMP_F; 103 104 return flags; 105 } 106 107 static int 108 cn10k_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask) 109 { 110 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 111 112 if (ptype_mask) { 113 dev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F; 114 dev->ptype_disable = 0; 115 } else { 116 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F; 117 dev->ptype_disable = 1; 118 } 119 120 cn10k_eth_set_rx_function(eth_dev); 121 return 0; 122 } 123 124 static void 125 nix_form_default_desc(struct cnxk_eth_dev *dev, struct cn10k_eth_txq *txq, 126 uint16_t qid) 127 { 128 struct nix_send_ext_s *send_hdr_ext; 129 union nix_send_hdr_w0_u send_hdr_w0; 130 struct nix_send_mem_s *send_mem; 131 union nix_send_sg_s sg_w0; 132 133 RTE_SET_USED(dev); 134 135 /* Initialize the fields based on basic single segment packet */ 136 memset(&txq->cmd, 0, sizeof(txq->cmd)); 137 send_hdr_w0.u = 0; 138 sg_w0.u = 0; 139 140 if (dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) { 141 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */ 142 send_hdr_w0.sizem1 = 2; 143 144 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[0]; 145 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT; 146 if (dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) { 147 /* Default: one seg packet would have: 148 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM) 149 * => 8/2 - 1 = 3 150 */ 151 send_hdr_w0.sizem1 = 3; 152 send_hdr_ext->w0.tstmp = 1; 153 154 /* To calculate the offset for send_mem, 155 * send_hdr->w0.sizem1 * 2 156 */ 157 send_mem = (struct nix_send_mem_s *)(txq->cmd + 2); 158 send_mem->w0.subdc = NIX_SUBDC_MEM; 159 send_mem->w0.alg = NIX_SENDMEMALG_SETTSTMP; 160 send_mem->addr = dev->tstamp.tx_tstamp_iova; 161 } 162 } else { 163 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */ 164 send_hdr_w0.sizem1 = 1; 165 } 166 167 send_hdr_w0.sq = qid; 168 sg_w0.subdc = NIX_SUBDC_SG; 169 sg_w0.segs = 1; 170 sg_w0.ld_type = NIX_SENDLDTYPE_LDD; 171 172 txq->send_hdr_w0 = send_hdr_w0.u; 173 txq->sg_w0 = sg_w0.u; 174 175 rte_wmb(); 176 } 177 178 static int 179 cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, 180 uint16_t nb_desc, unsigned int socket, 181 const struct rte_eth_txconf *tx_conf) 182 { 183 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 184 struct cn10k_eth_txq *txq; 185 struct roc_nix_sq *sq; 186 int rc; 187 188 RTE_SET_USED(socket); 189 190 /* Common Tx queue setup */ 191 rc = cnxk_nix_tx_queue_setup(eth_dev, qid, nb_desc, 192 sizeof(struct cn10k_eth_txq), tx_conf); 193 if (rc) 194 return rc; 195 196 sq = &dev->sqs[qid]; 197 /* Update fast path queue */ 198 txq = eth_dev->data->tx_queues[qid]; 199 txq->fc_mem = sq->fc; 200 /* Store lmt base in tx queue for easy access */ 201 txq->lmt_base = dev->nix.lmt_base; 202 txq->io_addr = sq->io_addr; 203 txq->nb_sqb_bufs_adj = sq->nb_sqb_bufs_adj; 204 txq->sqes_per_sqb_log2 = sq->sqes_per_sqb_log2; 205 206 nix_form_default_desc(dev, txq, qid); 207 txq->lso_tun_fmt = dev->lso_tun_fmt; 208 return 0; 209 } 210 211 static int 212 cn10k_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, 213 uint16_t nb_desc, unsigned int socket, 214 const struct rte_eth_rxconf *rx_conf, 215 struct rte_mempool *mp) 216 { 217 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 218 struct cn10k_eth_rxq *rxq; 219 struct roc_nix_rq *rq; 220 struct roc_nix_cq *cq; 221 int rc; 222 223 RTE_SET_USED(socket); 224 225 /* CQ Errata needs min 4K ring */ 226 if (dev->cq_min_4k && nb_desc < 4096) 227 nb_desc = 4096; 228 229 /* Common Rx queue setup */ 230 rc = cnxk_nix_rx_queue_setup(eth_dev, qid, nb_desc, 231 sizeof(struct cn10k_eth_rxq), rx_conf, mp); 232 if (rc) 233 return rc; 234 235 rq = &dev->rqs[qid]; 236 cq = &dev->cqs[qid]; 237 238 /* Update fast path queue */ 239 rxq = eth_dev->data->rx_queues[qid]; 240 rxq->rq = qid; 241 rxq->desc = (uintptr_t)cq->desc_base; 242 rxq->cq_door = cq->door; 243 rxq->cq_status = cq->status; 244 rxq->wdata = cq->wdata; 245 rxq->head = cq->head; 246 rxq->qmask = cq->qmask; 247 rxq->tstamp = &dev->tstamp; 248 249 /* Data offset from data to start of mbuf is first_skip */ 250 rxq->data_off = rq->first_skip; 251 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev); 252 253 /* Lookup mem */ 254 rxq->lookup_mem = cnxk_nix_fastpath_lookup_mem_get(); 255 return 0; 256 } 257 258 static int 259 cn10k_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx) 260 { 261 struct cn10k_eth_txq *txq = eth_dev->data->tx_queues[qidx]; 262 int rc; 263 264 rc = cnxk_nix_tx_queue_stop(eth_dev, qidx); 265 if (rc) 266 return rc; 267 268 /* Clear fc cache pkts to trigger worker stop */ 269 txq->fc_cache_pkts = 0; 270 return 0; 271 } 272 273 static int 274 cn10k_nix_configure(struct rte_eth_dev *eth_dev) 275 { 276 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 277 int rc; 278 279 /* Common nix configure */ 280 rc = cnxk_nix_configure(eth_dev); 281 if (rc) 282 return rc; 283 284 /* Update offload flags */ 285 dev->rx_offload_flags = nix_rx_offload_flags(eth_dev); 286 dev->tx_offload_flags = nix_tx_offload_flags(eth_dev); 287 288 plt_nix_dbg("Configured port%d platform specific rx_offload_flags=%x" 289 " tx_offload_flags=0x%x", 290 eth_dev->data->port_id, dev->rx_offload_flags, 291 dev->tx_offload_flags); 292 return 0; 293 } 294 295 /* Function to enable ptp config for VFs */ 296 static void 297 nix_ptp_enable_vf(struct rte_eth_dev *eth_dev) 298 { 299 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 300 301 if (nix_recalc_mtu(eth_dev)) 302 plt_err("Failed to set MTU size for ptp"); 303 304 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F; 305 306 /* Setting up the function pointers as per new offload flags */ 307 cn10k_eth_set_rx_function(eth_dev); 308 cn10k_eth_set_tx_function(eth_dev); 309 } 310 311 static uint16_t 312 nix_ptp_vf_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts) 313 { 314 struct cn10k_eth_rxq *rxq = queue; 315 struct cnxk_eth_rxq_sp *rxq_sp; 316 struct rte_eth_dev *eth_dev; 317 318 RTE_SET_USED(mbufs); 319 RTE_SET_USED(pkts); 320 321 rxq_sp = cnxk_eth_rxq_to_sp(rxq); 322 eth_dev = rxq_sp->dev->eth_dev; 323 nix_ptp_enable_vf(eth_dev); 324 325 return 0; 326 } 327 328 static int 329 cn10k_nix_ptp_info_update_cb(struct roc_nix *nix, bool ptp_en) 330 { 331 struct cnxk_eth_dev *dev = (struct cnxk_eth_dev *)nix; 332 struct rte_eth_dev *eth_dev; 333 struct cn10k_eth_rxq *rxq; 334 int i; 335 336 if (!dev) 337 return -EINVAL; 338 339 eth_dev = dev->eth_dev; 340 if (!eth_dev) 341 return -EINVAL; 342 343 dev->ptp_en = ptp_en; 344 345 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 346 rxq = eth_dev->data->rx_queues[i]; 347 rxq->mbuf_initializer = cnxk_nix_rxq_mbuf_setup(dev); 348 } 349 350 if (roc_nix_is_vf_or_sdp(nix) && !(roc_nix_is_sdp(nix)) && 351 !(roc_nix_is_lbk(nix))) { 352 /* In case of VF, setting of MTU cannot be done directly in this 353 * function as this is running as part of MBOX request(PF->VF) 354 * and MTU setting also requires MBOX message to be 355 * sent(VF->PF) 356 */ 357 eth_dev->rx_pkt_burst = nix_ptp_vf_burst; 358 rte_mb(); 359 } 360 361 return 0; 362 } 363 364 static int 365 cn10k_nix_timesync_enable(struct rte_eth_dev *eth_dev) 366 { 367 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 368 int i, rc; 369 370 rc = cnxk_nix_timesync_enable(eth_dev); 371 if (rc) 372 return rc; 373 374 dev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F; 375 dev->tx_offload_flags |= NIX_TX_OFFLOAD_TSTAMP_F; 376 377 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) 378 nix_form_default_desc(dev, eth_dev->data->tx_queues[i], i); 379 380 /* Setting up the rx[tx]_offload_flags due to change 381 * in rx[tx]_offloads. 382 */ 383 cn10k_eth_set_rx_function(eth_dev); 384 cn10k_eth_set_tx_function(eth_dev); 385 return 0; 386 } 387 388 static int 389 cn10k_nix_timesync_disable(struct rte_eth_dev *eth_dev) 390 { 391 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 392 int i, rc; 393 394 rc = cnxk_nix_timesync_disable(eth_dev); 395 if (rc) 396 return rc; 397 398 dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_TSTAMP_F; 399 dev->tx_offload_flags &= ~NIX_TX_OFFLOAD_TSTAMP_F; 400 401 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) 402 nix_form_default_desc(dev, eth_dev->data->tx_queues[i], i); 403 404 /* Setting up the rx[tx]_offload_flags due to change 405 * in rx[tx]_offloads. 406 */ 407 cn10k_eth_set_rx_function(eth_dev); 408 cn10k_eth_set_tx_function(eth_dev); 409 return 0; 410 } 411 412 static int 413 cn10k_nix_dev_start(struct rte_eth_dev *eth_dev) 414 { 415 struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); 416 struct roc_nix *nix = &dev->nix; 417 int rc; 418 419 /* Common eth dev start */ 420 rc = cnxk_nix_dev_start(eth_dev); 421 if (rc) 422 return rc; 423 424 /* Update VF about data off shifted by 8 bytes if PTP already 425 * enabled in PF owning this VF 426 */ 427 if (dev->ptp_en && (!roc_nix_is_pf(nix) && (!roc_nix_is_sdp(nix)))) 428 nix_ptp_enable_vf(eth_dev); 429 430 /* Setting up the rx[tx]_offload_flags due to change 431 * in rx[tx]_offloads. 432 */ 433 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev); 434 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev); 435 436 cn10k_eth_set_tx_function(eth_dev); 437 cn10k_eth_set_rx_function(eth_dev); 438 return 0; 439 } 440 441 /* Update platform specific eth dev ops */ 442 static void 443 nix_eth_dev_ops_override(void) 444 { 445 static int init_once; 446 447 if (init_once) 448 return; 449 init_once = 1; 450 451 /* Update platform specific ops */ 452 cnxk_eth_dev_ops.dev_configure = cn10k_nix_configure; 453 cnxk_eth_dev_ops.tx_queue_setup = cn10k_nix_tx_queue_setup; 454 cnxk_eth_dev_ops.rx_queue_setup = cn10k_nix_rx_queue_setup; 455 cnxk_eth_dev_ops.tx_queue_stop = cn10k_nix_tx_queue_stop; 456 cnxk_eth_dev_ops.dev_start = cn10k_nix_dev_start; 457 cnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set; 458 cnxk_eth_dev_ops.timesync_enable = cn10k_nix_timesync_enable; 459 cnxk_eth_dev_ops.timesync_disable = cn10k_nix_timesync_disable; 460 } 461 462 static void 463 npc_flow_ops_override(void) 464 { 465 static int init_once; 466 467 if (init_once) 468 return; 469 init_once = 1; 470 471 /* Update platform specific ops */ 472 cnxk_flow_ops.create = cn10k_flow_create; 473 cnxk_flow_ops.destroy = cn10k_flow_destroy; 474 } 475 476 static int 477 cn10k_nix_remove(struct rte_pci_device *pci_dev) 478 { 479 return cnxk_nix_remove(pci_dev); 480 } 481 482 static int 483 cn10k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) 484 { 485 struct rte_eth_dev *eth_dev; 486 struct cnxk_eth_dev *dev; 487 int rc; 488 489 if (RTE_CACHE_LINE_SIZE != 64) { 490 plt_err("Driver not compiled for CN10K"); 491 return -EFAULT; 492 } 493 494 rc = roc_plt_init(); 495 if (rc) { 496 plt_err("Failed to initialize platform model, rc=%d", rc); 497 return rc; 498 } 499 500 nix_eth_dev_ops_override(); 501 npc_flow_ops_override(); 502 503 /* Common probe */ 504 rc = cnxk_nix_probe(pci_drv, pci_dev); 505 if (rc) 506 return rc; 507 508 /* Find eth dev allocated */ 509 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 510 if (!eth_dev) 511 return -ENOENT; 512 513 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 514 /* Setup callbacks for secondary process */ 515 cn10k_eth_set_tx_function(eth_dev); 516 cn10k_eth_set_rx_function(eth_dev); 517 return 0; 518 } 519 520 dev = cnxk_eth_pmd_priv(eth_dev); 521 522 /* Register up msg callbacks for PTP information */ 523 roc_nix_ptp_info_cb_register(&dev->nix, cn10k_nix_ptp_info_update_cb); 524 525 return 0; 526 } 527 528 static const struct rte_pci_id cn10k_pci_nix_map[] = { 529 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_PF), 530 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_PF), 531 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_VF), 532 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_VF), 533 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_AF_VF), 534 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_AF_VF), 535 { 536 .vendor_id = 0, 537 }, 538 }; 539 540 static struct rte_pci_driver cn10k_pci_nix = { 541 .id_table = cn10k_pci_nix_map, 542 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA | 543 RTE_PCI_DRV_INTR_LSC, 544 .probe = cn10k_nix_probe, 545 .remove = cn10k_nix_remove, 546 }; 547 548 RTE_PMD_REGISTER_PCI(net_cn10k, cn10k_pci_nix); 549 RTE_PMD_REGISTER_PCI_TABLE(net_cn10k, cn10k_pci_nix_map); 550 RTE_PMD_REGISTER_KMOD_DEP(net_cn10k, "vfio-pci"); 551