1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_bitmap.h> 10 #include <rte_byteorder.h> 11 #include <rte_malloc.h> 12 #include <rte_memory.h> 13 14 #include "bnxt.h" 15 #include "bnxt_reps.h" 16 #include "bnxt_ring.h" 17 #include "bnxt_rxr.h" 18 #include "bnxt_rxq.h" 19 #include "hsi_struct_def_dpdk.h" 20 #ifdef RTE_LIBRTE_IEEE1588 21 #include "bnxt_hwrm.h" 22 #endif 23 24 #include <bnxt_tf_common.h> 25 #include <ulp_mark_mgr.h> 26 27 /* 28 * RX Ring handling 29 */ 30 31 static inline struct rte_mbuf *__bnxt_alloc_rx_data(struct rte_mempool *mb) 32 { 33 struct rte_mbuf *data; 34 35 data = rte_mbuf_raw_alloc(mb); 36 37 return data; 38 } 39 40 static inline int bnxt_alloc_rx_data(struct bnxt_rx_queue *rxq, 41 struct bnxt_rx_ring_info *rxr, 42 uint16_t prod) 43 { 44 struct rx_prod_pkt_bd *rxbd = &rxr->rx_desc_ring[prod]; 45 struct rte_mbuf **rx_buf = &rxr->rx_buf_ring[prod]; 46 struct rte_mbuf *mbuf; 47 48 mbuf = __bnxt_alloc_rx_data(rxq->mb_pool); 49 if (!mbuf) { 50 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail); 51 return -ENOMEM; 52 } 53 54 *rx_buf = mbuf; 55 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 56 57 rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf)); 58 59 return 0; 60 } 61 62 static inline int bnxt_alloc_ag_data(struct bnxt_rx_queue *rxq, 63 struct bnxt_rx_ring_info *rxr, 64 uint16_t prod) 65 { 66 struct rx_prod_pkt_bd *rxbd = &rxr->ag_desc_ring[prod]; 67 struct rte_mbuf **rx_buf = &rxr->ag_buf_ring[prod]; 68 struct rte_mbuf *mbuf; 69 70 if (rxbd == NULL) { 71 PMD_DRV_LOG(ERR, "Jumbo Frame. rxbd is NULL\n"); 72 return -EINVAL; 73 } 74 75 if (rx_buf == NULL) { 76 PMD_DRV_LOG(ERR, "Jumbo Frame. rx_buf is NULL\n"); 77 return -EINVAL; 78 } 79 80 mbuf = __bnxt_alloc_rx_data(rxq->mb_pool); 81 if (!mbuf) { 82 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail); 83 return -ENOMEM; 84 } 85 86 *rx_buf = mbuf; 87 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 88 89 rxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf)); 90 91 return 0; 92 } 93 94 static inline void bnxt_reuse_rx_mbuf(struct bnxt_rx_ring_info *rxr, 95 struct rte_mbuf *mbuf) 96 { 97 uint16_t prod = RING_NEXT(rxr->rx_ring_struct, rxr->rx_prod); 98 struct rte_mbuf **prod_rx_buf; 99 struct rx_prod_pkt_bd *prod_bd; 100 101 prod_rx_buf = &rxr->rx_buf_ring[prod]; 102 103 RTE_ASSERT(*prod_rx_buf == NULL); 104 RTE_ASSERT(mbuf != NULL); 105 106 *prod_rx_buf = mbuf; 107 108 prod_bd = &rxr->rx_desc_ring[prod]; 109 110 prod_bd->address = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf)); 111 112 rxr->rx_prod = prod; 113 } 114 115 static inline 116 struct rte_mbuf *bnxt_consume_rx_buf(struct bnxt_rx_ring_info *rxr, 117 uint16_t cons) 118 { 119 struct rte_mbuf **cons_rx_buf; 120 struct rte_mbuf *mbuf; 121 122 cons_rx_buf = &rxr->rx_buf_ring[cons]; 123 RTE_ASSERT(*cons_rx_buf != NULL); 124 mbuf = *cons_rx_buf; 125 *cons_rx_buf = NULL; 126 127 return mbuf; 128 } 129 130 static void bnxt_tpa_start(struct bnxt_rx_queue *rxq, 131 struct rx_tpa_start_cmpl *tpa_start, 132 struct rx_tpa_start_cmpl_hi *tpa_start1) 133 { 134 struct bnxt_rx_ring_info *rxr = rxq->rx_ring; 135 uint16_t agg_id; 136 uint16_t data_cons; 137 struct bnxt_tpa_info *tpa_info; 138 struct rte_mbuf *mbuf; 139 140 agg_id = bnxt_tpa_start_agg_id(rxq->bp, tpa_start); 141 142 data_cons = tpa_start->opaque; 143 tpa_info = &rxr->tpa_info[agg_id]; 144 145 mbuf = bnxt_consume_rx_buf(rxr, data_cons); 146 147 bnxt_reuse_rx_mbuf(rxr, tpa_info->mbuf); 148 149 tpa_info->agg_count = 0; 150 tpa_info->mbuf = mbuf; 151 tpa_info->len = rte_le_to_cpu_32(tpa_start->len); 152 153 mbuf->nb_segs = 1; 154 mbuf->next = NULL; 155 mbuf->pkt_len = rte_le_to_cpu_32(tpa_start->len); 156 mbuf->data_len = mbuf->pkt_len; 157 mbuf->port = rxq->port_id; 158 mbuf->ol_flags = PKT_RX_LRO; 159 if (likely(tpa_start->flags_type & 160 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS_RSS_VALID))) { 161 mbuf->hash.rss = rte_le_to_cpu_32(tpa_start->rss_hash); 162 mbuf->ol_flags |= PKT_RX_RSS_HASH; 163 } else { 164 mbuf->hash.fdir.id = rte_le_to_cpu_16(tpa_start1->cfa_code); 165 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID; 166 } 167 if (tpa_start1->flags2 & 168 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN)) { 169 mbuf->vlan_tci = rte_le_to_cpu_32(tpa_start1->metadata); 170 mbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 171 } 172 if (likely(tpa_start1->flags2 & 173 rte_cpu_to_le_32(RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC))) 174 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD; 175 176 /* recycle next mbuf */ 177 data_cons = RING_NEXT(rxr->rx_ring_struct, data_cons); 178 bnxt_reuse_rx_mbuf(rxr, bnxt_consume_rx_buf(rxr, data_cons)); 179 } 180 181 static int bnxt_agg_bufs_valid(struct bnxt_cp_ring_info *cpr, 182 uint8_t agg_bufs, uint32_t raw_cp_cons) 183 { 184 uint16_t last_cp_cons; 185 struct rx_pkt_cmpl *agg_cmpl; 186 187 raw_cp_cons = ADV_RAW_CMP(raw_cp_cons, agg_bufs); 188 last_cp_cons = RING_CMP(cpr->cp_ring_struct, raw_cp_cons); 189 agg_cmpl = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[last_cp_cons]; 190 cpr->valid = FLIP_VALID(raw_cp_cons, 191 cpr->cp_ring_struct->ring_mask, 192 cpr->valid); 193 return CMP_VALID(agg_cmpl, raw_cp_cons, cpr->cp_ring_struct); 194 } 195 196 /* TPA consume agg buffer out of order, allocate connected data only */ 197 static int bnxt_prod_ag_mbuf(struct bnxt_rx_queue *rxq) 198 { 199 struct bnxt_rx_ring_info *rxr = rxq->rx_ring; 200 uint16_t next = RING_NEXT(rxr->ag_ring_struct, rxr->ag_prod); 201 202 /* TODO batch allocation for better performance */ 203 while (rte_bitmap_get(rxr->ag_bitmap, next)) { 204 if (unlikely(bnxt_alloc_ag_data(rxq, rxr, next))) { 205 PMD_DRV_LOG(ERR, 206 "agg mbuf alloc failed: prod=0x%x\n", next); 207 break; 208 } 209 rte_bitmap_clear(rxr->ag_bitmap, next); 210 rxr->ag_prod = next; 211 next = RING_NEXT(rxr->ag_ring_struct, next); 212 } 213 214 return 0; 215 } 216 217 static int bnxt_rx_pages(struct bnxt_rx_queue *rxq, 218 struct rte_mbuf *mbuf, uint32_t *tmp_raw_cons, 219 uint8_t agg_buf, struct bnxt_tpa_info *tpa_info) 220 { 221 struct bnxt_cp_ring_info *cpr = rxq->cp_ring; 222 struct bnxt_rx_ring_info *rxr = rxq->rx_ring; 223 int i; 224 uint16_t cp_cons, ag_cons; 225 struct rx_pkt_cmpl *rxcmp; 226 struct rte_mbuf *last = mbuf; 227 bool is_thor_tpa = tpa_info && BNXT_CHIP_THOR(rxq->bp); 228 229 for (i = 0; i < agg_buf; i++) { 230 struct rte_mbuf **ag_buf; 231 struct rte_mbuf *ag_mbuf; 232 233 if (is_thor_tpa) { 234 rxcmp = (void *)&tpa_info->agg_arr[i]; 235 } else { 236 *tmp_raw_cons = NEXT_RAW_CMP(*tmp_raw_cons); 237 cp_cons = RING_CMP(cpr->cp_ring_struct, *tmp_raw_cons); 238 rxcmp = (struct rx_pkt_cmpl *) 239 &cpr->cp_desc_ring[cp_cons]; 240 } 241 242 #ifdef BNXT_DEBUG 243 bnxt_dump_cmpl(cp_cons, rxcmp); 244 #endif 245 246 ag_cons = rxcmp->opaque; 247 RTE_ASSERT(ag_cons <= rxr->ag_ring_struct->ring_mask); 248 ag_buf = &rxr->ag_buf_ring[ag_cons]; 249 ag_mbuf = *ag_buf; 250 RTE_ASSERT(ag_mbuf != NULL); 251 252 ag_mbuf->data_len = rte_le_to_cpu_16(rxcmp->len); 253 254 mbuf->nb_segs++; 255 mbuf->pkt_len += ag_mbuf->data_len; 256 257 last->next = ag_mbuf; 258 last = ag_mbuf; 259 260 *ag_buf = NULL; 261 262 /* 263 * As aggregation buffer consumed out of order in TPA module, 264 * use bitmap to track freed slots to be allocated and notified 265 * to NIC 266 */ 267 rte_bitmap_set(rxr->ag_bitmap, ag_cons); 268 } 269 bnxt_prod_ag_mbuf(rxq); 270 return 0; 271 } 272 273 static inline struct rte_mbuf *bnxt_tpa_end( 274 struct bnxt_rx_queue *rxq, 275 uint32_t *raw_cp_cons, 276 struct rx_tpa_end_cmpl *tpa_end, 277 struct rx_tpa_end_cmpl_hi *tpa_end1) 278 { 279 struct bnxt_cp_ring_info *cpr = rxq->cp_ring; 280 struct bnxt_rx_ring_info *rxr = rxq->rx_ring; 281 uint16_t agg_id; 282 struct rte_mbuf *mbuf; 283 uint8_t agg_bufs; 284 uint8_t payload_offset; 285 struct bnxt_tpa_info *tpa_info; 286 287 if (BNXT_CHIP_THOR(rxq->bp)) { 288 struct rx_tpa_v2_end_cmpl *th_tpa_end; 289 struct rx_tpa_v2_end_cmpl_hi *th_tpa_end1; 290 291 th_tpa_end = (void *)tpa_end; 292 th_tpa_end1 = (void *)tpa_end1; 293 agg_id = BNXT_TPA_END_AGG_ID_TH(th_tpa_end); 294 agg_bufs = BNXT_TPA_END_AGG_BUFS_TH(th_tpa_end1); 295 payload_offset = th_tpa_end1->payload_offset; 296 } else { 297 agg_id = BNXT_TPA_END_AGG_ID(tpa_end); 298 agg_bufs = BNXT_TPA_END_AGG_BUFS(tpa_end); 299 if (!bnxt_agg_bufs_valid(cpr, agg_bufs, *raw_cp_cons)) 300 return NULL; 301 payload_offset = tpa_end->payload_offset; 302 } 303 304 tpa_info = &rxr->tpa_info[agg_id]; 305 mbuf = tpa_info->mbuf; 306 RTE_ASSERT(mbuf != NULL); 307 308 rte_prefetch0(mbuf); 309 if (agg_bufs) { 310 bnxt_rx_pages(rxq, mbuf, raw_cp_cons, agg_bufs, tpa_info); 311 } 312 mbuf->l4_len = payload_offset; 313 314 struct rte_mbuf *new_data = __bnxt_alloc_rx_data(rxq->mb_pool); 315 RTE_ASSERT(new_data != NULL); 316 if (!new_data) { 317 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail); 318 return NULL; 319 } 320 tpa_info->mbuf = new_data; 321 322 return mbuf; 323 } 324 325 uint32_t bnxt_ptype_table[BNXT_PTYPE_TBL_DIM] __rte_cache_aligned; 326 327 static void __rte_cold 328 bnxt_init_ptype_table(void) 329 { 330 uint32_t *pt = bnxt_ptype_table; 331 static bool initialized; 332 int ip6, tun, type; 333 uint32_t l3; 334 int i; 335 336 if (initialized) 337 return; 338 339 for (i = 0; i < BNXT_PTYPE_TBL_DIM; i++) { 340 if (i & (RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN >> 2)) 341 pt[i] = RTE_PTYPE_L2_ETHER_VLAN; 342 else 343 pt[i] = RTE_PTYPE_L2_ETHER; 344 345 ip6 = i & (RX_PKT_CMPL_FLAGS2_IP_TYPE >> 7); 346 tun = i & (RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC >> 2); 347 type = (i & 0x38) << 9; 348 349 if (!tun && !ip6) 350 l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; 351 else if (!tun && ip6) 352 l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN; 353 else if (tun && !ip6) 354 l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN; 355 else 356 l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN; 357 358 switch (type) { 359 case RX_PKT_CMPL_FLAGS_ITYPE_ICMP: 360 if (tun) 361 pt[i] |= l3 | RTE_PTYPE_INNER_L4_ICMP; 362 else 363 pt[i] |= l3 | RTE_PTYPE_L4_ICMP; 364 break; 365 case RX_PKT_CMPL_FLAGS_ITYPE_TCP: 366 if (tun) 367 pt[i] |= l3 | RTE_PTYPE_INNER_L4_TCP; 368 else 369 pt[i] |= l3 | RTE_PTYPE_L4_TCP; 370 break; 371 case RX_PKT_CMPL_FLAGS_ITYPE_UDP: 372 if (tun) 373 pt[i] |= l3 | RTE_PTYPE_INNER_L4_UDP; 374 else 375 pt[i] |= l3 | RTE_PTYPE_L4_UDP; 376 break; 377 case RX_PKT_CMPL_FLAGS_ITYPE_IP: 378 pt[i] |= l3; 379 break; 380 } 381 } 382 initialized = true; 383 } 384 385 static uint32_t 386 bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1) 387 { 388 uint32_t flags_type, flags2; 389 uint8_t index; 390 391 flags_type = rte_le_to_cpu_16(rxcmp->flags_type); 392 flags2 = rte_le_to_cpu_32(rxcmp1->flags2); 393 394 /* 395 * Index format: 396 * bit 0: RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC 397 * bit 1: RX_CMPL_FLAGS2_IP_TYPE 398 * bit 2: RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN 399 * bits 3-6: RX_PKT_CMPL_FLAGS_ITYPE 400 */ 401 index = ((flags_type & RX_PKT_CMPL_FLAGS_ITYPE_MASK) >> 9) | 402 ((flags2 & (RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN | 403 RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)) >> 2) | 404 ((flags2 & RX_PKT_CMPL_FLAGS2_IP_TYPE) >> 7); 405 406 return bnxt_ptype_table[index]; 407 } 408 409 uint32_t 410 bnxt_ol_flags_table[BNXT_OL_FLAGS_TBL_DIM] __rte_cache_aligned; 411 412 uint32_t 413 bnxt_ol_flags_err_table[BNXT_OL_FLAGS_ERR_TBL_DIM] __rte_cache_aligned; 414 415 static void __rte_cold 416 bnxt_init_ol_flags_tables(void) 417 { 418 static bool initialized; 419 uint32_t *pt; 420 int i; 421 422 if (initialized) 423 return; 424 425 /* Initialize ol_flags table. */ 426 pt = bnxt_ol_flags_table; 427 for (i = 0; i < BNXT_OL_FLAGS_TBL_DIM; i++) { 428 pt[i] = 0; 429 if (i & RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) 430 pt[i] |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 431 432 if (i & RX_PKT_CMPL_FLAGS2_IP_CS_CALC) 433 pt[i] |= PKT_RX_IP_CKSUM_GOOD; 434 435 if (i & RX_PKT_CMPL_FLAGS2_L4_CS_CALC) 436 pt[i] |= PKT_RX_L4_CKSUM_GOOD; 437 438 if (i & RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC) 439 pt[i] |= PKT_RX_OUTER_L4_CKSUM_GOOD; 440 } 441 442 /* Initialize checksum error table. */ 443 pt = bnxt_ol_flags_err_table; 444 for (i = 0; i < BNXT_OL_FLAGS_ERR_TBL_DIM; i++) { 445 pt[i] = 0; 446 if (i & (RX_PKT_CMPL_ERRORS_IP_CS_ERROR >> 4)) 447 pt[i] |= PKT_RX_IP_CKSUM_BAD; 448 449 if (i & (RX_PKT_CMPL_ERRORS_L4_CS_ERROR >> 4)) 450 pt[i] |= PKT_RX_L4_CKSUM_BAD; 451 452 if (i & (RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR >> 4)) 453 pt[i] |= PKT_RX_EIP_CKSUM_BAD; 454 455 if (i & (RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR >> 4)) 456 pt[i] |= PKT_RX_OUTER_L4_CKSUM_BAD; 457 } 458 459 initialized = true; 460 } 461 462 static void 463 bnxt_set_ol_flags(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1, 464 struct rte_mbuf *mbuf) 465 { 466 uint16_t flags_type, errors, flags; 467 uint64_t ol_flags; 468 469 flags_type = rte_le_to_cpu_16(rxcmp->flags_type); 470 471 flags = rte_le_to_cpu_32(rxcmp1->flags2) & 472 (RX_PKT_CMPL_FLAGS2_IP_CS_CALC | 473 RX_PKT_CMPL_FLAGS2_L4_CS_CALC | 474 RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC | 475 RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC | 476 RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN); 477 478 errors = rte_le_to_cpu_16(rxcmp1->errors_v2) & 479 (RX_PKT_CMPL_ERRORS_IP_CS_ERROR | 480 RX_PKT_CMPL_ERRORS_L4_CS_ERROR | 481 RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR | 482 RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR); 483 errors = (errors >> 4) & flags; 484 485 ol_flags = bnxt_ol_flags_table[flags & ~errors]; 486 487 if (errors) 488 ol_flags |= bnxt_ol_flags_err_table[errors]; 489 490 if (flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID) { 491 mbuf->hash.rss = rte_le_to_cpu_32(rxcmp->rss_hash); 492 ol_flags |= PKT_RX_RSS_HASH; 493 } 494 495 mbuf->ol_flags = ol_flags; 496 } 497 498 #ifdef RTE_LIBRTE_IEEE1588 499 static void 500 bnxt_get_rx_ts_thor(struct bnxt *bp, uint32_t rx_ts_cmpl) 501 { 502 uint64_t systime_cycles = 0; 503 504 if (!BNXT_CHIP_THOR(bp)) 505 return; 506 507 /* On Thor, Rx timestamps are provided directly in the 508 * Rx completion records to the driver. Only 32 bits of 509 * the timestamp is present in the completion. Driver needs 510 * to read the current 48 bit free running timer using the 511 * HWRM_PORT_TS_QUERY command and combine the upper 16 bits 512 * from the HWRM response with the lower 32 bits in the 513 * Rx completion to produce the 48 bit timestamp for the Rx packet 514 */ 515 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 516 &systime_cycles); 517 bp->ptp_cfg->rx_timestamp = (systime_cycles & 0xFFFF00000000); 518 bp->ptp_cfg->rx_timestamp |= rx_ts_cmpl; 519 } 520 #endif 521 522 static uint32_t 523 bnxt_ulp_set_mark_in_mbuf(struct bnxt *bp, struct rx_pkt_cmpl_hi *rxcmp1, 524 struct rte_mbuf *mbuf, uint32_t *vfr_flag) 525 { 526 uint32_t cfa_code; 527 uint32_t meta_fmt; 528 uint32_t meta; 529 bool gfid = false; 530 uint32_t mark_id; 531 uint32_t flags2; 532 uint32_t gfid_support = 0; 533 int rc; 534 535 if (BNXT_GFID_ENABLED(bp)) 536 gfid_support = 1; 537 538 cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code); 539 flags2 = rte_le_to_cpu_32(rxcmp1->flags2); 540 meta = rte_le_to_cpu_32(rxcmp1->metadata); 541 542 /* 543 * The flags field holds extra bits of info from [6:4] 544 * which indicate if the flow is in TCAM or EM or EEM 545 */ 546 meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >> 547 BNXT_CFA_META_FMT_SHFT; 548 549 switch (meta_fmt) { 550 case 0: 551 if (gfid_support) { 552 /* Not an LFID or GFID, a flush cmd. */ 553 goto skip_mark; 554 } else { 555 /* LFID mode, no vlan scenario */ 556 gfid = false; 557 } 558 break; 559 case 4: 560 case 5: 561 /* 562 * EM/TCAM case 563 * Assume that EM doesn't support Mark due to GFID 564 * collisions with EEM. Simply return without setting the mark 565 * in the mbuf. 566 */ 567 if (BNXT_CFA_META_EM_TEST(meta)) { 568 /*This is EM hit {EM(1), GFID[27:16], 19'd0 or vtag } */ 569 gfid = true; 570 meta >>= BNXT_RX_META_CFA_CODE_SHIFT; 571 cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT; 572 } else { 573 /* 574 * It is a TCAM entry, so it is an LFID. 575 * The TCAM IDX and Mode can also be determined 576 * by decoding the meta_data. We are not 577 * using these for now. 578 */ 579 } 580 break; 581 case 6: 582 case 7: 583 /* EEM Case, only using gfid in EEM for now. */ 584 gfid = true; 585 586 /* 587 * For EEM flows, The first part of cfa_code is 16 bits. 588 * The second part is embedded in the 589 * metadata field from bit 19 onwards. The driver needs to 590 * ignore the first 19 bits of metadata and use the next 12 591 * bits as higher 12 bits of cfa_code. 592 */ 593 meta >>= BNXT_RX_META_CFA_CODE_SHIFT; 594 cfa_code |= meta << BNXT_CFA_CODE_META_SHIFT; 595 break; 596 default: 597 /* For other values, the cfa_code is assumed to be an LFID. */ 598 break; 599 } 600 601 rc = ulp_mark_db_mark_get(bp->ulp_ctx, gfid, 602 cfa_code, vfr_flag, &mark_id); 603 if (!rc) { 604 /* VF to VFR Rx path. So, skip mark_id injection in mbuf */ 605 if (vfr_flag && *vfr_flag) 606 return mark_id; 607 /* Got the mark, write it to the mbuf and return */ 608 mbuf->hash.fdir.hi = mark_id; 609 mbuf->udata64 = (cfa_code & 0xffffffffull) << 32; 610 mbuf->hash.fdir.id = rxcmp1->cfa_code; 611 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID; 612 return mark_id; 613 } 614 615 skip_mark: 616 mbuf->hash.fdir.hi = 0; 617 mbuf->hash.fdir.id = 0; 618 619 return 0; 620 } 621 622 void bnxt_set_mark_in_mbuf(struct bnxt *bp, 623 struct rx_pkt_cmpl_hi *rxcmp1, 624 struct rte_mbuf *mbuf) 625 { 626 uint32_t cfa_code = 0; 627 uint8_t meta_fmt = 0; 628 uint16_t flags2 = 0; 629 uint32_t meta = 0; 630 631 cfa_code = rte_le_to_cpu_16(rxcmp1->cfa_code); 632 if (!cfa_code) 633 return; 634 635 if (cfa_code && !bp->mark_table[cfa_code].valid) 636 return; 637 638 flags2 = rte_le_to_cpu_16(rxcmp1->flags2); 639 meta = rte_le_to_cpu_32(rxcmp1->metadata); 640 if (meta) { 641 meta >>= BNXT_RX_META_CFA_CODE_SHIFT; 642 643 /* The flags field holds extra bits of info from [6:4] 644 * which indicate if the flow is in TCAM or EM or EEM 645 */ 646 meta_fmt = (flags2 & BNXT_CFA_META_FMT_MASK) >> 647 BNXT_CFA_META_FMT_SHFT; 648 649 /* meta_fmt == 4 => 'b100 => 'b10x => EM. 650 * meta_fmt == 5 => 'b101 => 'b10x => EM + VLAN 651 * meta_fmt == 6 => 'b110 => 'b11x => EEM 652 * meta_fmt == 7 => 'b111 => 'b11x => EEM + VLAN. 653 */ 654 meta_fmt >>= BNXT_CFA_META_FMT_EM_EEM_SHFT; 655 } 656 657 mbuf->hash.fdir.hi = bp->mark_table[cfa_code].mark_id; 658 mbuf->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID; 659 } 660 661 static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt, 662 struct bnxt_rx_queue *rxq, uint32_t *raw_cons) 663 { 664 struct bnxt_cp_ring_info *cpr = rxq->cp_ring; 665 struct bnxt_rx_ring_info *rxr = rxq->rx_ring; 666 struct rx_pkt_cmpl *rxcmp; 667 struct rx_pkt_cmpl_hi *rxcmp1; 668 uint32_t tmp_raw_cons = *raw_cons; 669 uint16_t cons, prod, cp_cons = 670 RING_CMP(cpr->cp_ring_struct, tmp_raw_cons); 671 struct rte_mbuf *mbuf; 672 int rc = 0; 673 uint8_t agg_buf = 0; 674 uint16_t cmp_type; 675 uint32_t vfr_flag = 0, mark_id = 0; 676 struct bnxt *bp = rxq->bp; 677 678 rxcmp = (struct rx_pkt_cmpl *) 679 &cpr->cp_desc_ring[cp_cons]; 680 681 cmp_type = CMP_TYPE(rxcmp); 682 683 if (cmp_type == RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG) { 684 struct rx_tpa_v2_abuf_cmpl *rx_agg = (void *)rxcmp; 685 uint16_t agg_id = rte_cpu_to_le_16(rx_agg->agg_id); 686 struct bnxt_tpa_info *tpa_info; 687 688 tpa_info = &rxr->tpa_info[agg_id]; 689 RTE_ASSERT(tpa_info->agg_count < 16); 690 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg; 691 rc = -EINVAL; /* Continue w/o new mbuf */ 692 goto next_rx; 693 } 694 695 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); 696 cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons); 697 rxcmp1 = (struct rx_pkt_cmpl_hi *)&cpr->cp_desc_ring[cp_cons]; 698 699 if (!CMP_VALID(rxcmp1, tmp_raw_cons, cpr->cp_ring_struct)) 700 return -EBUSY; 701 702 cpr->valid = FLIP_VALID(cp_cons, 703 cpr->cp_ring_struct->ring_mask, 704 cpr->valid); 705 706 if (cmp_type == RX_TPA_START_CMPL_TYPE_RX_TPA_START) { 707 bnxt_tpa_start(rxq, (struct rx_tpa_start_cmpl *)rxcmp, 708 (struct rx_tpa_start_cmpl_hi *)rxcmp1); 709 rc = -EINVAL; /* Continue w/o new mbuf */ 710 goto next_rx; 711 } else if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) { 712 mbuf = bnxt_tpa_end(rxq, &tmp_raw_cons, 713 (struct rx_tpa_end_cmpl *)rxcmp, 714 (struct rx_tpa_end_cmpl_hi *)rxcmp1); 715 if (unlikely(!mbuf)) 716 return -EBUSY; 717 *rx_pkt = mbuf; 718 goto next_rx; 719 } else if (cmp_type != 0x11) { 720 rc = -EINVAL; 721 goto next_rx; 722 } 723 724 agg_buf = (rxcmp->agg_bufs_v1 & RX_PKT_CMPL_AGG_BUFS_MASK) 725 >> RX_PKT_CMPL_AGG_BUFS_SFT; 726 if (agg_buf && !bnxt_agg_bufs_valid(cpr, agg_buf, tmp_raw_cons)) 727 return -EBUSY; 728 729 prod = rxr->rx_prod; 730 731 cons = rxcmp->opaque; 732 mbuf = bnxt_consume_rx_buf(rxr, cons); 733 if (mbuf == NULL) 734 return -EBUSY; 735 736 rte_prefetch0(mbuf); 737 738 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 739 mbuf->nb_segs = 1; 740 mbuf->next = NULL; 741 mbuf->pkt_len = rxcmp->len; 742 mbuf->data_len = mbuf->pkt_len; 743 mbuf->port = rxq->port_id; 744 745 bnxt_set_ol_flags(rxcmp, rxcmp1, mbuf); 746 747 #ifdef RTE_LIBRTE_IEEE1588 748 if (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) & 749 RX_PKT_CMPL_FLAGS_MASK) == 750 RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP)) { 751 mbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST; 752 bnxt_get_rx_ts_thor(rxq->bp, rxcmp1->reorder); 753 } 754 #endif 755 756 if (BNXT_TRUFLOW_EN(bp)) 757 mark_id = bnxt_ulp_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf, 758 &vfr_flag); 759 else 760 bnxt_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf); 761 762 if (agg_buf) 763 bnxt_rx_pages(rxq, mbuf, &tmp_raw_cons, agg_buf, NULL); 764 765 mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1); 766 767 #ifdef BNXT_DEBUG 768 if (rxcmp1->errors_v2 & RX_CMP_L2_ERRORS) { 769 /* Re-install the mbuf back to the rx ring */ 770 bnxt_reuse_rx_mbuf(rxr, cons, mbuf); 771 772 rc = -EIO; 773 goto next_rx; 774 } 775 #endif 776 /* 777 * TODO: Redesign this.... 778 * If the allocation fails, the packet does not get received. 779 * Simply returning this will result in slowly falling behind 780 * on the producer ring buffers. 781 * Instead, "filling up" the producer just before ringing the 782 * doorbell could be a better solution since it will let the 783 * producer ring starve until memory is available again pushing 784 * the drops into hardware and getting them out of the driver 785 * allowing recovery to a full producer ring. 786 * 787 * This could also help with cache usage by preventing per-packet 788 * calls in favour of a tight loop with the same function being called 789 * in it. 790 */ 791 prod = RING_NEXT(rxr->rx_ring_struct, prod); 792 if (bnxt_alloc_rx_data(rxq, rxr, prod)) { 793 PMD_DRV_LOG(ERR, "mbuf alloc failed with prod=0x%x\n", prod); 794 rc = -ENOMEM; 795 goto rx; 796 } 797 rxr->rx_prod = prod; 798 799 if (BNXT_TRUFLOW_EN(bp) && (BNXT_VF_IS_TRUSTED(bp) || BNXT_PF(bp)) && 800 vfr_flag) { 801 bnxt_vfr_recv(mark_id, rxq->queue_id, mbuf); 802 /* Now return an error so that nb_rx_pkts is not 803 * incremented. 804 * This packet was meant to be given to the representor. 805 * So no need to account the packet and give it to 806 * parent Rx burst function. 807 */ 808 rc = -ENODEV; 809 goto next_rx; 810 } 811 /* 812 * All MBUFs are allocated with the same size under DPDK, 813 * no optimization for rx_copy_thresh 814 */ 815 rx: 816 *rx_pkt = mbuf; 817 818 next_rx: 819 820 *raw_cons = tmp_raw_cons; 821 822 return rc; 823 } 824 825 uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 826 uint16_t nb_pkts) 827 { 828 struct bnxt_rx_queue *rxq = rx_queue; 829 struct bnxt_cp_ring_info *cpr = rxq->cp_ring; 830 struct bnxt_rx_ring_info *rxr = rxq->rx_ring; 831 uint32_t raw_cons = cpr->cp_raw_cons; 832 uint32_t cons; 833 int nb_rx_pkts = 0; 834 int nb_rep_rx_pkts = 0; 835 struct rx_pkt_cmpl *rxcmp; 836 uint16_t prod = rxr->rx_prod; 837 uint16_t ag_prod = rxr->ag_prod; 838 int rc = 0; 839 bool evt = false; 840 841 if (unlikely(is_bnxt_in_error(rxq->bp))) 842 return 0; 843 844 /* If Rx Q was stopped return */ 845 if (unlikely(!rxq->rx_started || 846 !rte_spinlock_trylock(&rxq->lock))) 847 return 0; 848 849 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 850 /* 851 * Replenish buffers if needed when a transition has been made from 852 * vector- to non-vector- receive processing. 853 */ 854 while (unlikely(rxq->rxrearm_nb)) { 855 if (!bnxt_alloc_rx_data(rxq, rxr, rxq->rxrearm_start)) { 856 rxr->rx_prod = rxq->rxrearm_start; 857 bnxt_db_write(&rxr->rx_db, rxr->rx_prod); 858 rxq->rxrearm_start++; 859 rxq->rxrearm_nb--; 860 } else { 861 /* Retry allocation on next call. */ 862 break; 863 } 864 } 865 #endif 866 867 /* Handle RX burst request */ 868 while (1) { 869 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 870 rte_prefetch0(&cpr->cp_desc_ring[cons]); 871 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 872 873 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 874 break; 875 cpr->valid = FLIP_VALID(cons, 876 cpr->cp_ring_struct->ring_mask, 877 cpr->valid); 878 879 /* TODO: Avoid magic numbers... */ 880 if ((CMP_TYPE(rxcmp) & 0x30) == 0x10) { 881 rc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons); 882 if (likely(!rc) || rc == -ENOMEM) 883 nb_rx_pkts++; 884 if (rc == -EBUSY) /* partial completion */ 885 break; 886 if (rc == -ENODEV) /* completion for representor */ 887 nb_rep_rx_pkts++; 888 } else if (!BNXT_NUM_ASYNC_CPR(rxq->bp)) { 889 evt = 890 bnxt_event_hwrm_resp_handler(rxq->bp, 891 (struct cmpl_base *)rxcmp); 892 /* If the async event is Fatal error, return */ 893 if (unlikely(is_bnxt_in_error(rxq->bp))) 894 goto done; 895 } 896 897 raw_cons = NEXT_RAW_CMP(raw_cons); 898 if (nb_rx_pkts == nb_pkts || evt) 899 break; 900 /* Post some Rx buf early in case of larger burst processing */ 901 if (nb_rx_pkts == BNXT_RX_POST_THRESH) 902 bnxt_db_write(&rxr->rx_db, rxr->rx_prod); 903 } 904 905 cpr->cp_raw_cons = raw_cons; 906 if (!nb_rx_pkts && !nb_rep_rx_pkts && !evt) { 907 /* 908 * For PMD, there is no need to keep on pushing to REARM 909 * the doorbell if there are no new completions 910 */ 911 goto done; 912 } 913 914 if (prod != rxr->rx_prod) 915 bnxt_db_write(&rxr->rx_db, rxr->rx_prod); 916 917 /* Ring the AGG ring DB */ 918 if (ag_prod != rxr->ag_prod) 919 bnxt_db_write(&rxr->ag_db, rxr->ag_prod); 920 921 bnxt_db_cq(cpr); 922 923 /* Attempt to alloc Rx buf in case of a previous allocation failure. */ 924 if (rc == -ENOMEM) { 925 int i = RING_NEXT(rxr->rx_ring_struct, prod); 926 int cnt = nb_rx_pkts; 927 928 for (; cnt; 929 i = RING_NEXT(rxr->rx_ring_struct, i), cnt--) { 930 struct rte_mbuf **rx_buf = &rxr->rx_buf_ring[i]; 931 932 /* Buffer already allocated for this index. */ 933 if (*rx_buf != NULL && *rx_buf != &rxq->fake_mbuf) 934 continue; 935 936 /* This slot is empty. Alloc buffer for Rx */ 937 if (!bnxt_alloc_rx_data(rxq, rxr, i)) { 938 rxr->rx_prod = i; 939 bnxt_db_write(&rxr->rx_db, rxr->rx_prod); 940 } else { 941 PMD_DRV_LOG(ERR, "Alloc mbuf failed\n"); 942 break; 943 } 944 } 945 } 946 947 done: 948 rte_spinlock_unlock(&rxq->lock); 949 950 return nb_rx_pkts; 951 } 952 953 /* 954 * Dummy DPDK callback for RX. 955 * 956 * This function is used to temporarily replace the real callback during 957 * unsafe control operations on the queue, or in case of error. 958 */ 959 uint16_t 960 bnxt_dummy_recv_pkts(void *rx_queue __rte_unused, 961 struct rte_mbuf **rx_pkts __rte_unused, 962 uint16_t nb_pkts __rte_unused) 963 { 964 return 0; 965 } 966 967 void bnxt_free_rx_rings(struct bnxt *bp) 968 { 969 int i; 970 struct bnxt_rx_queue *rxq; 971 972 if (!bp->rx_queues) 973 return; 974 975 for (i = 0; i < (int)bp->rx_nr_rings; i++) { 976 rxq = bp->rx_queues[i]; 977 if (!rxq) 978 continue; 979 980 bnxt_free_ring(rxq->rx_ring->rx_ring_struct); 981 rte_free(rxq->rx_ring->rx_ring_struct); 982 983 /* Free the Aggregator ring */ 984 bnxt_free_ring(rxq->rx_ring->ag_ring_struct); 985 rte_free(rxq->rx_ring->ag_ring_struct); 986 rxq->rx_ring->ag_ring_struct = NULL; 987 988 rte_free(rxq->rx_ring); 989 990 bnxt_free_ring(rxq->cp_ring->cp_ring_struct); 991 rte_free(rxq->cp_ring->cp_ring_struct); 992 rte_free(rxq->cp_ring); 993 994 rte_free(rxq); 995 bp->rx_queues[i] = NULL; 996 } 997 } 998 999 int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id) 1000 { 1001 struct rte_eth_dev *eth_dev = rxq->bp->eth_dev; 1002 struct rte_eth_rxmode *rxmode; 1003 struct bnxt_cp_ring_info *cpr; 1004 struct bnxt_rx_ring_info *rxr; 1005 struct bnxt_ring *ring; 1006 bool use_agg_ring; 1007 1008 rxq->rx_buf_size = BNXT_MAX_PKT_LEN + sizeof(struct rte_mbuf); 1009 1010 rxr = rte_zmalloc_socket("bnxt_rx_ring", 1011 sizeof(struct bnxt_rx_ring_info), 1012 RTE_CACHE_LINE_SIZE, socket_id); 1013 if (rxr == NULL) 1014 return -ENOMEM; 1015 rxq->rx_ring = rxr; 1016 1017 ring = rte_zmalloc_socket("bnxt_rx_ring_struct", 1018 sizeof(struct bnxt_ring), 1019 RTE_CACHE_LINE_SIZE, socket_id); 1020 if (ring == NULL) 1021 return -ENOMEM; 1022 rxr->rx_ring_struct = ring; 1023 ring->ring_size = rte_align32pow2(rxq->nb_rx_desc); 1024 ring->ring_mask = ring->ring_size - 1; 1025 ring->bd = (void *)rxr->rx_desc_ring; 1026 ring->bd_dma = rxr->rx_desc_mapping; 1027 1028 /* Allocate extra rx ring entries for vector rx. */ 1029 ring->vmem_size = sizeof(struct rte_mbuf *) * 1030 (ring->ring_size + RTE_BNXT_DESCS_PER_LOOP); 1031 1032 ring->vmem = (void **)&rxr->rx_buf_ring; 1033 ring->fw_ring_id = INVALID_HW_RING_ID; 1034 1035 cpr = rte_zmalloc_socket("bnxt_rx_ring", 1036 sizeof(struct bnxt_cp_ring_info), 1037 RTE_CACHE_LINE_SIZE, socket_id); 1038 if (cpr == NULL) 1039 return -ENOMEM; 1040 rxq->cp_ring = cpr; 1041 1042 ring = rte_zmalloc_socket("bnxt_rx_ring_struct", 1043 sizeof(struct bnxt_ring), 1044 RTE_CACHE_LINE_SIZE, socket_id); 1045 if (ring == NULL) 1046 return -ENOMEM; 1047 cpr->cp_ring_struct = ring; 1048 1049 rxmode = ð_dev->data->dev_conf.rxmode; 1050 use_agg_ring = (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) || 1051 (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) || 1052 (rxmode->max_rx_pkt_len > 1053 (uint32_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1054 RTE_PKTMBUF_HEADROOM)); 1055 1056 /* Allocate two completion slots per entry in desc ring. */ 1057 ring->ring_size = rxr->rx_ring_struct->ring_size * 2; 1058 1059 /* Allocate additional slots if aggregation ring is in use. */ 1060 if (use_agg_ring) 1061 ring->ring_size *= AGG_RING_SIZE_FACTOR; 1062 1063 ring->ring_size = rte_align32pow2(ring->ring_size); 1064 ring->ring_mask = ring->ring_size - 1; 1065 ring->bd = (void *)cpr->cp_desc_ring; 1066 ring->bd_dma = cpr->cp_desc_mapping; 1067 ring->vmem_size = 0; 1068 ring->vmem = NULL; 1069 ring->fw_ring_id = INVALID_HW_RING_ID; 1070 1071 /* Allocate Aggregator rings */ 1072 ring = rte_zmalloc_socket("bnxt_rx_ring_struct", 1073 sizeof(struct bnxt_ring), 1074 RTE_CACHE_LINE_SIZE, socket_id); 1075 if (ring == NULL) 1076 return -ENOMEM; 1077 rxr->ag_ring_struct = ring; 1078 ring->ring_size = rte_align32pow2(rxq->nb_rx_desc * 1079 AGG_RING_SIZE_FACTOR); 1080 ring->ring_mask = ring->ring_size - 1; 1081 ring->bd = (void *)rxr->ag_desc_ring; 1082 ring->bd_dma = rxr->ag_desc_mapping; 1083 ring->vmem_size = ring->ring_size * sizeof(struct rte_mbuf *); 1084 ring->vmem = (void **)&rxr->ag_buf_ring; 1085 ring->fw_ring_id = INVALID_HW_RING_ID; 1086 1087 return 0; 1088 } 1089 1090 static void bnxt_init_rxbds(struct bnxt_ring *ring, uint32_t type, 1091 uint16_t len) 1092 { 1093 uint32_t j; 1094 struct rx_prod_pkt_bd *rx_bd_ring = (struct rx_prod_pkt_bd *)ring->bd; 1095 1096 if (!rx_bd_ring) 1097 return; 1098 for (j = 0; j < ring->ring_size; j++) { 1099 rx_bd_ring[j].flags_type = rte_cpu_to_le_16(type); 1100 rx_bd_ring[j].len = rte_cpu_to_le_16(len); 1101 rx_bd_ring[j].opaque = j; 1102 } 1103 } 1104 1105 int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq) 1106 { 1107 struct bnxt_rx_ring_info *rxr; 1108 struct bnxt_ring *ring; 1109 uint32_t prod, type; 1110 unsigned int i; 1111 uint16_t size; 1112 1113 /* Initialize packet type table. */ 1114 bnxt_init_ptype_table(); 1115 1116 /* Initialize offload flags parsing table. */ 1117 bnxt_init_ol_flags_tables(); 1118 1119 size = rte_pktmbuf_data_room_size(rxq->mb_pool) - RTE_PKTMBUF_HEADROOM; 1120 size = RTE_MIN(BNXT_MAX_PKT_LEN, size); 1121 1122 type = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT | RX_PROD_PKT_BD_FLAGS_EOP_PAD; 1123 1124 rxr = rxq->rx_ring; 1125 ring = rxr->rx_ring_struct; 1126 bnxt_init_rxbds(ring, type, size); 1127 1128 prod = rxr->rx_prod; 1129 for (i = 0; i < ring->ring_size; i++) { 1130 if (unlikely(!rxr->rx_buf_ring[i])) { 1131 if (bnxt_alloc_rx_data(rxq, rxr, prod) != 0) { 1132 PMD_DRV_LOG(WARNING, 1133 "init'ed rx ring %d with %d/%d mbufs only\n", 1134 rxq->queue_id, i, ring->ring_size); 1135 break; 1136 } 1137 } 1138 rxr->rx_prod = prod; 1139 prod = RING_NEXT(rxr->rx_ring_struct, prod); 1140 } 1141 1142 /* Initialize dummy mbuf pointers for vector mode rx. */ 1143 for (i = ring->ring_size; 1144 i < ring->ring_size + RTE_BNXT_DESCS_PER_LOOP; i++) { 1145 rxr->rx_buf_ring[i] = &rxq->fake_mbuf; 1146 } 1147 1148 ring = rxr->ag_ring_struct; 1149 type = RX_PROD_AGG_BD_TYPE_RX_PROD_AGG; 1150 bnxt_init_rxbds(ring, type, size); 1151 prod = rxr->ag_prod; 1152 1153 for (i = 0; i < ring->ring_size; i++) { 1154 if (unlikely(!rxr->ag_buf_ring[i])) { 1155 if (bnxt_alloc_ag_data(rxq, rxr, prod) != 0) { 1156 PMD_DRV_LOG(WARNING, 1157 "init'ed AG ring %d with %d/%d mbufs only\n", 1158 rxq->queue_id, i, ring->ring_size); 1159 break; 1160 } 1161 } 1162 rxr->ag_prod = prod; 1163 prod = RING_NEXT(rxr->ag_ring_struct, prod); 1164 } 1165 PMD_DRV_LOG(DEBUG, "AGG Done!\n"); 1166 1167 if (rxr->tpa_info) { 1168 unsigned int max_aggs = BNXT_TPA_MAX_AGGS(rxq->bp); 1169 1170 for (i = 0; i < max_aggs; i++) { 1171 if (unlikely(!rxr->tpa_info[i].mbuf)) { 1172 rxr->tpa_info[i].mbuf = 1173 __bnxt_alloc_rx_data(rxq->mb_pool); 1174 if (!rxr->tpa_info[i].mbuf) { 1175 rte_atomic64_inc(&rxq->rx_mbuf_alloc_fail); 1176 return -ENOMEM; 1177 } 1178 } 1179 } 1180 } 1181 PMD_DRV_LOG(DEBUG, "TPA alloc Done!\n"); 1182 1183 return 0; 1184 } 1185