1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <rte_bitmap.h> 7 #include <rte_memzone.h> 8 #include <rte_malloc.h> 9 #include <unistd.h> 10 11 #include "bnxt.h" 12 #include "bnxt_hwrm.h" 13 #include "bnxt_ring.h" 14 #include "bnxt_rxq.h" 15 #include "bnxt_rxr.h" 16 #include "bnxt_txq.h" 17 #include "bnxt_txr.h" 18 19 #include "hsi_struct_def_dpdk.h" 20 21 /* 22 * Generic ring handling 23 */ 24 25 void bnxt_free_ring(struct bnxt_ring *ring) 26 { 27 if (!ring) 28 return; 29 30 if (ring->vmem_size && *ring->vmem) { 31 memset((char *)*ring->vmem, 0, ring->vmem_size); 32 *ring->vmem = NULL; 33 } 34 ring->mem_zone = NULL; 35 } 36 37 /* 38 * Ring groups 39 */ 40 41 static void bnxt_init_ring_grps(struct bnxt *bp) 42 { 43 unsigned int i; 44 45 for (i = 0; i < bp->max_ring_grps; i++) 46 memset(&bp->grp_info[i], (uint8_t)HWRM_NA_SIGNATURE, 47 sizeof(struct bnxt_ring_grp_info)); 48 } 49 50 int bnxt_alloc_ring_grps(struct bnxt *bp) 51 { 52 if (bp->max_tx_rings == 0) { 53 PMD_DRV_LOG(ERR, "No TX rings available!\n"); 54 return -EBUSY; 55 } 56 57 /* THOR does not support ring groups. 58 * But we will use the array to save RSS context IDs. 59 */ 60 if (BNXT_CHIP_THOR(bp)) { 61 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR; 62 } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) { 63 /* 1 ring is for default completion ring */ 64 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n"); 65 return -ENOSPC; 66 } 67 68 if (BNXT_HAS_RING_GRPS(bp)) { 69 bp->grp_info = rte_zmalloc("bnxt_grp_info", 70 sizeof(*bp->grp_info) * 71 bp->max_ring_grps, 0); 72 if (!bp->grp_info) { 73 PMD_DRV_LOG(ERR, 74 "Failed to alloc grp info tbl.\n"); 75 return -ENOMEM; 76 } 77 bnxt_init_ring_grps(bp); 78 } 79 80 return 0; 81 } 82 83 /* 84 * Allocates a completion ring with vmem and stats optionally also allocating 85 * a TX and/or RX ring. Passing NULL as tx_ring_info and/or rx_ring_info 86 * to not allocate them. 87 * 88 * Order in the allocation is: 89 * stats - Always non-zero length 90 * cp vmem - Always zero-length, supported for the bnxt_ring abstraction 91 * tx vmem - Only non-zero length if tx_ring_info is not NULL 92 * rx vmem - Only non-zero length if rx_ring_info is not NULL 93 * cp bd ring - Always non-zero length 94 * tx bd ring - Only non-zero length if tx_ring_info is not NULL 95 * rx bd ring - Only non-zero length if rx_ring_info is not NULL 96 */ 97 int bnxt_alloc_rings(struct bnxt *bp, uint16_t qidx, 98 struct bnxt_tx_queue *txq, 99 struct bnxt_rx_queue *rxq, 100 struct bnxt_cp_ring_info *cp_ring_info, 101 struct bnxt_cp_ring_info *nq_ring_info, 102 const char *suffix) 103 { 104 struct bnxt_ring *cp_ring = cp_ring_info->cp_ring_struct; 105 struct bnxt_rx_ring_info *rx_ring_info = rxq ? rxq->rx_ring : NULL; 106 struct bnxt_tx_ring_info *tx_ring_info = txq ? txq->tx_ring : NULL; 107 struct bnxt_ring *tx_ring; 108 struct bnxt_ring *rx_ring; 109 struct rte_pci_device *pdev = bp->pdev; 110 uint64_t rx_offloads = bp->eth_dev->data->dev_conf.rxmode.offloads; 111 const struct rte_memzone *mz = NULL; 112 char mz_name[RTE_MEMZONE_NAMESIZE]; 113 rte_iova_t mz_phys_addr; 114 115 int stats_len = (tx_ring_info || rx_ring_info) ? 116 RTE_CACHE_LINE_ROUNDUP(sizeof(struct hwrm_stat_ctx_query_output) - 117 sizeof (struct hwrm_resp_hdr)) : 0; 118 stats_len = RTE_ALIGN(stats_len, 128); 119 120 int cp_vmem_start = stats_len; 121 int cp_vmem_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size); 122 cp_vmem_len = RTE_ALIGN(cp_vmem_len, 128); 123 124 int nq_vmem_len = nq_ring_info ? 125 RTE_CACHE_LINE_ROUNDUP(cp_ring->vmem_size) : 0; 126 nq_vmem_len = RTE_ALIGN(nq_vmem_len, 128); 127 128 int nq_vmem_start = cp_vmem_start + cp_vmem_len; 129 130 int tx_vmem_start = nq_vmem_start + nq_vmem_len; 131 int tx_vmem_len = 132 tx_ring_info ? RTE_CACHE_LINE_ROUNDUP(tx_ring_info-> 133 tx_ring_struct->vmem_size) : 0; 134 tx_vmem_len = RTE_ALIGN(tx_vmem_len, 128); 135 136 int rx_vmem_start = tx_vmem_start + tx_vmem_len; 137 int rx_vmem_len = rx_ring_info ? 138 RTE_CACHE_LINE_ROUNDUP(rx_ring_info-> 139 rx_ring_struct->vmem_size) : 0; 140 rx_vmem_len = RTE_ALIGN(rx_vmem_len, 128); 141 int ag_vmem_start = 0; 142 int ag_vmem_len = 0; 143 int cp_ring_start = 0; 144 int nq_ring_start = 0; 145 146 ag_vmem_start = rx_vmem_start + rx_vmem_len; 147 ag_vmem_len = rx_ring_info ? RTE_CACHE_LINE_ROUNDUP( 148 rx_ring_info->ag_ring_struct->vmem_size) : 0; 149 cp_ring_start = ag_vmem_start + ag_vmem_len; 150 cp_ring_start = RTE_ALIGN(cp_ring_start, 4096); 151 152 int cp_ring_len = RTE_CACHE_LINE_ROUNDUP(cp_ring->ring_size * 153 sizeof(struct cmpl_base)); 154 cp_ring_len = RTE_ALIGN(cp_ring_len, 128); 155 nq_ring_start = cp_ring_start + cp_ring_len; 156 nq_ring_start = RTE_ALIGN(nq_ring_start, 4096); 157 158 int nq_ring_len = nq_ring_info ? cp_ring_len : 0; 159 160 int tx_ring_start = nq_ring_start + nq_ring_len; 161 tx_ring_start = RTE_ALIGN(tx_ring_start, 4096); 162 int tx_ring_len = tx_ring_info ? 163 RTE_CACHE_LINE_ROUNDUP(tx_ring_info->tx_ring_struct->ring_size * 164 sizeof(struct tx_bd_long)) : 0; 165 tx_ring_len = RTE_ALIGN(tx_ring_len, 4096); 166 167 int rx_ring_start = tx_ring_start + tx_ring_len; 168 rx_ring_start = RTE_ALIGN(rx_ring_start, 4096); 169 int rx_ring_len = rx_ring_info ? 170 RTE_CACHE_LINE_ROUNDUP(rx_ring_info->rx_ring_struct->ring_size * 171 sizeof(struct rx_prod_pkt_bd)) : 0; 172 rx_ring_len = RTE_ALIGN(rx_ring_len, 4096); 173 174 int ag_ring_start = rx_ring_start + rx_ring_len; 175 ag_ring_start = RTE_ALIGN(ag_ring_start, 4096); 176 int ag_ring_len = rx_ring_len * AGG_RING_SIZE_FACTOR; 177 ag_ring_len = RTE_ALIGN(ag_ring_len, 4096); 178 179 int ag_bitmap_start = ag_ring_start + ag_ring_len; 180 int ag_bitmap_len = rx_ring_info ? 181 RTE_CACHE_LINE_ROUNDUP(rte_bitmap_get_memory_footprint( 182 rx_ring_info->rx_ring_struct->ring_size * 183 AGG_RING_SIZE_FACTOR)) : 0; 184 185 int tpa_info_start = ag_bitmap_start + ag_bitmap_len; 186 int tpa_info_len = 0; 187 188 if (rx_ring_info && (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)) { 189 int tpa_max = BNXT_TPA_MAX_AGGS(bp); 190 191 tpa_info_len = tpa_max * sizeof(struct bnxt_tpa_info); 192 tpa_info_len = RTE_CACHE_LINE_ROUNDUP(tpa_info_len); 193 } 194 195 int total_alloc_len = tpa_info_start; 196 total_alloc_len += tpa_info_len; 197 198 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 199 "bnxt_" PCI_PRI_FMT "-%04x_%s", pdev->addr.domain, 200 pdev->addr.bus, pdev->addr.devid, pdev->addr.function, qidx, 201 suffix); 202 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 203 mz = rte_memzone_lookup(mz_name); 204 if (!mz) { 205 mz = rte_memzone_reserve_aligned(mz_name, total_alloc_len, 206 SOCKET_ID_ANY, 207 RTE_MEMZONE_2MB | 208 RTE_MEMZONE_SIZE_HINT_ONLY | 209 RTE_MEMZONE_IOVA_CONTIG, 210 getpagesize()); 211 if (mz == NULL) 212 return -ENOMEM; 213 } 214 memset(mz->addr, 0, mz->len); 215 mz_phys_addr = mz->iova; 216 217 if (tx_ring_info) { 218 txq->mz = mz; 219 tx_ring = tx_ring_info->tx_ring_struct; 220 221 tx_ring->bd = ((char *)mz->addr + tx_ring_start); 222 tx_ring_info->tx_desc_ring = (struct tx_bd_long *)tx_ring->bd; 223 tx_ring->bd_dma = mz_phys_addr + tx_ring_start; 224 tx_ring_info->tx_desc_mapping = tx_ring->bd_dma; 225 tx_ring->mem_zone = (const void *)mz; 226 227 if (!tx_ring->bd) 228 return -ENOMEM; 229 if (tx_ring->vmem_size) { 230 tx_ring->vmem = 231 (void **)((char *)mz->addr + tx_vmem_start); 232 tx_ring_info->tx_buf_ring = 233 (struct bnxt_sw_tx_bd *)tx_ring->vmem; 234 } 235 } 236 237 if (rx_ring_info) { 238 rxq->mz = mz; 239 rx_ring = rx_ring_info->rx_ring_struct; 240 241 rx_ring->bd = ((char *)mz->addr + rx_ring_start); 242 rx_ring_info->rx_desc_ring = 243 (struct rx_prod_pkt_bd *)rx_ring->bd; 244 rx_ring->bd_dma = mz_phys_addr + rx_ring_start; 245 rx_ring_info->rx_desc_mapping = rx_ring->bd_dma; 246 rx_ring->mem_zone = (const void *)mz; 247 248 if (!rx_ring->bd) 249 return -ENOMEM; 250 if (rx_ring->vmem_size) { 251 rx_ring->vmem = 252 (void **)((char *)mz->addr + rx_vmem_start); 253 rx_ring_info->rx_buf_ring = 254 (struct rte_mbuf **)rx_ring->vmem; 255 } 256 257 rx_ring = rx_ring_info->ag_ring_struct; 258 259 rx_ring->bd = ((char *)mz->addr + ag_ring_start); 260 rx_ring_info->ag_desc_ring = 261 (struct rx_prod_pkt_bd *)rx_ring->bd; 262 rx_ring->bd_dma = mz->iova + ag_ring_start; 263 rx_ring_info->ag_desc_mapping = rx_ring->bd_dma; 264 rx_ring->mem_zone = (const void *)mz; 265 266 if (!rx_ring->bd) 267 return -ENOMEM; 268 if (rx_ring->vmem_size) { 269 rx_ring->vmem = 270 (void **)((char *)mz->addr + ag_vmem_start); 271 rx_ring_info->ag_buf_ring = 272 (struct rte_mbuf **)rx_ring->vmem; 273 } 274 275 rx_ring_info->ag_bitmap = 276 rte_bitmap_init(rx_ring_info->rx_ring_struct->ring_size * 277 AGG_RING_SIZE_FACTOR, (uint8_t *)mz->addr + 278 ag_bitmap_start, ag_bitmap_len); 279 280 /* TPA info */ 281 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) 282 rx_ring_info->tpa_info = 283 ((struct bnxt_tpa_info *)((char *)mz->addr + 284 tpa_info_start)); 285 } 286 287 cp_ring->bd = ((char *)mz->addr + cp_ring_start); 288 cp_ring->bd_dma = mz_phys_addr + cp_ring_start; 289 cp_ring_info->cp_desc_ring = cp_ring->bd; 290 cp_ring_info->cp_desc_mapping = cp_ring->bd_dma; 291 cp_ring->mem_zone = (const void *)mz; 292 293 if (!cp_ring->bd) 294 return -ENOMEM; 295 if (cp_ring->vmem_size) 296 *cp_ring->vmem = ((char *)mz->addr + stats_len); 297 if (stats_len) { 298 cp_ring_info->hw_stats = mz->addr; 299 cp_ring_info->hw_stats_map = mz_phys_addr; 300 } 301 cp_ring_info->hw_stats_ctx_id = HWRM_NA_SIGNATURE; 302 303 if (nq_ring_info) { 304 struct bnxt_ring *nq_ring = nq_ring_info->cp_ring_struct; 305 306 nq_ring->bd = (char *)mz->addr + nq_ring_start; 307 nq_ring->bd_dma = mz_phys_addr + nq_ring_start; 308 nq_ring_info->cp_desc_ring = nq_ring->bd; 309 nq_ring_info->cp_desc_mapping = nq_ring->bd_dma; 310 nq_ring->mem_zone = (const void *)mz; 311 312 if (!nq_ring->bd) 313 return -ENOMEM; 314 if (nq_ring->vmem_size) 315 *nq_ring->vmem = (char *)mz->addr + nq_vmem_start; 316 317 nq_ring_info->hw_stats_ctx_id = HWRM_NA_SIGNATURE; 318 } 319 320 return 0; 321 } 322 323 static void bnxt_init_dflt_coal(struct bnxt_coal *coal) 324 { 325 /* Tick values in micro seconds. 326 * 1 coal_buf x bufs_per_record = 1 completion record. 327 */ 328 coal->num_cmpl_aggr_int = BNXT_NUM_CMPL_AGGR_INT; 329 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */ 330 coal->num_cmpl_dma_aggr = BNXT_NUM_CMPL_DMA_AGGR; 331 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */ 332 coal->num_cmpl_dma_aggr_during_int = BNXT_NUM_CMPL_DMA_AGGR_DURING_INT; 333 coal->int_lat_tmr_max = BNXT_INT_LAT_TMR_MAX; 334 /* min timer set to 1/2 of interrupt timer */ 335 coal->int_lat_tmr_min = BNXT_INT_LAT_TMR_MIN; 336 /* buf timer set to 1/4 of interrupt timer */ 337 coal->cmpl_aggr_dma_tmr = BNXT_CMPL_AGGR_DMA_TMR; 338 coal->cmpl_aggr_dma_tmr_during_int = BNXT_CMPL_AGGR_DMA_TMR_DURING_INT; 339 } 340 341 static void bnxt_set_db(struct bnxt *bp, 342 struct bnxt_db_info *db, 343 uint32_t ring_type, 344 uint32_t map_idx, 345 uint32_t fid) 346 { 347 if (BNXT_CHIP_THOR(bp)) { 348 if (BNXT_PF(bp)) 349 db->doorbell = (char *)bp->doorbell_base + 0x10000; 350 else 351 db->doorbell = (char *)bp->doorbell_base + 0x4000; 352 switch (ring_type) { 353 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX: 354 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ; 355 break; 356 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX: 357 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG: 358 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ; 359 break; 360 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL: 361 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_CQ; 362 break; 363 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ: 364 db->db_key64 = DBR_PATH_L2; 365 break; 366 } 367 db->db_key64 |= (uint64_t)fid << DBR_XID_SFT; 368 db->db_64 = true; 369 } else { 370 db->doorbell = (char *)bp->doorbell_base + map_idx * 0x80; 371 switch (ring_type) { 372 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX: 373 db->db_key32 = DB_KEY_TX; 374 break; 375 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX: 376 db->db_key32 = DB_KEY_RX; 377 break; 378 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL: 379 db->db_key32 = DB_KEY_CP; 380 break; 381 } 382 db->db_64 = false; 383 } 384 } 385 386 static int bnxt_alloc_cmpl_ring(struct bnxt *bp, int queue_index, 387 struct bnxt_cp_ring_info *cpr) 388 { 389 struct bnxt_ring *cp_ring = cpr->cp_ring_struct; 390 uint32_t nq_ring_id = HWRM_NA_SIGNATURE; 391 int cp_ring_index = queue_index + BNXT_RX_VEC_START; 392 struct bnxt_cp_ring_info *nqr = bp->rxtx_nq_ring; 393 uint8_t ring_type; 394 int rc = 0; 395 396 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL; 397 398 if (BNXT_HAS_NQ(bp)) { 399 if (nqr) { 400 nq_ring_id = nqr->cp_ring_struct->fw_ring_id; 401 } else { 402 PMD_DRV_LOG(ERR, "NQ ring is NULL\n"); 403 return -EINVAL; 404 } 405 } 406 407 rc = bnxt_hwrm_ring_alloc(bp, cp_ring, ring_type, cp_ring_index, 408 HWRM_NA_SIGNATURE, nq_ring_id, 0); 409 if (rc) 410 return rc; 411 412 cpr->cp_cons = 0; 413 bnxt_set_db(bp, &cpr->cp_db, ring_type, cp_ring_index, 414 cp_ring->fw_ring_id); 415 bnxt_db_cq(cpr); 416 417 return 0; 418 } 419 420 int bnxt_alloc_rxtx_nq_ring(struct bnxt *bp) 421 { 422 struct bnxt_cp_ring_info *nqr; 423 struct bnxt_ring *ring; 424 int ring_index = BNXT_NUM_ASYNC_CPR(bp); 425 unsigned int socket_id; 426 uint8_t ring_type; 427 int rc = 0; 428 429 if (!BNXT_HAS_NQ(bp) || bp->rxtx_nq_ring) 430 return 0; 431 432 socket_id = rte_lcore_to_socket_id(rte_get_master_lcore()); 433 434 nqr = rte_zmalloc_socket("nqr", 435 sizeof(struct bnxt_cp_ring_info), 436 RTE_CACHE_LINE_SIZE, socket_id); 437 if (nqr == NULL) 438 return -ENOMEM; 439 440 ring = rte_zmalloc_socket("bnxt_cp_ring_struct", 441 sizeof(struct bnxt_ring), 442 RTE_CACHE_LINE_SIZE, socket_id); 443 if (ring == NULL) { 444 rte_free(nqr); 445 return -ENOMEM; 446 } 447 448 ring->bd = (void *)nqr->cp_desc_ring; 449 ring->bd_dma = nqr->cp_desc_mapping; 450 ring->ring_size = rte_align32pow2(DEFAULT_CP_RING_SIZE); 451 ring->ring_mask = ring->ring_size - 1; 452 ring->vmem_size = 0; 453 ring->vmem = NULL; 454 ring->fw_ring_id = INVALID_HW_RING_ID; 455 456 nqr->cp_ring_struct = ring; 457 rc = bnxt_alloc_rings(bp, 0, NULL, NULL, nqr, NULL, "l2_nqr"); 458 if (rc) { 459 rte_free(ring); 460 rte_free(nqr); 461 return -ENOMEM; 462 } 463 464 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ; 465 466 rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, ring_index, 467 HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE, 0); 468 if (rc) { 469 rte_free(ring); 470 rte_free(nqr); 471 return rc; 472 } 473 474 bnxt_set_db(bp, &nqr->cp_db, ring_type, ring_index, 475 ring->fw_ring_id); 476 bnxt_db_nq(nqr); 477 478 bp->rxtx_nq_ring = nqr; 479 480 return 0; 481 } 482 483 /* Free RX/TX NQ ring. */ 484 void bnxt_free_rxtx_nq_ring(struct bnxt *bp) 485 { 486 struct bnxt_cp_ring_info *nqr = bp->rxtx_nq_ring; 487 488 if (!nqr) 489 return; 490 491 bnxt_free_nq_ring(bp, nqr); 492 493 bnxt_free_ring(nqr->cp_ring_struct); 494 rte_free(nqr->cp_ring_struct); 495 nqr->cp_ring_struct = NULL; 496 rte_free(nqr); 497 bp->rxtx_nq_ring = NULL; 498 } 499 500 static int bnxt_alloc_rx_ring(struct bnxt *bp, int queue_index) 501 { 502 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index]; 503 struct bnxt_cp_ring_info *cpr = rxq->cp_ring; 504 struct bnxt_ring *cp_ring = cpr->cp_ring_struct; 505 struct bnxt_rx_ring_info *rxr = rxq->rx_ring; 506 struct bnxt_ring *ring = rxr->rx_ring_struct; 507 uint8_t ring_type; 508 int rc = 0; 509 510 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX; 511 512 rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, 513 queue_index, cpr->hw_stats_ctx_id, 514 cp_ring->fw_ring_id, 0); 515 if (rc) 516 return rc; 517 518 rxr->rx_prod = 0; 519 if (BNXT_HAS_RING_GRPS(bp)) 520 bp->grp_info[queue_index].rx_fw_ring_id = ring->fw_ring_id; 521 bnxt_set_db(bp, &rxr->rx_db, ring_type, queue_index, ring->fw_ring_id); 522 bnxt_db_write(&rxr->rx_db, rxr->rx_prod); 523 524 return 0; 525 } 526 527 static int bnxt_alloc_rx_agg_ring(struct bnxt *bp, int queue_index) 528 { 529 unsigned int map_idx = queue_index + bp->rx_cp_nr_rings; 530 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index]; 531 struct bnxt_cp_ring_info *cpr = rxq->cp_ring; 532 struct bnxt_ring *cp_ring = cpr->cp_ring_struct; 533 struct bnxt_rx_ring_info *rxr = rxq->rx_ring; 534 struct bnxt_ring *ring = rxr->ag_ring_struct; 535 uint32_t hw_stats_ctx_id = HWRM_NA_SIGNATURE; 536 uint8_t ring_type; 537 int rc = 0; 538 539 ring->fw_rx_ring_id = rxr->rx_ring_struct->fw_ring_id; 540 541 if (BNXT_CHIP_THOR(bp)) { 542 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG; 543 hw_stats_ctx_id = cpr->hw_stats_ctx_id; 544 } else { 545 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX; 546 } 547 548 rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, map_idx, 549 hw_stats_ctx_id, cp_ring->fw_ring_id, 0); 550 551 if (rc) 552 return rc; 553 554 rxr->ag_prod = 0; 555 if (BNXT_HAS_RING_GRPS(bp)) 556 bp->grp_info[queue_index].ag_fw_ring_id = ring->fw_ring_id; 557 bnxt_set_db(bp, &rxr->ag_db, ring_type, map_idx, ring->fw_ring_id); 558 bnxt_db_write(&rxr->ag_db, rxr->ag_prod); 559 560 return 0; 561 } 562 563 int bnxt_alloc_hwrm_rx_ring(struct bnxt *bp, int queue_index) 564 { 565 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index]; 566 struct bnxt_cp_ring_info *cpr = rxq->cp_ring; 567 struct bnxt_ring *cp_ring = cpr->cp_ring_struct; 568 struct bnxt_rx_ring_info *rxr = rxq->rx_ring; 569 int rc; 570 571 rc = bnxt_alloc_cmpl_ring(bp, queue_index, cpr); 572 if (rc) 573 goto err_out; 574 575 if (BNXT_HAS_RING_GRPS(bp)) { 576 bp->grp_info[queue_index].fw_stats_ctx = cpr->hw_stats_ctx_id; 577 bp->grp_info[queue_index].cp_fw_ring_id = cp_ring->fw_ring_id; 578 } 579 580 if (!BNXT_NUM_ASYNC_CPR(bp) && !queue_index) { 581 /* 582 * If a dedicated async event completion ring is not enabled, 583 * use the first completion ring from PF or VF as the default 584 * completion ring for async event handling. 585 */ 586 bp->async_cp_ring = cpr; 587 rc = bnxt_hwrm_set_async_event_cr(bp); 588 if (rc) 589 goto err_out; 590 } 591 592 rc = bnxt_alloc_rx_ring(bp, queue_index); 593 if (rc) 594 goto err_out; 595 596 rc = bnxt_alloc_rx_agg_ring(bp, queue_index); 597 if (rc) 598 goto err_out; 599 600 if (rxq->rx_started) { 601 if (bnxt_init_one_rx_ring(rxq)) { 602 PMD_DRV_LOG(ERR, 603 "bnxt_init_one_rx_ring failed!\n"); 604 bnxt_rx_queue_release_op(rxq); 605 rc = -ENOMEM; 606 goto err_out; 607 } 608 bnxt_db_write(&rxr->rx_db, rxr->rx_prod); 609 bnxt_db_write(&rxr->ag_db, rxr->ag_prod); 610 } 611 rxq->index = queue_index; 612 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 613 bnxt_rxq_vec_setup(rxq); 614 #endif 615 616 return 0; 617 618 err_out: 619 PMD_DRV_LOG(ERR, 620 "Failed to allocate receive queue %d, rc %d.\n", 621 queue_index, rc); 622 return rc; 623 } 624 625 /* Initialise all rings to -1, its used to free rings later if allocation 626 * of few rings fails. 627 */ 628 static void bnxt_init_all_rings(struct bnxt *bp) 629 { 630 unsigned int i = 0; 631 struct bnxt_rx_queue *rxq; 632 struct bnxt_ring *cp_ring; 633 struct bnxt_ring *ring; 634 struct bnxt_rx_ring_info *rxr; 635 struct bnxt_tx_queue *txq; 636 637 for (i = 0; i < bp->rx_cp_nr_rings; i++) { 638 rxq = bp->rx_queues[i]; 639 /* Rx-compl */ 640 cp_ring = rxq->cp_ring->cp_ring_struct; 641 cp_ring->fw_ring_id = INVALID_HW_RING_ID; 642 /* Rx-Reg */ 643 rxr = rxq->rx_ring; 644 ring = rxr->rx_ring_struct; 645 ring->fw_ring_id = INVALID_HW_RING_ID; 646 /* Rx-AGG */ 647 ring = rxr->ag_ring_struct; 648 ring->fw_ring_id = INVALID_HW_RING_ID; 649 } 650 for (i = 0; i < bp->tx_cp_nr_rings; i++) { 651 txq = bp->tx_queues[i]; 652 /* Tx cmpl */ 653 cp_ring = txq->cp_ring->cp_ring_struct; 654 cp_ring->fw_ring_id = INVALID_HW_RING_ID; 655 /*Tx Ring */ 656 ring = txq->tx_ring->tx_ring_struct; 657 ring->fw_ring_id = INVALID_HW_RING_ID; 658 } 659 } 660 661 /* ring_grp usage: 662 * [0] = default completion ring 663 * [1 -> +rx_cp_nr_rings] = rx_cp, rx rings 664 * [1+rx_cp_nr_rings + 1 -> +tx_cp_nr_rings] = tx_cp, tx rings 665 */ 666 int bnxt_alloc_hwrm_rings(struct bnxt *bp) 667 { 668 struct bnxt_coal coal; 669 unsigned int i; 670 uint8_t ring_type; 671 int rc = 0; 672 673 bnxt_init_dflt_coal(&coal); 674 bnxt_init_all_rings(bp); 675 676 for (i = 0; i < bp->rx_cp_nr_rings; i++) { 677 struct bnxt_rx_queue *rxq = bp->rx_queues[i]; 678 struct bnxt_cp_ring_info *cpr = rxq->cp_ring; 679 struct bnxt_ring *cp_ring = cpr->cp_ring_struct; 680 struct bnxt_rx_ring_info *rxr = rxq->rx_ring; 681 682 if (bnxt_alloc_cmpl_ring(bp, i, cpr)) 683 goto err_out; 684 685 if (BNXT_HAS_RING_GRPS(bp)) { 686 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; 687 bp->grp_info[i].cp_fw_ring_id = cp_ring->fw_ring_id; 688 } 689 690 bnxt_hwrm_set_ring_coal(bp, &coal, cp_ring->fw_ring_id); 691 if (!BNXT_NUM_ASYNC_CPR(bp) && !i) { 692 /* 693 * If a dedicated async event completion ring is not 694 * enabled, use the first completion ring as the default 695 * completion ring for async event handling. 696 */ 697 bp->async_cp_ring = cpr; 698 rc = bnxt_hwrm_set_async_event_cr(bp); 699 if (rc) 700 goto err_out; 701 } 702 703 if (bnxt_alloc_rx_ring(bp, i)) 704 goto err_out; 705 706 if (bnxt_alloc_rx_agg_ring(bp, i)) 707 goto err_out; 708 709 if (bnxt_init_one_rx_ring(rxq)) { 710 PMD_DRV_LOG(ERR, "bnxt_init_one_rx_ring failed!\n"); 711 bnxt_rx_queue_release_op(rxq); 712 return -ENOMEM; 713 } 714 bnxt_db_write(&rxr->rx_db, rxr->rx_prod); 715 bnxt_db_write(&rxr->ag_db, rxr->ag_prod); 716 rxq->index = i; 717 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 718 bnxt_rxq_vec_setup(rxq); 719 #endif 720 } 721 722 for (i = 0; i < bp->tx_cp_nr_rings; i++) { 723 struct bnxt_tx_queue *txq = bp->tx_queues[i]; 724 struct bnxt_cp_ring_info *cpr = txq->cp_ring; 725 struct bnxt_ring *cp_ring = cpr->cp_ring_struct; 726 struct bnxt_tx_ring_info *txr = txq->tx_ring; 727 struct bnxt_ring *ring = txr->tx_ring_struct; 728 unsigned int idx = i + bp->rx_cp_nr_rings; 729 uint16_t tx_cosq_id = 0; 730 731 if (bnxt_alloc_cmpl_ring(bp, idx, cpr)) 732 goto err_out; 733 734 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) 735 tx_cosq_id = bp->tx_cosq_id[i < bp->max_lltc ? i : 0]; 736 else 737 tx_cosq_id = bp->tx_cosq_id[0]; 738 /* Tx ring */ 739 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_TX; 740 rc = bnxt_hwrm_ring_alloc(bp, ring, 741 ring_type, 742 i, cpr->hw_stats_ctx_id, 743 cp_ring->fw_ring_id, 744 tx_cosq_id); 745 if (rc) 746 goto err_out; 747 748 bnxt_set_db(bp, &txr->tx_db, ring_type, i, ring->fw_ring_id); 749 txq->index = idx; 750 bnxt_hwrm_set_ring_coal(bp, &coal, cp_ring->fw_ring_id); 751 } 752 753 err_out: 754 return rc; 755 } 756 757 /* Allocate dedicated async completion ring. */ 758 int bnxt_alloc_async_cp_ring(struct bnxt *bp) 759 { 760 struct bnxt_cp_ring_info *cpr = bp->async_cp_ring; 761 struct bnxt_ring *cp_ring; 762 uint8_t ring_type; 763 int rc; 764 765 if (BNXT_NUM_ASYNC_CPR(bp) == 0 || cpr == NULL) 766 return 0; 767 768 cp_ring = cpr->cp_ring_struct; 769 770 if (BNXT_HAS_NQ(bp)) 771 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ; 772 else 773 ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL; 774 775 rc = bnxt_hwrm_ring_alloc(bp, cp_ring, ring_type, 0, 776 HWRM_NA_SIGNATURE, HWRM_NA_SIGNATURE, 0); 777 778 if (rc) 779 return rc; 780 781 cpr->cp_cons = 0; 782 cpr->valid = 0; 783 bnxt_set_db(bp, &cpr->cp_db, ring_type, 0, 784 cp_ring->fw_ring_id); 785 786 if (BNXT_HAS_NQ(bp)) 787 bnxt_db_nq(cpr); 788 else 789 bnxt_db_cq(cpr); 790 791 return bnxt_hwrm_set_async_event_cr(bp); 792 } 793 794 /* Free dedicated async completion ring. */ 795 void bnxt_free_async_cp_ring(struct bnxt *bp) 796 { 797 struct bnxt_cp_ring_info *cpr = bp->async_cp_ring; 798 799 if (BNXT_NUM_ASYNC_CPR(bp) == 0 || cpr == NULL) 800 return; 801 802 if (BNXT_HAS_NQ(bp)) 803 bnxt_free_nq_ring(bp, cpr); 804 else 805 bnxt_free_cp_ring(bp, cpr); 806 807 bnxt_free_ring(cpr->cp_ring_struct); 808 rte_free(cpr->cp_ring_struct); 809 cpr->cp_ring_struct = NULL; 810 rte_free(cpr); 811 bp->async_cp_ring = NULL; 812 } 813 814 int bnxt_alloc_async_ring_struct(struct bnxt *bp) 815 { 816 struct bnxt_cp_ring_info *cpr = NULL; 817 struct bnxt_ring *ring = NULL; 818 unsigned int socket_id; 819 820 if (BNXT_NUM_ASYNC_CPR(bp) == 0) 821 return 0; 822 823 socket_id = rte_lcore_to_socket_id(rte_get_master_lcore()); 824 825 cpr = rte_zmalloc_socket("cpr", 826 sizeof(struct bnxt_cp_ring_info), 827 RTE_CACHE_LINE_SIZE, socket_id); 828 if (cpr == NULL) 829 return -ENOMEM; 830 831 ring = rte_zmalloc_socket("bnxt_cp_ring_struct", 832 sizeof(struct bnxt_ring), 833 RTE_CACHE_LINE_SIZE, socket_id); 834 if (ring == NULL) { 835 rte_free(cpr); 836 return -ENOMEM; 837 } 838 839 ring->bd = (void *)cpr->cp_desc_ring; 840 ring->bd_dma = cpr->cp_desc_mapping; 841 ring->ring_size = rte_align32pow2(DEFAULT_CP_RING_SIZE); 842 ring->ring_mask = ring->ring_size - 1; 843 ring->vmem_size = 0; 844 ring->vmem = NULL; 845 846 bp->async_cp_ring = cpr; 847 cpr->cp_ring_struct = ring; 848 849 return bnxt_alloc_rings(bp, 0, NULL, NULL, 850 bp->async_cp_ring, NULL, 851 "def_cp"); 852 } 853