1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <rte_ethdev_driver.h> 11 #include <rte_ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 #include <rte_kvargs.h> 16 17 #include "bnxt.h" 18 #include "bnxt_filter.h" 19 #include "bnxt_hwrm.h" 20 #include "bnxt_irq.h" 21 #include "bnxt_reps.h" 22 #include "bnxt_ring.h" 23 #include "bnxt_rxq.h" 24 #include "bnxt_rxr.h" 25 #include "bnxt_stats.h" 26 #include "bnxt_txq.h" 27 #include "bnxt_txr.h" 28 #include "bnxt_vnic.h" 29 #include "hsi_struct_def_dpdk.h" 30 #include "bnxt_nvm_defs.h" 31 #include "bnxt_tf_common.h" 32 #include "ulp_flow_db.h" 33 34 #define DRV_MODULE_NAME "bnxt" 35 static const char bnxt_version[] = 36 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 37 38 /* 39 * The set of PCI devices this driver supports 40 */ 41 static const struct rte_pci_id bnxt_pci_id_map[] = { 42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 45 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 95 { .vendor_id = 0, /* sentinel */ }, 96 }; 97 98 #define BNXT_DEVARG_TRUFLOW "host-based-truflow" 99 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" 101 #define BNXT_DEVARG_REPRESENTOR "representor" 102 103 static const char *const bnxt_dev_args[] = { 104 BNXT_DEVARG_REPRESENTOR, 105 BNXT_DEVARG_TRUFLOW, 106 BNXT_DEVARG_FLOW_XSTAT, 107 BNXT_DEVARG_MAX_NUM_KFLOWS, 108 NULL 109 }; 110 111 /* 112 * truflow == false to disable the feature 113 * truflow == true to enable the feature 114 */ 115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1) 116 117 /* 118 * flow_xstat == false to disable the feature 119 * flow_xstat == true to enable the feature 120 */ 121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1) 122 123 /* 124 * max_num_kflows must be >= 32 125 * and must be a power-of-2 supported value 126 * return: 1 -> invalid 127 * 0 -> valid 128 */ 129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows) 130 { 131 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows)) 132 return 1; 133 return 0; 134 } 135 136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 140 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 141 static int bnxt_restore_vlan_filters(struct bnxt *bp); 142 static void bnxt_dev_recover(void *arg); 143 static void bnxt_free_error_recovery_info(struct bnxt *bp); 144 static void bnxt_free_rep_info(struct bnxt *bp); 145 146 int is_bnxt_in_error(struct bnxt *bp) 147 { 148 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 149 return -EIO; 150 if (bp->flags & BNXT_FLAG_FW_RESET) 151 return -EBUSY; 152 153 return 0; 154 } 155 156 /***********************/ 157 158 /* 159 * High level utility functions 160 */ 161 162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 163 { 164 if (!BNXT_CHIP_THOR(bp)) 165 return 1; 166 167 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings, 168 BNXT_RSS_ENTRIES_PER_CTX_THOR) / 169 BNXT_RSS_ENTRIES_PER_CTX_THOR; 170 } 171 172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 173 { 174 if (!BNXT_CHIP_THOR(bp)) 175 return HW_HASH_INDEX_SIZE; 176 177 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR; 178 } 179 180 static void bnxt_free_parent_info(struct bnxt *bp) 181 { 182 rte_free(bp->parent); 183 } 184 185 static void bnxt_free_pf_info(struct bnxt *bp) 186 { 187 rte_free(bp->pf); 188 } 189 190 static void bnxt_free_link_info(struct bnxt *bp) 191 { 192 rte_free(bp->link_info); 193 } 194 195 static void bnxt_free_leds_info(struct bnxt *bp) 196 { 197 rte_free(bp->leds); 198 bp->leds = NULL; 199 } 200 201 static void bnxt_free_flow_stats_info(struct bnxt *bp) 202 { 203 rte_free(bp->flow_stat); 204 bp->flow_stat = NULL; 205 } 206 207 static void bnxt_free_cos_queues(struct bnxt *bp) 208 { 209 rte_free(bp->rx_cos_queue); 210 rte_free(bp->tx_cos_queue); 211 } 212 213 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 214 { 215 bnxt_free_filter_mem(bp); 216 bnxt_free_vnic_attributes(bp); 217 bnxt_free_vnic_mem(bp); 218 219 /* tx/rx rings are configured as part of *_queue_setup callbacks. 220 * If the number of rings change across fw update, 221 * we don't have much choice except to warn the user. 222 */ 223 if (!reconfig) { 224 bnxt_free_stats(bp); 225 bnxt_free_tx_rings(bp); 226 bnxt_free_rx_rings(bp); 227 } 228 bnxt_free_async_cp_ring(bp); 229 bnxt_free_rxtx_nq_ring(bp); 230 231 rte_free(bp->grp_info); 232 bp->grp_info = NULL; 233 } 234 235 static int bnxt_alloc_parent_info(struct bnxt *bp) 236 { 237 bp->parent = rte_zmalloc("bnxt_parent_info", 238 sizeof(struct bnxt_parent_info), 0); 239 if (bp->parent == NULL) 240 return -ENOMEM; 241 242 return 0; 243 } 244 245 static int bnxt_alloc_pf_info(struct bnxt *bp) 246 { 247 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0); 248 if (bp->pf == NULL) 249 return -ENOMEM; 250 251 return 0; 252 } 253 254 static int bnxt_alloc_link_info(struct bnxt *bp) 255 { 256 bp->link_info = 257 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0); 258 if (bp->link_info == NULL) 259 return -ENOMEM; 260 261 return 0; 262 } 263 264 static int bnxt_alloc_leds_info(struct bnxt *bp) 265 { 266 bp->leds = rte_zmalloc("bnxt_leds", 267 BNXT_MAX_LED * sizeof(struct bnxt_led_info), 268 0); 269 if (bp->leds == NULL) 270 return -ENOMEM; 271 272 return 0; 273 } 274 275 static int bnxt_alloc_cos_queues(struct bnxt *bp) 276 { 277 bp->rx_cos_queue = 278 rte_zmalloc("bnxt_rx_cosq", 279 BNXT_COS_QUEUE_COUNT * 280 sizeof(struct bnxt_cos_queue_info), 281 0); 282 if (bp->rx_cos_queue == NULL) 283 return -ENOMEM; 284 285 bp->tx_cos_queue = 286 rte_zmalloc("bnxt_tx_cosq", 287 BNXT_COS_QUEUE_COUNT * 288 sizeof(struct bnxt_cos_queue_info), 289 0); 290 if (bp->tx_cos_queue == NULL) 291 return -ENOMEM; 292 293 return 0; 294 } 295 296 static int bnxt_alloc_flow_stats_info(struct bnxt *bp) 297 { 298 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat", 299 sizeof(struct bnxt_flow_stat_info), 0); 300 if (bp->flow_stat == NULL) 301 return -ENOMEM; 302 303 return 0; 304 } 305 306 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 307 { 308 int rc; 309 310 rc = bnxt_alloc_ring_grps(bp); 311 if (rc) 312 goto alloc_mem_err; 313 314 rc = bnxt_alloc_async_ring_struct(bp); 315 if (rc) 316 goto alloc_mem_err; 317 318 rc = bnxt_alloc_vnic_mem(bp); 319 if (rc) 320 goto alloc_mem_err; 321 322 rc = bnxt_alloc_vnic_attributes(bp); 323 if (rc) 324 goto alloc_mem_err; 325 326 rc = bnxt_alloc_filter_mem(bp); 327 if (rc) 328 goto alloc_mem_err; 329 330 rc = bnxt_alloc_async_cp_ring(bp); 331 if (rc) 332 goto alloc_mem_err; 333 334 rc = bnxt_alloc_rxtx_nq_ring(bp); 335 if (rc) 336 goto alloc_mem_err; 337 338 if (BNXT_FLOW_XSTATS_EN(bp)) { 339 rc = bnxt_alloc_flow_stats_info(bp); 340 if (rc) 341 goto alloc_mem_err; 342 } 343 344 return 0; 345 346 alloc_mem_err: 347 bnxt_free_mem(bp, reconfig); 348 return rc; 349 } 350 351 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 352 { 353 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 354 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 355 uint64_t rx_offloads = dev_conf->rxmode.offloads; 356 struct bnxt_rx_queue *rxq; 357 unsigned int j; 358 int rc; 359 360 rc = bnxt_vnic_grp_alloc(bp, vnic); 361 if (rc) 362 goto err_out; 363 364 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 365 vnic_id, vnic, vnic->fw_grp_ids); 366 367 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 368 if (rc) 369 goto err_out; 370 371 /* Alloc RSS context only if RSS mode is enabled */ 372 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 373 int j, nr_ctxs = bnxt_rss_ctxts(bp); 374 375 rc = 0; 376 for (j = 0; j < nr_ctxs; j++) { 377 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 378 if (rc) 379 break; 380 } 381 if (rc) { 382 PMD_DRV_LOG(ERR, 383 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 384 vnic_id, j, rc); 385 goto err_out; 386 } 387 vnic->num_lb_ctxts = nr_ctxs; 388 } 389 390 /* 391 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 392 * setting is not available at this time, it will not be 393 * configured correctly in the CFA. 394 */ 395 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 396 vnic->vlan_strip = true; 397 else 398 vnic->vlan_strip = false; 399 400 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 401 if (rc) 402 goto err_out; 403 404 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 405 if (rc) 406 goto err_out; 407 408 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 409 rxq = bp->eth_dev->data->rx_queues[j]; 410 411 PMD_DRV_LOG(DEBUG, 412 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 413 j, rxq->vnic, rxq->vnic->fw_grp_ids); 414 415 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 416 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 417 else 418 vnic->rx_queue_cnt++; 419 } 420 421 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 422 423 rc = bnxt_vnic_rss_configure(bp, vnic); 424 if (rc) 425 goto err_out; 426 427 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 428 429 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) 430 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 431 else 432 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 433 434 return 0; 435 err_out: 436 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 437 vnic_id, rc); 438 return rc; 439 } 440 441 static int bnxt_register_fc_ctx_mem(struct bnxt *bp) 442 { 443 int rc = 0; 444 445 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma, 446 &bp->flow_stat->rx_fc_in_tbl.ctx_id); 447 if (rc) 448 return rc; 449 450 PMD_DRV_LOG(DEBUG, 451 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p" 452 " rx_fc_in_tbl.ctx_id = %d\n", 453 bp->flow_stat->rx_fc_in_tbl.va, 454 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma), 455 bp->flow_stat->rx_fc_in_tbl.ctx_id); 456 457 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma, 458 &bp->flow_stat->rx_fc_out_tbl.ctx_id); 459 if (rc) 460 return rc; 461 462 PMD_DRV_LOG(DEBUG, 463 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p" 464 " rx_fc_out_tbl.ctx_id = %d\n", 465 bp->flow_stat->rx_fc_out_tbl.va, 466 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma), 467 bp->flow_stat->rx_fc_out_tbl.ctx_id); 468 469 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma, 470 &bp->flow_stat->tx_fc_in_tbl.ctx_id); 471 if (rc) 472 return rc; 473 474 PMD_DRV_LOG(DEBUG, 475 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p" 476 " tx_fc_in_tbl.ctx_id = %d\n", 477 bp->flow_stat->tx_fc_in_tbl.va, 478 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma), 479 bp->flow_stat->tx_fc_in_tbl.ctx_id); 480 481 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma, 482 &bp->flow_stat->tx_fc_out_tbl.ctx_id); 483 if (rc) 484 return rc; 485 486 PMD_DRV_LOG(DEBUG, 487 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p" 488 " tx_fc_out_tbl.ctx_id = %d\n", 489 bp->flow_stat->tx_fc_out_tbl.va, 490 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma), 491 bp->flow_stat->tx_fc_out_tbl.ctx_id); 492 493 memset(bp->flow_stat->rx_fc_out_tbl.va, 494 0, 495 bp->flow_stat->rx_fc_out_tbl.size); 496 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 497 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 498 bp->flow_stat->rx_fc_out_tbl.ctx_id, 499 bp->flow_stat->max_fc, 500 true); 501 if (rc) 502 return rc; 503 504 memset(bp->flow_stat->tx_fc_out_tbl.va, 505 0, 506 bp->flow_stat->tx_fc_out_tbl.size); 507 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 508 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 509 bp->flow_stat->tx_fc_out_tbl.ctx_id, 510 bp->flow_stat->max_fc, 511 true); 512 513 return rc; 514 } 515 516 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size, 517 struct bnxt_ctx_mem_buf_info *ctx) 518 { 519 if (!ctx) 520 return -EINVAL; 521 522 ctx->va = rte_zmalloc(type, size, 0); 523 if (ctx->va == NULL) 524 return -ENOMEM; 525 rte_mem_lock_page(ctx->va); 526 ctx->size = size; 527 ctx->dma = rte_mem_virt2iova(ctx->va); 528 if (ctx->dma == RTE_BAD_IOVA) 529 return -ENOMEM; 530 531 return 0; 532 } 533 534 static int bnxt_init_fc_ctx_mem(struct bnxt *bp) 535 { 536 struct rte_pci_device *pdev = bp->pdev; 537 char type[RTE_MEMZONE_NAMESIZE]; 538 uint16_t max_fc; 539 int rc = 0; 540 541 max_fc = bp->flow_stat->max_fc; 542 543 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 544 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 545 /* 4 bytes for each counter-id */ 546 rc = bnxt_alloc_ctx_mem_buf(type, 547 max_fc * 4, 548 &bp->flow_stat->rx_fc_in_tbl); 549 if (rc) 550 return rc; 551 552 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 553 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 554 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 555 rc = bnxt_alloc_ctx_mem_buf(type, 556 max_fc * 16, 557 &bp->flow_stat->rx_fc_out_tbl); 558 if (rc) 559 return rc; 560 561 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 562 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 563 /* 4 bytes for each counter-id */ 564 rc = bnxt_alloc_ctx_mem_buf(type, 565 max_fc * 4, 566 &bp->flow_stat->tx_fc_in_tbl); 567 if (rc) 568 return rc; 569 570 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 571 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 572 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 573 rc = bnxt_alloc_ctx_mem_buf(type, 574 max_fc * 16, 575 &bp->flow_stat->tx_fc_out_tbl); 576 if (rc) 577 return rc; 578 579 rc = bnxt_register_fc_ctx_mem(bp); 580 581 return rc; 582 } 583 584 static int bnxt_init_ctx_mem(struct bnxt *bp) 585 { 586 int rc = 0; 587 588 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) || 589 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) || 590 !BNXT_FLOW_XSTATS_EN(bp)) 591 return 0; 592 593 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc); 594 if (rc) 595 return rc; 596 597 rc = bnxt_init_fc_ctx_mem(bp); 598 599 return rc; 600 } 601 602 static int bnxt_init_chip(struct bnxt *bp) 603 { 604 struct rte_eth_link new; 605 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 606 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 607 uint32_t intr_vector = 0; 608 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 609 uint32_t vec = BNXT_MISC_VEC_ID; 610 unsigned int i, j; 611 int rc; 612 613 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 614 bp->eth_dev->data->dev_conf.rxmode.offloads |= 615 DEV_RX_OFFLOAD_JUMBO_FRAME; 616 bp->flags |= BNXT_FLAG_JUMBO; 617 } else { 618 bp->eth_dev->data->dev_conf.rxmode.offloads &= 619 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 620 bp->flags &= ~BNXT_FLAG_JUMBO; 621 } 622 623 /* THOR does not support ring groups. 624 * But we will use the array to save RSS context IDs. 625 */ 626 if (BNXT_CHIP_THOR(bp)) 627 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR; 628 629 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 630 if (rc) { 631 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 632 goto err_out; 633 } 634 635 rc = bnxt_alloc_hwrm_rings(bp); 636 if (rc) { 637 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 638 goto err_out; 639 } 640 641 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 642 if (rc) { 643 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 644 goto err_out; 645 } 646 647 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 648 goto skip_cosq_cfg; 649 650 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 651 if (bp->rx_cos_queue[i].id != 0xff) { 652 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 653 654 if (!vnic) { 655 PMD_DRV_LOG(ERR, 656 "Num pools more than FW profile\n"); 657 rc = -EINVAL; 658 goto err_out; 659 } 660 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 661 bp->rx_cosq_cnt++; 662 } 663 } 664 665 skip_cosq_cfg: 666 rc = bnxt_mq_rx_configure(bp); 667 if (rc) { 668 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 669 goto err_out; 670 } 671 672 /* VNIC configuration */ 673 for (i = 0; i < bp->nr_vnics; i++) { 674 rc = bnxt_setup_one_vnic(bp, i); 675 if (rc) 676 goto err_out; 677 } 678 679 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 680 if (rc) { 681 PMD_DRV_LOG(ERR, 682 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 683 goto err_out; 684 } 685 686 /* check and configure queue intr-vector mapping */ 687 if ((rte_intr_cap_multiple(intr_handle) || 688 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 689 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 690 intr_vector = bp->eth_dev->data->nb_rx_queues; 691 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 692 if (intr_vector > bp->rx_cp_nr_rings) { 693 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 694 bp->rx_cp_nr_rings); 695 return -ENOTSUP; 696 } 697 rc = rte_intr_efd_enable(intr_handle, intr_vector); 698 if (rc) 699 return rc; 700 } 701 702 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 703 intr_handle->intr_vec = 704 rte_zmalloc("intr_vec", 705 bp->eth_dev->data->nb_rx_queues * 706 sizeof(int), 0); 707 if (intr_handle->intr_vec == NULL) { 708 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 709 " intr_vec", bp->eth_dev->data->nb_rx_queues); 710 rc = -ENOMEM; 711 goto err_disable; 712 } 713 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 714 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 715 intr_handle->intr_vec, intr_handle->nb_efd, 716 intr_handle->max_intr); 717 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 718 queue_id++) { 719 intr_handle->intr_vec[queue_id] = 720 vec + BNXT_RX_VEC_START; 721 if (vec < base + intr_handle->nb_efd - 1) 722 vec++; 723 } 724 } 725 726 /* enable uio/vfio intr/eventfd mapping */ 727 rc = rte_intr_enable(intr_handle); 728 #ifndef RTE_EXEC_ENV_FREEBSD 729 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 730 if (rc) 731 goto err_free; 732 #endif 733 734 rc = bnxt_get_hwrm_link_config(bp, &new); 735 if (rc) { 736 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc); 737 goto err_free; 738 } 739 740 if (!bp->link_info->link_up) { 741 rc = bnxt_set_hwrm_link_config(bp, true); 742 if (rc) { 743 PMD_DRV_LOG(ERR, 744 "HWRM link config failure rc: %x\n", rc); 745 goto err_free; 746 } 747 } 748 bnxt_print_link_info(bp->eth_dev); 749 750 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 751 if (!bp->mark_table) 752 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 753 754 return 0; 755 756 err_free: 757 rte_free(intr_handle->intr_vec); 758 err_disable: 759 rte_intr_efd_disable(intr_handle); 760 err_out: 761 /* Some of the error status returned by FW may not be from errno.h */ 762 if (rc > 0) 763 rc = -EIO; 764 765 return rc; 766 } 767 768 static int bnxt_shutdown_nic(struct bnxt *bp) 769 { 770 bnxt_free_all_hwrm_resources(bp); 771 bnxt_free_all_filters(bp); 772 bnxt_free_all_vnics(bp); 773 return 0; 774 } 775 776 /* 777 * Device configuration and status function 778 */ 779 780 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) 781 { 782 uint32_t link_speed = bp->link_info->support_speeds; 783 uint32_t speed_capa = 0; 784 785 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) 786 speed_capa |= ETH_LINK_SPEED_100M; 787 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) 788 speed_capa |= ETH_LINK_SPEED_100M_HD; 789 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) 790 speed_capa |= ETH_LINK_SPEED_1G; 791 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 792 speed_capa |= ETH_LINK_SPEED_2_5G; 793 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) 794 speed_capa |= ETH_LINK_SPEED_10G; 795 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 796 speed_capa |= ETH_LINK_SPEED_20G; 797 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) 798 speed_capa |= ETH_LINK_SPEED_25G; 799 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) 800 speed_capa |= ETH_LINK_SPEED_40G; 801 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) 802 speed_capa |= ETH_LINK_SPEED_50G; 803 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) 804 speed_capa |= ETH_LINK_SPEED_100G; 805 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB) 806 speed_capa |= ETH_LINK_SPEED_200G; 807 808 if (bp->link_info->auto_mode == 809 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 810 speed_capa |= ETH_LINK_SPEED_FIXED; 811 else 812 speed_capa |= ETH_LINK_SPEED_AUTONEG; 813 814 return speed_capa; 815 } 816 817 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 818 struct rte_eth_dev_info *dev_info) 819 { 820 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 821 struct bnxt *bp = eth_dev->data->dev_private; 822 uint16_t max_vnics, i, j, vpool, vrxq; 823 unsigned int max_rx_rings; 824 int rc; 825 826 rc = is_bnxt_in_error(bp); 827 if (rc) 828 return rc; 829 830 /* MAC Specifics */ 831 dev_info->max_mac_addrs = bp->max_l2_ctx; 832 dev_info->max_hash_mac_addrs = 0; 833 834 /* PF/VF specifics */ 835 if (BNXT_PF(bp)) 836 dev_info->max_vfs = pdev->max_vfs; 837 838 max_rx_rings = BNXT_MAX_RINGS(bp); 839 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 840 dev_info->max_rx_queues = max_rx_rings; 841 dev_info->max_tx_queues = max_rx_rings; 842 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 843 dev_info->hash_key_size = 40; 844 max_vnics = bp->max_vnics; 845 846 /* MTU specifics */ 847 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 848 dev_info->max_mtu = BNXT_MAX_MTU; 849 850 /* Fast path specifics */ 851 dev_info->min_rx_bufsize = 1; 852 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 853 854 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 855 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 856 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 857 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT; 858 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 859 860 dev_info->speed_capa = bnxt_get_speed_capabilities(bp); 861 862 /* *INDENT-OFF* */ 863 dev_info->default_rxconf = (struct rte_eth_rxconf) { 864 .rx_thresh = { 865 .pthresh = 8, 866 .hthresh = 8, 867 .wthresh = 0, 868 }, 869 .rx_free_thresh = 32, 870 /* If no descriptors available, pkts are dropped by default */ 871 .rx_drop_en = 1, 872 }; 873 874 dev_info->default_txconf = (struct rte_eth_txconf) { 875 .tx_thresh = { 876 .pthresh = 32, 877 .hthresh = 0, 878 .wthresh = 0, 879 }, 880 .tx_free_thresh = 32, 881 .tx_rs_thresh = 32, 882 }; 883 eth_dev->data->dev_conf.intr_conf.lsc = 1; 884 885 eth_dev->data->dev_conf.intr_conf.rxq = 1; 886 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 887 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 888 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 889 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 890 891 /* *INDENT-ON* */ 892 893 /* 894 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 895 * need further investigation. 896 */ 897 898 /* VMDq resources */ 899 vpool = 64; /* ETH_64_POOLS */ 900 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 901 for (i = 0; i < 4; vpool >>= 1, i++) { 902 if (max_vnics > vpool) { 903 for (j = 0; j < 5; vrxq >>= 1, j++) { 904 if (dev_info->max_rx_queues > vrxq) { 905 if (vpool > vrxq) 906 vpool = vrxq; 907 goto found; 908 } 909 } 910 /* Not enough resources to support VMDq */ 911 break; 912 } 913 } 914 /* Not enough resources to support VMDq */ 915 vpool = 0; 916 vrxq = 0; 917 found: 918 dev_info->max_vmdq_pools = vpool; 919 dev_info->vmdq_queue_num = vrxq; 920 921 dev_info->vmdq_pool_base = 0; 922 dev_info->vmdq_queue_base = 0; 923 924 return 0; 925 } 926 927 /* Configure the device based on the configuration provided */ 928 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 929 { 930 struct bnxt *bp = eth_dev->data->dev_private; 931 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 932 int rc; 933 934 bp->rx_queues = (void *)eth_dev->data->rx_queues; 935 bp->tx_queues = (void *)eth_dev->data->tx_queues; 936 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 937 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 938 939 rc = is_bnxt_in_error(bp); 940 if (rc) 941 return rc; 942 943 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 944 rc = bnxt_hwrm_check_vf_rings(bp); 945 if (rc) { 946 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 947 return -ENOSPC; 948 } 949 950 /* If a resource has already been allocated - in this case 951 * it is the async completion ring, free it. Reallocate it after 952 * resource reservation. This will ensure the resource counts 953 * are calculated correctly. 954 */ 955 956 pthread_mutex_lock(&bp->def_cp_lock); 957 958 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 959 bnxt_disable_int(bp); 960 bnxt_free_cp_ring(bp, bp->async_cp_ring); 961 } 962 963 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 964 if (rc) { 965 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 966 pthread_mutex_unlock(&bp->def_cp_lock); 967 return -ENOSPC; 968 } 969 970 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 971 rc = bnxt_alloc_async_cp_ring(bp); 972 if (rc) { 973 pthread_mutex_unlock(&bp->def_cp_lock); 974 return rc; 975 } 976 bnxt_enable_int(bp); 977 } 978 979 pthread_mutex_unlock(&bp->def_cp_lock); 980 } else { 981 /* legacy driver needs to get updated values */ 982 rc = bnxt_hwrm_func_qcaps(bp); 983 if (rc) { 984 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc); 985 return rc; 986 } 987 } 988 989 /* Inherit new configurations */ 990 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 991 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 992 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 993 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 994 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 995 bp->max_stat_ctx) 996 goto resource_error; 997 998 if (BNXT_HAS_RING_GRPS(bp) && 999 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 1000 goto resource_error; 1001 1002 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 1003 bp->max_vnics < eth_dev->data->nb_rx_queues) 1004 goto resource_error; 1005 1006 bp->rx_cp_nr_rings = bp->rx_nr_rings; 1007 bp->tx_cp_nr_rings = bp->tx_nr_rings; 1008 1009 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1010 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1011 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 1012 1013 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1014 eth_dev->data->mtu = 1015 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1016 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 1017 BNXT_NUM_VLANS; 1018 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 1019 } 1020 return 0; 1021 1022 resource_error: 1023 PMD_DRV_LOG(ERR, 1024 "Insufficient resources to support requested config\n"); 1025 PMD_DRV_LOG(ERR, 1026 "Num Queues Requested: Tx %d, Rx %d\n", 1027 eth_dev->data->nb_tx_queues, 1028 eth_dev->data->nb_rx_queues); 1029 PMD_DRV_LOG(ERR, 1030 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 1031 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 1032 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 1033 return -ENOSPC; 1034 } 1035 1036 void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 1037 { 1038 struct rte_eth_link *link = ð_dev->data->dev_link; 1039 1040 if (link->link_status) 1041 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 1042 eth_dev->data->port_id, 1043 (uint32_t)link->link_speed, 1044 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 1045 ("full-duplex") : ("half-duplex\n")); 1046 else 1047 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 1048 eth_dev->data->port_id); 1049 } 1050 1051 /* 1052 * Determine whether the current configuration requires support for scattered 1053 * receive; return 1 if scattered receive is required and 0 if not. 1054 */ 1055 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 1056 { 1057 uint16_t buf_size; 1058 int i; 1059 1060 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 1061 return 1; 1062 1063 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 1064 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 1065 1066 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1067 RTE_PKTMBUF_HEADROOM); 1068 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 1069 return 1; 1070 } 1071 return 0; 1072 } 1073 1074 static eth_rx_burst_t 1075 bnxt_receive_function(struct rte_eth_dev *eth_dev) 1076 { 1077 struct bnxt *bp = eth_dev->data->dev_private; 1078 1079 #ifdef RTE_ARCH_X86 1080 #ifndef RTE_LIBRTE_IEEE1588 1081 /* 1082 * Vector mode receive can be enabled only if scatter rx is not 1083 * in use and rx offloads are limited to VLAN stripping and 1084 * CRC stripping. 1085 */ 1086 if (!eth_dev->data->scattered_rx && 1087 !(eth_dev->data->dev_conf.rxmode.offloads & 1088 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 1089 DEV_RX_OFFLOAD_KEEP_CRC | 1090 DEV_RX_OFFLOAD_JUMBO_FRAME | 1091 DEV_RX_OFFLOAD_IPV4_CKSUM | 1092 DEV_RX_OFFLOAD_UDP_CKSUM | 1093 DEV_RX_OFFLOAD_TCP_CKSUM | 1094 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1095 DEV_RX_OFFLOAD_RSS_HASH | 1096 DEV_RX_OFFLOAD_VLAN_FILTER)) && 1097 !BNXT_TRUFLOW_EN(bp)) { 1098 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 1099 eth_dev->data->port_id); 1100 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1101 return bnxt_recv_pkts_vec; 1102 } 1103 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 1104 eth_dev->data->port_id); 1105 PMD_DRV_LOG(INFO, 1106 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 1107 eth_dev->data->port_id, 1108 eth_dev->data->scattered_rx, 1109 eth_dev->data->dev_conf.rxmode.offloads); 1110 #endif 1111 #endif 1112 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1113 return bnxt_recv_pkts; 1114 } 1115 1116 static eth_tx_burst_t 1117 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) 1118 { 1119 #ifdef RTE_ARCH_X86 1120 #ifndef RTE_LIBRTE_IEEE1588 1121 struct bnxt *bp = eth_dev->data->dev_private; 1122 1123 /* 1124 * Vector mode transmit can be enabled only if not using scatter rx 1125 * or tx offloads. 1126 */ 1127 if (!eth_dev->data->scattered_rx && 1128 !eth_dev->data->dev_conf.txmode.offloads && 1129 !BNXT_TRUFLOW_EN(bp)) { 1130 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 1131 eth_dev->data->port_id); 1132 return bnxt_xmit_pkts_vec; 1133 } 1134 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 1135 eth_dev->data->port_id); 1136 PMD_DRV_LOG(INFO, 1137 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 1138 eth_dev->data->port_id, 1139 eth_dev->data->scattered_rx, 1140 eth_dev->data->dev_conf.txmode.offloads); 1141 #endif 1142 #endif 1143 return bnxt_xmit_pkts; 1144 } 1145 1146 static int bnxt_handle_if_change_status(struct bnxt *bp) 1147 { 1148 int rc; 1149 1150 /* Since fw has undergone a reset and lost all contexts, 1151 * set fatal flag to not issue hwrm during cleanup 1152 */ 1153 bp->flags |= BNXT_FLAG_FATAL_ERROR; 1154 bnxt_uninit_resources(bp, true); 1155 1156 /* clear fatal flag so that re-init happens */ 1157 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 1158 rc = bnxt_init_resources(bp, true); 1159 1160 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 1161 1162 return rc; 1163 } 1164 1165 static int32_t 1166 bnxt_create_port_app_df_rule(struct bnxt *bp, uint8_t flow_type, 1167 uint32_t *flow_id) 1168 { 1169 uint16_t port_id = bp->eth_dev->data->port_id; 1170 struct ulp_tlv_param param_list[] = { 1171 { 1172 .type = BNXT_ULP_DF_PARAM_TYPE_DEV_PORT_ID, 1173 .length = 2, 1174 .value = {(port_id >> 8) & 0xff, port_id & 0xff} 1175 }, 1176 { 1177 .type = BNXT_ULP_DF_PARAM_TYPE_LAST, 1178 .length = 0, 1179 .value = {0} 1180 } 1181 }; 1182 1183 return ulp_default_flow_create(bp->eth_dev, param_list, flow_type, 1184 flow_id); 1185 } 1186 1187 static int32_t 1188 bnxt_create_df_rules(struct bnxt *bp) 1189 { 1190 struct bnxt_ulp_data *cfg_data; 1191 int rc; 1192 1193 cfg_data = bp->ulp_ctx->cfg_data; 1194 rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_PORT_TO_VS, 1195 &cfg_data->port_to_app_flow_id); 1196 if (rc) { 1197 PMD_DRV_LOG(ERR, 1198 "Failed to create port to app default rule\n"); 1199 return rc; 1200 } 1201 1202 BNXT_TF_DBG(DEBUG, "***** created port to app default rule ******\n"); 1203 rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_VS_TO_PORT, 1204 &cfg_data->app_to_port_flow_id); 1205 if (!rc) { 1206 rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx, 1207 cfg_data->app_to_port_flow_id, 1208 &cfg_data->tx_cfa_action); 1209 if (rc) 1210 goto err; 1211 1212 BNXT_TF_DBG(DEBUG, 1213 "***** created app to port default rule *****\n"); 1214 return 0; 1215 } 1216 1217 err: 1218 BNXT_TF_DBG(DEBUG, "Failed to create app to port default rule\n"); 1219 return rc; 1220 } 1221 1222 static void 1223 bnxt_destroy_df_rules(struct bnxt *bp) 1224 { 1225 struct bnxt_ulp_data *cfg_data; 1226 1227 cfg_data = bp->ulp_ctx->cfg_data; 1228 ulp_default_flow_destroy(bp->eth_dev, cfg_data->port_to_app_flow_id); 1229 ulp_default_flow_destroy(bp->eth_dev, cfg_data->app_to_port_flow_id); 1230 } 1231 1232 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 1233 { 1234 struct bnxt *bp = eth_dev->data->dev_private; 1235 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1236 int vlan_mask = 0; 1237 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; 1238 1239 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 1240 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 1241 return -EINVAL; 1242 } 1243 1244 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) { 1245 PMD_DRV_LOG(ERR, 1246 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 1247 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1248 } 1249 1250 do { 1251 rc = bnxt_hwrm_if_change(bp, true); 1252 if (rc == 0 || rc != -EAGAIN) 1253 break; 1254 1255 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); 1256 } while (retry_cnt--); 1257 1258 if (rc) 1259 return rc; 1260 1261 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 1262 rc = bnxt_handle_if_change_status(bp); 1263 if (rc) 1264 return rc; 1265 } 1266 1267 bnxt_enable_int(bp); 1268 1269 rc = bnxt_init_chip(bp); 1270 if (rc) 1271 goto error; 1272 1273 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 1274 eth_dev->data->dev_started = 1; 1275 1276 bnxt_link_update(eth_dev, 1, ETH_LINK_UP); 1277 1278 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1279 vlan_mask |= ETH_VLAN_FILTER_MASK; 1280 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1281 vlan_mask |= ETH_VLAN_STRIP_MASK; 1282 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 1283 if (rc) 1284 goto error; 1285 1286 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 1287 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 1288 1289 pthread_mutex_lock(&bp->def_cp_lock); 1290 bnxt_schedule_fw_health_check(bp); 1291 pthread_mutex_unlock(&bp->def_cp_lock); 1292 1293 if (BNXT_TRUFLOW_EN(bp)) 1294 bnxt_ulp_init(bp); 1295 1296 return 0; 1297 1298 error: 1299 bnxt_shutdown_nic(bp); 1300 bnxt_free_tx_mbufs(bp); 1301 bnxt_free_rx_mbufs(bp); 1302 bnxt_hwrm_if_change(bp, false); 1303 eth_dev->data->dev_started = 0; 1304 return rc; 1305 } 1306 1307 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 1308 { 1309 struct bnxt *bp = eth_dev->data->dev_private; 1310 int rc = 0; 1311 1312 if (!bp->link_info->link_up) 1313 rc = bnxt_set_hwrm_link_config(bp, true); 1314 if (!rc) 1315 eth_dev->data->dev_link.link_status = 1; 1316 1317 bnxt_print_link_info(eth_dev); 1318 return rc; 1319 } 1320 1321 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 1322 { 1323 struct bnxt *bp = eth_dev->data->dev_private; 1324 1325 eth_dev->data->dev_link.link_status = 0; 1326 bnxt_set_hwrm_link_config(bp, false); 1327 bp->link_info->link_up = 0; 1328 1329 return 0; 1330 } 1331 1332 static void bnxt_free_switch_domain(struct bnxt *bp) 1333 { 1334 if (bp->switch_domain_id) 1335 rte_eth_switch_domain_free(bp->switch_domain_id); 1336 } 1337 1338 /* Unload the driver, release resources */ 1339 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 1340 { 1341 struct bnxt *bp = eth_dev->data->dev_private; 1342 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1343 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1344 1345 eth_dev->data->dev_started = 0; 1346 /* Prevent crashes when queues are still in use */ 1347 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 1348 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 1349 1350 bnxt_disable_int(bp); 1351 1352 /* disable uio/vfio intr/eventfd mapping */ 1353 rte_intr_disable(intr_handle); 1354 1355 bnxt_cancel_fw_health_check(bp); 1356 1357 bnxt_dev_set_link_down_op(eth_dev); 1358 1359 /* Wait for link to be reset and the async notification to process. 1360 * During reset recovery, there is no need to wait and 1361 * VF/NPAR functions do not have privilege to change PHY config. 1362 */ 1363 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp)) 1364 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN); 1365 1366 /* Clean queue intr-vector mapping */ 1367 rte_intr_efd_disable(intr_handle); 1368 if (intr_handle->intr_vec != NULL) { 1369 rte_free(intr_handle->intr_vec); 1370 intr_handle->intr_vec = NULL; 1371 } 1372 1373 bnxt_hwrm_port_clr_stats(bp); 1374 bnxt_free_tx_mbufs(bp); 1375 bnxt_free_rx_mbufs(bp); 1376 /* Process any remaining notifications in default completion queue */ 1377 bnxt_int_handler(eth_dev); 1378 bnxt_shutdown_nic(bp); 1379 bnxt_hwrm_if_change(bp, false); 1380 1381 rte_free(bp->mark_table); 1382 bp->mark_table = NULL; 1383 1384 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1385 bp->rx_cosq_cnt = 0; 1386 /* All filters are deleted on a port stop. */ 1387 if (BNXT_FLOW_XSTATS_EN(bp)) 1388 bp->flow_stat->flow_count = 0; 1389 } 1390 1391 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 1392 { 1393 struct bnxt *bp = eth_dev->data->dev_private; 1394 1395 /* cancel the recovery handler before remove dev */ 1396 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); 1397 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); 1398 bnxt_cancel_fc_thread(bp); 1399 1400 if (BNXT_TRUFLOW_EN(bp)) { 1401 if (bp->rep_info != NULL) 1402 bnxt_destroy_df_rules(bp); 1403 bnxt_ulp_deinit(bp); 1404 } 1405 1406 if (eth_dev->data->dev_started) 1407 bnxt_dev_stop_op(eth_dev); 1408 1409 bnxt_free_switch_domain(bp); 1410 1411 bnxt_uninit_resources(bp, false); 1412 1413 bnxt_free_leds_info(bp); 1414 bnxt_free_cos_queues(bp); 1415 bnxt_free_link_info(bp); 1416 bnxt_free_pf_info(bp); 1417 bnxt_free_parent_info(bp); 1418 1419 eth_dev->dev_ops = NULL; 1420 eth_dev->rx_pkt_burst = NULL; 1421 eth_dev->tx_pkt_burst = NULL; 1422 1423 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 1424 bp->tx_mem_zone = NULL; 1425 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 1426 bp->rx_mem_zone = NULL; 1427 1428 rte_free(bp->pf->vf_info); 1429 bp->pf->vf_info = NULL; 1430 1431 rte_free(bp->grp_info); 1432 bp->grp_info = NULL; 1433 } 1434 1435 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1436 uint32_t index) 1437 { 1438 struct bnxt *bp = eth_dev->data->dev_private; 1439 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1440 struct bnxt_vnic_info *vnic; 1441 struct bnxt_filter_info *filter, *temp_filter; 1442 uint32_t i; 1443 1444 if (is_bnxt_in_error(bp)) 1445 return; 1446 1447 /* 1448 * Loop through all VNICs from the specified filter flow pools to 1449 * remove the corresponding MAC addr filter 1450 */ 1451 for (i = 0; i < bp->nr_vnics; i++) { 1452 if (!(pool_mask & (1ULL << i))) 1453 continue; 1454 1455 vnic = &bp->vnic_info[i]; 1456 filter = STAILQ_FIRST(&vnic->filter); 1457 while (filter) { 1458 temp_filter = STAILQ_NEXT(filter, next); 1459 if (filter->mac_index == index) { 1460 STAILQ_REMOVE(&vnic->filter, filter, 1461 bnxt_filter_info, next); 1462 bnxt_hwrm_clear_l2_filter(bp, filter); 1463 bnxt_free_filter(bp, filter); 1464 } 1465 filter = temp_filter; 1466 } 1467 } 1468 } 1469 1470 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1471 struct rte_ether_addr *mac_addr, uint32_t index, 1472 uint32_t pool) 1473 { 1474 struct bnxt_filter_info *filter; 1475 int rc = 0; 1476 1477 /* Attach requested MAC address to the new l2_filter */ 1478 STAILQ_FOREACH(filter, &vnic->filter, next) { 1479 if (filter->mac_index == index) { 1480 PMD_DRV_LOG(DEBUG, 1481 "MAC addr already existed for pool %d\n", 1482 pool); 1483 return 0; 1484 } 1485 } 1486 1487 filter = bnxt_alloc_filter(bp); 1488 if (!filter) { 1489 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1490 return -ENODEV; 1491 } 1492 1493 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1494 * if the MAC that's been programmed now is a different one, then, 1495 * copy that addr to filter->l2_addr 1496 */ 1497 if (mac_addr) 1498 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1499 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1500 1501 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1502 if (!rc) { 1503 filter->mac_index = index; 1504 if (filter->mac_index == 0) 1505 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1506 else 1507 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1508 } else { 1509 bnxt_free_filter(bp, filter); 1510 } 1511 1512 return rc; 1513 } 1514 1515 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1516 struct rte_ether_addr *mac_addr, 1517 uint32_t index, uint32_t pool) 1518 { 1519 struct bnxt *bp = eth_dev->data->dev_private; 1520 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1521 int rc = 0; 1522 1523 rc = is_bnxt_in_error(bp); 1524 if (rc) 1525 return rc; 1526 1527 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) { 1528 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1529 return -ENOTSUP; 1530 } 1531 1532 if (!vnic) { 1533 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1534 return -EINVAL; 1535 } 1536 1537 /* Filter settings will get applied when port is started */ 1538 if (!eth_dev->data->dev_started) 1539 return 0; 1540 1541 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1542 1543 return rc; 1544 } 1545 1546 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 1547 bool exp_link_status) 1548 { 1549 int rc = 0; 1550 struct bnxt *bp = eth_dev->data->dev_private; 1551 struct rte_eth_link new; 1552 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT : 1553 BNXT_LINK_DOWN_WAIT_CNT; 1554 1555 rc = is_bnxt_in_error(bp); 1556 if (rc) 1557 return rc; 1558 1559 memset(&new, 0, sizeof(new)); 1560 do { 1561 /* Retrieve link info from hardware */ 1562 rc = bnxt_get_hwrm_link_config(bp, &new); 1563 if (rc) { 1564 new.link_speed = ETH_LINK_SPEED_100M; 1565 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1566 PMD_DRV_LOG(ERR, 1567 "Failed to retrieve link rc = 0x%x!\n", rc); 1568 goto out; 1569 } 1570 1571 if (!wait_to_complete || new.link_status == exp_link_status) 1572 break; 1573 1574 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1575 } while (cnt--); 1576 1577 out: 1578 /* Timed out or success */ 1579 if (new.link_status != eth_dev->data->dev_link.link_status || 1580 new.link_speed != eth_dev->data->dev_link.link_speed) { 1581 rte_eth_linkstatus_set(eth_dev, &new); 1582 1583 _rte_eth_dev_callback_process(eth_dev, 1584 RTE_ETH_EVENT_INTR_LSC, 1585 NULL); 1586 1587 bnxt_print_link_info(eth_dev); 1588 } 1589 1590 return rc; 1591 } 1592 1593 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 1594 int wait_to_complete) 1595 { 1596 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP); 1597 } 1598 1599 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1600 { 1601 struct bnxt *bp = eth_dev->data->dev_private; 1602 struct bnxt_vnic_info *vnic; 1603 uint32_t old_flags; 1604 int rc; 1605 1606 rc = is_bnxt_in_error(bp); 1607 if (rc) 1608 return rc; 1609 1610 /* Filter settings will get applied when port is started */ 1611 if (!eth_dev->data->dev_started) 1612 return 0; 1613 1614 if (bp->vnic_info == NULL) 1615 return 0; 1616 1617 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1618 1619 old_flags = vnic->flags; 1620 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1621 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1622 if (rc != 0) 1623 vnic->flags = old_flags; 1624 1625 return rc; 1626 } 1627 1628 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1629 { 1630 struct bnxt *bp = eth_dev->data->dev_private; 1631 struct bnxt_vnic_info *vnic; 1632 uint32_t old_flags; 1633 int rc; 1634 1635 rc = is_bnxt_in_error(bp); 1636 if (rc) 1637 return rc; 1638 1639 /* Filter settings will get applied when port is started */ 1640 if (!eth_dev->data->dev_started) 1641 return 0; 1642 1643 if (bp->vnic_info == NULL) 1644 return 0; 1645 1646 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1647 1648 old_flags = vnic->flags; 1649 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1650 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1651 if (rc != 0) 1652 vnic->flags = old_flags; 1653 1654 if (BNXT_TRUFLOW_EN(bp) && bp->rep_info != NULL) 1655 bnxt_create_df_rules(bp); 1656 1657 return rc; 1658 } 1659 1660 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1661 { 1662 struct bnxt *bp = eth_dev->data->dev_private; 1663 struct bnxt_vnic_info *vnic; 1664 uint32_t old_flags; 1665 int rc; 1666 1667 rc = is_bnxt_in_error(bp); 1668 if (rc) 1669 return rc; 1670 1671 /* Filter settings will get applied when port is started */ 1672 if (!eth_dev->data->dev_started) 1673 return 0; 1674 1675 if (bp->vnic_info == NULL) 1676 return 0; 1677 1678 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1679 1680 old_flags = vnic->flags; 1681 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1682 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1683 if (rc != 0) 1684 vnic->flags = old_flags; 1685 1686 return rc; 1687 } 1688 1689 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1690 { 1691 struct bnxt *bp = eth_dev->data->dev_private; 1692 struct bnxt_vnic_info *vnic; 1693 uint32_t old_flags; 1694 int rc; 1695 1696 rc = is_bnxt_in_error(bp); 1697 if (rc) 1698 return rc; 1699 1700 /* Filter settings will get applied when port is started */ 1701 if (!eth_dev->data->dev_started) 1702 return 0; 1703 1704 if (bp->vnic_info == NULL) 1705 return 0; 1706 1707 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1708 1709 old_flags = vnic->flags; 1710 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1711 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1712 if (rc != 0) 1713 vnic->flags = old_flags; 1714 1715 return rc; 1716 } 1717 1718 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1719 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1720 { 1721 if (qid >= bp->rx_nr_rings) 1722 return NULL; 1723 1724 return bp->eth_dev->data->rx_queues[qid]; 1725 } 1726 1727 /* Return rxq corresponding to a given rss table ring/group ID. */ 1728 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1729 { 1730 struct bnxt_rx_queue *rxq; 1731 unsigned int i; 1732 1733 if (!BNXT_HAS_RING_GRPS(bp)) { 1734 for (i = 0; i < bp->rx_nr_rings; i++) { 1735 rxq = bp->eth_dev->data->rx_queues[i]; 1736 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1737 return rxq->index; 1738 } 1739 } else { 1740 for (i = 0; i < bp->rx_nr_rings; i++) { 1741 if (bp->grp_info[i].fw_grp_id == fwr) 1742 return i; 1743 } 1744 } 1745 1746 return INVALID_HW_RING_ID; 1747 } 1748 1749 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1750 struct rte_eth_rss_reta_entry64 *reta_conf, 1751 uint16_t reta_size) 1752 { 1753 struct bnxt *bp = eth_dev->data->dev_private; 1754 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1755 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1756 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1757 uint16_t idx, sft; 1758 int i, rc; 1759 1760 rc = is_bnxt_in_error(bp); 1761 if (rc) 1762 return rc; 1763 1764 if (!vnic->rss_table) 1765 return -EINVAL; 1766 1767 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1768 return -EINVAL; 1769 1770 if (reta_size != tbl_size) { 1771 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1772 "(%d) must equal the size supported by the hardware " 1773 "(%d)\n", reta_size, tbl_size); 1774 return -EINVAL; 1775 } 1776 1777 for (i = 0; i < reta_size; i++) { 1778 struct bnxt_rx_queue *rxq; 1779 1780 idx = i / RTE_RETA_GROUP_SIZE; 1781 sft = i % RTE_RETA_GROUP_SIZE; 1782 1783 if (!(reta_conf[idx].mask & (1ULL << sft))) 1784 continue; 1785 1786 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1787 if (!rxq) { 1788 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1789 return -EINVAL; 1790 } 1791 1792 if (BNXT_CHIP_THOR(bp)) { 1793 vnic->rss_table[i * 2] = 1794 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1795 vnic->rss_table[i * 2 + 1] = 1796 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1797 } else { 1798 vnic->rss_table[i] = 1799 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1800 } 1801 } 1802 1803 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1804 return 0; 1805 } 1806 1807 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1808 struct rte_eth_rss_reta_entry64 *reta_conf, 1809 uint16_t reta_size) 1810 { 1811 struct bnxt *bp = eth_dev->data->dev_private; 1812 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1813 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1814 uint16_t idx, sft, i; 1815 int rc; 1816 1817 rc = is_bnxt_in_error(bp); 1818 if (rc) 1819 return rc; 1820 1821 /* Retrieve from the default VNIC */ 1822 if (!vnic) 1823 return -EINVAL; 1824 if (!vnic->rss_table) 1825 return -EINVAL; 1826 1827 if (reta_size != tbl_size) { 1828 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1829 "(%d) must equal the size supported by the hardware " 1830 "(%d)\n", reta_size, tbl_size); 1831 return -EINVAL; 1832 } 1833 1834 for (idx = 0, i = 0; i < reta_size; i++) { 1835 idx = i / RTE_RETA_GROUP_SIZE; 1836 sft = i % RTE_RETA_GROUP_SIZE; 1837 1838 if (reta_conf[idx].mask & (1ULL << sft)) { 1839 uint16_t qid; 1840 1841 if (BNXT_CHIP_THOR(bp)) 1842 qid = bnxt_rss_to_qid(bp, 1843 vnic->rss_table[i * 2]); 1844 else 1845 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 1846 1847 if (qid == INVALID_HW_RING_ID) { 1848 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 1849 return -EINVAL; 1850 } 1851 reta_conf[idx].reta[sft] = qid; 1852 } 1853 } 1854 1855 return 0; 1856 } 1857 1858 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 1859 struct rte_eth_rss_conf *rss_conf) 1860 { 1861 struct bnxt *bp = eth_dev->data->dev_private; 1862 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1863 struct bnxt_vnic_info *vnic; 1864 int rc; 1865 1866 rc = is_bnxt_in_error(bp); 1867 if (rc) 1868 return rc; 1869 1870 /* 1871 * If RSS enablement were different than dev_configure, 1872 * then return -EINVAL 1873 */ 1874 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 1875 if (!rss_conf->rss_hf) 1876 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 1877 } else { 1878 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 1879 return -EINVAL; 1880 } 1881 1882 bp->flags |= BNXT_FLAG_UPDATE_HASH; 1883 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf, 1884 rss_conf, 1885 sizeof(*rss_conf)); 1886 1887 /* Update the default RSS VNIC(s) */ 1888 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1889 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 1890 1891 /* 1892 * If hashkey is not specified, use the previously configured 1893 * hashkey 1894 */ 1895 if (!rss_conf->rss_key) 1896 goto rss_config; 1897 1898 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 1899 PMD_DRV_LOG(ERR, 1900 "Invalid hashkey length, should be 16 bytes\n"); 1901 return -EINVAL; 1902 } 1903 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 1904 1905 rss_config: 1906 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1907 return 0; 1908 } 1909 1910 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 1911 struct rte_eth_rss_conf *rss_conf) 1912 { 1913 struct bnxt *bp = eth_dev->data->dev_private; 1914 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1915 int len, rc; 1916 uint32_t hash_types; 1917 1918 rc = is_bnxt_in_error(bp); 1919 if (rc) 1920 return rc; 1921 1922 /* RSS configuration is the same for all VNICs */ 1923 if (vnic && vnic->rss_hash_key) { 1924 if (rss_conf->rss_key) { 1925 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 1926 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 1927 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 1928 } 1929 1930 hash_types = vnic->hash_type; 1931 rss_conf->rss_hf = 0; 1932 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 1933 rss_conf->rss_hf |= ETH_RSS_IPV4; 1934 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 1935 } 1936 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 1937 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 1938 hash_types &= 1939 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1940 } 1941 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 1942 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 1943 hash_types &= 1944 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1945 } 1946 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 1947 rss_conf->rss_hf |= ETH_RSS_IPV6; 1948 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1949 } 1950 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 1951 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 1952 hash_types &= 1953 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1954 } 1955 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 1956 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 1957 hash_types &= 1958 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1959 } 1960 if (hash_types) { 1961 PMD_DRV_LOG(ERR, 1962 "Unknown RSS config from firmware (%08x), RSS disabled", 1963 vnic->hash_type); 1964 return -ENOTSUP; 1965 } 1966 } else { 1967 rss_conf->rss_hf = 0; 1968 } 1969 return 0; 1970 } 1971 1972 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 1973 struct rte_eth_fc_conf *fc_conf) 1974 { 1975 struct bnxt *bp = dev->data->dev_private; 1976 struct rte_eth_link link_info; 1977 int rc; 1978 1979 rc = is_bnxt_in_error(bp); 1980 if (rc) 1981 return rc; 1982 1983 rc = bnxt_get_hwrm_link_config(bp, &link_info); 1984 if (rc) 1985 return rc; 1986 1987 memset(fc_conf, 0, sizeof(*fc_conf)); 1988 if (bp->link_info->auto_pause) 1989 fc_conf->autoneg = 1; 1990 switch (bp->link_info->pause) { 1991 case 0: 1992 fc_conf->mode = RTE_FC_NONE; 1993 break; 1994 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 1995 fc_conf->mode = RTE_FC_TX_PAUSE; 1996 break; 1997 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 1998 fc_conf->mode = RTE_FC_RX_PAUSE; 1999 break; 2000 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 2001 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 2002 fc_conf->mode = RTE_FC_FULL; 2003 break; 2004 } 2005 return 0; 2006 } 2007 2008 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 2009 struct rte_eth_fc_conf *fc_conf) 2010 { 2011 struct bnxt *bp = dev->data->dev_private; 2012 int rc; 2013 2014 rc = is_bnxt_in_error(bp); 2015 if (rc) 2016 return rc; 2017 2018 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2019 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 2020 return -ENOTSUP; 2021 } 2022 2023 switch (fc_conf->mode) { 2024 case RTE_FC_NONE: 2025 bp->link_info->auto_pause = 0; 2026 bp->link_info->force_pause = 0; 2027 break; 2028 case RTE_FC_RX_PAUSE: 2029 if (fc_conf->autoneg) { 2030 bp->link_info->auto_pause = 2031 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2032 bp->link_info->force_pause = 0; 2033 } else { 2034 bp->link_info->auto_pause = 0; 2035 bp->link_info->force_pause = 2036 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2037 } 2038 break; 2039 case RTE_FC_TX_PAUSE: 2040 if (fc_conf->autoneg) { 2041 bp->link_info->auto_pause = 2042 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 2043 bp->link_info->force_pause = 0; 2044 } else { 2045 bp->link_info->auto_pause = 0; 2046 bp->link_info->force_pause = 2047 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 2048 } 2049 break; 2050 case RTE_FC_FULL: 2051 if (fc_conf->autoneg) { 2052 bp->link_info->auto_pause = 2053 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 2054 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2055 bp->link_info->force_pause = 0; 2056 } else { 2057 bp->link_info->auto_pause = 0; 2058 bp->link_info->force_pause = 2059 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 2060 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2061 } 2062 break; 2063 } 2064 return bnxt_set_hwrm_link_config(bp, true); 2065 } 2066 2067 /* Add UDP tunneling port */ 2068 static int 2069 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 2070 struct rte_eth_udp_tunnel *udp_tunnel) 2071 { 2072 struct bnxt *bp = eth_dev->data->dev_private; 2073 uint16_t tunnel_type = 0; 2074 int rc = 0; 2075 2076 rc = is_bnxt_in_error(bp); 2077 if (rc) 2078 return rc; 2079 2080 switch (udp_tunnel->prot_type) { 2081 case RTE_TUNNEL_TYPE_VXLAN: 2082 if (bp->vxlan_port_cnt) { 2083 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2084 udp_tunnel->udp_port); 2085 if (bp->vxlan_port != udp_tunnel->udp_port) { 2086 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2087 return -ENOSPC; 2088 } 2089 bp->vxlan_port_cnt++; 2090 return 0; 2091 } 2092 tunnel_type = 2093 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 2094 bp->vxlan_port_cnt++; 2095 break; 2096 case RTE_TUNNEL_TYPE_GENEVE: 2097 if (bp->geneve_port_cnt) { 2098 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2099 udp_tunnel->udp_port); 2100 if (bp->geneve_port != udp_tunnel->udp_port) { 2101 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2102 return -ENOSPC; 2103 } 2104 bp->geneve_port_cnt++; 2105 return 0; 2106 } 2107 tunnel_type = 2108 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 2109 bp->geneve_port_cnt++; 2110 break; 2111 default: 2112 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2113 return -ENOTSUP; 2114 } 2115 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 2116 tunnel_type); 2117 return rc; 2118 } 2119 2120 static int 2121 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 2122 struct rte_eth_udp_tunnel *udp_tunnel) 2123 { 2124 struct bnxt *bp = eth_dev->data->dev_private; 2125 uint16_t tunnel_type = 0; 2126 uint16_t port = 0; 2127 int rc = 0; 2128 2129 rc = is_bnxt_in_error(bp); 2130 if (rc) 2131 return rc; 2132 2133 switch (udp_tunnel->prot_type) { 2134 case RTE_TUNNEL_TYPE_VXLAN: 2135 if (!bp->vxlan_port_cnt) { 2136 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2137 return -EINVAL; 2138 } 2139 if (bp->vxlan_port != udp_tunnel->udp_port) { 2140 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2141 udp_tunnel->udp_port, bp->vxlan_port); 2142 return -EINVAL; 2143 } 2144 if (--bp->vxlan_port_cnt) 2145 return 0; 2146 2147 tunnel_type = 2148 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 2149 port = bp->vxlan_fw_dst_port_id; 2150 break; 2151 case RTE_TUNNEL_TYPE_GENEVE: 2152 if (!bp->geneve_port_cnt) { 2153 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2154 return -EINVAL; 2155 } 2156 if (bp->geneve_port != udp_tunnel->udp_port) { 2157 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2158 udp_tunnel->udp_port, bp->geneve_port); 2159 return -EINVAL; 2160 } 2161 if (--bp->geneve_port_cnt) 2162 return 0; 2163 2164 tunnel_type = 2165 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 2166 port = bp->geneve_fw_dst_port_id; 2167 break; 2168 default: 2169 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2170 return -ENOTSUP; 2171 } 2172 2173 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 2174 if (!rc) { 2175 if (tunnel_type == 2176 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) 2177 bp->vxlan_port = 0; 2178 if (tunnel_type == 2179 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) 2180 bp->geneve_port = 0; 2181 } 2182 return rc; 2183 } 2184 2185 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2186 { 2187 struct bnxt_filter_info *filter; 2188 struct bnxt_vnic_info *vnic; 2189 int rc = 0; 2190 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2191 2192 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2193 filter = STAILQ_FIRST(&vnic->filter); 2194 while (filter) { 2195 /* Search for this matching MAC+VLAN filter */ 2196 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 2197 /* Delete the filter */ 2198 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2199 if (rc) 2200 return rc; 2201 STAILQ_REMOVE(&vnic->filter, filter, 2202 bnxt_filter_info, next); 2203 bnxt_free_filter(bp, filter); 2204 PMD_DRV_LOG(INFO, 2205 "Deleted vlan filter for %d\n", 2206 vlan_id); 2207 return 0; 2208 } 2209 filter = STAILQ_NEXT(filter, next); 2210 } 2211 return -ENOENT; 2212 } 2213 2214 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2215 { 2216 struct bnxt_filter_info *filter; 2217 struct bnxt_vnic_info *vnic; 2218 int rc = 0; 2219 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 2220 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 2221 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2222 2223 /* Implementation notes on the use of VNIC in this command: 2224 * 2225 * By default, these filters belong to default vnic for the function. 2226 * Once these filters are set up, only destination VNIC can be modified. 2227 * If the destination VNIC is not specified in this command, 2228 * then the HWRM shall only create an l2 context id. 2229 */ 2230 2231 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2232 filter = STAILQ_FIRST(&vnic->filter); 2233 /* Check if the VLAN has already been added */ 2234 while (filter) { 2235 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 2236 return -EEXIST; 2237 2238 filter = STAILQ_NEXT(filter, next); 2239 } 2240 2241 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 2242 * command to create MAC+VLAN filter with the right flags, enables set. 2243 */ 2244 filter = bnxt_alloc_filter(bp); 2245 if (!filter) { 2246 PMD_DRV_LOG(ERR, 2247 "MAC/VLAN filter alloc failed\n"); 2248 return -ENOMEM; 2249 } 2250 /* MAC + VLAN ID filter */ 2251 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 2252 * untagged packets are received 2253 * 2254 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 2255 * packets and only the programmed vlan's packets are received 2256 */ 2257 filter->l2_ivlan = vlan_id; 2258 filter->l2_ivlan_mask = 0x0FFF; 2259 filter->enables |= en; 2260 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2261 2262 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2263 if (rc) { 2264 /* Free the newly allocated filter as we were 2265 * not able to create the filter in hardware. 2266 */ 2267 bnxt_free_filter(bp, filter); 2268 return rc; 2269 } 2270 2271 filter->mac_index = 0; 2272 /* Add this new filter to the list */ 2273 if (vlan_id == 0) 2274 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 2275 else 2276 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2277 2278 PMD_DRV_LOG(INFO, 2279 "Added Vlan filter for %d\n", vlan_id); 2280 return rc; 2281 } 2282 2283 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 2284 uint16_t vlan_id, int on) 2285 { 2286 struct bnxt *bp = eth_dev->data->dev_private; 2287 int rc; 2288 2289 rc = is_bnxt_in_error(bp); 2290 if (rc) 2291 return rc; 2292 2293 if (!eth_dev->data->dev_started) { 2294 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n"); 2295 return -EINVAL; 2296 } 2297 2298 /* These operations apply to ALL existing MAC/VLAN filters */ 2299 if (on) 2300 return bnxt_add_vlan_filter(bp, vlan_id); 2301 else 2302 return bnxt_del_vlan_filter(bp, vlan_id); 2303 } 2304 2305 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 2306 struct bnxt_vnic_info *vnic) 2307 { 2308 struct bnxt_filter_info *filter; 2309 int rc; 2310 2311 filter = STAILQ_FIRST(&vnic->filter); 2312 while (filter) { 2313 if (filter->mac_index == 0 && 2314 !memcmp(filter->l2_addr, bp->mac_addr, 2315 RTE_ETHER_ADDR_LEN)) { 2316 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2317 if (!rc) { 2318 STAILQ_REMOVE(&vnic->filter, filter, 2319 bnxt_filter_info, next); 2320 bnxt_free_filter(bp, filter); 2321 } 2322 return rc; 2323 } 2324 filter = STAILQ_NEXT(filter, next); 2325 } 2326 return 0; 2327 } 2328 2329 static int 2330 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 2331 { 2332 struct bnxt_vnic_info *vnic; 2333 unsigned int i; 2334 int rc; 2335 2336 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2337 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 2338 /* Remove any VLAN filters programmed */ 2339 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2340 bnxt_del_vlan_filter(bp, i); 2341 2342 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2343 if (rc) 2344 return rc; 2345 } else { 2346 /* Default filter will allow packets that match the 2347 * dest mac. So, it has to be deleted, otherwise, we 2348 * will endup receiving vlan packets for which the 2349 * filter is not programmed, when hw-vlan-filter 2350 * configuration is ON 2351 */ 2352 bnxt_del_dflt_mac_filter(bp, vnic); 2353 /* This filter will allow only untagged packets */ 2354 bnxt_add_vlan_filter(bp, 0); 2355 } 2356 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 2357 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 2358 2359 return 0; 2360 } 2361 2362 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 2363 { 2364 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2365 unsigned int i; 2366 int rc; 2367 2368 /* Destroy vnic filters and vnic */ 2369 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2370 DEV_RX_OFFLOAD_VLAN_FILTER) { 2371 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2372 bnxt_del_vlan_filter(bp, i); 2373 } 2374 bnxt_del_dflt_mac_filter(bp, vnic); 2375 2376 rc = bnxt_hwrm_vnic_free(bp, vnic); 2377 if (rc) 2378 return rc; 2379 2380 rte_free(vnic->fw_grp_ids); 2381 vnic->fw_grp_ids = NULL; 2382 2383 vnic->rx_queue_cnt = 0; 2384 2385 return 0; 2386 } 2387 2388 static int 2389 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 2390 { 2391 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2392 int rc; 2393 2394 /* Destroy, recreate and reconfigure the default vnic */ 2395 rc = bnxt_free_one_vnic(bp, 0); 2396 if (rc) 2397 return rc; 2398 2399 /* default vnic 0 */ 2400 rc = bnxt_setup_one_vnic(bp, 0); 2401 if (rc) 2402 return rc; 2403 2404 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2405 DEV_RX_OFFLOAD_VLAN_FILTER) { 2406 rc = bnxt_add_vlan_filter(bp, 0); 2407 if (rc) 2408 return rc; 2409 rc = bnxt_restore_vlan_filters(bp); 2410 if (rc) 2411 return rc; 2412 } else { 2413 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2414 if (rc) 2415 return rc; 2416 } 2417 2418 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2419 if (rc) 2420 return rc; 2421 2422 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 2423 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 2424 2425 return rc; 2426 } 2427 2428 static int 2429 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 2430 { 2431 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 2432 struct bnxt *bp = dev->data->dev_private; 2433 int rc; 2434 2435 rc = is_bnxt_in_error(bp); 2436 if (rc) 2437 return rc; 2438 2439 /* Filter settings will get applied when port is started */ 2440 if (!dev->data->dev_started) 2441 return 0; 2442 2443 if (mask & ETH_VLAN_FILTER_MASK) { 2444 /* Enable or disable VLAN filtering */ 2445 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 2446 if (rc) 2447 return rc; 2448 } 2449 2450 if (mask & ETH_VLAN_STRIP_MASK) { 2451 /* Enable or disable VLAN stripping */ 2452 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2453 if (rc) 2454 return rc; 2455 } 2456 2457 if (mask & ETH_VLAN_EXTEND_MASK) { 2458 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2459 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2460 else 2461 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2462 } 2463 2464 return 0; 2465 } 2466 2467 static int 2468 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2469 uint16_t tpid) 2470 { 2471 struct bnxt *bp = dev->data->dev_private; 2472 int qinq = dev->data->dev_conf.rxmode.offloads & 2473 DEV_RX_OFFLOAD_VLAN_EXTEND; 2474 2475 if (vlan_type != ETH_VLAN_TYPE_INNER && 2476 vlan_type != ETH_VLAN_TYPE_OUTER) { 2477 PMD_DRV_LOG(ERR, 2478 "Unsupported vlan type."); 2479 return -EINVAL; 2480 } 2481 if (!qinq) { 2482 PMD_DRV_LOG(ERR, 2483 "QinQ not enabled. Needs to be ON as we can " 2484 "accelerate only outer vlan\n"); 2485 return -EINVAL; 2486 } 2487 2488 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 2489 switch (tpid) { 2490 case RTE_ETHER_TYPE_QINQ: 2491 bp->outer_tpid_bd = 2492 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2493 break; 2494 case RTE_ETHER_TYPE_VLAN: 2495 bp->outer_tpid_bd = 2496 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2497 break; 2498 case 0x9100: 2499 bp->outer_tpid_bd = 2500 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2501 break; 2502 case 0x9200: 2503 bp->outer_tpid_bd = 2504 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2505 break; 2506 case 0x9300: 2507 bp->outer_tpid_bd = 2508 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2509 break; 2510 default: 2511 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2512 return -EINVAL; 2513 } 2514 bp->outer_tpid_bd |= tpid; 2515 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2516 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 2517 PMD_DRV_LOG(ERR, 2518 "Can accelerate only outer vlan in QinQ\n"); 2519 return -EINVAL; 2520 } 2521 2522 return 0; 2523 } 2524 2525 static int 2526 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2527 struct rte_ether_addr *addr) 2528 { 2529 struct bnxt *bp = dev->data->dev_private; 2530 /* Default Filter is tied to VNIC 0 */ 2531 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2532 int rc; 2533 2534 rc = is_bnxt_in_error(bp); 2535 if (rc) 2536 return rc; 2537 2538 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2539 return -EPERM; 2540 2541 if (rte_is_zero_ether_addr(addr)) 2542 return -EINVAL; 2543 2544 /* Filter settings will get applied when port is started */ 2545 if (!dev->data->dev_started) 2546 return 0; 2547 2548 /* Check if the requested MAC is already added */ 2549 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2550 return 0; 2551 2552 /* Destroy filter and re-create it */ 2553 bnxt_del_dflt_mac_filter(bp, vnic); 2554 2555 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2556 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 2557 /* This filter will allow only untagged packets */ 2558 rc = bnxt_add_vlan_filter(bp, 0); 2559 } else { 2560 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2561 } 2562 2563 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2564 return rc; 2565 } 2566 2567 static int 2568 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2569 struct rte_ether_addr *mc_addr_set, 2570 uint32_t nb_mc_addr) 2571 { 2572 struct bnxt *bp = eth_dev->data->dev_private; 2573 char *mc_addr_list = (char *)mc_addr_set; 2574 struct bnxt_vnic_info *vnic; 2575 uint32_t off = 0, i = 0; 2576 int rc; 2577 2578 rc = is_bnxt_in_error(bp); 2579 if (rc) 2580 return rc; 2581 2582 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2583 2584 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2585 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2586 goto allmulti; 2587 } 2588 2589 /* TODO Check for Duplicate mcast addresses */ 2590 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2591 for (i = 0; i < nb_mc_addr; i++) { 2592 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2593 RTE_ETHER_ADDR_LEN); 2594 off += RTE_ETHER_ADDR_LEN; 2595 } 2596 2597 vnic->mc_addr_cnt = i; 2598 if (vnic->mc_addr_cnt) 2599 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2600 else 2601 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2602 2603 allmulti: 2604 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2605 } 2606 2607 static int 2608 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2609 { 2610 struct bnxt *bp = dev->data->dev_private; 2611 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2612 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2613 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2614 uint8_t fw_rsvd = bp->fw_ver & 0xff; 2615 int ret; 2616 2617 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", 2618 fw_major, fw_minor, fw_updt, fw_rsvd); 2619 2620 ret += 1; /* add the size of '\0' */ 2621 if (fw_size < (uint32_t)ret) 2622 return ret; 2623 else 2624 return 0; 2625 } 2626 2627 static void 2628 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2629 struct rte_eth_rxq_info *qinfo) 2630 { 2631 struct bnxt *bp = dev->data->dev_private; 2632 struct bnxt_rx_queue *rxq; 2633 2634 if (is_bnxt_in_error(bp)) 2635 return; 2636 2637 rxq = dev->data->rx_queues[queue_id]; 2638 2639 qinfo->mp = rxq->mb_pool; 2640 qinfo->scattered_rx = dev->data->scattered_rx; 2641 qinfo->nb_desc = rxq->nb_rx_desc; 2642 2643 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2644 qinfo->conf.rx_drop_en = 0; 2645 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2646 } 2647 2648 static void 2649 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2650 struct rte_eth_txq_info *qinfo) 2651 { 2652 struct bnxt *bp = dev->data->dev_private; 2653 struct bnxt_tx_queue *txq; 2654 2655 if (is_bnxt_in_error(bp)) 2656 return; 2657 2658 txq = dev->data->tx_queues[queue_id]; 2659 2660 qinfo->nb_desc = txq->nb_tx_desc; 2661 2662 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2663 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2664 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2665 2666 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2667 qinfo->conf.tx_rs_thresh = 0; 2668 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2669 } 2670 2671 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 2672 { 2673 struct bnxt *bp = eth_dev->data->dev_private; 2674 uint32_t new_pkt_size; 2675 uint32_t rc = 0; 2676 uint32_t i; 2677 2678 rc = is_bnxt_in_error(bp); 2679 if (rc) 2680 return rc; 2681 2682 /* Exit if receive queues are not configured yet */ 2683 if (!eth_dev->data->nb_rx_queues) 2684 return rc; 2685 2686 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 2687 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 2688 2689 #ifdef RTE_ARCH_X86 2690 /* 2691 * If vector-mode tx/rx is active, disallow any MTU change that would 2692 * require scattered receive support. 2693 */ 2694 if (eth_dev->data->dev_started && 2695 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec || 2696 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) && 2697 (new_pkt_size > 2698 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 2699 PMD_DRV_LOG(ERR, 2700 "MTU change would require scattered rx support. "); 2701 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 2702 return -EINVAL; 2703 } 2704 #endif 2705 2706 if (new_mtu > RTE_ETHER_MTU) { 2707 bp->flags |= BNXT_FLAG_JUMBO; 2708 bp->eth_dev->data->dev_conf.rxmode.offloads |= 2709 DEV_RX_OFFLOAD_JUMBO_FRAME; 2710 } else { 2711 bp->eth_dev->data->dev_conf.rxmode.offloads &= 2712 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2713 bp->flags &= ~BNXT_FLAG_JUMBO; 2714 } 2715 2716 /* Is there a change in mtu setting? */ 2717 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) 2718 return rc; 2719 2720 for (i = 0; i < bp->nr_vnics; i++) { 2721 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2722 uint16_t size = 0; 2723 2724 vnic->mru = BNXT_VNIC_MRU(new_mtu); 2725 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 2726 if (rc) 2727 break; 2728 2729 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 2730 size -= RTE_PKTMBUF_HEADROOM; 2731 2732 if (size < new_mtu) { 2733 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 2734 if (rc) 2735 return rc; 2736 } 2737 } 2738 2739 if (!rc) 2740 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 2741 2742 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 2743 2744 return rc; 2745 } 2746 2747 static int 2748 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 2749 { 2750 struct bnxt *bp = dev->data->dev_private; 2751 uint16_t vlan = bp->vlan; 2752 int rc; 2753 2754 rc = is_bnxt_in_error(bp); 2755 if (rc) 2756 return rc; 2757 2758 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2759 PMD_DRV_LOG(ERR, 2760 "PVID cannot be modified for this function\n"); 2761 return -ENOTSUP; 2762 } 2763 bp->vlan = on ? pvid : 0; 2764 2765 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 2766 if (rc) 2767 bp->vlan = vlan; 2768 return rc; 2769 } 2770 2771 static int 2772 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 2773 { 2774 struct bnxt *bp = dev->data->dev_private; 2775 int rc; 2776 2777 rc = is_bnxt_in_error(bp); 2778 if (rc) 2779 return rc; 2780 2781 return bnxt_hwrm_port_led_cfg(bp, true); 2782 } 2783 2784 static int 2785 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 2786 { 2787 struct bnxt *bp = dev->data->dev_private; 2788 int rc; 2789 2790 rc = is_bnxt_in_error(bp); 2791 if (rc) 2792 return rc; 2793 2794 return bnxt_hwrm_port_led_cfg(bp, false); 2795 } 2796 2797 static uint32_t 2798 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 2799 { 2800 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2801 uint32_t desc = 0, raw_cons = 0, cons; 2802 struct bnxt_cp_ring_info *cpr; 2803 struct bnxt_rx_queue *rxq; 2804 struct rx_pkt_cmpl *rxcmp; 2805 int rc; 2806 2807 rc = is_bnxt_in_error(bp); 2808 if (rc) 2809 return rc; 2810 2811 rxq = dev->data->rx_queues[rx_queue_id]; 2812 cpr = rxq->cp_ring; 2813 raw_cons = cpr->cp_raw_cons; 2814 2815 while (1) { 2816 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 2817 rte_prefetch0(&cpr->cp_desc_ring[cons]); 2818 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2819 2820 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) { 2821 break; 2822 } else { 2823 raw_cons++; 2824 desc++; 2825 } 2826 } 2827 2828 return desc; 2829 } 2830 2831 static int 2832 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 2833 { 2834 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 2835 struct bnxt_rx_ring_info *rxr; 2836 struct bnxt_cp_ring_info *cpr; 2837 struct bnxt_sw_rx_bd *rx_buf; 2838 struct rx_pkt_cmpl *rxcmp; 2839 uint32_t cons, cp_cons; 2840 int rc; 2841 2842 if (!rxq) 2843 return -EINVAL; 2844 2845 rc = is_bnxt_in_error(rxq->bp); 2846 if (rc) 2847 return rc; 2848 2849 cpr = rxq->cp_ring; 2850 rxr = rxq->rx_ring; 2851 2852 if (offset >= rxq->nb_rx_desc) 2853 return -EINVAL; 2854 2855 cons = RING_CMP(cpr->cp_ring_struct, offset); 2856 cp_cons = cpr->cp_raw_cons; 2857 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2858 2859 if (cons > cp_cons) { 2860 if (CMPL_VALID(rxcmp, cpr->valid)) 2861 return RTE_ETH_RX_DESC_DONE; 2862 } else { 2863 if (CMPL_VALID(rxcmp, !cpr->valid)) 2864 return RTE_ETH_RX_DESC_DONE; 2865 } 2866 rx_buf = &rxr->rx_buf_ring[cons]; 2867 if (rx_buf->mbuf == NULL) 2868 return RTE_ETH_RX_DESC_UNAVAIL; 2869 2870 2871 return RTE_ETH_RX_DESC_AVAIL; 2872 } 2873 2874 static int 2875 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 2876 { 2877 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 2878 struct bnxt_tx_ring_info *txr; 2879 struct bnxt_cp_ring_info *cpr; 2880 struct bnxt_sw_tx_bd *tx_buf; 2881 struct tx_pkt_cmpl *txcmp; 2882 uint32_t cons, cp_cons; 2883 int rc; 2884 2885 if (!txq) 2886 return -EINVAL; 2887 2888 rc = is_bnxt_in_error(txq->bp); 2889 if (rc) 2890 return rc; 2891 2892 cpr = txq->cp_ring; 2893 txr = txq->tx_ring; 2894 2895 if (offset >= txq->nb_tx_desc) 2896 return -EINVAL; 2897 2898 cons = RING_CMP(cpr->cp_ring_struct, offset); 2899 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2900 cp_cons = cpr->cp_raw_cons; 2901 2902 if (cons > cp_cons) { 2903 if (CMPL_VALID(txcmp, cpr->valid)) 2904 return RTE_ETH_TX_DESC_UNAVAIL; 2905 } else { 2906 if (CMPL_VALID(txcmp, !cpr->valid)) 2907 return RTE_ETH_TX_DESC_UNAVAIL; 2908 } 2909 tx_buf = &txr->tx_buf_ring[cons]; 2910 if (tx_buf->mbuf == NULL) 2911 return RTE_ETH_TX_DESC_DONE; 2912 2913 return RTE_ETH_TX_DESC_FULL; 2914 } 2915 2916 static struct bnxt_filter_info * 2917 bnxt_match_and_validate_ether_filter(struct bnxt *bp, 2918 struct rte_eth_ethertype_filter *efilter, 2919 struct bnxt_vnic_info *vnic0, 2920 struct bnxt_vnic_info *vnic, 2921 int *ret) 2922 { 2923 struct bnxt_filter_info *mfilter = NULL; 2924 int match = 0; 2925 *ret = 0; 2926 2927 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 || 2928 efilter->ether_type == RTE_ETHER_TYPE_IPV6) { 2929 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in" 2930 " ethertype filter.", efilter->ether_type); 2931 *ret = -EINVAL; 2932 goto exit; 2933 } 2934 if (efilter->queue >= bp->rx_nr_rings) { 2935 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2936 *ret = -EINVAL; 2937 goto exit; 2938 } 2939 2940 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 2941 vnic = &bp->vnic_info[efilter->queue]; 2942 if (vnic == NULL) { 2943 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2944 *ret = -EINVAL; 2945 goto exit; 2946 } 2947 2948 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2949 STAILQ_FOREACH(mfilter, &vnic0->filter, next) { 2950 if ((!memcmp(efilter->mac_addr.addr_bytes, 2951 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2952 mfilter->flags == 2953 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP && 2954 mfilter->ethertype == efilter->ether_type)) { 2955 match = 1; 2956 break; 2957 } 2958 } 2959 } else { 2960 STAILQ_FOREACH(mfilter, &vnic->filter, next) 2961 if ((!memcmp(efilter->mac_addr.addr_bytes, 2962 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2963 mfilter->ethertype == efilter->ether_type && 2964 mfilter->flags == 2965 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) { 2966 match = 1; 2967 break; 2968 } 2969 } 2970 2971 if (match) 2972 *ret = -EEXIST; 2973 2974 exit: 2975 return mfilter; 2976 } 2977 2978 static int 2979 bnxt_ethertype_filter(struct rte_eth_dev *dev, 2980 enum rte_filter_op filter_op, 2981 void *arg) 2982 { 2983 struct bnxt *bp = dev->data->dev_private; 2984 struct rte_eth_ethertype_filter *efilter = 2985 (struct rte_eth_ethertype_filter *)arg; 2986 struct bnxt_filter_info *bfilter, *filter1; 2987 struct bnxt_vnic_info *vnic, *vnic0; 2988 int ret; 2989 2990 if (filter_op == RTE_ETH_FILTER_NOP) 2991 return 0; 2992 2993 if (arg == NULL) { 2994 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2995 filter_op); 2996 return -EINVAL; 2997 } 2998 2999 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 3000 vnic = &bp->vnic_info[efilter->queue]; 3001 3002 switch (filter_op) { 3003 case RTE_ETH_FILTER_ADD: 3004 bnxt_match_and_validate_ether_filter(bp, efilter, 3005 vnic0, vnic, &ret); 3006 if (ret < 0) 3007 return ret; 3008 3009 bfilter = bnxt_get_unused_filter(bp); 3010 if (bfilter == NULL) { 3011 PMD_DRV_LOG(ERR, 3012 "Not enough resources for a new filter.\n"); 3013 return -ENOMEM; 3014 } 3015 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 3016 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes, 3017 RTE_ETHER_ADDR_LEN); 3018 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes, 3019 RTE_ETHER_ADDR_LEN); 3020 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 3021 bfilter->ethertype = efilter->ether_type; 3022 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3023 3024 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0); 3025 if (filter1 == NULL) { 3026 ret = -EINVAL; 3027 goto cleanup; 3028 } 3029 bfilter->enables |= 3030 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 3031 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 3032 3033 bfilter->dst_id = vnic->fw_vnic_id; 3034 3035 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 3036 bfilter->flags = 3037 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 3038 } 3039 3040 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 3041 if (ret) 3042 goto cleanup; 3043 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 3044 break; 3045 case RTE_ETH_FILTER_DELETE: 3046 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter, 3047 vnic0, vnic, &ret); 3048 if (ret == -EEXIST) { 3049 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1); 3050 3051 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info, 3052 next); 3053 bnxt_free_filter(bp, filter1); 3054 } else if (ret == 0) { 3055 PMD_DRV_LOG(ERR, "No matching filter found\n"); 3056 } 3057 break; 3058 default: 3059 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 3060 ret = -EINVAL; 3061 goto error; 3062 } 3063 return ret; 3064 cleanup: 3065 bnxt_free_filter(bp, bfilter); 3066 error: 3067 return ret; 3068 } 3069 3070 static inline int 3071 parse_ntuple_filter(struct bnxt *bp, 3072 struct rte_eth_ntuple_filter *nfilter, 3073 struct bnxt_filter_info *bfilter) 3074 { 3075 uint32_t en = 0; 3076 3077 if (nfilter->queue >= bp->rx_nr_rings) { 3078 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue); 3079 return -EINVAL; 3080 } 3081 3082 switch (nfilter->dst_port_mask) { 3083 case UINT16_MAX: 3084 bfilter->dst_port_mask = -1; 3085 bfilter->dst_port = nfilter->dst_port; 3086 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT | 3087 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3088 break; 3089 default: 3090 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 3091 return -EINVAL; 3092 } 3093 3094 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 3095 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3096 3097 switch (nfilter->proto_mask) { 3098 case UINT8_MAX: 3099 if (nfilter->proto == 17) /* IPPROTO_UDP */ 3100 bfilter->ip_protocol = 17; 3101 else if (nfilter->proto == 6) /* IPPROTO_TCP */ 3102 bfilter->ip_protocol = 6; 3103 else 3104 return -EINVAL; 3105 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3106 break; 3107 default: 3108 PMD_DRV_LOG(ERR, "invalid protocol mask."); 3109 return -EINVAL; 3110 } 3111 3112 switch (nfilter->dst_ip_mask) { 3113 case UINT32_MAX: 3114 bfilter->dst_ipaddr_mask[0] = -1; 3115 bfilter->dst_ipaddr[0] = nfilter->dst_ip; 3116 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR | 3117 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3118 break; 3119 default: 3120 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 3121 return -EINVAL; 3122 } 3123 3124 switch (nfilter->src_ip_mask) { 3125 case UINT32_MAX: 3126 bfilter->src_ipaddr_mask[0] = -1; 3127 bfilter->src_ipaddr[0] = nfilter->src_ip; 3128 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR | 3129 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3130 break; 3131 default: 3132 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 3133 return -EINVAL; 3134 } 3135 3136 switch (nfilter->src_port_mask) { 3137 case UINT16_MAX: 3138 bfilter->src_port_mask = -1; 3139 bfilter->src_port = nfilter->src_port; 3140 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT | 3141 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3142 break; 3143 default: 3144 PMD_DRV_LOG(ERR, "invalid src_port mask."); 3145 return -EINVAL; 3146 } 3147 3148 bfilter->enables = en; 3149 return 0; 3150 } 3151 3152 static struct bnxt_filter_info* 3153 bnxt_match_ntuple_filter(struct bnxt *bp, 3154 struct bnxt_filter_info *bfilter, 3155 struct bnxt_vnic_info **mvnic) 3156 { 3157 struct bnxt_filter_info *mfilter = NULL; 3158 int i; 3159 3160 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3161 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3162 STAILQ_FOREACH(mfilter, &vnic->filter, next) { 3163 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] && 3164 bfilter->src_ipaddr_mask[0] == 3165 mfilter->src_ipaddr_mask[0] && 3166 bfilter->src_port == mfilter->src_port && 3167 bfilter->src_port_mask == mfilter->src_port_mask && 3168 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] && 3169 bfilter->dst_ipaddr_mask[0] == 3170 mfilter->dst_ipaddr_mask[0] && 3171 bfilter->dst_port == mfilter->dst_port && 3172 bfilter->dst_port_mask == mfilter->dst_port_mask && 3173 bfilter->flags == mfilter->flags && 3174 bfilter->enables == mfilter->enables) { 3175 if (mvnic) 3176 *mvnic = vnic; 3177 return mfilter; 3178 } 3179 } 3180 } 3181 return NULL; 3182 } 3183 3184 static int 3185 bnxt_cfg_ntuple_filter(struct bnxt *bp, 3186 struct rte_eth_ntuple_filter *nfilter, 3187 enum rte_filter_op filter_op) 3188 { 3189 struct bnxt_filter_info *bfilter, *mfilter, *filter1; 3190 struct bnxt_vnic_info *vnic, *vnic0, *mvnic; 3191 int ret; 3192 3193 if (nfilter->flags != RTE_5TUPLE_FLAGS) { 3194 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 3195 return -EINVAL; 3196 } 3197 3198 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) { 3199 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n"); 3200 return -EINVAL; 3201 } 3202 3203 bfilter = bnxt_get_unused_filter(bp); 3204 if (bfilter == NULL) { 3205 PMD_DRV_LOG(ERR, 3206 "Not enough resources for a new filter.\n"); 3207 return -ENOMEM; 3208 } 3209 ret = parse_ntuple_filter(bp, nfilter, bfilter); 3210 if (ret < 0) 3211 goto free_filter; 3212 3213 vnic = &bp->vnic_info[nfilter->queue]; 3214 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 3215 filter1 = STAILQ_FIRST(&vnic0->filter); 3216 if (filter1 == NULL) { 3217 ret = -EINVAL; 3218 goto free_filter; 3219 } 3220 3221 bfilter->dst_id = vnic->fw_vnic_id; 3222 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 3223 bfilter->enables |= 3224 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 3225 bfilter->ethertype = 0x800; 3226 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3227 3228 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic); 3229 3230 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 3231 bfilter->dst_id == mfilter->dst_id) { 3232 PMD_DRV_LOG(ERR, "filter exists.\n"); 3233 ret = -EEXIST; 3234 goto free_filter; 3235 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 3236 bfilter->dst_id != mfilter->dst_id) { 3237 mfilter->dst_id = vnic->fw_vnic_id; 3238 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter); 3239 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next); 3240 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next); 3241 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n"); 3242 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n"); 3243 goto free_filter; 3244 } 3245 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 3246 PMD_DRV_LOG(ERR, "filter doesn't exist."); 3247 ret = -ENOENT; 3248 goto free_filter; 3249 } 3250 3251 if (filter_op == RTE_ETH_FILTER_ADD) { 3252 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 3253 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 3254 if (ret) 3255 goto free_filter; 3256 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 3257 } else { 3258 if (mfilter == NULL) { 3259 /* This should not happen. But for Coverity! */ 3260 ret = -ENOENT; 3261 goto free_filter; 3262 } 3263 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter); 3264 3265 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next); 3266 bnxt_free_filter(bp, mfilter); 3267 bnxt_free_filter(bp, bfilter); 3268 } 3269 3270 return 0; 3271 free_filter: 3272 bnxt_free_filter(bp, bfilter); 3273 return ret; 3274 } 3275 3276 static int 3277 bnxt_ntuple_filter(struct rte_eth_dev *dev, 3278 enum rte_filter_op filter_op, 3279 void *arg) 3280 { 3281 struct bnxt *bp = dev->data->dev_private; 3282 int ret; 3283 3284 if (filter_op == RTE_ETH_FILTER_NOP) 3285 return 0; 3286 3287 if (arg == NULL) { 3288 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 3289 filter_op); 3290 return -EINVAL; 3291 } 3292 3293 switch (filter_op) { 3294 case RTE_ETH_FILTER_ADD: 3295 ret = bnxt_cfg_ntuple_filter(bp, 3296 (struct rte_eth_ntuple_filter *)arg, 3297 filter_op); 3298 break; 3299 case RTE_ETH_FILTER_DELETE: 3300 ret = bnxt_cfg_ntuple_filter(bp, 3301 (struct rte_eth_ntuple_filter *)arg, 3302 filter_op); 3303 break; 3304 default: 3305 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 3306 ret = -EINVAL; 3307 break; 3308 } 3309 return ret; 3310 } 3311 3312 static int 3313 bnxt_parse_fdir_filter(struct bnxt *bp, 3314 struct rte_eth_fdir_filter *fdir, 3315 struct bnxt_filter_info *filter) 3316 { 3317 enum rte_fdir_mode fdir_mode = 3318 bp->eth_dev->data->dev_conf.fdir_conf.mode; 3319 struct bnxt_vnic_info *vnic0, *vnic; 3320 struct bnxt_filter_info *filter1; 3321 uint32_t en = 0; 3322 int i; 3323 3324 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 3325 return -EINVAL; 3326 3327 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci; 3328 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID; 3329 3330 switch (fdir->input.flow_type) { 3331 case RTE_ETH_FLOW_IPV4: 3332 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 3333 /* FALLTHROUGH */ 3334 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip; 3335 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3336 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip; 3337 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3338 filter->ip_protocol = fdir->input.flow.ip4_flow.proto; 3339 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3340 filter->ip_addr_type = 3341 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 3342 filter->src_ipaddr_mask[0] = 0xffffffff; 3343 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3344 filter->dst_ipaddr_mask[0] = 0xffffffff; 3345 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3346 filter->ethertype = 0x800; 3347 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3348 break; 3349 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 3350 filter->src_port = fdir->input.flow.tcp4_flow.src_port; 3351 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 3352 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port; 3353 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 3354 filter->dst_port_mask = 0xffff; 3355 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3356 filter->src_port_mask = 0xffff; 3357 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3358 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip; 3359 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3360 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip; 3361 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3362 filter->ip_protocol = 6; 3363 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3364 filter->ip_addr_type = 3365 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 3366 filter->src_ipaddr_mask[0] = 0xffffffff; 3367 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3368 filter->dst_ipaddr_mask[0] = 0xffffffff; 3369 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3370 filter->ethertype = 0x800; 3371 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3372 break; 3373 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 3374 filter->src_port = fdir->input.flow.udp4_flow.src_port; 3375 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 3376 filter->dst_port = fdir->input.flow.udp4_flow.dst_port; 3377 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 3378 filter->dst_port_mask = 0xffff; 3379 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3380 filter->src_port_mask = 0xffff; 3381 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3382 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip; 3383 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3384 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip; 3385 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3386 filter->ip_protocol = 17; 3387 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3388 filter->ip_addr_type = 3389 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 3390 filter->src_ipaddr_mask[0] = 0xffffffff; 3391 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3392 filter->dst_ipaddr_mask[0] = 0xffffffff; 3393 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3394 filter->ethertype = 0x800; 3395 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3396 break; 3397 case RTE_ETH_FLOW_IPV6: 3398 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 3399 /* FALLTHROUGH */ 3400 filter->ip_addr_type = 3401 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 3402 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto; 3403 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3404 rte_memcpy(filter->src_ipaddr, 3405 fdir->input.flow.ipv6_flow.src_ip, 16); 3406 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3407 rte_memcpy(filter->dst_ipaddr, 3408 fdir->input.flow.ipv6_flow.dst_ip, 16); 3409 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3410 memset(filter->dst_ipaddr_mask, 0xff, 16); 3411 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3412 memset(filter->src_ipaddr_mask, 0xff, 16); 3413 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3414 filter->ethertype = 0x86dd; 3415 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3416 break; 3417 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 3418 filter->src_port = fdir->input.flow.tcp6_flow.src_port; 3419 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 3420 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port; 3421 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 3422 filter->dst_port_mask = 0xffff; 3423 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3424 filter->src_port_mask = 0xffff; 3425 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3426 filter->ip_addr_type = 3427 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 3428 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto; 3429 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3430 rte_memcpy(filter->src_ipaddr, 3431 fdir->input.flow.tcp6_flow.ip.src_ip, 16); 3432 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3433 rte_memcpy(filter->dst_ipaddr, 3434 fdir->input.flow.tcp6_flow.ip.dst_ip, 16); 3435 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3436 memset(filter->dst_ipaddr_mask, 0xff, 16); 3437 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3438 memset(filter->src_ipaddr_mask, 0xff, 16); 3439 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3440 filter->ethertype = 0x86dd; 3441 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3442 break; 3443 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 3444 filter->src_port = fdir->input.flow.udp6_flow.src_port; 3445 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 3446 filter->dst_port = fdir->input.flow.udp6_flow.dst_port; 3447 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 3448 filter->dst_port_mask = 0xffff; 3449 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 3450 filter->src_port_mask = 0xffff; 3451 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 3452 filter->ip_addr_type = 3453 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 3454 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto; 3455 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3456 rte_memcpy(filter->src_ipaddr, 3457 fdir->input.flow.udp6_flow.ip.src_ip, 16); 3458 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3459 rte_memcpy(filter->dst_ipaddr, 3460 fdir->input.flow.udp6_flow.ip.dst_ip, 16); 3461 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3462 memset(filter->dst_ipaddr_mask, 0xff, 16); 3463 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3464 memset(filter->src_ipaddr_mask, 0xff, 16); 3465 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3466 filter->ethertype = 0x86dd; 3467 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3468 break; 3469 case RTE_ETH_FLOW_L2_PAYLOAD: 3470 filter->ethertype = fdir->input.flow.l2_flow.ether_type; 3471 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3472 break; 3473 case RTE_ETH_FLOW_VXLAN: 3474 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3475 return -EINVAL; 3476 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 3477 filter->tunnel_type = 3478 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN; 3479 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 3480 break; 3481 case RTE_ETH_FLOW_NVGRE: 3482 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3483 return -EINVAL; 3484 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 3485 filter->tunnel_type = 3486 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE; 3487 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 3488 break; 3489 case RTE_ETH_FLOW_UNKNOWN: 3490 case RTE_ETH_FLOW_RAW: 3491 case RTE_ETH_FLOW_FRAG_IPV4: 3492 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 3493 case RTE_ETH_FLOW_FRAG_IPV6: 3494 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 3495 case RTE_ETH_FLOW_IPV6_EX: 3496 case RTE_ETH_FLOW_IPV6_TCP_EX: 3497 case RTE_ETH_FLOW_IPV6_UDP_EX: 3498 case RTE_ETH_FLOW_GENEVE: 3499 /* FALLTHROUGH */ 3500 default: 3501 return -EINVAL; 3502 } 3503 3504 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 3505 vnic = &bp->vnic_info[fdir->action.rx_queue]; 3506 if (vnic == NULL) { 3507 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue); 3508 return -EINVAL; 3509 } 3510 3511 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 3512 rte_memcpy(filter->dst_macaddr, 3513 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6); 3514 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 3515 } 3516 3517 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) { 3518 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 3519 filter1 = STAILQ_FIRST(&vnic0->filter); 3520 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0); 3521 } else { 3522 filter->dst_id = vnic->fw_vnic_id; 3523 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 3524 if (filter->dst_macaddr[i] == 0x00) 3525 filter1 = STAILQ_FIRST(&vnic0->filter); 3526 else 3527 filter1 = bnxt_get_l2_filter(bp, filter, vnic); 3528 } 3529 3530 if (filter1 == NULL) 3531 return -EINVAL; 3532 3533 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 3534 filter->fw_l2_filter_id = filter1->fw_l2_filter_id; 3535 3536 filter->enables = en; 3537 3538 return 0; 3539 } 3540 3541 static struct bnxt_filter_info * 3542 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf, 3543 struct bnxt_vnic_info **mvnic) 3544 { 3545 struct bnxt_filter_info *mf = NULL; 3546 int i; 3547 3548 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3549 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3550 3551 STAILQ_FOREACH(mf, &vnic->filter, next) { 3552 if (mf->filter_type == nf->filter_type && 3553 mf->flags == nf->flags && 3554 mf->src_port == nf->src_port && 3555 mf->src_port_mask == nf->src_port_mask && 3556 mf->dst_port == nf->dst_port && 3557 mf->dst_port_mask == nf->dst_port_mask && 3558 mf->ip_protocol == nf->ip_protocol && 3559 mf->ip_addr_type == nf->ip_addr_type && 3560 mf->ethertype == nf->ethertype && 3561 mf->vni == nf->vni && 3562 mf->tunnel_type == nf->tunnel_type && 3563 mf->l2_ovlan == nf->l2_ovlan && 3564 mf->l2_ovlan_mask == nf->l2_ovlan_mask && 3565 mf->l2_ivlan == nf->l2_ivlan && 3566 mf->l2_ivlan_mask == nf->l2_ivlan_mask && 3567 !memcmp(mf->l2_addr, nf->l2_addr, 3568 RTE_ETHER_ADDR_LEN) && 3569 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask, 3570 RTE_ETHER_ADDR_LEN) && 3571 !memcmp(mf->src_macaddr, nf->src_macaddr, 3572 RTE_ETHER_ADDR_LEN) && 3573 !memcmp(mf->dst_macaddr, nf->dst_macaddr, 3574 RTE_ETHER_ADDR_LEN) && 3575 !memcmp(mf->src_ipaddr, nf->src_ipaddr, 3576 sizeof(nf->src_ipaddr)) && 3577 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask, 3578 sizeof(nf->src_ipaddr_mask)) && 3579 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr, 3580 sizeof(nf->dst_ipaddr)) && 3581 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask, 3582 sizeof(nf->dst_ipaddr_mask))) { 3583 if (mvnic) 3584 *mvnic = vnic; 3585 return mf; 3586 } 3587 } 3588 } 3589 return NULL; 3590 } 3591 3592 static int 3593 bnxt_fdir_filter(struct rte_eth_dev *dev, 3594 enum rte_filter_op filter_op, 3595 void *arg) 3596 { 3597 struct bnxt *bp = dev->data->dev_private; 3598 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg; 3599 struct bnxt_filter_info *filter, *match; 3600 struct bnxt_vnic_info *vnic, *mvnic; 3601 int ret = 0, i; 3602 3603 if (filter_op == RTE_ETH_FILTER_NOP) 3604 return 0; 3605 3606 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 3607 return -EINVAL; 3608 3609 switch (filter_op) { 3610 case RTE_ETH_FILTER_ADD: 3611 case RTE_ETH_FILTER_DELETE: 3612 /* FALLTHROUGH */ 3613 filter = bnxt_get_unused_filter(bp); 3614 if (filter == NULL) { 3615 PMD_DRV_LOG(ERR, 3616 "Not enough resources for a new flow.\n"); 3617 return -ENOMEM; 3618 } 3619 3620 ret = bnxt_parse_fdir_filter(bp, fdir, filter); 3621 if (ret != 0) 3622 goto free_filter; 3623 filter->filter_type = HWRM_CFA_NTUPLE_FILTER; 3624 3625 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3626 vnic = &bp->vnic_info[0]; 3627 else 3628 vnic = &bp->vnic_info[fdir->action.rx_queue]; 3629 3630 match = bnxt_match_fdir(bp, filter, &mvnic); 3631 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { 3632 if (match->dst_id == vnic->fw_vnic_id) { 3633 PMD_DRV_LOG(ERR, "Flow already exists.\n"); 3634 ret = -EEXIST; 3635 goto free_filter; 3636 } else { 3637 match->dst_id = vnic->fw_vnic_id; 3638 ret = bnxt_hwrm_set_ntuple_filter(bp, 3639 match->dst_id, 3640 match); 3641 STAILQ_REMOVE(&mvnic->filter, match, 3642 bnxt_filter_info, next); 3643 STAILQ_INSERT_TAIL(&vnic->filter, match, next); 3644 PMD_DRV_LOG(ERR, 3645 "Filter with matching pattern exist\n"); 3646 PMD_DRV_LOG(ERR, 3647 "Updated it to new destination q\n"); 3648 goto free_filter; 3649 } 3650 } 3651 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 3652 PMD_DRV_LOG(ERR, "Flow does not exist.\n"); 3653 ret = -ENOENT; 3654 goto free_filter; 3655 } 3656 3657 if (filter_op == RTE_ETH_FILTER_ADD) { 3658 ret = bnxt_hwrm_set_ntuple_filter(bp, 3659 filter->dst_id, 3660 filter); 3661 if (ret) 3662 goto free_filter; 3663 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 3664 } else { 3665 ret = bnxt_hwrm_clear_ntuple_filter(bp, match); 3666 STAILQ_REMOVE(&vnic->filter, match, 3667 bnxt_filter_info, next); 3668 bnxt_free_filter(bp, match); 3669 bnxt_free_filter(bp, filter); 3670 } 3671 break; 3672 case RTE_ETH_FILTER_FLUSH: 3673 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3674 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3675 3676 STAILQ_FOREACH(filter, &vnic->filter, next) { 3677 if (filter->filter_type == 3678 HWRM_CFA_NTUPLE_FILTER) { 3679 ret = 3680 bnxt_hwrm_clear_ntuple_filter(bp, 3681 filter); 3682 STAILQ_REMOVE(&vnic->filter, filter, 3683 bnxt_filter_info, next); 3684 } 3685 } 3686 } 3687 return ret; 3688 case RTE_ETH_FILTER_UPDATE: 3689 case RTE_ETH_FILTER_STATS: 3690 case RTE_ETH_FILTER_INFO: 3691 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op); 3692 break; 3693 default: 3694 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 3695 ret = -EINVAL; 3696 break; 3697 } 3698 return ret; 3699 3700 free_filter: 3701 bnxt_free_filter(bp, filter); 3702 return ret; 3703 } 3704 3705 static int 3706 bnxt_filter_ctrl_op(struct rte_eth_dev *dev, 3707 enum rte_filter_type filter_type, 3708 enum rte_filter_op filter_op, void *arg) 3709 { 3710 struct bnxt *bp = dev->data->dev_private; 3711 int ret = 0; 3712 3713 ret = is_bnxt_in_error(dev->data->dev_private); 3714 if (ret) 3715 return ret; 3716 3717 switch (filter_type) { 3718 case RTE_ETH_FILTER_TUNNEL: 3719 PMD_DRV_LOG(ERR, 3720 "filter type: %d: To be implemented\n", filter_type); 3721 break; 3722 case RTE_ETH_FILTER_FDIR: 3723 ret = bnxt_fdir_filter(dev, filter_op, arg); 3724 break; 3725 case RTE_ETH_FILTER_NTUPLE: 3726 ret = bnxt_ntuple_filter(dev, filter_op, arg); 3727 break; 3728 case RTE_ETH_FILTER_ETHERTYPE: 3729 ret = bnxt_ethertype_filter(dev, filter_op, arg); 3730 break; 3731 case RTE_ETH_FILTER_GENERIC: 3732 if (filter_op != RTE_ETH_FILTER_GET) 3733 return -EINVAL; 3734 if (BNXT_TRUFLOW_EN(bp)) 3735 *(const void **)arg = &bnxt_ulp_rte_flow_ops; 3736 else 3737 *(const void **)arg = &bnxt_flow_ops; 3738 break; 3739 default: 3740 PMD_DRV_LOG(ERR, 3741 "Filter type (%d) not supported", filter_type); 3742 ret = -EINVAL; 3743 break; 3744 } 3745 return ret; 3746 } 3747 3748 static const uint32_t * 3749 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3750 { 3751 static const uint32_t ptypes[] = { 3752 RTE_PTYPE_L2_ETHER_VLAN, 3753 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3754 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3755 RTE_PTYPE_L4_ICMP, 3756 RTE_PTYPE_L4_TCP, 3757 RTE_PTYPE_L4_UDP, 3758 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3759 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3760 RTE_PTYPE_INNER_L4_ICMP, 3761 RTE_PTYPE_INNER_L4_TCP, 3762 RTE_PTYPE_INNER_L4_UDP, 3763 RTE_PTYPE_UNKNOWN 3764 }; 3765 3766 if (!dev->rx_pkt_burst) 3767 return NULL; 3768 3769 return ptypes; 3770 } 3771 3772 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3773 int reg_win) 3774 { 3775 uint32_t reg_base = *reg_arr & 0xfffff000; 3776 uint32_t win_off; 3777 int i; 3778 3779 for (i = 0; i < count; i++) { 3780 if ((reg_arr[i] & 0xfffff000) != reg_base) 3781 return -ERANGE; 3782 } 3783 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3784 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3785 return 0; 3786 } 3787 3788 static int bnxt_map_ptp_regs(struct bnxt *bp) 3789 { 3790 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3791 uint32_t *reg_arr; 3792 int rc, i; 3793 3794 reg_arr = ptp->rx_regs; 3795 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3796 if (rc) 3797 return rc; 3798 3799 reg_arr = ptp->tx_regs; 3800 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3801 if (rc) 3802 return rc; 3803 3804 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3805 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3806 3807 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3808 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3809 3810 return 0; 3811 } 3812 3813 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3814 { 3815 rte_write32(0, (uint8_t *)bp->bar0 + 3816 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3817 rte_write32(0, (uint8_t *)bp->bar0 + 3818 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3819 } 3820 3821 static uint64_t bnxt_cc_read(struct bnxt *bp) 3822 { 3823 uint64_t ns; 3824 3825 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3826 BNXT_GRCPF_REG_SYNC_TIME)); 3827 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3828 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3829 return ns; 3830 } 3831 3832 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3833 { 3834 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3835 uint32_t fifo; 3836 3837 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3838 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3839 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3840 return -EAGAIN; 3841 3842 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3843 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3844 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3845 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3846 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3847 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3848 3849 return 0; 3850 } 3851 3852 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3853 { 3854 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3855 struct bnxt_pf_info *pf = bp->pf; 3856 uint16_t port_id; 3857 uint32_t fifo; 3858 3859 if (!ptp) 3860 return -ENODEV; 3861 3862 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3863 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3864 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3865 return -EAGAIN; 3866 3867 port_id = pf->port_id; 3868 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3869 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3870 3871 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3872 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3873 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 3874 /* bnxt_clr_rx_ts(bp); TBD */ 3875 return -EBUSY; 3876 } 3877 3878 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3879 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3880 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3881 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3882 3883 return 0; 3884 } 3885 3886 static int 3887 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3888 { 3889 uint64_t ns; 3890 struct bnxt *bp = dev->data->dev_private; 3891 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3892 3893 if (!ptp) 3894 return 0; 3895 3896 ns = rte_timespec_to_ns(ts); 3897 /* Set the timecounters to a new value. */ 3898 ptp->tc.nsec = ns; 3899 3900 return 0; 3901 } 3902 3903 static int 3904 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3905 { 3906 struct bnxt *bp = dev->data->dev_private; 3907 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3908 uint64_t ns, systime_cycles = 0; 3909 int rc = 0; 3910 3911 if (!ptp) 3912 return 0; 3913 3914 if (BNXT_CHIP_THOR(bp)) 3915 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3916 &systime_cycles); 3917 else 3918 systime_cycles = bnxt_cc_read(bp); 3919 3920 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3921 *ts = rte_ns_to_timespec(ns); 3922 3923 return rc; 3924 } 3925 static int 3926 bnxt_timesync_enable(struct rte_eth_dev *dev) 3927 { 3928 struct bnxt *bp = dev->data->dev_private; 3929 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3930 uint32_t shift = 0; 3931 int rc; 3932 3933 if (!ptp) 3934 return 0; 3935 3936 ptp->rx_filter = 1; 3937 ptp->tx_tstamp_en = 1; 3938 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3939 3940 rc = bnxt_hwrm_ptp_cfg(bp); 3941 if (rc) 3942 return rc; 3943 3944 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3945 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3946 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3947 3948 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3949 ptp->tc.cc_shift = shift; 3950 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3951 3952 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3953 ptp->rx_tstamp_tc.cc_shift = shift; 3954 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3955 3956 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3957 ptp->tx_tstamp_tc.cc_shift = shift; 3958 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3959 3960 if (!BNXT_CHIP_THOR(bp)) 3961 bnxt_map_ptp_regs(bp); 3962 3963 return 0; 3964 } 3965 3966 static int 3967 bnxt_timesync_disable(struct rte_eth_dev *dev) 3968 { 3969 struct bnxt *bp = dev->data->dev_private; 3970 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3971 3972 if (!ptp) 3973 return 0; 3974 3975 ptp->rx_filter = 0; 3976 ptp->tx_tstamp_en = 0; 3977 ptp->rxctl = 0; 3978 3979 bnxt_hwrm_ptp_cfg(bp); 3980 3981 if (!BNXT_CHIP_THOR(bp)) 3982 bnxt_unmap_ptp_regs(bp); 3983 3984 return 0; 3985 } 3986 3987 static int 3988 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3989 struct timespec *timestamp, 3990 uint32_t flags __rte_unused) 3991 { 3992 struct bnxt *bp = dev->data->dev_private; 3993 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3994 uint64_t rx_tstamp_cycles = 0; 3995 uint64_t ns; 3996 3997 if (!ptp) 3998 return 0; 3999 4000 if (BNXT_CHIP_THOR(bp)) 4001 rx_tstamp_cycles = ptp->rx_timestamp; 4002 else 4003 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 4004 4005 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 4006 *timestamp = rte_ns_to_timespec(ns); 4007 return 0; 4008 } 4009 4010 static int 4011 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 4012 struct timespec *timestamp) 4013 { 4014 struct bnxt *bp = dev->data->dev_private; 4015 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 4016 uint64_t tx_tstamp_cycles = 0; 4017 uint64_t ns; 4018 int rc = 0; 4019 4020 if (!ptp) 4021 return 0; 4022 4023 if (BNXT_CHIP_THOR(bp)) 4024 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 4025 &tx_tstamp_cycles); 4026 else 4027 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 4028 4029 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 4030 *timestamp = rte_ns_to_timespec(ns); 4031 4032 return rc; 4033 } 4034 4035 static int 4036 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 4037 { 4038 struct bnxt *bp = dev->data->dev_private; 4039 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 4040 4041 if (!ptp) 4042 return 0; 4043 4044 ptp->tc.nsec += delta; 4045 4046 return 0; 4047 } 4048 4049 static int 4050 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 4051 { 4052 struct bnxt *bp = dev->data->dev_private; 4053 int rc; 4054 uint32_t dir_entries; 4055 uint32_t entry_length; 4056 4057 rc = is_bnxt_in_error(bp); 4058 if (rc) 4059 return rc; 4060 4061 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 4062 bp->pdev->addr.domain, bp->pdev->addr.bus, 4063 bp->pdev->addr.devid, bp->pdev->addr.function); 4064 4065 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 4066 if (rc != 0) 4067 return rc; 4068 4069 return dir_entries * entry_length; 4070 } 4071 4072 static int 4073 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 4074 struct rte_dev_eeprom_info *in_eeprom) 4075 { 4076 struct bnxt *bp = dev->data->dev_private; 4077 uint32_t index; 4078 uint32_t offset; 4079 int rc; 4080 4081 rc = is_bnxt_in_error(bp); 4082 if (rc) 4083 return rc; 4084 4085 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 4086 bp->pdev->addr.domain, bp->pdev->addr.bus, 4087 bp->pdev->addr.devid, bp->pdev->addr.function, 4088 in_eeprom->offset, in_eeprom->length); 4089 4090 if (in_eeprom->offset == 0) /* special offset value to get directory */ 4091 return bnxt_get_nvram_directory(bp, in_eeprom->length, 4092 in_eeprom->data); 4093 4094 index = in_eeprom->offset >> 24; 4095 offset = in_eeprom->offset & 0xffffff; 4096 4097 if (index != 0) 4098 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 4099 in_eeprom->length, in_eeprom->data); 4100 4101 return 0; 4102 } 4103 4104 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 4105 { 4106 switch (dir_type) { 4107 case BNX_DIR_TYPE_CHIMP_PATCH: 4108 case BNX_DIR_TYPE_BOOTCODE: 4109 case BNX_DIR_TYPE_BOOTCODE_2: 4110 case BNX_DIR_TYPE_APE_FW: 4111 case BNX_DIR_TYPE_APE_PATCH: 4112 case BNX_DIR_TYPE_KONG_FW: 4113 case BNX_DIR_TYPE_KONG_PATCH: 4114 case BNX_DIR_TYPE_BONO_FW: 4115 case BNX_DIR_TYPE_BONO_PATCH: 4116 /* FALLTHROUGH */ 4117 return true; 4118 } 4119 4120 return false; 4121 } 4122 4123 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 4124 { 4125 switch (dir_type) { 4126 case BNX_DIR_TYPE_AVS: 4127 case BNX_DIR_TYPE_EXP_ROM_MBA: 4128 case BNX_DIR_TYPE_PCIE: 4129 case BNX_DIR_TYPE_TSCF_UCODE: 4130 case BNX_DIR_TYPE_EXT_PHY: 4131 case BNX_DIR_TYPE_CCM: 4132 case BNX_DIR_TYPE_ISCSI_BOOT: 4133 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 4134 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 4135 /* FALLTHROUGH */ 4136 return true; 4137 } 4138 4139 return false; 4140 } 4141 4142 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 4143 { 4144 return bnxt_dir_type_is_ape_bin_format(dir_type) || 4145 bnxt_dir_type_is_other_exec_format(dir_type); 4146 } 4147 4148 static int 4149 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 4150 struct rte_dev_eeprom_info *in_eeprom) 4151 { 4152 struct bnxt *bp = dev->data->dev_private; 4153 uint8_t index, dir_op; 4154 uint16_t type, ext, ordinal, attr; 4155 int rc; 4156 4157 rc = is_bnxt_in_error(bp); 4158 if (rc) 4159 return rc; 4160 4161 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 4162 bp->pdev->addr.domain, bp->pdev->addr.bus, 4163 bp->pdev->addr.devid, bp->pdev->addr.function, 4164 in_eeprom->offset, in_eeprom->length); 4165 4166 if (!BNXT_PF(bp)) { 4167 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 4168 return -EINVAL; 4169 } 4170 4171 type = in_eeprom->magic >> 16; 4172 4173 if (type == 0xffff) { /* special value for directory operations */ 4174 index = in_eeprom->magic & 0xff; 4175 dir_op = in_eeprom->magic >> 8; 4176 if (index == 0) 4177 return -EINVAL; 4178 switch (dir_op) { 4179 case 0x0e: /* erase */ 4180 if (in_eeprom->offset != ~in_eeprom->magic) 4181 return -EINVAL; 4182 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 4183 default: 4184 return -EINVAL; 4185 } 4186 } 4187 4188 /* Create or re-write an NVM item: */ 4189 if (bnxt_dir_type_is_executable(type) == true) 4190 return -EOPNOTSUPP; 4191 ext = in_eeprom->magic & 0xffff; 4192 ordinal = in_eeprom->offset >> 16; 4193 attr = in_eeprom->offset & 0xffff; 4194 4195 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 4196 in_eeprom->data, in_eeprom->length); 4197 } 4198 4199 /* 4200 * Initialization 4201 */ 4202 4203 static const struct eth_dev_ops bnxt_dev_ops = { 4204 .dev_infos_get = bnxt_dev_info_get_op, 4205 .dev_close = bnxt_dev_close_op, 4206 .dev_configure = bnxt_dev_configure_op, 4207 .dev_start = bnxt_dev_start_op, 4208 .dev_stop = bnxt_dev_stop_op, 4209 .dev_set_link_up = bnxt_dev_set_link_up_op, 4210 .dev_set_link_down = bnxt_dev_set_link_down_op, 4211 .stats_get = bnxt_stats_get_op, 4212 .stats_reset = bnxt_stats_reset_op, 4213 .rx_queue_setup = bnxt_rx_queue_setup_op, 4214 .rx_queue_release = bnxt_rx_queue_release_op, 4215 .tx_queue_setup = bnxt_tx_queue_setup_op, 4216 .tx_queue_release = bnxt_tx_queue_release_op, 4217 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 4218 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 4219 .reta_update = bnxt_reta_update_op, 4220 .reta_query = bnxt_reta_query_op, 4221 .rss_hash_update = bnxt_rss_hash_update_op, 4222 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 4223 .link_update = bnxt_link_update_op, 4224 .promiscuous_enable = bnxt_promiscuous_enable_op, 4225 .promiscuous_disable = bnxt_promiscuous_disable_op, 4226 .allmulticast_enable = bnxt_allmulticast_enable_op, 4227 .allmulticast_disable = bnxt_allmulticast_disable_op, 4228 .mac_addr_add = bnxt_mac_addr_add_op, 4229 .mac_addr_remove = bnxt_mac_addr_remove_op, 4230 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 4231 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 4232 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 4233 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 4234 .vlan_filter_set = bnxt_vlan_filter_set_op, 4235 .vlan_offload_set = bnxt_vlan_offload_set_op, 4236 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 4237 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 4238 .mtu_set = bnxt_mtu_set_op, 4239 .mac_addr_set = bnxt_set_default_mac_addr_op, 4240 .xstats_get = bnxt_dev_xstats_get_op, 4241 .xstats_get_names = bnxt_dev_xstats_get_names_op, 4242 .xstats_reset = bnxt_dev_xstats_reset_op, 4243 .fw_version_get = bnxt_fw_version_get, 4244 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 4245 .rxq_info_get = bnxt_rxq_info_get_op, 4246 .txq_info_get = bnxt_txq_info_get_op, 4247 .dev_led_on = bnxt_dev_led_on_op, 4248 .dev_led_off = bnxt_dev_led_off_op, 4249 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op, 4250 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op, 4251 .rx_queue_count = bnxt_rx_queue_count_op, 4252 .rx_descriptor_status = bnxt_rx_descriptor_status_op, 4253 .tx_descriptor_status = bnxt_tx_descriptor_status_op, 4254 .rx_queue_start = bnxt_rx_queue_start, 4255 .rx_queue_stop = bnxt_rx_queue_stop, 4256 .tx_queue_start = bnxt_tx_queue_start, 4257 .tx_queue_stop = bnxt_tx_queue_stop, 4258 .filter_ctrl = bnxt_filter_ctrl_op, 4259 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 4260 .get_eeprom_length = bnxt_get_eeprom_length_op, 4261 .get_eeprom = bnxt_get_eeprom_op, 4262 .set_eeprom = bnxt_set_eeprom_op, 4263 .timesync_enable = bnxt_timesync_enable, 4264 .timesync_disable = bnxt_timesync_disable, 4265 .timesync_read_time = bnxt_timesync_read_time, 4266 .timesync_write_time = bnxt_timesync_write_time, 4267 .timesync_adjust_time = bnxt_timesync_adjust_time, 4268 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 4269 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 4270 }; 4271 4272 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 4273 { 4274 uint32_t offset; 4275 4276 /* Only pre-map the reset GRC registers using window 3 */ 4277 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 4278 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 4279 4280 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 4281 4282 return offset; 4283 } 4284 4285 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 4286 { 4287 struct bnxt_error_recovery_info *info = bp->recovery_info; 4288 uint32_t reg_base = 0xffffffff; 4289 int i; 4290 4291 /* Only pre-map the monitoring GRC registers using window 2 */ 4292 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 4293 uint32_t reg = info->status_regs[i]; 4294 4295 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 4296 continue; 4297 4298 if (reg_base == 0xffffffff) 4299 reg_base = reg & 0xfffff000; 4300 if ((reg & 0xfffff000) != reg_base) 4301 return -ERANGE; 4302 4303 /* Use mask 0xffc as the Lower 2 bits indicates 4304 * address space location 4305 */ 4306 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 4307 (reg & 0xffc); 4308 } 4309 4310 if (reg_base == 0xffffffff) 4311 return 0; 4312 4313 rte_write32(reg_base, (uint8_t *)bp->bar0 + 4314 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4315 4316 return 0; 4317 } 4318 4319 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 4320 { 4321 struct bnxt_error_recovery_info *info = bp->recovery_info; 4322 uint32_t delay = info->delay_after_reset[index]; 4323 uint32_t val = info->reset_reg_val[index]; 4324 uint32_t reg = info->reset_reg[index]; 4325 uint32_t type, offset; 4326 4327 type = BNXT_FW_STATUS_REG_TYPE(reg); 4328 offset = BNXT_FW_STATUS_REG_OFF(reg); 4329 4330 switch (type) { 4331 case BNXT_FW_STATUS_REG_TYPE_CFG: 4332 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 4333 break; 4334 case BNXT_FW_STATUS_REG_TYPE_GRC: 4335 offset = bnxt_map_reset_regs(bp, offset); 4336 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4337 break; 4338 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4339 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4340 break; 4341 } 4342 /* wait on a specific interval of time until core reset is complete */ 4343 if (delay) 4344 rte_delay_ms(delay); 4345 } 4346 4347 static void bnxt_dev_cleanup(struct bnxt *bp) 4348 { 4349 bnxt_set_hwrm_link_config(bp, false); 4350 bp->link_info->link_up = 0; 4351 if (bp->eth_dev->data->dev_started) 4352 bnxt_dev_stop_op(bp->eth_dev); 4353 4354 bnxt_uninit_resources(bp, true); 4355 } 4356 4357 static int bnxt_restore_vlan_filters(struct bnxt *bp) 4358 { 4359 struct rte_eth_dev *dev = bp->eth_dev; 4360 struct rte_vlan_filter_conf *vfc; 4361 int vidx, vbit, rc; 4362 uint16_t vlan_id; 4363 4364 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 4365 vfc = &dev->data->vlan_filter_conf; 4366 vidx = vlan_id / 64; 4367 vbit = vlan_id % 64; 4368 4369 /* Each bit corresponds to a VLAN id */ 4370 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 4371 rc = bnxt_add_vlan_filter(bp, vlan_id); 4372 if (rc) 4373 return rc; 4374 } 4375 } 4376 4377 return 0; 4378 } 4379 4380 static int bnxt_restore_mac_filters(struct bnxt *bp) 4381 { 4382 struct rte_eth_dev *dev = bp->eth_dev; 4383 struct rte_eth_dev_info dev_info; 4384 struct rte_ether_addr *addr; 4385 uint64_t pool_mask; 4386 uint32_t pool = 0; 4387 uint16_t i; 4388 int rc; 4389 4390 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) 4391 return 0; 4392 4393 rc = bnxt_dev_info_get_op(dev, &dev_info); 4394 if (rc) 4395 return rc; 4396 4397 /* replay MAC address configuration */ 4398 for (i = 1; i < dev_info.max_mac_addrs; i++) { 4399 addr = &dev->data->mac_addrs[i]; 4400 4401 /* skip zero address */ 4402 if (rte_is_zero_ether_addr(addr)) 4403 continue; 4404 4405 pool = 0; 4406 pool_mask = dev->data->mac_pool_sel[i]; 4407 4408 do { 4409 if (pool_mask & 1ULL) { 4410 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 4411 if (rc) 4412 return rc; 4413 } 4414 pool_mask >>= 1; 4415 pool++; 4416 } while (pool_mask); 4417 } 4418 4419 return 0; 4420 } 4421 4422 static int bnxt_restore_filters(struct bnxt *bp) 4423 { 4424 struct rte_eth_dev *dev = bp->eth_dev; 4425 int ret = 0; 4426 4427 if (dev->data->all_multicast) { 4428 ret = bnxt_allmulticast_enable_op(dev); 4429 if (ret) 4430 return ret; 4431 } 4432 if (dev->data->promiscuous) { 4433 ret = bnxt_promiscuous_enable_op(dev); 4434 if (ret) 4435 return ret; 4436 } 4437 4438 ret = bnxt_restore_mac_filters(bp); 4439 if (ret) 4440 return ret; 4441 4442 ret = bnxt_restore_vlan_filters(bp); 4443 /* TODO restore other filters as well */ 4444 return ret; 4445 } 4446 4447 static void bnxt_dev_recover(void *arg) 4448 { 4449 struct bnxt *bp = arg; 4450 int timeout = bp->fw_reset_max_msecs; 4451 int rc = 0; 4452 4453 /* Clear Error flag so that device re-init should happen */ 4454 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 4455 4456 do { 4457 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT); 4458 if (rc == 0) 4459 break; 4460 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 4461 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 4462 } while (rc && timeout); 4463 4464 if (rc) { 4465 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 4466 goto err; 4467 } 4468 4469 rc = bnxt_init_resources(bp, true); 4470 if (rc) { 4471 PMD_DRV_LOG(ERR, 4472 "Failed to initialize resources after reset\n"); 4473 goto err; 4474 } 4475 /* clear reset flag as the device is initialized now */ 4476 bp->flags &= ~BNXT_FLAG_FW_RESET; 4477 4478 rc = bnxt_dev_start_op(bp->eth_dev); 4479 if (rc) { 4480 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 4481 goto err_start; 4482 } 4483 4484 rc = bnxt_restore_filters(bp); 4485 if (rc) 4486 goto err_start; 4487 4488 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 4489 return; 4490 err_start: 4491 bnxt_dev_stop_op(bp->eth_dev); 4492 err: 4493 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4494 bnxt_uninit_resources(bp, false); 4495 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 4496 } 4497 4498 void bnxt_dev_reset_and_resume(void *arg) 4499 { 4500 struct bnxt *bp = arg; 4501 int rc; 4502 4503 bnxt_dev_cleanup(bp); 4504 4505 bnxt_wait_for_device_shutdown(bp); 4506 4507 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, 4508 bnxt_dev_recover, (void *)bp); 4509 if (rc) 4510 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 4511 } 4512 4513 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 4514 { 4515 struct bnxt_error_recovery_info *info = bp->recovery_info; 4516 uint32_t reg = info->status_regs[index]; 4517 uint32_t type, offset, val = 0; 4518 4519 type = BNXT_FW_STATUS_REG_TYPE(reg); 4520 offset = BNXT_FW_STATUS_REG_OFF(reg); 4521 4522 switch (type) { 4523 case BNXT_FW_STATUS_REG_TYPE_CFG: 4524 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 4525 break; 4526 case BNXT_FW_STATUS_REG_TYPE_GRC: 4527 offset = info->mapped_status_regs[index]; 4528 /* FALLTHROUGH */ 4529 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4530 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4531 offset)); 4532 break; 4533 } 4534 4535 return val; 4536 } 4537 4538 static int bnxt_fw_reset_all(struct bnxt *bp) 4539 { 4540 struct bnxt_error_recovery_info *info = bp->recovery_info; 4541 uint32_t i; 4542 int rc = 0; 4543 4544 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4545 /* Reset through master function driver */ 4546 for (i = 0; i < info->reg_array_cnt; i++) 4547 bnxt_write_fw_reset_reg(bp, i); 4548 /* Wait for time specified by FW after triggering reset */ 4549 rte_delay_ms(info->master_func_wait_period_after_reset); 4550 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 4551 /* Reset with the help of Kong processor */ 4552 rc = bnxt_hwrm_fw_reset(bp); 4553 if (rc) 4554 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 4555 } 4556 4557 return rc; 4558 } 4559 4560 static void bnxt_fw_reset_cb(void *arg) 4561 { 4562 struct bnxt *bp = arg; 4563 struct bnxt_error_recovery_info *info = bp->recovery_info; 4564 int rc = 0; 4565 4566 /* Only Master function can do FW reset */ 4567 if (bnxt_is_master_func(bp) && 4568 bnxt_is_recovery_enabled(bp)) { 4569 rc = bnxt_fw_reset_all(bp); 4570 if (rc) { 4571 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 4572 return; 4573 } 4574 } 4575 4576 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 4577 * EXCEPTION_FATAL_ASYNC event to all the functions 4578 * (including MASTER FUNC). After receiving this Async, all the active 4579 * drivers should treat this case as FW initiated recovery 4580 */ 4581 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4582 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 4583 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 4584 4585 /* To recover from error */ 4586 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 4587 (void *)bp); 4588 } 4589 } 4590 4591 /* Driver should poll FW heartbeat, reset_counter with the frequency 4592 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 4593 * When the driver detects heartbeat stop or change in reset_counter, 4594 * it has to trigger a reset to recover from the error condition. 4595 * A “master PF” is the function who will have the privilege to 4596 * initiate the chimp reset. The master PF will be elected by the 4597 * firmware and will be notified through async message. 4598 */ 4599 static void bnxt_check_fw_health(void *arg) 4600 { 4601 struct bnxt *bp = arg; 4602 struct bnxt_error_recovery_info *info = bp->recovery_info; 4603 uint32_t val = 0, wait_msec; 4604 4605 if (!info || !bnxt_is_recovery_enabled(bp) || 4606 is_bnxt_in_error(bp)) 4607 return; 4608 4609 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4610 if (val == info->last_heart_beat) 4611 goto reset; 4612 4613 info->last_heart_beat = val; 4614 4615 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4616 if (val != info->last_reset_counter) 4617 goto reset; 4618 4619 info->last_reset_counter = val; 4620 4621 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4622 bnxt_check_fw_health, (void *)bp); 4623 4624 return; 4625 reset: 4626 /* Stop DMA to/from device */ 4627 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4628 bp->flags |= BNXT_FLAG_FW_RESET; 4629 4630 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4631 4632 if (bnxt_is_master_func(bp)) 4633 wait_msec = info->master_func_wait_period; 4634 else 4635 wait_msec = info->normal_func_wait_period; 4636 4637 rte_eal_alarm_set(US_PER_MS * wait_msec, 4638 bnxt_fw_reset_cb, (void *)bp); 4639 } 4640 4641 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4642 { 4643 uint32_t polling_freq; 4644 4645 if (!bnxt_is_recovery_enabled(bp)) 4646 return; 4647 4648 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4649 return; 4650 4651 polling_freq = bp->recovery_info->driver_polling_freq; 4652 4653 rte_eal_alarm_set(US_PER_MS * polling_freq, 4654 bnxt_check_fw_health, (void *)bp); 4655 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4656 } 4657 4658 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4659 { 4660 if (!bnxt_is_recovery_enabled(bp)) 4661 return; 4662 4663 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4664 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4665 } 4666 4667 static bool bnxt_vf_pciid(uint16_t device_id) 4668 { 4669 switch (device_id) { 4670 case BROADCOM_DEV_ID_57304_VF: 4671 case BROADCOM_DEV_ID_57406_VF: 4672 case BROADCOM_DEV_ID_5731X_VF: 4673 case BROADCOM_DEV_ID_5741X_VF: 4674 case BROADCOM_DEV_ID_57414_VF: 4675 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4676 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4677 case BROADCOM_DEV_ID_58802_VF: 4678 case BROADCOM_DEV_ID_57500_VF1: 4679 case BROADCOM_DEV_ID_57500_VF2: 4680 /* FALLTHROUGH */ 4681 return true; 4682 default: 4683 return false; 4684 } 4685 } 4686 4687 static bool bnxt_thor_device(uint16_t device_id) 4688 { 4689 switch (device_id) { 4690 case BROADCOM_DEV_ID_57508: 4691 case BROADCOM_DEV_ID_57504: 4692 case BROADCOM_DEV_ID_57502: 4693 case BROADCOM_DEV_ID_57508_MF1: 4694 case BROADCOM_DEV_ID_57504_MF1: 4695 case BROADCOM_DEV_ID_57502_MF1: 4696 case BROADCOM_DEV_ID_57508_MF2: 4697 case BROADCOM_DEV_ID_57504_MF2: 4698 case BROADCOM_DEV_ID_57502_MF2: 4699 case BROADCOM_DEV_ID_57500_VF1: 4700 case BROADCOM_DEV_ID_57500_VF2: 4701 /* FALLTHROUGH */ 4702 return true; 4703 default: 4704 return false; 4705 } 4706 } 4707 4708 bool bnxt_stratus_device(struct bnxt *bp) 4709 { 4710 uint16_t device_id = bp->pdev->id.device_id; 4711 4712 switch (device_id) { 4713 case BROADCOM_DEV_ID_STRATUS_NIC: 4714 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4715 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4716 /* FALLTHROUGH */ 4717 return true; 4718 default: 4719 return false; 4720 } 4721 } 4722 4723 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 4724 { 4725 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4726 struct bnxt *bp = eth_dev->data->dev_private; 4727 4728 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4729 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4730 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4731 if (!bp->bar0 || !bp->doorbell_base) { 4732 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4733 return -ENODEV; 4734 } 4735 4736 bp->eth_dev = eth_dev; 4737 bp->pdev = pci_dev; 4738 4739 return 0; 4740 } 4741 4742 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4743 struct bnxt_ctx_pg_info *ctx_pg, 4744 uint32_t mem_size, 4745 const char *suffix, 4746 uint16_t idx) 4747 { 4748 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4749 const struct rte_memzone *mz = NULL; 4750 char mz_name[RTE_MEMZONE_NAMESIZE]; 4751 rte_iova_t mz_phys_addr; 4752 uint64_t valid_bits = 0; 4753 uint32_t sz; 4754 int i; 4755 4756 if (!mem_size) 4757 return 0; 4758 4759 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4760 BNXT_PAGE_SIZE; 4761 rmem->page_size = BNXT_PAGE_SIZE; 4762 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4763 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4764 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4765 4766 valid_bits = PTU_PTE_VALID; 4767 4768 if (rmem->nr_pages > 1) { 4769 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4770 "bnxt_ctx_pg_tbl%s_%x_%d", 4771 suffix, idx, bp->eth_dev->data->port_id); 4772 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4773 mz = rte_memzone_lookup(mz_name); 4774 if (!mz) { 4775 mz = rte_memzone_reserve_aligned(mz_name, 4776 rmem->nr_pages * 8, 4777 SOCKET_ID_ANY, 4778 RTE_MEMZONE_2MB | 4779 RTE_MEMZONE_SIZE_HINT_ONLY | 4780 RTE_MEMZONE_IOVA_CONTIG, 4781 BNXT_PAGE_SIZE); 4782 if (mz == NULL) 4783 return -ENOMEM; 4784 } 4785 4786 memset(mz->addr, 0, mz->len); 4787 mz_phys_addr = mz->iova; 4788 4789 rmem->pg_tbl = mz->addr; 4790 rmem->pg_tbl_map = mz_phys_addr; 4791 rmem->pg_tbl_mz = mz; 4792 } 4793 4794 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4795 suffix, idx, bp->eth_dev->data->port_id); 4796 mz = rte_memzone_lookup(mz_name); 4797 if (!mz) { 4798 mz = rte_memzone_reserve_aligned(mz_name, 4799 mem_size, 4800 SOCKET_ID_ANY, 4801 RTE_MEMZONE_1GB | 4802 RTE_MEMZONE_SIZE_HINT_ONLY | 4803 RTE_MEMZONE_IOVA_CONTIG, 4804 BNXT_PAGE_SIZE); 4805 if (mz == NULL) 4806 return -ENOMEM; 4807 } 4808 4809 memset(mz->addr, 0, mz->len); 4810 mz_phys_addr = mz->iova; 4811 4812 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4813 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4814 rmem->dma_arr[i] = mz_phys_addr + sz; 4815 4816 if (rmem->nr_pages > 1) { 4817 if (i == rmem->nr_pages - 2 && 4818 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4819 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4820 else if (i == rmem->nr_pages - 1 && 4821 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4822 valid_bits |= PTU_PTE_LAST; 4823 4824 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4825 valid_bits); 4826 } 4827 } 4828 4829 rmem->mz = mz; 4830 if (rmem->vmem_size) 4831 rmem->vmem = (void **)mz->addr; 4832 rmem->dma_arr[0] = mz_phys_addr; 4833 return 0; 4834 } 4835 4836 static void bnxt_free_ctx_mem(struct bnxt *bp) 4837 { 4838 int i; 4839 4840 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4841 return; 4842 4843 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4844 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4845 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4846 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4847 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4848 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4849 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4850 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4851 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4852 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4853 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4854 4855 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) { 4856 if (bp->ctx->tqm_mem[i]) 4857 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4858 } 4859 4860 rte_free(bp->ctx); 4861 bp->ctx = NULL; 4862 } 4863 4864 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4865 4866 #define min_t(type, x, y) ({ \ 4867 type __min1 = (x); \ 4868 type __min2 = (y); \ 4869 __min1 < __min2 ? __min1 : __min2; }) 4870 4871 #define max_t(type, x, y) ({ \ 4872 type __max1 = (x); \ 4873 type __max2 = (y); \ 4874 __max1 > __max2 ? __max1 : __max2; }) 4875 4876 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4877 4878 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4879 { 4880 struct bnxt_ctx_pg_info *ctx_pg; 4881 struct bnxt_ctx_mem_info *ctx; 4882 uint32_t mem_size, ena, entries; 4883 uint32_t entries_sp, min; 4884 int i, rc; 4885 4886 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4887 if (rc) { 4888 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4889 return rc; 4890 } 4891 ctx = bp->ctx; 4892 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4893 return 0; 4894 4895 ctx_pg = &ctx->qp_mem; 4896 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4897 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4898 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4899 if (rc) 4900 return rc; 4901 4902 ctx_pg = &ctx->srq_mem; 4903 ctx_pg->entries = ctx->srq_max_l2_entries; 4904 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4905 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4906 if (rc) 4907 return rc; 4908 4909 ctx_pg = &ctx->cq_mem; 4910 ctx_pg->entries = ctx->cq_max_l2_entries; 4911 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4912 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4913 if (rc) 4914 return rc; 4915 4916 ctx_pg = &ctx->vnic_mem; 4917 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4918 ctx->vnic_max_ring_table_entries; 4919 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4920 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4921 if (rc) 4922 return rc; 4923 4924 ctx_pg = &ctx->stat_mem; 4925 ctx_pg->entries = ctx->stat_max_entries; 4926 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4927 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4928 if (rc) 4929 return rc; 4930 4931 min = ctx->tqm_min_entries_per_ring; 4932 4933 entries_sp = ctx->qp_max_l2_entries + 4934 ctx->vnic_max_vnic_entries + 4935 2 * ctx->qp_min_qp1_entries + min; 4936 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple); 4937 4938 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries; 4939 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4940 entries = clamp_t(uint32_t, entries, min, 4941 ctx->tqm_max_entries_per_ring); 4942 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 4943 ctx_pg = ctx->tqm_mem[i]; 4944 ctx_pg->entries = i ? entries : entries_sp; 4945 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4946 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i); 4947 if (rc) 4948 return rc; 4949 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4950 } 4951 4952 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4953 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4954 if (rc) 4955 PMD_DRV_LOG(ERR, 4956 "Failed to configure context mem: rc = %d\n", rc); 4957 else 4958 ctx->flags |= BNXT_CTX_FLAG_INITED; 4959 4960 return rc; 4961 } 4962 4963 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4964 { 4965 struct rte_pci_device *pci_dev = bp->pdev; 4966 char mz_name[RTE_MEMZONE_NAMESIZE]; 4967 const struct rte_memzone *mz = NULL; 4968 uint32_t total_alloc_len; 4969 rte_iova_t mz_phys_addr; 4970 4971 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4972 return 0; 4973 4974 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4975 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4976 pci_dev->addr.bus, pci_dev->addr.devid, 4977 pci_dev->addr.function, "rx_port_stats"); 4978 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4979 mz = rte_memzone_lookup(mz_name); 4980 total_alloc_len = 4981 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4982 sizeof(struct rx_port_stats_ext) + 512); 4983 if (!mz) { 4984 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4985 SOCKET_ID_ANY, 4986 RTE_MEMZONE_2MB | 4987 RTE_MEMZONE_SIZE_HINT_ONLY | 4988 RTE_MEMZONE_IOVA_CONTIG); 4989 if (mz == NULL) 4990 return -ENOMEM; 4991 } 4992 memset(mz->addr, 0, mz->len); 4993 mz_phys_addr = mz->iova; 4994 4995 bp->rx_mem_zone = (const void *)mz; 4996 bp->hw_rx_port_stats = mz->addr; 4997 bp->hw_rx_port_stats_map = mz_phys_addr; 4998 4999 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 5000 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 5001 pci_dev->addr.bus, pci_dev->addr.devid, 5002 pci_dev->addr.function, "tx_port_stats"); 5003 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 5004 mz = rte_memzone_lookup(mz_name); 5005 total_alloc_len = 5006 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 5007 sizeof(struct tx_port_stats_ext) + 512); 5008 if (!mz) { 5009 mz = rte_memzone_reserve(mz_name, 5010 total_alloc_len, 5011 SOCKET_ID_ANY, 5012 RTE_MEMZONE_2MB | 5013 RTE_MEMZONE_SIZE_HINT_ONLY | 5014 RTE_MEMZONE_IOVA_CONTIG); 5015 if (mz == NULL) 5016 return -ENOMEM; 5017 } 5018 memset(mz->addr, 0, mz->len); 5019 mz_phys_addr = mz->iova; 5020 5021 bp->tx_mem_zone = (const void *)mz; 5022 bp->hw_tx_port_stats = mz->addr; 5023 bp->hw_tx_port_stats_map = mz_phys_addr; 5024 bp->flags |= BNXT_FLAG_PORT_STATS; 5025 5026 /* Display extended statistics if FW supports it */ 5027 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 5028 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 5029 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 5030 return 0; 5031 5032 bp->hw_rx_port_stats_ext = (void *) 5033 ((uint8_t *)bp->hw_rx_port_stats + 5034 sizeof(struct rx_port_stats)); 5035 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 5036 sizeof(struct rx_port_stats); 5037 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 5038 5039 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 5040 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 5041 bp->hw_tx_port_stats_ext = (void *) 5042 ((uint8_t *)bp->hw_tx_port_stats + 5043 sizeof(struct tx_port_stats)); 5044 bp->hw_tx_port_stats_ext_map = 5045 bp->hw_tx_port_stats_map + 5046 sizeof(struct tx_port_stats); 5047 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 5048 } 5049 5050 return 0; 5051 } 5052 5053 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 5054 { 5055 struct bnxt *bp = eth_dev->data->dev_private; 5056 int rc = 0; 5057 5058 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 5059 RTE_ETHER_ADDR_LEN * 5060 bp->max_l2_ctx, 5061 0); 5062 if (eth_dev->data->mac_addrs == NULL) { 5063 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 5064 return -ENOMEM; 5065 } 5066 5067 if (!BNXT_HAS_DFLT_MAC_SET(bp)) { 5068 if (BNXT_PF(bp)) 5069 return -EINVAL; 5070 5071 /* Generate a random MAC address, if none was assigned by PF */ 5072 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 5073 bnxt_eth_hw_addr_random(bp->mac_addr); 5074 PMD_DRV_LOG(INFO, 5075 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 5076 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 5077 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 5078 5079 rc = bnxt_hwrm_set_mac(bp); 5080 if (rc) 5081 return rc; 5082 } 5083 5084 /* Copy the permanent MAC from the FUNC_QCAPS response */ 5085 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 5086 5087 return rc; 5088 } 5089 5090 static int bnxt_restore_dflt_mac(struct bnxt *bp) 5091 { 5092 int rc = 0; 5093 5094 /* MAC is already configured in FW */ 5095 if (BNXT_HAS_DFLT_MAC_SET(bp)) 5096 return 0; 5097 5098 /* Restore the old MAC configured */ 5099 rc = bnxt_hwrm_set_mac(bp); 5100 if (rc) 5101 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 5102 5103 return rc; 5104 } 5105 5106 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 5107 { 5108 if (!BNXT_PF(bp)) 5109 return; 5110 5111 #define ALLOW_FUNC(x) \ 5112 { \ 5113 uint32_t arg = (x); \ 5114 bp->pf->vf_req_fwd[((arg) >> 5)] &= \ 5115 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \ 5116 } 5117 5118 /* Forward all requests if firmware is new enough */ 5119 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) && 5120 (bp->fw_ver < ((20 << 24) | (7 << 16)))) || 5121 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) { 5122 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd)); 5123 } else { 5124 PMD_DRV_LOG(WARNING, 5125 "Firmware too old for VF mailbox functionality\n"); 5126 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd)); 5127 } 5128 5129 /* 5130 * The following are used for driver cleanup. If we disallow these, 5131 * VF drivers can't clean up cleanly. 5132 */ 5133 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR); 5134 ALLOW_FUNC(HWRM_VNIC_FREE); 5135 ALLOW_FUNC(HWRM_RING_FREE); 5136 ALLOW_FUNC(HWRM_RING_GRP_FREE); 5137 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE); 5138 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE); 5139 ALLOW_FUNC(HWRM_STAT_CTX_FREE); 5140 ALLOW_FUNC(HWRM_PORT_PHY_QCFG); 5141 ALLOW_FUNC(HWRM_VNIC_TPA_CFG); 5142 } 5143 5144 uint16_t 5145 bnxt_get_svif(uint16_t port_id, bool func_svif, 5146 enum bnxt_ulp_intf_type type) 5147 { 5148 struct rte_eth_dev *eth_dev; 5149 struct bnxt *bp; 5150 5151 eth_dev = &rte_eth_devices[port_id]; 5152 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5153 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private; 5154 if (!vfr) 5155 return 0; 5156 5157 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5158 return vfr->svif; 5159 5160 eth_dev = vfr->parent_dev; 5161 } 5162 5163 bp = eth_dev->data->dev_private; 5164 5165 return func_svif ? bp->func_svif : bp->port_svif; 5166 } 5167 5168 uint16_t 5169 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 5170 { 5171 struct rte_eth_dev *eth_dev; 5172 struct bnxt_vnic_info *vnic; 5173 struct bnxt *bp; 5174 5175 eth_dev = &rte_eth_devices[port]; 5176 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5177 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private; 5178 if (!vfr) 5179 return 0; 5180 5181 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5182 return vfr->dflt_vnic_id; 5183 5184 eth_dev = vfr->parent_dev; 5185 } 5186 5187 bp = eth_dev->data->dev_private; 5188 5189 vnic = BNXT_GET_DEFAULT_VNIC(bp); 5190 5191 return vnic->fw_vnic_id; 5192 } 5193 5194 uint16_t 5195 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) 5196 { 5197 struct rte_eth_dev *eth_dev; 5198 struct bnxt *bp; 5199 5200 eth_dev = &rte_eth_devices[port]; 5201 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5202 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private; 5203 if (!vfr) 5204 return 0; 5205 5206 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5207 return vfr->fw_fid; 5208 5209 eth_dev = vfr->parent_dev; 5210 } 5211 5212 bp = eth_dev->data->dev_private; 5213 5214 return bp->fw_fid; 5215 } 5216 5217 enum bnxt_ulp_intf_type 5218 bnxt_get_interface_type(uint16_t port) 5219 { 5220 struct rte_eth_dev *eth_dev; 5221 struct bnxt *bp; 5222 5223 eth_dev = &rte_eth_devices[port]; 5224 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) 5225 return BNXT_ULP_INTF_TYPE_VF_REP; 5226 5227 bp = eth_dev->data->dev_private; 5228 if (BNXT_PF(bp)) 5229 return BNXT_ULP_INTF_TYPE_PF; 5230 else if (BNXT_VF_IS_TRUSTED(bp)) 5231 return BNXT_ULP_INTF_TYPE_TRUSTED_VF; 5232 else if (BNXT_VF(bp)) 5233 return BNXT_ULP_INTF_TYPE_VF; 5234 5235 return BNXT_ULP_INTF_TYPE_INVALID; 5236 } 5237 5238 uint16_t 5239 bnxt_get_phy_port_id(uint16_t port_id) 5240 { 5241 struct bnxt_vf_representor *vfr; 5242 struct rte_eth_dev *eth_dev; 5243 struct bnxt *bp; 5244 5245 eth_dev = &rte_eth_devices[port_id]; 5246 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5247 vfr = eth_dev->data->dev_private; 5248 if (!vfr) 5249 return 0; 5250 5251 eth_dev = vfr->parent_dev; 5252 } 5253 5254 bp = eth_dev->data->dev_private; 5255 5256 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; 5257 } 5258 5259 uint16_t 5260 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) 5261 { 5262 struct rte_eth_dev *eth_dev; 5263 struct bnxt *bp; 5264 5265 eth_dev = &rte_eth_devices[port_id]; 5266 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5267 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private; 5268 if (!vfr) 5269 return 0; 5270 5271 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5272 return vfr->fw_fid - 1; 5273 5274 eth_dev = vfr->parent_dev; 5275 } 5276 5277 bp = eth_dev->data->dev_private; 5278 5279 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; 5280 } 5281 5282 uint16_t 5283 bnxt_get_vport(uint16_t port_id) 5284 { 5285 return (1 << bnxt_get_phy_port_id(port_id)); 5286 } 5287 5288 static void bnxt_alloc_error_recovery_info(struct bnxt *bp) 5289 { 5290 struct bnxt_error_recovery_info *info = bp->recovery_info; 5291 5292 if (info) { 5293 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)) 5294 memset(info, 0, sizeof(*info)); 5295 return; 5296 } 5297 5298 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 5299 return; 5300 5301 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5302 sizeof(*info), 0); 5303 if (!info) 5304 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5305 5306 bp->recovery_info = info; 5307 } 5308 5309 static void bnxt_check_fw_status(struct bnxt *bp) 5310 { 5311 uint32_t fw_status; 5312 5313 if (!(bp->recovery_info && 5314 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))) 5315 return; 5316 5317 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG); 5318 if (fw_status != BNXT_FW_STATUS_HEALTHY) 5319 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n", 5320 fw_status); 5321 } 5322 5323 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) 5324 { 5325 struct bnxt_error_recovery_info *info = bp->recovery_info; 5326 uint32_t status_loc; 5327 uint32_t sig_ver; 5328 5329 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 + 5330 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5331 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5332 BNXT_GRCP_WINDOW_2_BASE + 5333 offsetof(struct hcomm_status, 5334 sig_ver))); 5335 /* If the signature is absent, then FW does not support this feature */ 5336 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) != 5337 HCOMM_STATUS_SIGNATURE_VAL) 5338 return 0; 5339 5340 if (!info) { 5341 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5342 sizeof(*info), 0); 5343 if (!info) 5344 return -ENOMEM; 5345 bp->recovery_info = info; 5346 } else { 5347 memset(info, 0, sizeof(*info)); 5348 } 5349 5350 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5351 BNXT_GRCP_WINDOW_2_BASE + 5352 offsetof(struct hcomm_status, 5353 fw_status_loc))); 5354 5355 /* Only pre-map the FW health status GRC register */ 5356 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC) 5357 return 0; 5358 5359 info->status_regs[BNXT_FW_STATUS_REG] = status_loc; 5360 info->mapped_status_regs[BNXT_FW_STATUS_REG] = 5361 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK); 5362 5363 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 + 5364 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5365 5366 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS; 5367 5368 return 0; 5369 } 5370 5371 static int bnxt_init_fw(struct bnxt *bp) 5372 { 5373 uint16_t mtu; 5374 int rc = 0; 5375 5376 bp->fw_cap = 0; 5377 5378 rc = bnxt_map_hcomm_fw_status_reg(bp); 5379 if (rc) 5380 return rc; 5381 5382 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT); 5383 if (rc) { 5384 bnxt_check_fw_status(bp); 5385 return rc; 5386 } 5387 5388 rc = bnxt_hwrm_func_reset(bp); 5389 if (rc) 5390 return -EIO; 5391 5392 rc = bnxt_hwrm_vnic_qcaps(bp); 5393 if (rc) 5394 return rc; 5395 5396 rc = bnxt_hwrm_queue_qportcfg(bp); 5397 if (rc) 5398 return rc; 5399 5400 /* Get the MAX capabilities for this function. 5401 * This function also allocates context memory for TQM rings and 5402 * informs the firmware about this allocated backing store memory. 5403 */ 5404 rc = bnxt_hwrm_func_qcaps(bp); 5405 if (rc) 5406 return rc; 5407 5408 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 5409 if (rc) 5410 return rc; 5411 5412 bnxt_hwrm_port_mac_qcfg(bp); 5413 5414 bnxt_hwrm_parent_pf_qcfg(bp); 5415 5416 bnxt_hwrm_port_phy_qcaps(bp); 5417 5418 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 5419 if (rc) 5420 return rc; 5421 5422 bnxt_alloc_error_recovery_info(bp); 5423 /* Get the adapter error recovery support info */ 5424 rc = bnxt_hwrm_error_recovery_qcfg(bp); 5425 if (rc) 5426 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5427 5428 bnxt_hwrm_port_led_qcaps(bp); 5429 5430 return 0; 5431 } 5432 5433 static int 5434 bnxt_init_locks(struct bnxt *bp) 5435 { 5436 int err; 5437 5438 err = pthread_mutex_init(&bp->flow_lock, NULL); 5439 if (err) { 5440 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 5441 return err; 5442 } 5443 5444 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 5445 if (err) 5446 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 5447 return err; 5448 } 5449 5450 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 5451 { 5452 int rc = 0; 5453 5454 rc = bnxt_init_fw(bp); 5455 if (rc) 5456 return rc; 5457 5458 if (!reconfig_dev) { 5459 rc = bnxt_setup_mac_addr(bp->eth_dev); 5460 if (rc) 5461 return rc; 5462 } else { 5463 rc = bnxt_restore_dflt_mac(bp); 5464 if (rc) 5465 return rc; 5466 } 5467 5468 bnxt_config_vf_req_fwd(bp); 5469 5470 rc = bnxt_hwrm_func_driver_register(bp); 5471 if (rc) { 5472 PMD_DRV_LOG(ERR, "Failed to register driver"); 5473 return -EBUSY; 5474 } 5475 5476 if (BNXT_PF(bp)) { 5477 if (bp->pdev->max_vfs) { 5478 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 5479 if (rc) { 5480 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 5481 return rc; 5482 } 5483 } else { 5484 rc = bnxt_hwrm_allocate_pf_only(bp); 5485 if (rc) { 5486 PMD_DRV_LOG(ERR, 5487 "Failed to allocate PF resources"); 5488 return rc; 5489 } 5490 } 5491 } 5492 5493 rc = bnxt_alloc_mem(bp, reconfig_dev); 5494 if (rc) 5495 return rc; 5496 5497 rc = bnxt_setup_int(bp); 5498 if (rc) 5499 return rc; 5500 5501 rc = bnxt_request_int(bp); 5502 if (rc) 5503 return rc; 5504 5505 rc = bnxt_init_ctx_mem(bp); 5506 if (rc) { 5507 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n"); 5508 return rc; 5509 } 5510 5511 rc = bnxt_init_locks(bp); 5512 if (rc) 5513 return rc; 5514 5515 return 0; 5516 } 5517 5518 static int 5519 bnxt_parse_devarg_truflow(__rte_unused const char *key, 5520 const char *value, void *opaque_arg) 5521 { 5522 struct bnxt *bp = opaque_arg; 5523 unsigned long truflow; 5524 char *end = NULL; 5525 5526 if (!value || !opaque_arg) { 5527 PMD_DRV_LOG(ERR, 5528 "Invalid parameter passed to truflow devargs.\n"); 5529 return -EINVAL; 5530 } 5531 5532 truflow = strtoul(value, &end, 10); 5533 if (end == NULL || *end != '\0' || 5534 (truflow == ULONG_MAX && errno == ERANGE)) { 5535 PMD_DRV_LOG(ERR, 5536 "Invalid parameter passed to truflow devargs.\n"); 5537 return -EINVAL; 5538 } 5539 5540 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) { 5541 PMD_DRV_LOG(ERR, 5542 "Invalid value passed to truflow devargs.\n"); 5543 return -EINVAL; 5544 } 5545 5546 bp->flags |= BNXT_FLAG_TRUFLOW_EN; 5547 if (BNXT_TRUFLOW_EN(bp)) 5548 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n"); 5549 5550 return 0; 5551 } 5552 5553 static int 5554 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, 5555 const char *value, void *opaque_arg) 5556 { 5557 struct bnxt *bp = opaque_arg; 5558 unsigned long flow_xstat; 5559 char *end = NULL; 5560 5561 if (!value || !opaque_arg) { 5562 PMD_DRV_LOG(ERR, 5563 "Invalid parameter passed to flow_xstat devarg.\n"); 5564 return -EINVAL; 5565 } 5566 5567 flow_xstat = strtoul(value, &end, 10); 5568 if (end == NULL || *end != '\0' || 5569 (flow_xstat == ULONG_MAX && errno == ERANGE)) { 5570 PMD_DRV_LOG(ERR, 5571 "Invalid parameter passed to flow_xstat devarg.\n"); 5572 return -EINVAL; 5573 } 5574 5575 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) { 5576 PMD_DRV_LOG(ERR, 5577 "Invalid value passed to flow_xstat devarg.\n"); 5578 return -EINVAL; 5579 } 5580 5581 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN; 5582 if (BNXT_FLOW_XSTATS_EN(bp)) 5583 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n"); 5584 5585 return 0; 5586 } 5587 5588 static int 5589 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, 5590 const char *value, void *opaque_arg) 5591 { 5592 struct bnxt *bp = opaque_arg; 5593 unsigned long max_num_kflows; 5594 char *end = NULL; 5595 5596 if (!value || !opaque_arg) { 5597 PMD_DRV_LOG(ERR, 5598 "Invalid parameter passed to max_num_kflows devarg.\n"); 5599 return -EINVAL; 5600 } 5601 5602 max_num_kflows = strtoul(value, &end, 10); 5603 if (end == NULL || *end != '\0' || 5604 (max_num_kflows == ULONG_MAX && errno == ERANGE)) { 5605 PMD_DRV_LOG(ERR, 5606 "Invalid parameter passed to max_num_kflows devarg.\n"); 5607 return -EINVAL; 5608 } 5609 5610 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) { 5611 PMD_DRV_LOG(ERR, 5612 "Invalid value passed to max_num_kflows devarg.\n"); 5613 return -EINVAL; 5614 } 5615 5616 bp->max_num_kflows = max_num_kflows; 5617 if (bp->max_num_kflows) 5618 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n", 5619 max_num_kflows); 5620 5621 return 0; 5622 } 5623 5624 static void 5625 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) 5626 { 5627 struct rte_kvargs *kvlist; 5628 5629 if (devargs == NULL) 5630 return; 5631 5632 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); 5633 if (kvlist == NULL) 5634 return; 5635 5636 /* 5637 * Handler for "truflow" devarg. 5638 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1" 5639 */ 5640 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW, 5641 bnxt_parse_devarg_truflow, bp); 5642 5643 /* 5644 * Handler for "flow_xstat" devarg. 5645 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1" 5646 */ 5647 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, 5648 bnxt_parse_devarg_flow_xstat, bp); 5649 5650 /* 5651 * Handler for "max_num_kflows" devarg. 5652 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32" 5653 */ 5654 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, 5655 bnxt_parse_devarg_max_num_kflows, bp); 5656 5657 rte_kvargs_free(kvlist); 5658 } 5659 5660 static int bnxt_alloc_switch_domain(struct bnxt *bp) 5661 { 5662 int rc = 0; 5663 5664 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 5665 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id); 5666 if (rc) 5667 PMD_DRV_LOG(ERR, 5668 "Failed to alloc switch domain: %d\n", rc); 5669 else 5670 PMD_DRV_LOG(INFO, 5671 "Switch domain allocated %d\n", 5672 bp->switch_domain_id); 5673 } 5674 5675 return rc; 5676 } 5677 5678 static int 5679 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) 5680 { 5681 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5682 static int version_printed; 5683 struct bnxt *bp; 5684 int rc; 5685 5686 if (version_printed++ == 0) 5687 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 5688 5689 eth_dev->dev_ops = &bnxt_dev_ops; 5690 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 5691 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 5692 5693 /* 5694 * For secondary processes, we don't initialise any further 5695 * as primary has already done this work. 5696 */ 5697 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5698 return 0; 5699 5700 rte_eth_copy_pci_info(eth_dev, pci_dev); 5701 5702 bp = eth_dev->data->dev_private; 5703 5704 /* Parse dev arguments passed on when starting the DPDK application. */ 5705 bnxt_parse_dev_args(bp, pci_dev->device.devargs); 5706 5707 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 5708 5709 if (bnxt_vf_pciid(pci_dev->id.device_id)) 5710 bp->flags |= BNXT_FLAG_VF; 5711 5712 if (bnxt_thor_device(pci_dev->id.device_id)) 5713 bp->flags |= BNXT_FLAG_THOR_CHIP; 5714 5715 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 5716 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 5717 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 5718 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 5719 bp->flags |= BNXT_FLAG_STINGRAY; 5720 5721 rc = bnxt_init_board(eth_dev); 5722 if (rc) { 5723 PMD_DRV_LOG(ERR, 5724 "Failed to initialize board rc: %x\n", rc); 5725 return rc; 5726 } 5727 5728 rc = bnxt_alloc_pf_info(bp); 5729 if (rc) 5730 goto error_free; 5731 5732 rc = bnxt_alloc_link_info(bp); 5733 if (rc) 5734 goto error_free; 5735 5736 rc = bnxt_alloc_parent_info(bp); 5737 if (rc) 5738 goto error_free; 5739 5740 rc = bnxt_alloc_hwrm_resources(bp); 5741 if (rc) { 5742 PMD_DRV_LOG(ERR, 5743 "Failed to allocate hwrm resource rc: %x\n", rc); 5744 goto error_free; 5745 } 5746 rc = bnxt_alloc_leds_info(bp); 5747 if (rc) 5748 goto error_free; 5749 5750 rc = bnxt_alloc_cos_queues(bp); 5751 if (rc) 5752 goto error_free; 5753 5754 rc = bnxt_init_resources(bp, false); 5755 if (rc) 5756 goto error_free; 5757 5758 rc = bnxt_alloc_stats_mem(bp); 5759 if (rc) 5760 goto error_free; 5761 5762 bnxt_alloc_switch_domain(bp); 5763 5764 /* Pass the information to the rte_eth_dev_close() that it should also 5765 * release the private port resources. 5766 */ 5767 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 5768 5769 PMD_DRV_LOG(INFO, 5770 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", 5771 pci_dev->mem_resource[0].phys_addr, 5772 pci_dev->mem_resource[0].addr); 5773 5774 return 0; 5775 5776 error_free: 5777 bnxt_dev_uninit(eth_dev); 5778 return rc; 5779 } 5780 5781 5782 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx) 5783 { 5784 if (!ctx) 5785 return; 5786 5787 if (ctx->va) 5788 rte_free(ctx->va); 5789 5790 ctx->va = NULL; 5791 ctx->dma = RTE_BAD_IOVA; 5792 ctx->ctx_id = BNXT_CTX_VAL_INVAL; 5793 } 5794 5795 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp) 5796 { 5797 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 5798 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5799 bp->flow_stat->rx_fc_out_tbl.ctx_id, 5800 bp->flow_stat->max_fc, 5801 false); 5802 5803 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 5804 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5805 bp->flow_stat->tx_fc_out_tbl.ctx_id, 5806 bp->flow_stat->max_fc, 5807 false); 5808 5809 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5810 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id); 5811 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5812 5813 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5814 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id); 5815 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5816 5817 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5818 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id); 5819 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5820 5821 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5822 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id); 5823 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5824 } 5825 5826 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp) 5827 { 5828 bnxt_unregister_fc_ctx_mem(bp); 5829 5830 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl); 5831 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl); 5832 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl); 5833 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl); 5834 } 5835 5836 static void bnxt_uninit_ctx_mem(struct bnxt *bp) 5837 { 5838 if (BNXT_FLOW_XSTATS_EN(bp)) 5839 bnxt_uninit_fc_ctx_mem(bp); 5840 } 5841 5842 static void 5843 bnxt_free_error_recovery_info(struct bnxt *bp) 5844 { 5845 rte_free(bp->recovery_info); 5846 bp->recovery_info = NULL; 5847 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5848 } 5849 5850 static void 5851 bnxt_uninit_locks(struct bnxt *bp) 5852 { 5853 pthread_mutex_destroy(&bp->flow_lock); 5854 pthread_mutex_destroy(&bp->def_cp_lock); 5855 if (bp->rep_info) 5856 pthread_mutex_destroy(&bp->rep_info->vfr_lock); 5857 } 5858 5859 static int 5860 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 5861 { 5862 int rc; 5863 5864 bnxt_free_int(bp); 5865 bnxt_free_mem(bp, reconfig_dev); 5866 bnxt_hwrm_func_buf_unrgtr(bp); 5867 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 5868 bp->flags &= ~BNXT_FLAG_REGISTERED; 5869 bnxt_free_ctx_mem(bp); 5870 if (!reconfig_dev) { 5871 bnxt_free_hwrm_resources(bp); 5872 bnxt_free_error_recovery_info(bp); 5873 } 5874 5875 bnxt_uninit_ctx_mem(bp); 5876 5877 bnxt_uninit_locks(bp); 5878 bnxt_free_flow_stats_info(bp); 5879 bnxt_free_rep_info(bp); 5880 rte_free(bp->ptp_cfg); 5881 bp->ptp_cfg = NULL; 5882 return rc; 5883 } 5884 5885 static int 5886 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 5887 { 5888 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5889 return -EPERM; 5890 5891 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 5892 5893 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 5894 bnxt_dev_close_op(eth_dev); 5895 5896 return 0; 5897 } 5898 5899 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev) 5900 { 5901 struct bnxt *bp = eth_dev->data->dev_private; 5902 struct rte_eth_dev *vf_rep_eth_dev; 5903 int ret = 0, i; 5904 5905 if (!bp) 5906 return -EINVAL; 5907 5908 for (i = 0; i < bp->num_reps; i++) { 5909 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev; 5910 if (!vf_rep_eth_dev) 5911 continue; 5912 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit); 5913 } 5914 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit); 5915 5916 return ret; 5917 } 5918 5919 static void bnxt_free_rep_info(struct bnxt *bp) 5920 { 5921 rte_free(bp->rep_info); 5922 bp->rep_info = NULL; 5923 rte_free(bp->cfa_code_map); 5924 bp->cfa_code_map = NULL; 5925 } 5926 5927 static int bnxt_init_rep_info(struct bnxt *bp) 5928 { 5929 int i = 0, rc; 5930 5931 if (bp->rep_info) 5932 return 0; 5933 5934 bp->rep_info = rte_zmalloc("bnxt_rep_info", 5935 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, 5936 0); 5937 if (!bp->rep_info) { 5938 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); 5939 return -ENOMEM; 5940 } 5941 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map", 5942 sizeof(*bp->cfa_code_map) * 5943 BNXT_MAX_CFA_CODE, 0); 5944 if (!bp->cfa_code_map) { 5945 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n"); 5946 bnxt_free_rep_info(bp); 5947 return -ENOMEM; 5948 } 5949 5950 for (i = 0; i < BNXT_MAX_CFA_CODE; i++) 5951 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID; 5952 5953 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL); 5954 if (rc) { 5955 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n"); 5956 bnxt_free_rep_info(bp); 5957 return rc; 5958 } 5959 return rc; 5960 } 5961 5962 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, 5963 struct rte_eth_devargs eth_da, 5964 struct rte_eth_dev *backing_eth_dev) 5965 { 5966 struct rte_eth_dev *vf_rep_eth_dev; 5967 char name[RTE_ETH_NAME_MAX_LEN]; 5968 struct bnxt *backing_bp; 5969 uint16_t num_rep; 5970 int i, ret = 0; 5971 5972 num_rep = eth_da.nb_representor_ports; 5973 if (num_rep > BNXT_MAX_VF_REPS) { 5974 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", 5975 num_rep, BNXT_MAX_VF_REPS); 5976 return -EINVAL; 5977 } 5978 5979 if (num_rep > RTE_MAX_ETHPORTS) { 5980 PMD_DRV_LOG(ERR, 5981 "nb_representor_ports = %d > %d MAX ETHPORTS\n", 5982 num_rep, RTE_MAX_ETHPORTS); 5983 return -EINVAL; 5984 } 5985 5986 backing_bp = backing_eth_dev->data->dev_private; 5987 5988 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { 5989 PMD_DRV_LOG(ERR, 5990 "Not a PF or trusted VF. No Representor support\n"); 5991 /* Returning an error is not an option. 5992 * Applications are not handling this correctly 5993 */ 5994 return 0; 5995 } 5996 5997 if (bnxt_init_rep_info(backing_bp)) 5998 return 0; 5999 6000 for (i = 0; i < num_rep; i++) { 6001 struct bnxt_vf_representor representor = { 6002 .vf_id = eth_da.representor_ports[i], 6003 .switch_domain_id = backing_bp->switch_domain_id, 6004 .parent_dev = backing_eth_dev 6005 }; 6006 6007 if (representor.vf_id >= BNXT_MAX_VF_REPS) { 6008 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", 6009 representor.vf_id, BNXT_MAX_VF_REPS); 6010 continue; 6011 } 6012 6013 /* representor port net_bdf_port */ 6014 snprintf(name, sizeof(name), "net_%s_representor_%d", 6015 pci_dev->device.name, eth_da.representor_ports[i]); 6016 6017 ret = rte_eth_dev_create(&pci_dev->device, name, 6018 sizeof(struct bnxt_vf_representor), 6019 NULL, NULL, 6020 bnxt_vf_representor_init, 6021 &representor); 6022 6023 if (!ret) { 6024 vf_rep_eth_dev = rte_eth_dev_allocated(name); 6025 if (!vf_rep_eth_dev) { 6026 PMD_DRV_LOG(ERR, "Failed to find the eth_dev" 6027 " for VF-Rep: %s.", name); 6028 bnxt_pci_remove_dev_with_reps(backing_eth_dev); 6029 ret = -ENODEV; 6030 return ret; 6031 } 6032 backing_bp->rep_info[representor.vf_id].vfr_eth_dev = 6033 vf_rep_eth_dev; 6034 backing_bp->num_reps++; 6035 } else { 6036 PMD_DRV_LOG(ERR, "failed to create bnxt vf " 6037 "representor %s.", name); 6038 bnxt_pci_remove_dev_with_reps(backing_eth_dev); 6039 } 6040 } 6041 6042 return ret; 6043 } 6044 6045 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 6046 struct rte_pci_device *pci_dev) 6047 { 6048 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 6049 struct rte_eth_dev *backing_eth_dev; 6050 uint16_t num_rep; 6051 int ret = 0; 6052 6053 if (pci_dev->device.devargs) { 6054 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, 6055 ð_da); 6056 if (ret) 6057 return ret; 6058 } 6059 6060 num_rep = eth_da.nb_representor_ports; 6061 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n", 6062 num_rep); 6063 6064 /* We could come here after first level of probe is already invoked 6065 * as part of an application bringup(OVS-DPDK vswitchd), so first check 6066 * for already allocated eth_dev for the backing device (PF/Trusted VF) 6067 */ 6068 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6069 if (backing_eth_dev == NULL) { 6070 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 6071 sizeof(struct bnxt), 6072 eth_dev_pci_specific_init, pci_dev, 6073 bnxt_dev_init, NULL); 6074 6075 if (ret || !num_rep) 6076 return ret; 6077 6078 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6079 } 6080 6081 /* probe representor ports now */ 6082 ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev); 6083 6084 return ret; 6085 } 6086 6087 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 6088 { 6089 struct rte_eth_dev *eth_dev; 6090 6091 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6092 if (!eth_dev) 6093 return 0; /* Invoked typically only by OVS-DPDK, by the 6094 * time it comes here the eth_dev is already 6095 * deleted by rte_eth_dev_close(), so returning 6096 * +ve value will at least help in proper cleanup 6097 */ 6098 6099 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 6100 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 6101 return rte_eth_dev_destroy(eth_dev, 6102 bnxt_vf_representor_uninit); 6103 else 6104 return rte_eth_dev_destroy(eth_dev, 6105 bnxt_dev_uninit); 6106 } else { 6107 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 6108 } 6109 } 6110 6111 static struct rte_pci_driver bnxt_rte_pmd = { 6112 .id_table = bnxt_pci_id_map, 6113 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 6114 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs 6115 * and OVS-DPDK 6116 */ 6117 .probe = bnxt_pci_probe, 6118 .remove = bnxt_pci_remove, 6119 }; 6120 6121 static bool 6122 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 6123 { 6124 if (strcmp(dev->device->driver->name, drv->driver.name)) 6125 return false; 6126 6127 return true; 6128 } 6129 6130 bool is_bnxt_supported(struct rte_eth_dev *dev) 6131 { 6132 return is_device_supported(dev, &bnxt_rte_pmd); 6133 } 6134 6135 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE); 6136 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 6137 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 6138 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 6139