1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <ethdev_driver.h> 11 #include <ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 #include <rte_kvargs.h> 16 #include <rte_vect.h> 17 18 #include "bnxt.h" 19 #include "bnxt_filter.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_irq.h" 22 #include "bnxt_reps.h" 23 #include "bnxt_ring.h" 24 #include "bnxt_rxq.h" 25 #include "bnxt_rxr.h" 26 #include "bnxt_stats.h" 27 #include "bnxt_txq.h" 28 #include "bnxt_txr.h" 29 #include "bnxt_vnic.h" 30 #include "hsi_struct_def_dpdk.h" 31 #include "bnxt_nvm_defs.h" 32 #include "bnxt_tf_common.h" 33 #include "ulp_flow_db.h" 34 #include "rte_pmd_bnxt.h" 35 36 #define DRV_MODULE_NAME "bnxt" 37 static const char bnxt_version[] = 38 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 39 40 /* 41 * The set of PCI devices this driver supports 42 */ 43 static const struct rte_pci_id bnxt_pci_id_map[] = { 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) }, 87 { .vendor_id = 0, /* sentinel */ }, 88 }; 89 90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats" 91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" 92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" 93 #define BNXT_DEVARG_REPRESENTOR "representor" 94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf" 95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf" 96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f" 97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r" 98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f" 99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r" 100 #define BNXT_DEVARG_APP_ID "app-id" 101 102 static const char *const bnxt_dev_args[] = { 103 BNXT_DEVARG_REPRESENTOR, 104 BNXT_DEVARG_ACCUM_STATS, 105 BNXT_DEVARG_FLOW_XSTAT, 106 BNXT_DEVARG_MAX_NUM_KFLOWS, 107 BNXT_DEVARG_REP_BASED_PF, 108 BNXT_DEVARG_REP_IS_PF, 109 BNXT_DEVARG_REP_Q_R2F, 110 BNXT_DEVARG_REP_Q_F2R, 111 BNXT_DEVARG_REP_FC_R2F, 112 BNXT_DEVARG_REP_FC_F2R, 113 BNXT_DEVARG_APP_ID, 114 NULL 115 }; 116 117 /* 118 * accum-stats == false to disable flow counter accumulation 119 * accum-stats == true to enable flow counter accumulation 120 */ 121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1) 122 123 /* 124 * app-id = an non-negative 8-bit number 125 */ 126 #define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255) 127 128 /* 129 * flow_xstat == false to disable the feature 130 * flow_xstat == true to enable the feature 131 */ 132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1) 133 134 /* 135 * rep_is_pf == false to indicate VF representor 136 * rep_is_pf == true to indicate PF representor 137 */ 138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1) 139 140 /* 141 * rep_based_pf == Physical index of the PF 142 */ 143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15) 144 /* 145 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction 146 */ 147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3) 148 149 /* 150 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction 151 */ 152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3) 153 154 /* 155 * rep_fc_r2f == Flow control for the representor to endpoint direction 156 */ 157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1) 158 159 /* 160 * rep_fc_f2r == Flow control for the endpoint to representor direction 161 */ 162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1) 163 164 int bnxt_cfa_code_dynfield_offset = -1; 165 166 /* 167 * max_num_kflows must be >= 32 168 * and must be a power-of-2 supported value 169 * return: 1 -> invalid 170 * 0 -> valid 171 */ 172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows) 173 { 174 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows)) 175 return 1; 176 return 0; 177 } 178 179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 183 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 184 static int bnxt_restore_vlan_filters(struct bnxt *bp); 185 static void bnxt_dev_recover(void *arg); 186 static void bnxt_free_error_recovery_info(struct bnxt *bp); 187 static void bnxt_free_rep_info(struct bnxt *bp); 188 189 int is_bnxt_in_error(struct bnxt *bp) 190 { 191 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 192 return -EIO; 193 if (bp->flags & BNXT_FLAG_FW_RESET) 194 return -EBUSY; 195 196 return 0; 197 } 198 199 /***********************/ 200 201 /* 202 * High level utility functions 203 */ 204 205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 206 { 207 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings, 208 BNXT_RSS_TBL_SIZE_P5); 209 210 if (!BNXT_CHIP_P5(bp)) 211 return 1; 212 213 return RTE_ALIGN_MUL_CEIL(num_rss_rings, 214 BNXT_RSS_ENTRIES_PER_CTX_P5) / 215 BNXT_RSS_ENTRIES_PER_CTX_P5; 216 } 217 218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 219 { 220 if (!BNXT_CHIP_P5(bp)) 221 return HW_HASH_INDEX_SIZE; 222 223 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5; 224 } 225 226 static void bnxt_free_parent_info(struct bnxt *bp) 227 { 228 rte_free(bp->parent); 229 bp->parent = NULL; 230 } 231 232 static void bnxt_free_pf_info(struct bnxt *bp) 233 { 234 rte_free(bp->pf); 235 bp->pf = NULL; 236 } 237 238 static void bnxt_free_link_info(struct bnxt *bp) 239 { 240 rte_free(bp->link_info); 241 bp->link_info = NULL; 242 } 243 244 static void bnxt_free_leds_info(struct bnxt *bp) 245 { 246 if (BNXT_VF(bp)) 247 return; 248 249 rte_free(bp->leds); 250 bp->leds = NULL; 251 } 252 253 static void bnxt_free_flow_stats_info(struct bnxt *bp) 254 { 255 rte_free(bp->flow_stat); 256 bp->flow_stat = NULL; 257 } 258 259 static void bnxt_free_cos_queues(struct bnxt *bp) 260 { 261 rte_free(bp->rx_cos_queue); 262 bp->rx_cos_queue = NULL; 263 rte_free(bp->tx_cos_queue); 264 bp->tx_cos_queue = NULL; 265 } 266 267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 268 { 269 bnxt_free_filter_mem(bp); 270 bnxt_free_vnic_attributes(bp); 271 bnxt_free_vnic_mem(bp); 272 273 /* tx/rx rings are configured as part of *_queue_setup callbacks. 274 * If the number of rings change across fw update, 275 * we don't have much choice except to warn the user. 276 */ 277 if (!reconfig) { 278 bnxt_free_stats(bp); 279 bnxt_free_tx_rings(bp); 280 bnxt_free_rx_rings(bp); 281 } 282 bnxt_free_async_cp_ring(bp); 283 bnxt_free_rxtx_nq_ring(bp); 284 285 rte_free(bp->grp_info); 286 bp->grp_info = NULL; 287 } 288 289 static int bnxt_alloc_parent_info(struct bnxt *bp) 290 { 291 bp->parent = rte_zmalloc("bnxt_parent_info", 292 sizeof(struct bnxt_parent_info), 0); 293 if (bp->parent == NULL) 294 return -ENOMEM; 295 296 return 0; 297 } 298 299 static int bnxt_alloc_pf_info(struct bnxt *bp) 300 { 301 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0); 302 if (bp->pf == NULL) 303 return -ENOMEM; 304 305 return 0; 306 } 307 308 static int bnxt_alloc_link_info(struct bnxt *bp) 309 { 310 bp->link_info = 311 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0); 312 if (bp->link_info == NULL) 313 return -ENOMEM; 314 315 return 0; 316 } 317 318 static int bnxt_alloc_leds_info(struct bnxt *bp) 319 { 320 if (BNXT_VF(bp)) 321 return 0; 322 323 bp->leds = rte_zmalloc("bnxt_leds", 324 BNXT_MAX_LED * sizeof(struct bnxt_led_info), 325 0); 326 if (bp->leds == NULL) 327 return -ENOMEM; 328 329 return 0; 330 } 331 332 static int bnxt_alloc_cos_queues(struct bnxt *bp) 333 { 334 bp->rx_cos_queue = 335 rte_zmalloc("bnxt_rx_cosq", 336 BNXT_COS_QUEUE_COUNT * 337 sizeof(struct bnxt_cos_queue_info), 338 0); 339 if (bp->rx_cos_queue == NULL) 340 return -ENOMEM; 341 342 bp->tx_cos_queue = 343 rte_zmalloc("bnxt_tx_cosq", 344 BNXT_COS_QUEUE_COUNT * 345 sizeof(struct bnxt_cos_queue_info), 346 0); 347 if (bp->tx_cos_queue == NULL) 348 return -ENOMEM; 349 350 return 0; 351 } 352 353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp) 354 { 355 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat", 356 sizeof(struct bnxt_flow_stat_info), 0); 357 if (bp->flow_stat == NULL) 358 return -ENOMEM; 359 360 return 0; 361 } 362 363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 364 { 365 int rc; 366 367 rc = bnxt_alloc_ring_grps(bp); 368 if (rc) 369 goto alloc_mem_err; 370 371 rc = bnxt_alloc_async_ring_struct(bp); 372 if (rc) 373 goto alloc_mem_err; 374 375 rc = bnxt_alloc_vnic_mem(bp); 376 if (rc) 377 goto alloc_mem_err; 378 379 rc = bnxt_alloc_vnic_attributes(bp); 380 if (rc) 381 goto alloc_mem_err; 382 383 rc = bnxt_alloc_filter_mem(bp); 384 if (rc) 385 goto alloc_mem_err; 386 387 rc = bnxt_alloc_async_cp_ring(bp); 388 if (rc) 389 goto alloc_mem_err; 390 391 rc = bnxt_alloc_rxtx_nq_ring(bp); 392 if (rc) 393 goto alloc_mem_err; 394 395 if (BNXT_FLOW_XSTATS_EN(bp)) { 396 rc = bnxt_alloc_flow_stats_info(bp); 397 if (rc) 398 goto alloc_mem_err; 399 } 400 401 return 0; 402 403 alloc_mem_err: 404 bnxt_free_mem(bp, reconfig); 405 return rc; 406 } 407 408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 409 { 410 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 411 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 412 uint64_t rx_offloads = dev_conf->rxmode.offloads; 413 struct bnxt_rx_queue *rxq; 414 unsigned int j; 415 int rc; 416 417 rc = bnxt_vnic_grp_alloc(bp, vnic); 418 if (rc) 419 goto err_out; 420 421 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 422 vnic_id, vnic, vnic->fw_grp_ids); 423 424 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 425 if (rc) 426 goto err_out; 427 428 /* Alloc RSS context only if RSS mode is enabled */ 429 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 430 int j, nr_ctxs = bnxt_rss_ctxts(bp); 431 432 /* RSS table size in Thor is 512. 433 * Cap max Rx rings to same value 434 */ 435 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) { 436 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n", 437 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5); 438 goto err_out; 439 } 440 441 rc = 0; 442 for (j = 0; j < nr_ctxs; j++) { 443 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 444 if (rc) 445 break; 446 } 447 if (rc) { 448 PMD_DRV_LOG(ERR, 449 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 450 vnic_id, j, rc); 451 goto err_out; 452 } 453 vnic->num_lb_ctxts = nr_ctxs; 454 } 455 456 /* 457 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 458 * setting is not available at this time, it will not be 459 * configured correctly in the CFA. 460 */ 461 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 462 vnic->vlan_strip = true; 463 else 464 vnic->vlan_strip = false; 465 466 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 467 if (rc) 468 goto err_out; 469 470 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 471 if (rc) 472 goto err_out; 473 474 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 475 rxq = bp->eth_dev->data->rx_queues[j]; 476 477 PMD_DRV_LOG(DEBUG, 478 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 479 j, rxq->vnic, rxq->vnic->fw_grp_ids); 480 481 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 482 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 483 else 484 vnic->rx_queue_cnt++; 485 } 486 487 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 488 489 rc = bnxt_vnic_rss_configure(bp, vnic); 490 if (rc) 491 goto err_out; 492 493 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 494 495 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 496 (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ? 497 true : false); 498 if (rc) 499 goto err_out; 500 501 return 0; 502 err_out: 503 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 504 vnic_id, rc); 505 return rc; 506 } 507 508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp) 509 { 510 int rc = 0; 511 512 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma, 513 &bp->flow_stat->rx_fc_in_tbl.ctx_id); 514 if (rc) 515 return rc; 516 517 PMD_DRV_LOG(DEBUG, 518 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p" 519 " rx_fc_in_tbl.ctx_id = %d\n", 520 bp->flow_stat->rx_fc_in_tbl.va, 521 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma), 522 bp->flow_stat->rx_fc_in_tbl.ctx_id); 523 524 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma, 525 &bp->flow_stat->rx_fc_out_tbl.ctx_id); 526 if (rc) 527 return rc; 528 529 PMD_DRV_LOG(DEBUG, 530 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p" 531 " rx_fc_out_tbl.ctx_id = %d\n", 532 bp->flow_stat->rx_fc_out_tbl.va, 533 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma), 534 bp->flow_stat->rx_fc_out_tbl.ctx_id); 535 536 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma, 537 &bp->flow_stat->tx_fc_in_tbl.ctx_id); 538 if (rc) 539 return rc; 540 541 PMD_DRV_LOG(DEBUG, 542 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p" 543 " tx_fc_in_tbl.ctx_id = %d\n", 544 bp->flow_stat->tx_fc_in_tbl.va, 545 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma), 546 bp->flow_stat->tx_fc_in_tbl.ctx_id); 547 548 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma, 549 &bp->flow_stat->tx_fc_out_tbl.ctx_id); 550 if (rc) 551 return rc; 552 553 PMD_DRV_LOG(DEBUG, 554 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p" 555 " tx_fc_out_tbl.ctx_id = %d\n", 556 bp->flow_stat->tx_fc_out_tbl.va, 557 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma), 558 bp->flow_stat->tx_fc_out_tbl.ctx_id); 559 560 memset(bp->flow_stat->rx_fc_out_tbl.va, 561 0, 562 bp->flow_stat->rx_fc_out_tbl.size); 563 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 564 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 565 bp->flow_stat->rx_fc_out_tbl.ctx_id, 566 bp->flow_stat->max_fc, 567 true); 568 if (rc) 569 return rc; 570 571 memset(bp->flow_stat->tx_fc_out_tbl.va, 572 0, 573 bp->flow_stat->tx_fc_out_tbl.size); 574 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 575 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 576 bp->flow_stat->tx_fc_out_tbl.ctx_id, 577 bp->flow_stat->max_fc, 578 true); 579 580 return rc; 581 } 582 583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size, 584 struct bnxt_ctx_mem_buf_info *ctx) 585 { 586 if (!ctx) 587 return -EINVAL; 588 589 ctx->va = rte_zmalloc_socket(type, size, 0, 590 bp->eth_dev->device->numa_node); 591 if (ctx->va == NULL) 592 return -ENOMEM; 593 rte_mem_lock_page(ctx->va); 594 ctx->size = size; 595 ctx->dma = rte_mem_virt2iova(ctx->va); 596 if (ctx->dma == RTE_BAD_IOVA) 597 return -ENOMEM; 598 599 return 0; 600 } 601 602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp) 603 { 604 struct rte_pci_device *pdev = bp->pdev; 605 char type[RTE_MEMZONE_NAMESIZE]; 606 uint16_t max_fc; 607 int rc = 0; 608 609 max_fc = bp->flow_stat->max_fc; 610 611 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 612 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 613 /* 4 bytes for each counter-id */ 614 rc = bnxt_alloc_ctx_mem_buf(bp, type, 615 max_fc * 4, 616 &bp->flow_stat->rx_fc_in_tbl); 617 if (rc) 618 return rc; 619 620 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 621 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 622 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 623 rc = bnxt_alloc_ctx_mem_buf(bp, type, 624 max_fc * 16, 625 &bp->flow_stat->rx_fc_out_tbl); 626 if (rc) 627 return rc; 628 629 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 630 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 631 /* 4 bytes for each counter-id */ 632 rc = bnxt_alloc_ctx_mem_buf(bp, type, 633 max_fc * 4, 634 &bp->flow_stat->tx_fc_in_tbl); 635 if (rc) 636 return rc; 637 638 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 639 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 640 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 641 rc = bnxt_alloc_ctx_mem_buf(bp, type, 642 max_fc * 16, 643 &bp->flow_stat->tx_fc_out_tbl); 644 if (rc) 645 return rc; 646 647 rc = bnxt_register_fc_ctx_mem(bp); 648 649 return rc; 650 } 651 652 static int bnxt_init_ctx_mem(struct bnxt *bp) 653 { 654 int rc = 0; 655 656 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) || 657 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) || 658 !BNXT_FLOW_XSTATS_EN(bp)) 659 return 0; 660 661 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc); 662 if (rc) 663 return rc; 664 665 rc = bnxt_init_fc_ctx_mem(bp); 666 667 return rc; 668 } 669 670 static int bnxt_update_phy_setting(struct bnxt *bp) 671 { 672 struct rte_eth_link new; 673 int rc; 674 675 rc = bnxt_get_hwrm_link_config(bp, &new); 676 if (rc) { 677 PMD_DRV_LOG(ERR, "Failed to get link settings\n"); 678 return rc; 679 } 680 681 /* 682 * On BCM957508-N2100 adapters, FW will not allow any user other 683 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call 684 * always returns link up. Force phy update always in that case. 685 */ 686 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) { 687 rc = bnxt_set_hwrm_link_config(bp, true); 688 if (rc) { 689 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n"); 690 return rc; 691 } 692 } 693 694 return rc; 695 } 696 697 static void bnxt_free_prev_ring_stats(struct bnxt *bp) 698 { 699 rte_free(bp->prev_rx_ring_stats); 700 rte_free(bp->prev_tx_ring_stats); 701 702 bp->prev_rx_ring_stats = NULL; 703 bp->prev_tx_ring_stats = NULL; 704 } 705 706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp) 707 { 708 bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats", 709 sizeof(struct bnxt_ring_stats) * 710 bp->rx_cp_nr_rings, 711 0); 712 if (bp->prev_rx_ring_stats == NULL) 713 return -ENOMEM; 714 715 bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats", 716 sizeof(struct bnxt_ring_stats) * 717 bp->tx_cp_nr_rings, 718 0); 719 if (bp->prev_tx_ring_stats == NULL) 720 goto error; 721 722 return 0; 723 724 error: 725 bnxt_free_prev_ring_stats(bp); 726 return -ENOMEM; 727 } 728 729 static int bnxt_start_nic(struct bnxt *bp) 730 { 731 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 732 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 733 uint32_t intr_vector = 0; 734 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 735 uint32_t vec = BNXT_MISC_VEC_ID; 736 unsigned int i, j; 737 int rc; 738 739 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 740 bp->eth_dev->data->dev_conf.rxmode.offloads |= 741 DEV_RX_OFFLOAD_JUMBO_FRAME; 742 bp->flags |= BNXT_FLAG_JUMBO; 743 } else { 744 bp->eth_dev->data->dev_conf.rxmode.offloads &= 745 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 746 bp->flags &= ~BNXT_FLAG_JUMBO; 747 } 748 749 /* THOR does not support ring groups. 750 * But we will use the array to save RSS context IDs. 751 */ 752 if (BNXT_CHIP_P5(bp)) 753 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; 754 755 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 756 if (rc) { 757 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 758 goto err_out; 759 } 760 761 rc = bnxt_alloc_hwrm_rings(bp); 762 if (rc) { 763 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 764 goto err_out; 765 } 766 767 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 768 if (rc) { 769 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 770 goto err_out; 771 } 772 773 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 774 goto skip_cosq_cfg; 775 776 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 777 if (bp->rx_cos_queue[i].id != 0xff) { 778 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 779 780 if (!vnic) { 781 PMD_DRV_LOG(ERR, 782 "Num pools more than FW profile\n"); 783 rc = -EINVAL; 784 goto err_out; 785 } 786 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 787 bp->rx_cosq_cnt++; 788 } 789 } 790 791 skip_cosq_cfg: 792 rc = bnxt_mq_rx_configure(bp); 793 if (rc) { 794 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 795 goto err_out; 796 } 797 798 /* default vnic 0 */ 799 rc = bnxt_setup_one_vnic(bp, 0); 800 if (rc) 801 goto err_out; 802 /* VNIC configuration */ 803 if (BNXT_RFS_NEEDS_VNIC(bp)) { 804 for (i = 1; i < bp->nr_vnics; i++) { 805 rc = bnxt_setup_one_vnic(bp, i); 806 if (rc) 807 goto err_out; 808 } 809 } 810 811 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 812 if (rc) { 813 PMD_DRV_LOG(ERR, 814 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 815 goto err_out; 816 } 817 818 /* check and configure queue intr-vector mapping */ 819 if ((rte_intr_cap_multiple(intr_handle) || 820 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 821 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 822 intr_vector = bp->eth_dev->data->nb_rx_queues; 823 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 824 if (intr_vector > bp->rx_cp_nr_rings) { 825 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 826 bp->rx_cp_nr_rings); 827 return -ENOTSUP; 828 } 829 rc = rte_intr_efd_enable(intr_handle, intr_vector); 830 if (rc) 831 return rc; 832 } 833 834 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 835 intr_handle->intr_vec = 836 rte_zmalloc("intr_vec", 837 bp->eth_dev->data->nb_rx_queues * 838 sizeof(int), 0); 839 if (intr_handle->intr_vec == NULL) { 840 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 841 " intr_vec", bp->eth_dev->data->nb_rx_queues); 842 rc = -ENOMEM; 843 goto err_out; 844 } 845 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 846 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 847 intr_handle->intr_vec, intr_handle->nb_efd, 848 intr_handle->max_intr); 849 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 850 queue_id++) { 851 intr_handle->intr_vec[queue_id] = 852 vec + BNXT_RX_VEC_START; 853 if (vec < base + intr_handle->nb_efd - 1) 854 vec++; 855 } 856 } 857 858 /* enable uio/vfio intr/eventfd mapping */ 859 rc = rte_intr_enable(intr_handle); 860 #ifndef RTE_EXEC_ENV_FREEBSD 861 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 862 if (rc) 863 goto err_out; 864 #endif 865 866 rc = bnxt_update_phy_setting(bp); 867 if (rc) 868 goto err_out; 869 870 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 871 if (!bp->mark_table) 872 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 873 874 return 0; 875 876 err_out: 877 /* Some of the error status returned by FW may not be from errno.h */ 878 if (rc > 0) 879 rc = -EIO; 880 881 return rc; 882 } 883 884 static int bnxt_shutdown_nic(struct bnxt *bp) 885 { 886 bnxt_free_all_hwrm_resources(bp); 887 bnxt_free_all_filters(bp); 888 bnxt_free_all_vnics(bp); 889 return 0; 890 } 891 892 /* 893 * Device configuration and status function 894 */ 895 896 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) 897 { 898 uint32_t link_speed = 0; 899 uint32_t speed_capa = 0; 900 901 if (bp->link_info == NULL) 902 return 0; 903 904 link_speed = bp->link_info->support_speeds; 905 906 /* If PAM4 is configured, use PAM4 supported speed */ 907 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0) 908 link_speed = bp->link_info->support_pam4_speeds; 909 910 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) 911 speed_capa |= ETH_LINK_SPEED_100M; 912 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) 913 speed_capa |= ETH_LINK_SPEED_100M_HD; 914 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) 915 speed_capa |= ETH_LINK_SPEED_1G; 916 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 917 speed_capa |= ETH_LINK_SPEED_2_5G; 918 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) 919 speed_capa |= ETH_LINK_SPEED_10G; 920 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 921 speed_capa |= ETH_LINK_SPEED_20G; 922 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) 923 speed_capa |= ETH_LINK_SPEED_25G; 924 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) 925 speed_capa |= ETH_LINK_SPEED_40G; 926 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) 927 speed_capa |= ETH_LINK_SPEED_50G; 928 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) 929 speed_capa |= ETH_LINK_SPEED_100G; 930 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) 931 speed_capa |= ETH_LINK_SPEED_50G; 932 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) 933 speed_capa |= ETH_LINK_SPEED_100G; 934 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G) 935 speed_capa |= ETH_LINK_SPEED_200G; 936 937 if (bp->link_info->auto_mode == 938 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 939 speed_capa |= ETH_LINK_SPEED_FIXED; 940 941 return speed_capa; 942 } 943 944 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 945 struct rte_eth_dev_info *dev_info) 946 { 947 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 948 struct bnxt *bp = eth_dev->data->dev_private; 949 uint16_t max_vnics, i, j, vpool, vrxq; 950 unsigned int max_rx_rings; 951 int rc; 952 953 rc = is_bnxt_in_error(bp); 954 if (rc) 955 return rc; 956 957 /* MAC Specifics */ 958 dev_info->max_mac_addrs = bp->max_l2_ctx; 959 dev_info->max_hash_mac_addrs = 0; 960 961 /* PF/VF specifics */ 962 if (BNXT_PF(bp)) 963 dev_info->max_vfs = pdev->max_vfs; 964 965 max_rx_rings = bnxt_max_rings(bp); 966 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 967 dev_info->max_rx_queues = max_rx_rings; 968 dev_info->max_tx_queues = max_rx_rings; 969 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 970 dev_info->hash_key_size = HW_HASH_KEY_SIZE; 971 max_vnics = bp->max_vnics; 972 973 /* MTU specifics */ 974 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 975 dev_info->max_mtu = BNXT_MAX_MTU; 976 977 /* Fast path specifics */ 978 dev_info->min_rx_bufsize = 1; 979 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 980 981 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 982 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 983 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 984 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP) 985 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_VLAN_STRIP; 986 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 987 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT | 988 dev_info->tx_queue_offload_capa; 989 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT) 990 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_VLAN_INSERT; 991 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 992 993 dev_info->speed_capa = bnxt_get_speed_capabilities(bp); 994 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 995 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 996 997 dev_info->default_rxconf = (struct rte_eth_rxconf) { 998 .rx_thresh = { 999 .pthresh = 8, 1000 .hthresh = 8, 1001 .wthresh = 0, 1002 }, 1003 .rx_free_thresh = 32, 1004 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN, 1005 }; 1006 1007 dev_info->default_txconf = (struct rte_eth_txconf) { 1008 .tx_thresh = { 1009 .pthresh = 32, 1010 .hthresh = 0, 1011 .wthresh = 0, 1012 }, 1013 .tx_free_thresh = 32, 1014 .tx_rs_thresh = 32, 1015 }; 1016 eth_dev->data->dev_conf.intr_conf.lsc = 1; 1017 1018 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 1019 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 1020 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 1021 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 1022 1023 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 1024 dev_info->switch_info.name = eth_dev->device->name; 1025 dev_info->switch_info.domain_id = bp->switch_domain_id; 1026 dev_info->switch_info.port_id = 1027 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF : 1028 BNXT_SWITCH_PORT_ID_TRUSTED_VF; 1029 } 1030 1031 /* 1032 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 1033 * need further investigation. 1034 */ 1035 1036 /* VMDq resources */ 1037 vpool = 64; /* ETH_64_POOLS */ 1038 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 1039 for (i = 0; i < 4; vpool >>= 1, i++) { 1040 if (max_vnics > vpool) { 1041 for (j = 0; j < 5; vrxq >>= 1, j++) { 1042 if (dev_info->max_rx_queues > vrxq) { 1043 if (vpool > vrxq) 1044 vpool = vrxq; 1045 goto found; 1046 } 1047 } 1048 /* Not enough resources to support VMDq */ 1049 break; 1050 } 1051 } 1052 /* Not enough resources to support VMDq */ 1053 vpool = 0; 1054 vrxq = 0; 1055 found: 1056 dev_info->max_vmdq_pools = vpool; 1057 dev_info->vmdq_queue_num = vrxq; 1058 1059 dev_info->vmdq_pool_base = 0; 1060 dev_info->vmdq_queue_base = 0; 1061 1062 return 0; 1063 } 1064 1065 /* Configure the device based on the configuration provided */ 1066 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 1067 { 1068 struct bnxt *bp = eth_dev->data->dev_private; 1069 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1070 int rc; 1071 1072 bp->rx_queues = (void *)eth_dev->data->rx_queues; 1073 bp->tx_queues = (void *)eth_dev->data->tx_queues; 1074 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 1075 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 1076 1077 rc = is_bnxt_in_error(bp); 1078 if (rc) 1079 return rc; 1080 1081 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 1082 rc = bnxt_hwrm_check_vf_rings(bp); 1083 if (rc) { 1084 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 1085 return -ENOSPC; 1086 } 1087 1088 /* If a resource has already been allocated - in this case 1089 * it is the async completion ring, free it. Reallocate it after 1090 * resource reservation. This will ensure the resource counts 1091 * are calculated correctly. 1092 */ 1093 1094 pthread_mutex_lock(&bp->def_cp_lock); 1095 1096 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1097 bnxt_disable_int(bp); 1098 bnxt_free_cp_ring(bp, bp->async_cp_ring); 1099 } 1100 1101 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 1102 if (rc) { 1103 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 1104 pthread_mutex_unlock(&bp->def_cp_lock); 1105 return -ENOSPC; 1106 } 1107 1108 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1109 rc = bnxt_alloc_async_cp_ring(bp); 1110 if (rc) { 1111 pthread_mutex_unlock(&bp->def_cp_lock); 1112 return rc; 1113 } 1114 bnxt_enable_int(bp); 1115 } 1116 1117 pthread_mutex_unlock(&bp->def_cp_lock); 1118 } 1119 1120 /* Inherit new configurations */ 1121 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 1122 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 1123 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 1124 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 1125 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 1126 bp->max_stat_ctx) 1127 goto resource_error; 1128 1129 if (BNXT_HAS_RING_GRPS(bp) && 1130 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 1131 goto resource_error; 1132 1133 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 1134 bp->max_vnics < eth_dev->data->nb_rx_queues) 1135 goto resource_error; 1136 1137 bp->rx_cp_nr_rings = bp->rx_nr_rings; 1138 bp->tx_cp_nr_rings = bp->tx_nr_rings; 1139 1140 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1141 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1142 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 1143 1144 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1145 eth_dev->data->mtu = 1146 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1147 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 1148 BNXT_NUM_VLANS; 1149 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 1150 } 1151 return 0; 1152 1153 resource_error: 1154 PMD_DRV_LOG(ERR, 1155 "Insufficient resources to support requested config\n"); 1156 PMD_DRV_LOG(ERR, 1157 "Num Queues Requested: Tx %d, Rx %d\n", 1158 eth_dev->data->nb_tx_queues, 1159 eth_dev->data->nb_rx_queues); 1160 PMD_DRV_LOG(ERR, 1161 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 1162 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 1163 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 1164 return -ENOSPC; 1165 } 1166 1167 void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 1168 { 1169 struct rte_eth_link *link = ð_dev->data->dev_link; 1170 1171 if (link->link_status) 1172 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 1173 eth_dev->data->port_id, 1174 (uint32_t)link->link_speed, 1175 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 1176 ("full-duplex") : ("half-duplex\n")); 1177 else 1178 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 1179 eth_dev->data->port_id); 1180 } 1181 1182 /* 1183 * Determine whether the current configuration requires support for scattered 1184 * receive; return 1 if scattered receive is required and 0 if not. 1185 */ 1186 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 1187 { 1188 uint16_t buf_size; 1189 int i; 1190 1191 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 1192 return 1; 1193 1194 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) 1195 return 1; 1196 1197 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 1198 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 1199 1200 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1201 RTE_PKTMBUF_HEADROOM); 1202 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 1203 return 1; 1204 } 1205 return 0; 1206 } 1207 1208 static eth_rx_burst_t 1209 bnxt_receive_function(struct rte_eth_dev *eth_dev) 1210 { 1211 struct bnxt *bp = eth_dev->data->dev_private; 1212 1213 /* Disable vector mode RX for Stingray2 for now */ 1214 if (BNXT_CHIP_SR2(bp)) { 1215 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1216 return bnxt_recv_pkts; 1217 } 1218 1219 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \ 1220 !defined(RTE_LIBRTE_IEEE1588) 1221 1222 /* Vector mode receive cannot be enabled if scattered rx is in use. */ 1223 if (eth_dev->data->scattered_rx) 1224 goto use_scalar_rx; 1225 1226 /* 1227 * Vector mode receive cannot be enabled if Truflow is enabled or if 1228 * asynchronous completions and receive completions can be placed in 1229 * the same completion ring. 1230 */ 1231 if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp)) 1232 goto use_scalar_rx; 1233 1234 /* 1235 * Vector mode receive cannot be enabled if any receive offloads outside 1236 * a limited subset have been enabled. 1237 */ 1238 if (eth_dev->data->dev_conf.rxmode.offloads & 1239 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 1240 DEV_RX_OFFLOAD_KEEP_CRC | 1241 DEV_RX_OFFLOAD_JUMBO_FRAME | 1242 DEV_RX_OFFLOAD_IPV4_CKSUM | 1243 DEV_RX_OFFLOAD_UDP_CKSUM | 1244 DEV_RX_OFFLOAD_TCP_CKSUM | 1245 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1246 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 1247 DEV_RX_OFFLOAD_RSS_HASH | 1248 DEV_RX_OFFLOAD_VLAN_FILTER)) 1249 goto use_scalar_rx; 1250 1251 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 1252 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && 1253 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) { 1254 PMD_DRV_LOG(INFO, 1255 "Using AVX2 vector mode receive for port %d\n", 1256 eth_dev->data->port_id); 1257 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1258 return bnxt_recv_pkts_vec_avx2; 1259 } 1260 #endif 1261 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1262 PMD_DRV_LOG(INFO, 1263 "Using SSE vector mode receive for port %d\n", 1264 eth_dev->data->port_id); 1265 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1266 return bnxt_recv_pkts_vec; 1267 } 1268 1269 use_scalar_rx: 1270 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 1271 eth_dev->data->port_id); 1272 PMD_DRV_LOG(INFO, 1273 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 1274 eth_dev->data->port_id, 1275 eth_dev->data->scattered_rx, 1276 eth_dev->data->dev_conf.rxmode.offloads); 1277 #endif 1278 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1279 return bnxt_recv_pkts; 1280 } 1281 1282 static eth_tx_burst_t 1283 bnxt_transmit_function(struct rte_eth_dev *eth_dev) 1284 { 1285 struct bnxt *bp = eth_dev->data->dev_private; 1286 1287 /* Disable vector mode TX for Stingray2 for now */ 1288 if (BNXT_CHIP_SR2(bp)) 1289 return bnxt_xmit_pkts; 1290 1291 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \ 1292 !defined(RTE_LIBRTE_IEEE1588) 1293 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; 1294 1295 /* 1296 * Vector mode transmit can be enabled only if not using scatter rx 1297 * or tx offloads. 1298 */ 1299 if (eth_dev->data->scattered_rx || 1300 (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) || 1301 BNXT_TRUFLOW_EN(bp)) 1302 goto use_scalar_tx; 1303 1304 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 1305 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && 1306 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) { 1307 PMD_DRV_LOG(INFO, 1308 "Using AVX2 vector mode transmit for port %d\n", 1309 eth_dev->data->port_id); 1310 return bnxt_xmit_pkts_vec_avx2; 1311 } 1312 #endif 1313 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1314 PMD_DRV_LOG(INFO, 1315 "Using SSE vector mode transmit for port %d\n", 1316 eth_dev->data->port_id); 1317 return bnxt_xmit_pkts_vec; 1318 } 1319 1320 use_scalar_tx: 1321 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 1322 eth_dev->data->port_id); 1323 PMD_DRV_LOG(INFO, 1324 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 1325 eth_dev->data->port_id, 1326 eth_dev->data->scattered_rx, 1327 offloads); 1328 #endif 1329 return bnxt_xmit_pkts; 1330 } 1331 1332 static int bnxt_handle_if_change_status(struct bnxt *bp) 1333 { 1334 int rc; 1335 1336 /* Since fw has undergone a reset and lost all contexts, 1337 * set fatal flag to not issue hwrm during cleanup 1338 */ 1339 bp->flags |= BNXT_FLAG_FATAL_ERROR; 1340 bnxt_uninit_resources(bp, true); 1341 1342 /* clear fatal flag so that re-init happens */ 1343 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 1344 rc = bnxt_init_resources(bp, true); 1345 1346 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 1347 1348 return rc; 1349 } 1350 1351 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 1352 { 1353 struct bnxt *bp = eth_dev->data->dev_private; 1354 int rc = 0; 1355 1356 if (!BNXT_SINGLE_PF(bp)) 1357 return -ENOTSUP; 1358 1359 if (!bp->link_info->link_up) 1360 rc = bnxt_set_hwrm_link_config(bp, true); 1361 if (!rc) 1362 eth_dev->data->dev_link.link_status = 1; 1363 1364 bnxt_print_link_info(eth_dev); 1365 return rc; 1366 } 1367 1368 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 1369 { 1370 struct bnxt *bp = eth_dev->data->dev_private; 1371 1372 if (!BNXT_SINGLE_PF(bp)) 1373 return -ENOTSUP; 1374 1375 eth_dev->data->dev_link.link_status = 0; 1376 bnxt_set_hwrm_link_config(bp, false); 1377 bp->link_info->link_up = 0; 1378 1379 return 0; 1380 } 1381 1382 static void bnxt_free_switch_domain(struct bnxt *bp) 1383 { 1384 int rc = 0; 1385 1386 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) 1387 return; 1388 1389 rc = rte_eth_switch_domain_free(bp->switch_domain_id); 1390 if (rc) 1391 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n", 1392 bp->switch_domain_id, rc); 1393 } 1394 1395 static void bnxt_ptp_get_current_time(void *arg) 1396 { 1397 struct bnxt *bp = arg; 1398 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1399 int rc; 1400 1401 rc = is_bnxt_in_error(bp); 1402 if (rc) 1403 return; 1404 1405 if (!ptp) 1406 return; 1407 1408 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1409 &ptp->current_time); 1410 1411 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1412 if (rc != 0) { 1413 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n"); 1414 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1415 } 1416 } 1417 1418 static int bnxt_schedule_ptp_alarm(struct bnxt *bp) 1419 { 1420 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1421 int rc; 1422 1423 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) 1424 return 0; 1425 1426 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1427 &ptp->current_time); 1428 1429 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1430 return rc; 1431 } 1432 1433 static void bnxt_cancel_ptp_alarm(struct bnxt *bp) 1434 { 1435 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) { 1436 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp); 1437 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1438 } 1439 } 1440 1441 static void bnxt_ptp_stop(struct bnxt *bp) 1442 { 1443 bnxt_cancel_ptp_alarm(bp); 1444 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1445 } 1446 1447 static int bnxt_ptp_start(struct bnxt *bp) 1448 { 1449 int rc; 1450 1451 rc = bnxt_schedule_ptp_alarm(bp); 1452 if (rc != 0) { 1453 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n"); 1454 } else { 1455 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1456 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1457 } 1458 1459 return rc; 1460 } 1461 1462 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev) 1463 { 1464 struct bnxt *bp = eth_dev->data->dev_private; 1465 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1466 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1467 struct rte_eth_link link; 1468 int ret; 1469 1470 eth_dev->data->dev_started = 0; 1471 eth_dev->data->scattered_rx = 0; 1472 1473 /* Prevent crashes when queues are still in use */ 1474 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 1475 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 1476 1477 bnxt_disable_int(bp); 1478 1479 /* disable uio/vfio intr/eventfd mapping */ 1480 rte_intr_disable(intr_handle); 1481 1482 /* Stop the child representors for this device */ 1483 ret = bnxt_rep_stop_all(bp); 1484 if (ret != 0) 1485 return ret; 1486 1487 /* delete the bnxt ULP port details */ 1488 bnxt_ulp_port_deinit(bp); 1489 1490 bnxt_cancel_fw_health_check(bp); 1491 1492 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1493 bnxt_cancel_ptp_alarm(bp); 1494 1495 /* Do not bring link down during reset recovery */ 1496 if (!is_bnxt_in_error(bp)) { 1497 bnxt_dev_set_link_down_op(eth_dev); 1498 /* Wait for link to be reset */ 1499 if (BNXT_SINGLE_PF(bp)) 1500 rte_delay_ms(500); 1501 /* clear the recorded link status */ 1502 memset(&link, 0, sizeof(link)); 1503 rte_eth_linkstatus_set(eth_dev, &link); 1504 } 1505 1506 /* Clean queue intr-vector mapping */ 1507 rte_intr_efd_disable(intr_handle); 1508 if (intr_handle->intr_vec != NULL) { 1509 rte_free(intr_handle->intr_vec); 1510 intr_handle->intr_vec = NULL; 1511 } 1512 1513 bnxt_hwrm_port_clr_stats(bp); 1514 bnxt_free_tx_mbufs(bp); 1515 bnxt_free_rx_mbufs(bp); 1516 /* Process any remaining notifications in default completion queue */ 1517 bnxt_int_handler(eth_dev); 1518 bnxt_shutdown_nic(bp); 1519 bnxt_hwrm_if_change(bp, false); 1520 1521 bnxt_free_prev_ring_stats(bp); 1522 rte_free(bp->mark_table); 1523 bp->mark_table = NULL; 1524 1525 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1526 bp->rx_cosq_cnt = 0; 1527 /* All filters are deleted on a port stop. */ 1528 if (BNXT_FLOW_XSTATS_EN(bp)) 1529 bp->flow_stat->flow_count = 0; 1530 1531 return 0; 1532 } 1533 1534 /* Unload the driver, release resources */ 1535 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 1536 { 1537 struct bnxt *bp = eth_dev->data->dev_private; 1538 1539 pthread_mutex_lock(&bp->err_recovery_lock); 1540 if (bp->flags & BNXT_FLAG_FW_RESET) { 1541 PMD_DRV_LOG(ERR, 1542 "Adapter recovering from error..Please retry\n"); 1543 pthread_mutex_unlock(&bp->err_recovery_lock); 1544 return -EAGAIN; 1545 } 1546 pthread_mutex_unlock(&bp->err_recovery_lock); 1547 1548 return bnxt_dev_stop(eth_dev); 1549 } 1550 1551 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 1552 { 1553 struct bnxt *bp = eth_dev->data->dev_private; 1554 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1555 int vlan_mask = 0; 1556 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; 1557 1558 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 1559 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 1560 return -EINVAL; 1561 } 1562 1563 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) 1564 PMD_DRV_LOG(ERR, 1565 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 1566 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1567 1568 do { 1569 rc = bnxt_hwrm_if_change(bp, true); 1570 if (rc == 0 || rc != -EAGAIN) 1571 break; 1572 1573 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); 1574 } while (retry_cnt--); 1575 1576 if (rc) 1577 return rc; 1578 1579 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 1580 rc = bnxt_handle_if_change_status(bp); 1581 if (rc) 1582 return rc; 1583 } 1584 1585 bnxt_enable_int(bp); 1586 1587 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 1588 1589 rc = bnxt_start_nic(bp); 1590 if (rc) 1591 goto error; 1592 1593 rc = bnxt_alloc_prev_ring_stats(bp); 1594 if (rc) 1595 goto error; 1596 1597 eth_dev->data->dev_started = 1; 1598 1599 bnxt_link_update_op(eth_dev, 1); 1600 1601 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1602 vlan_mask |= ETH_VLAN_FILTER_MASK; 1603 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1604 vlan_mask |= ETH_VLAN_STRIP_MASK; 1605 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 1606 if (rc) 1607 goto error; 1608 1609 /* Initialize bnxt ULP port details */ 1610 rc = bnxt_ulp_port_init(bp); 1611 if (rc) 1612 goto error; 1613 1614 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 1615 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 1616 1617 bnxt_schedule_fw_health_check(bp); 1618 1619 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1620 bnxt_schedule_ptp_alarm(bp); 1621 1622 return 0; 1623 1624 error: 1625 bnxt_dev_stop(eth_dev); 1626 return rc; 1627 } 1628 1629 static void 1630 bnxt_uninit_locks(struct bnxt *bp) 1631 { 1632 pthread_mutex_destroy(&bp->flow_lock); 1633 pthread_mutex_destroy(&bp->def_cp_lock); 1634 pthread_mutex_destroy(&bp->health_check_lock); 1635 pthread_mutex_destroy(&bp->err_recovery_lock); 1636 if (bp->rep_info) { 1637 pthread_mutex_destroy(&bp->rep_info->vfr_lock); 1638 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); 1639 } 1640 } 1641 1642 static void bnxt_drv_uninit(struct bnxt *bp) 1643 { 1644 bnxt_free_leds_info(bp); 1645 bnxt_free_cos_queues(bp); 1646 bnxt_free_link_info(bp); 1647 bnxt_free_parent_info(bp); 1648 bnxt_uninit_locks(bp); 1649 1650 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 1651 bp->tx_mem_zone = NULL; 1652 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 1653 bp->rx_mem_zone = NULL; 1654 1655 bnxt_free_vf_info(bp); 1656 bnxt_free_pf_info(bp); 1657 1658 rte_free(bp->grp_info); 1659 bp->grp_info = NULL; 1660 } 1661 1662 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 1663 { 1664 struct bnxt *bp = eth_dev->data->dev_private; 1665 int ret = 0; 1666 1667 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1668 return 0; 1669 1670 pthread_mutex_lock(&bp->err_recovery_lock); 1671 if (bp->flags & BNXT_FLAG_FW_RESET) { 1672 PMD_DRV_LOG(ERR, 1673 "Adapter recovering from error...Please retry\n"); 1674 pthread_mutex_unlock(&bp->err_recovery_lock); 1675 return -EAGAIN; 1676 } 1677 pthread_mutex_unlock(&bp->err_recovery_lock); 1678 1679 /* cancel the recovery handler before remove dev */ 1680 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); 1681 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); 1682 bnxt_cancel_fc_thread(bp); 1683 1684 if (eth_dev->data->dev_started) 1685 ret = bnxt_dev_stop(eth_dev); 1686 1687 bnxt_uninit_resources(bp, false); 1688 1689 bnxt_drv_uninit(bp); 1690 1691 return ret; 1692 } 1693 1694 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1695 uint32_t index) 1696 { 1697 struct bnxt *bp = eth_dev->data->dev_private; 1698 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1699 struct bnxt_vnic_info *vnic; 1700 struct bnxt_filter_info *filter, *temp_filter; 1701 uint32_t i; 1702 1703 if (is_bnxt_in_error(bp)) 1704 return; 1705 1706 /* 1707 * Loop through all VNICs from the specified filter flow pools to 1708 * remove the corresponding MAC addr filter 1709 */ 1710 for (i = 0; i < bp->nr_vnics; i++) { 1711 if (!(pool_mask & (1ULL << i))) 1712 continue; 1713 1714 vnic = &bp->vnic_info[i]; 1715 filter = STAILQ_FIRST(&vnic->filter); 1716 while (filter) { 1717 temp_filter = STAILQ_NEXT(filter, next); 1718 if (filter->mac_index == index) { 1719 STAILQ_REMOVE(&vnic->filter, filter, 1720 bnxt_filter_info, next); 1721 bnxt_hwrm_clear_l2_filter(bp, filter); 1722 bnxt_free_filter(bp, filter); 1723 } 1724 filter = temp_filter; 1725 } 1726 } 1727 } 1728 1729 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1730 struct rte_ether_addr *mac_addr, uint32_t index, 1731 uint32_t pool) 1732 { 1733 struct bnxt_filter_info *filter; 1734 int rc = 0; 1735 1736 /* Attach requested MAC address to the new l2_filter */ 1737 STAILQ_FOREACH(filter, &vnic->filter, next) { 1738 if (filter->mac_index == index) { 1739 PMD_DRV_LOG(DEBUG, 1740 "MAC addr already existed for pool %d\n", 1741 pool); 1742 return 0; 1743 } 1744 } 1745 1746 filter = bnxt_alloc_filter(bp); 1747 if (!filter) { 1748 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1749 return -ENODEV; 1750 } 1751 1752 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1753 * if the MAC that's been programmed now is a different one, then, 1754 * copy that addr to filter->l2_addr 1755 */ 1756 if (mac_addr) 1757 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1758 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1759 1760 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1761 if (!rc) { 1762 filter->mac_index = index; 1763 if (filter->mac_index == 0) 1764 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1765 else 1766 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1767 } else { 1768 bnxt_free_filter(bp, filter); 1769 } 1770 1771 return rc; 1772 } 1773 1774 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1775 struct rte_ether_addr *mac_addr, 1776 uint32_t index, uint32_t pool) 1777 { 1778 struct bnxt *bp = eth_dev->data->dev_private; 1779 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1780 int rc = 0; 1781 1782 rc = is_bnxt_in_error(bp); 1783 if (rc) 1784 return rc; 1785 1786 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 1787 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1788 return -ENOTSUP; 1789 } 1790 1791 if (!vnic) { 1792 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1793 return -EINVAL; 1794 } 1795 1796 /* Filter settings will get applied when port is started */ 1797 if (!eth_dev->data->dev_started) 1798 return 0; 1799 1800 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1801 1802 return rc; 1803 } 1804 1805 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 1806 { 1807 int rc = 0; 1808 struct bnxt *bp = eth_dev->data->dev_private; 1809 struct rte_eth_link new; 1810 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT : 1811 BNXT_MIN_LINK_WAIT_CNT; 1812 1813 rc = is_bnxt_in_error(bp); 1814 if (rc) 1815 return rc; 1816 1817 memset(&new, 0, sizeof(new)); 1818 1819 if (bp->link_info == NULL) 1820 goto out; 1821 1822 do { 1823 /* Retrieve link info from hardware */ 1824 rc = bnxt_get_hwrm_link_config(bp, &new); 1825 if (rc) { 1826 new.link_speed = ETH_LINK_SPEED_100M; 1827 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1828 PMD_DRV_LOG(ERR, 1829 "Failed to retrieve link rc = 0x%x!\n", rc); 1830 goto out; 1831 } 1832 1833 if (!wait_to_complete || new.link_status) 1834 break; 1835 1836 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1837 } while (cnt--); 1838 1839 /* Only single function PF can bring phy down. 1840 * When port is stopped, report link down for VF/MH/NPAR functions. 1841 */ 1842 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started) 1843 memset(&new, 0, sizeof(new)); 1844 1845 out: 1846 /* Timed out or success */ 1847 if (new.link_status != eth_dev->data->dev_link.link_status || 1848 new.link_speed != eth_dev->data->dev_link.link_speed) { 1849 rte_eth_linkstatus_set(eth_dev, &new); 1850 bnxt_print_link_info(eth_dev); 1851 } 1852 1853 return rc; 1854 } 1855 1856 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1857 { 1858 struct bnxt *bp = eth_dev->data->dev_private; 1859 struct bnxt_vnic_info *vnic; 1860 uint32_t old_flags; 1861 int rc; 1862 1863 rc = is_bnxt_in_error(bp); 1864 if (rc) 1865 return rc; 1866 1867 /* Filter settings will get applied when port is started */ 1868 if (!eth_dev->data->dev_started) 1869 return 0; 1870 1871 if (bp->vnic_info == NULL) 1872 return 0; 1873 1874 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1875 1876 old_flags = vnic->flags; 1877 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1878 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1879 if (rc != 0) 1880 vnic->flags = old_flags; 1881 1882 return rc; 1883 } 1884 1885 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1886 { 1887 struct bnxt *bp = eth_dev->data->dev_private; 1888 struct bnxt_vnic_info *vnic; 1889 uint32_t old_flags; 1890 int rc; 1891 1892 rc = is_bnxt_in_error(bp); 1893 if (rc) 1894 return rc; 1895 1896 /* Filter settings will get applied when port is started */ 1897 if (!eth_dev->data->dev_started) 1898 return 0; 1899 1900 if (bp->vnic_info == NULL) 1901 return 0; 1902 1903 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1904 1905 old_flags = vnic->flags; 1906 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1907 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1908 if (rc != 0) 1909 vnic->flags = old_flags; 1910 1911 return rc; 1912 } 1913 1914 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1915 { 1916 struct bnxt *bp = eth_dev->data->dev_private; 1917 struct bnxt_vnic_info *vnic; 1918 uint32_t old_flags; 1919 int rc; 1920 1921 rc = is_bnxt_in_error(bp); 1922 if (rc) 1923 return rc; 1924 1925 /* Filter settings will get applied when port is started */ 1926 if (!eth_dev->data->dev_started) 1927 return 0; 1928 1929 if (bp->vnic_info == NULL) 1930 return 0; 1931 1932 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1933 1934 old_flags = vnic->flags; 1935 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1936 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1937 if (rc != 0) 1938 vnic->flags = old_flags; 1939 1940 return rc; 1941 } 1942 1943 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1944 { 1945 struct bnxt *bp = eth_dev->data->dev_private; 1946 struct bnxt_vnic_info *vnic; 1947 uint32_t old_flags; 1948 int rc; 1949 1950 rc = is_bnxt_in_error(bp); 1951 if (rc) 1952 return rc; 1953 1954 /* Filter settings will get applied when port is started */ 1955 if (!eth_dev->data->dev_started) 1956 return 0; 1957 1958 if (bp->vnic_info == NULL) 1959 return 0; 1960 1961 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1962 1963 old_flags = vnic->flags; 1964 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1965 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1966 if (rc != 0) 1967 vnic->flags = old_flags; 1968 1969 return rc; 1970 } 1971 1972 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1973 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1974 { 1975 if (qid >= bp->rx_nr_rings) 1976 return NULL; 1977 1978 return bp->eth_dev->data->rx_queues[qid]; 1979 } 1980 1981 /* Return rxq corresponding to a given rss table ring/group ID. */ 1982 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1983 { 1984 struct bnxt_rx_queue *rxq; 1985 unsigned int i; 1986 1987 if (!BNXT_HAS_RING_GRPS(bp)) { 1988 for (i = 0; i < bp->rx_nr_rings; i++) { 1989 rxq = bp->eth_dev->data->rx_queues[i]; 1990 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1991 return rxq->index; 1992 } 1993 } else { 1994 for (i = 0; i < bp->rx_nr_rings; i++) { 1995 if (bp->grp_info[i].fw_grp_id == fwr) 1996 return i; 1997 } 1998 } 1999 2000 return INVALID_HW_RING_ID; 2001 } 2002 2003 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 2004 struct rte_eth_rss_reta_entry64 *reta_conf, 2005 uint16_t reta_size) 2006 { 2007 struct bnxt *bp = eth_dev->data->dev_private; 2008 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 2009 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2010 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 2011 uint16_t idx, sft; 2012 int i, rc; 2013 2014 rc = is_bnxt_in_error(bp); 2015 if (rc) 2016 return rc; 2017 2018 if (!vnic->rss_table) 2019 return -EINVAL; 2020 2021 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 2022 return -EINVAL; 2023 2024 if (reta_size != tbl_size) { 2025 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 2026 "(%d) must equal the size supported by the hardware " 2027 "(%d)\n", reta_size, tbl_size); 2028 return -EINVAL; 2029 } 2030 2031 for (i = 0; i < reta_size; i++) { 2032 struct bnxt_rx_queue *rxq; 2033 2034 idx = i / RTE_RETA_GROUP_SIZE; 2035 sft = i % RTE_RETA_GROUP_SIZE; 2036 2037 if (!(reta_conf[idx].mask & (1ULL << sft))) 2038 continue; 2039 2040 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 2041 if (!rxq) { 2042 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 2043 return -EINVAL; 2044 } 2045 2046 if (BNXT_CHIP_P5(bp)) { 2047 vnic->rss_table[i * 2] = 2048 rxq->rx_ring->rx_ring_struct->fw_ring_id; 2049 vnic->rss_table[i * 2 + 1] = 2050 rxq->cp_ring->cp_ring_struct->fw_ring_id; 2051 } else { 2052 vnic->rss_table[i] = 2053 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 2054 } 2055 } 2056 2057 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 2058 return rc; 2059 } 2060 2061 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 2062 struct rte_eth_rss_reta_entry64 *reta_conf, 2063 uint16_t reta_size) 2064 { 2065 struct bnxt *bp = eth_dev->data->dev_private; 2066 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2067 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 2068 uint16_t idx, sft, i; 2069 int rc; 2070 2071 rc = is_bnxt_in_error(bp); 2072 if (rc) 2073 return rc; 2074 2075 if (!vnic) 2076 return -EINVAL; 2077 if (!vnic->rss_table) 2078 return -EINVAL; 2079 2080 if (reta_size != tbl_size) { 2081 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 2082 "(%d) must equal the size supported by the hardware " 2083 "(%d)\n", reta_size, tbl_size); 2084 return -EINVAL; 2085 } 2086 2087 for (idx = 0, i = 0; i < reta_size; i++) { 2088 idx = i / RTE_RETA_GROUP_SIZE; 2089 sft = i % RTE_RETA_GROUP_SIZE; 2090 2091 if (reta_conf[idx].mask & (1ULL << sft)) { 2092 uint16_t qid; 2093 2094 if (BNXT_CHIP_P5(bp)) 2095 qid = bnxt_rss_to_qid(bp, 2096 vnic->rss_table[i * 2]); 2097 else 2098 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 2099 2100 if (qid == INVALID_HW_RING_ID) { 2101 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 2102 return -EINVAL; 2103 } 2104 reta_conf[idx].reta[sft] = qid; 2105 } 2106 } 2107 2108 return 0; 2109 } 2110 2111 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 2112 struct rte_eth_rss_conf *rss_conf) 2113 { 2114 struct bnxt *bp = eth_dev->data->dev_private; 2115 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 2116 struct bnxt_vnic_info *vnic; 2117 int rc; 2118 2119 rc = is_bnxt_in_error(bp); 2120 if (rc) 2121 return rc; 2122 2123 /* 2124 * If RSS enablement were different than dev_configure, 2125 * then return -EINVAL 2126 */ 2127 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 2128 if (!rss_conf->rss_hf) 2129 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 2130 } else { 2131 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 2132 return -EINVAL; 2133 } 2134 2135 bp->flags |= BNXT_FLAG_UPDATE_HASH; 2136 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf, 2137 rss_conf, 2138 sizeof(*rss_conf)); 2139 2140 /* Update the default RSS VNIC(s) */ 2141 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2142 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 2143 vnic->hash_mode = 2144 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf, 2145 ETH_RSS_LEVEL(rss_conf->rss_hf)); 2146 2147 /* 2148 * If hashkey is not specified, use the previously configured 2149 * hashkey 2150 */ 2151 if (!rss_conf->rss_key) 2152 goto rss_config; 2153 2154 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 2155 PMD_DRV_LOG(ERR, 2156 "Invalid hashkey length, should be %d bytes\n", 2157 HW_HASH_KEY_SIZE); 2158 return -EINVAL; 2159 } 2160 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 2161 2162 rss_config: 2163 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 2164 return rc; 2165 } 2166 2167 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 2168 struct rte_eth_rss_conf *rss_conf) 2169 { 2170 struct bnxt *bp = eth_dev->data->dev_private; 2171 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2172 int len, rc; 2173 uint32_t hash_types; 2174 2175 rc = is_bnxt_in_error(bp); 2176 if (rc) 2177 return rc; 2178 2179 /* RSS configuration is the same for all VNICs */ 2180 if (vnic && vnic->rss_hash_key) { 2181 if (rss_conf->rss_key) { 2182 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 2183 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 2184 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 2185 } 2186 2187 hash_types = vnic->hash_type; 2188 rss_conf->rss_hf = 0; 2189 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 2190 rss_conf->rss_hf |= ETH_RSS_IPV4; 2191 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 2192 } 2193 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 2194 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 2195 hash_types &= 2196 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 2197 } 2198 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 2199 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 2200 hash_types &= 2201 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 2202 } 2203 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 2204 rss_conf->rss_hf |= ETH_RSS_IPV6; 2205 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 2206 } 2207 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 2208 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 2209 hash_types &= 2210 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 2211 } 2212 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 2213 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 2214 hash_types &= 2215 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 2216 } 2217 2218 rss_conf->rss_hf |= 2219 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode); 2220 2221 if (hash_types) { 2222 PMD_DRV_LOG(ERR, 2223 "Unknown RSS config from firmware (%08x), RSS disabled", 2224 vnic->hash_type); 2225 return -ENOTSUP; 2226 } 2227 } else { 2228 rss_conf->rss_hf = 0; 2229 } 2230 return 0; 2231 } 2232 2233 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 2234 struct rte_eth_fc_conf *fc_conf) 2235 { 2236 struct bnxt *bp = dev->data->dev_private; 2237 struct rte_eth_link link_info; 2238 int rc; 2239 2240 rc = is_bnxt_in_error(bp); 2241 if (rc) 2242 return rc; 2243 2244 rc = bnxt_get_hwrm_link_config(bp, &link_info); 2245 if (rc) 2246 return rc; 2247 2248 memset(fc_conf, 0, sizeof(*fc_conf)); 2249 if (bp->link_info->auto_pause) 2250 fc_conf->autoneg = 1; 2251 switch (bp->link_info->pause) { 2252 case 0: 2253 fc_conf->mode = RTE_FC_NONE; 2254 break; 2255 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 2256 fc_conf->mode = RTE_FC_TX_PAUSE; 2257 break; 2258 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 2259 fc_conf->mode = RTE_FC_RX_PAUSE; 2260 break; 2261 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 2262 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 2263 fc_conf->mode = RTE_FC_FULL; 2264 break; 2265 } 2266 return 0; 2267 } 2268 2269 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 2270 struct rte_eth_fc_conf *fc_conf) 2271 { 2272 struct bnxt *bp = dev->data->dev_private; 2273 int rc; 2274 2275 rc = is_bnxt_in_error(bp); 2276 if (rc) 2277 return rc; 2278 2279 if (!BNXT_SINGLE_PF(bp)) { 2280 PMD_DRV_LOG(ERR, 2281 "Flow Control Settings cannot be modified on VF or on shared PF\n"); 2282 return -ENOTSUP; 2283 } 2284 2285 switch (fc_conf->mode) { 2286 case RTE_FC_NONE: 2287 bp->link_info->auto_pause = 0; 2288 bp->link_info->force_pause = 0; 2289 break; 2290 case RTE_FC_RX_PAUSE: 2291 if (fc_conf->autoneg) { 2292 bp->link_info->auto_pause = 2293 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2294 bp->link_info->force_pause = 0; 2295 } else { 2296 bp->link_info->auto_pause = 0; 2297 bp->link_info->force_pause = 2298 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2299 } 2300 break; 2301 case RTE_FC_TX_PAUSE: 2302 if (fc_conf->autoneg) { 2303 bp->link_info->auto_pause = 2304 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 2305 bp->link_info->force_pause = 0; 2306 } else { 2307 bp->link_info->auto_pause = 0; 2308 bp->link_info->force_pause = 2309 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 2310 } 2311 break; 2312 case RTE_FC_FULL: 2313 if (fc_conf->autoneg) { 2314 bp->link_info->auto_pause = 2315 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 2316 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2317 bp->link_info->force_pause = 0; 2318 } else { 2319 bp->link_info->auto_pause = 0; 2320 bp->link_info->force_pause = 2321 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 2322 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2323 } 2324 break; 2325 } 2326 return bnxt_set_hwrm_link_config(bp, true); 2327 } 2328 2329 /* Add UDP tunneling port */ 2330 static int 2331 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 2332 struct rte_eth_udp_tunnel *udp_tunnel) 2333 { 2334 struct bnxt *bp = eth_dev->data->dev_private; 2335 uint16_t tunnel_type = 0; 2336 int rc = 0; 2337 2338 rc = is_bnxt_in_error(bp); 2339 if (rc) 2340 return rc; 2341 2342 switch (udp_tunnel->prot_type) { 2343 case RTE_TUNNEL_TYPE_VXLAN: 2344 if (bp->vxlan_port_cnt) { 2345 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2346 udp_tunnel->udp_port); 2347 if (bp->vxlan_port != udp_tunnel->udp_port) { 2348 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2349 return -ENOSPC; 2350 } 2351 bp->vxlan_port_cnt++; 2352 return 0; 2353 } 2354 tunnel_type = 2355 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 2356 bp->vxlan_port_cnt++; 2357 break; 2358 case RTE_TUNNEL_TYPE_GENEVE: 2359 if (bp->geneve_port_cnt) { 2360 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2361 udp_tunnel->udp_port); 2362 if (bp->geneve_port != udp_tunnel->udp_port) { 2363 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2364 return -ENOSPC; 2365 } 2366 bp->geneve_port_cnt++; 2367 return 0; 2368 } 2369 tunnel_type = 2370 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 2371 bp->geneve_port_cnt++; 2372 break; 2373 default: 2374 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2375 return -ENOTSUP; 2376 } 2377 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 2378 tunnel_type); 2379 return rc; 2380 } 2381 2382 static int 2383 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 2384 struct rte_eth_udp_tunnel *udp_tunnel) 2385 { 2386 struct bnxt *bp = eth_dev->data->dev_private; 2387 uint16_t tunnel_type = 0; 2388 uint16_t port = 0; 2389 int rc = 0; 2390 2391 rc = is_bnxt_in_error(bp); 2392 if (rc) 2393 return rc; 2394 2395 switch (udp_tunnel->prot_type) { 2396 case RTE_TUNNEL_TYPE_VXLAN: 2397 if (!bp->vxlan_port_cnt) { 2398 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2399 return -EINVAL; 2400 } 2401 if (bp->vxlan_port != udp_tunnel->udp_port) { 2402 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2403 udp_tunnel->udp_port, bp->vxlan_port); 2404 return -EINVAL; 2405 } 2406 if (--bp->vxlan_port_cnt) 2407 return 0; 2408 2409 tunnel_type = 2410 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 2411 port = bp->vxlan_fw_dst_port_id; 2412 break; 2413 case RTE_TUNNEL_TYPE_GENEVE: 2414 if (!bp->geneve_port_cnt) { 2415 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2416 return -EINVAL; 2417 } 2418 if (bp->geneve_port != udp_tunnel->udp_port) { 2419 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2420 udp_tunnel->udp_port, bp->geneve_port); 2421 return -EINVAL; 2422 } 2423 if (--bp->geneve_port_cnt) 2424 return 0; 2425 2426 tunnel_type = 2427 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 2428 port = bp->geneve_fw_dst_port_id; 2429 break; 2430 default: 2431 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2432 return -ENOTSUP; 2433 } 2434 2435 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 2436 return rc; 2437 } 2438 2439 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2440 { 2441 struct bnxt_filter_info *filter; 2442 struct bnxt_vnic_info *vnic; 2443 int rc = 0; 2444 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2445 2446 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2447 filter = STAILQ_FIRST(&vnic->filter); 2448 while (filter) { 2449 /* Search for this matching MAC+VLAN filter */ 2450 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 2451 /* Delete the filter */ 2452 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2453 if (rc) 2454 return rc; 2455 STAILQ_REMOVE(&vnic->filter, filter, 2456 bnxt_filter_info, next); 2457 bnxt_free_filter(bp, filter); 2458 PMD_DRV_LOG(INFO, 2459 "Deleted vlan filter for %d\n", 2460 vlan_id); 2461 return 0; 2462 } 2463 filter = STAILQ_NEXT(filter, next); 2464 } 2465 return -ENOENT; 2466 } 2467 2468 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2469 { 2470 struct bnxt_filter_info *filter; 2471 struct bnxt_vnic_info *vnic; 2472 int rc = 0; 2473 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 2474 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 2475 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2476 2477 /* Implementation notes on the use of VNIC in this command: 2478 * 2479 * By default, these filters belong to default vnic for the function. 2480 * Once these filters are set up, only destination VNIC can be modified. 2481 * If the destination VNIC is not specified in this command, 2482 * then the HWRM shall only create an l2 context id. 2483 */ 2484 2485 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2486 filter = STAILQ_FIRST(&vnic->filter); 2487 /* Check if the VLAN has already been added */ 2488 while (filter) { 2489 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 2490 return -EEXIST; 2491 2492 filter = STAILQ_NEXT(filter, next); 2493 } 2494 2495 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 2496 * command to create MAC+VLAN filter with the right flags, enables set. 2497 */ 2498 filter = bnxt_alloc_filter(bp); 2499 if (!filter) { 2500 PMD_DRV_LOG(ERR, 2501 "MAC/VLAN filter alloc failed\n"); 2502 return -ENOMEM; 2503 } 2504 /* MAC + VLAN ID filter */ 2505 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 2506 * untagged packets are received 2507 * 2508 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 2509 * packets and only the programmed vlan's packets are received 2510 */ 2511 filter->l2_ivlan = vlan_id; 2512 filter->l2_ivlan_mask = 0x0FFF; 2513 filter->enables |= en; 2514 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2515 2516 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2517 if (rc) { 2518 /* Free the newly allocated filter as we were 2519 * not able to create the filter in hardware. 2520 */ 2521 bnxt_free_filter(bp, filter); 2522 return rc; 2523 } 2524 2525 filter->mac_index = 0; 2526 /* Add this new filter to the list */ 2527 if (vlan_id == 0) 2528 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 2529 else 2530 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2531 2532 PMD_DRV_LOG(INFO, 2533 "Added Vlan filter for %d\n", vlan_id); 2534 return rc; 2535 } 2536 2537 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 2538 uint16_t vlan_id, int on) 2539 { 2540 struct bnxt *bp = eth_dev->data->dev_private; 2541 int rc; 2542 2543 rc = is_bnxt_in_error(bp); 2544 if (rc) 2545 return rc; 2546 2547 if (!eth_dev->data->dev_started) { 2548 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n"); 2549 return -EINVAL; 2550 } 2551 2552 /* These operations apply to ALL existing MAC/VLAN filters */ 2553 if (on) 2554 return bnxt_add_vlan_filter(bp, vlan_id); 2555 else 2556 return bnxt_del_vlan_filter(bp, vlan_id); 2557 } 2558 2559 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 2560 struct bnxt_vnic_info *vnic) 2561 { 2562 struct bnxt_filter_info *filter; 2563 int rc; 2564 2565 filter = STAILQ_FIRST(&vnic->filter); 2566 while (filter) { 2567 if (filter->mac_index == 0 && 2568 !memcmp(filter->l2_addr, bp->mac_addr, 2569 RTE_ETHER_ADDR_LEN)) { 2570 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2571 if (!rc) { 2572 STAILQ_REMOVE(&vnic->filter, filter, 2573 bnxt_filter_info, next); 2574 bnxt_free_filter(bp, filter); 2575 } 2576 return rc; 2577 } 2578 filter = STAILQ_NEXT(filter, next); 2579 } 2580 return 0; 2581 } 2582 2583 static int 2584 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 2585 { 2586 struct bnxt_vnic_info *vnic; 2587 unsigned int i; 2588 int rc; 2589 2590 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2591 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 2592 /* Remove any VLAN filters programmed */ 2593 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2594 bnxt_del_vlan_filter(bp, i); 2595 2596 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2597 if (rc) 2598 return rc; 2599 } else { 2600 /* Default filter will allow packets that match the 2601 * dest mac. So, it has to be deleted, otherwise, we 2602 * will endup receiving vlan packets for which the 2603 * filter is not programmed, when hw-vlan-filter 2604 * configuration is ON 2605 */ 2606 bnxt_del_dflt_mac_filter(bp, vnic); 2607 /* This filter will allow only untagged packets */ 2608 bnxt_add_vlan_filter(bp, 0); 2609 } 2610 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 2611 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 2612 2613 return 0; 2614 } 2615 2616 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 2617 { 2618 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2619 unsigned int i; 2620 int rc; 2621 2622 /* Destroy vnic filters and vnic */ 2623 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2624 DEV_RX_OFFLOAD_VLAN_FILTER) { 2625 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2626 bnxt_del_vlan_filter(bp, i); 2627 } 2628 bnxt_del_dflt_mac_filter(bp, vnic); 2629 2630 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic); 2631 if (rc) 2632 return rc; 2633 2634 rc = bnxt_hwrm_vnic_free(bp, vnic); 2635 if (rc) 2636 return rc; 2637 2638 rte_free(vnic->fw_grp_ids); 2639 vnic->fw_grp_ids = NULL; 2640 2641 vnic->rx_queue_cnt = 0; 2642 2643 return 0; 2644 } 2645 2646 static int 2647 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 2648 { 2649 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2650 int rc; 2651 2652 /* Destroy, recreate and reconfigure the default vnic */ 2653 rc = bnxt_free_one_vnic(bp, 0); 2654 if (rc) 2655 return rc; 2656 2657 /* default vnic 0 */ 2658 rc = bnxt_setup_one_vnic(bp, 0); 2659 if (rc) 2660 return rc; 2661 2662 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2663 DEV_RX_OFFLOAD_VLAN_FILTER) { 2664 rc = bnxt_add_vlan_filter(bp, 0); 2665 if (rc) 2666 return rc; 2667 rc = bnxt_restore_vlan_filters(bp); 2668 if (rc) 2669 return rc; 2670 } else { 2671 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2672 if (rc) 2673 return rc; 2674 } 2675 2676 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2677 if (rc) 2678 return rc; 2679 2680 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 2681 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 2682 2683 return rc; 2684 } 2685 2686 static int 2687 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 2688 { 2689 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 2690 struct bnxt *bp = dev->data->dev_private; 2691 int rc; 2692 2693 rc = is_bnxt_in_error(bp); 2694 if (rc) 2695 return rc; 2696 2697 /* Filter settings will get applied when port is started */ 2698 if (!dev->data->dev_started) 2699 return 0; 2700 2701 if (mask & ETH_VLAN_FILTER_MASK) { 2702 /* Enable or disable VLAN filtering */ 2703 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 2704 if (rc) 2705 return rc; 2706 } 2707 2708 if (mask & ETH_VLAN_STRIP_MASK) { 2709 /* Enable or disable VLAN stripping */ 2710 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2711 if (rc) 2712 return rc; 2713 } 2714 2715 if (mask & ETH_VLAN_EXTEND_MASK) { 2716 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2717 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2718 else 2719 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2720 } 2721 2722 return 0; 2723 } 2724 2725 static int 2726 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2727 uint16_t tpid) 2728 { 2729 struct bnxt *bp = dev->data->dev_private; 2730 int qinq = dev->data->dev_conf.rxmode.offloads & 2731 DEV_RX_OFFLOAD_VLAN_EXTEND; 2732 2733 if (vlan_type != ETH_VLAN_TYPE_INNER && 2734 vlan_type != ETH_VLAN_TYPE_OUTER) { 2735 PMD_DRV_LOG(ERR, 2736 "Unsupported vlan type."); 2737 return -EINVAL; 2738 } 2739 if (!qinq) { 2740 PMD_DRV_LOG(ERR, 2741 "QinQ not enabled. Needs to be ON as we can " 2742 "accelerate only outer vlan\n"); 2743 return -EINVAL; 2744 } 2745 2746 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 2747 switch (tpid) { 2748 case RTE_ETHER_TYPE_QINQ: 2749 bp->outer_tpid_bd = 2750 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2751 break; 2752 case RTE_ETHER_TYPE_VLAN: 2753 bp->outer_tpid_bd = 2754 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2755 break; 2756 case RTE_ETHER_TYPE_QINQ1: 2757 bp->outer_tpid_bd = 2758 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2759 break; 2760 case RTE_ETHER_TYPE_QINQ2: 2761 bp->outer_tpid_bd = 2762 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2763 break; 2764 case RTE_ETHER_TYPE_QINQ3: 2765 bp->outer_tpid_bd = 2766 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2767 break; 2768 default: 2769 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2770 return -EINVAL; 2771 } 2772 bp->outer_tpid_bd |= tpid; 2773 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2774 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 2775 PMD_DRV_LOG(ERR, 2776 "Can accelerate only outer vlan in QinQ\n"); 2777 return -EINVAL; 2778 } 2779 2780 return 0; 2781 } 2782 2783 static int 2784 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2785 struct rte_ether_addr *addr) 2786 { 2787 struct bnxt *bp = dev->data->dev_private; 2788 /* Default Filter is tied to VNIC 0 */ 2789 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2790 int rc; 2791 2792 rc = is_bnxt_in_error(bp); 2793 if (rc) 2794 return rc; 2795 2796 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2797 return -EPERM; 2798 2799 if (rte_is_zero_ether_addr(addr)) 2800 return -EINVAL; 2801 2802 /* Filter settings will get applied when port is started */ 2803 if (!dev->data->dev_started) 2804 return 0; 2805 2806 /* Check if the requested MAC is already added */ 2807 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2808 return 0; 2809 2810 /* Destroy filter and re-create it */ 2811 bnxt_del_dflt_mac_filter(bp, vnic); 2812 2813 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2814 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 2815 /* This filter will allow only untagged packets */ 2816 rc = bnxt_add_vlan_filter(bp, 0); 2817 } else { 2818 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2819 } 2820 2821 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2822 return rc; 2823 } 2824 2825 static int 2826 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2827 struct rte_ether_addr *mc_addr_set, 2828 uint32_t nb_mc_addr) 2829 { 2830 struct bnxt *bp = eth_dev->data->dev_private; 2831 char *mc_addr_list = (char *)mc_addr_set; 2832 struct bnxt_vnic_info *vnic; 2833 uint32_t off = 0, i = 0; 2834 int rc; 2835 2836 rc = is_bnxt_in_error(bp); 2837 if (rc) 2838 return rc; 2839 2840 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2841 2842 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2843 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2844 goto allmulti; 2845 } 2846 2847 /* TODO Check for Duplicate mcast addresses */ 2848 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2849 for (i = 0; i < nb_mc_addr; i++) { 2850 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2851 RTE_ETHER_ADDR_LEN); 2852 off += RTE_ETHER_ADDR_LEN; 2853 } 2854 2855 vnic->mc_addr_cnt = i; 2856 if (vnic->mc_addr_cnt) 2857 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2858 else 2859 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2860 2861 allmulti: 2862 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2863 } 2864 2865 static int 2866 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2867 { 2868 struct bnxt *bp = dev->data->dev_private; 2869 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2870 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2871 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2872 uint8_t fw_rsvd = bp->fw_ver & 0xff; 2873 int ret; 2874 2875 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", 2876 fw_major, fw_minor, fw_updt, fw_rsvd); 2877 if (ret < 0) 2878 return -EINVAL; 2879 2880 ret += 1; /* add the size of '\0' */ 2881 if (fw_size < (size_t)ret) 2882 return ret; 2883 else 2884 return 0; 2885 } 2886 2887 static void 2888 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2889 struct rte_eth_rxq_info *qinfo) 2890 { 2891 struct bnxt *bp = dev->data->dev_private; 2892 struct bnxt_rx_queue *rxq; 2893 2894 if (is_bnxt_in_error(bp)) 2895 return; 2896 2897 rxq = dev->data->rx_queues[queue_id]; 2898 2899 qinfo->mp = rxq->mb_pool; 2900 qinfo->scattered_rx = dev->data->scattered_rx; 2901 qinfo->nb_desc = rxq->nb_rx_desc; 2902 2903 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2904 qinfo->conf.rx_drop_en = rxq->drop_en; 2905 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2906 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 2907 } 2908 2909 static void 2910 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2911 struct rte_eth_txq_info *qinfo) 2912 { 2913 struct bnxt *bp = dev->data->dev_private; 2914 struct bnxt_tx_queue *txq; 2915 2916 if (is_bnxt_in_error(bp)) 2917 return; 2918 2919 txq = dev->data->tx_queues[queue_id]; 2920 2921 qinfo->nb_desc = txq->nb_tx_desc; 2922 2923 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2924 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2925 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2926 2927 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2928 qinfo->conf.tx_rs_thresh = 0; 2929 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2930 qinfo->conf.offloads = txq->offloads; 2931 } 2932 2933 static const struct { 2934 eth_rx_burst_t pkt_burst; 2935 const char *info; 2936 } bnxt_rx_burst_info[] = { 2937 {bnxt_recv_pkts, "Scalar"}, 2938 #if defined(RTE_ARCH_X86) 2939 {bnxt_recv_pkts_vec, "Vector SSE"}, 2940 #endif 2941 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 2942 {bnxt_recv_pkts_vec_avx2, "Vector AVX2"}, 2943 #endif 2944 #if defined(RTE_ARCH_ARM64) 2945 {bnxt_recv_pkts_vec, "Vector Neon"}, 2946 #endif 2947 }; 2948 2949 static int 2950 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2951 struct rte_eth_burst_mode *mode) 2952 { 2953 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 2954 size_t i; 2955 2956 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) { 2957 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) { 2958 snprintf(mode->info, sizeof(mode->info), "%s", 2959 bnxt_rx_burst_info[i].info); 2960 return 0; 2961 } 2962 } 2963 2964 return -EINVAL; 2965 } 2966 2967 static const struct { 2968 eth_tx_burst_t pkt_burst; 2969 const char *info; 2970 } bnxt_tx_burst_info[] = { 2971 {bnxt_xmit_pkts, "Scalar"}, 2972 #if defined(RTE_ARCH_X86) 2973 {bnxt_xmit_pkts_vec, "Vector SSE"}, 2974 #endif 2975 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 2976 {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"}, 2977 #endif 2978 #if defined(RTE_ARCH_ARM64) 2979 {bnxt_xmit_pkts_vec, "Vector Neon"}, 2980 #endif 2981 }; 2982 2983 static int 2984 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2985 struct rte_eth_burst_mode *mode) 2986 { 2987 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 2988 size_t i; 2989 2990 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) { 2991 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) { 2992 snprintf(mode->info, sizeof(mode->info), "%s", 2993 bnxt_tx_burst_info[i].info); 2994 return 0; 2995 } 2996 } 2997 2998 return -EINVAL; 2999 } 3000 3001 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 3002 { 3003 struct bnxt *bp = eth_dev->data->dev_private; 3004 uint32_t new_pkt_size; 3005 uint32_t rc = 0; 3006 uint32_t i; 3007 3008 rc = is_bnxt_in_error(bp); 3009 if (rc) 3010 return rc; 3011 3012 /* Exit if receive queues are not configured yet */ 3013 if (!eth_dev->data->nb_rx_queues) 3014 return rc; 3015 3016 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 3017 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 3018 3019 /* 3020 * Disallow any MTU change that would require scattered receive support 3021 * if it is not already enabled. 3022 */ 3023 if (eth_dev->data->dev_started && 3024 !eth_dev->data->scattered_rx && 3025 (new_pkt_size > 3026 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 3027 PMD_DRV_LOG(ERR, 3028 "MTU change would require scattered rx support. "); 3029 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 3030 return -EINVAL; 3031 } 3032 3033 if (new_mtu > RTE_ETHER_MTU) { 3034 bp->flags |= BNXT_FLAG_JUMBO; 3035 bp->eth_dev->data->dev_conf.rxmode.offloads |= 3036 DEV_RX_OFFLOAD_JUMBO_FRAME; 3037 } else { 3038 bp->eth_dev->data->dev_conf.rxmode.offloads &= 3039 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 3040 bp->flags &= ~BNXT_FLAG_JUMBO; 3041 } 3042 3043 /* Is there a change in mtu setting? */ 3044 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) 3045 return rc; 3046 3047 for (i = 0; i < bp->nr_vnics; i++) { 3048 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3049 uint16_t size = 0; 3050 3051 vnic->mru = BNXT_VNIC_MRU(new_mtu); 3052 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 3053 if (rc) 3054 break; 3055 3056 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 3057 size -= RTE_PKTMBUF_HEADROOM; 3058 3059 if (size < new_mtu) { 3060 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 3061 if (rc) 3062 return rc; 3063 } 3064 } 3065 3066 if (!rc) 3067 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 3068 3069 if (bnxt_hwrm_config_host_mtu(bp)) 3070 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n"); 3071 3072 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 3073 3074 return rc; 3075 } 3076 3077 static int 3078 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 3079 { 3080 struct bnxt *bp = dev->data->dev_private; 3081 uint16_t vlan = bp->vlan; 3082 int rc; 3083 3084 rc = is_bnxt_in_error(bp); 3085 if (rc) 3086 return rc; 3087 3088 if (!BNXT_SINGLE_PF(bp)) { 3089 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n"); 3090 return -ENOTSUP; 3091 } 3092 bp->vlan = on ? pvid : 0; 3093 3094 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 3095 if (rc) 3096 bp->vlan = vlan; 3097 return rc; 3098 } 3099 3100 static int 3101 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 3102 { 3103 struct bnxt *bp = dev->data->dev_private; 3104 int rc; 3105 3106 rc = is_bnxt_in_error(bp); 3107 if (rc) 3108 return rc; 3109 3110 return bnxt_hwrm_port_led_cfg(bp, true); 3111 } 3112 3113 static int 3114 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 3115 { 3116 struct bnxt *bp = dev->data->dev_private; 3117 int rc; 3118 3119 rc = is_bnxt_in_error(bp); 3120 if (rc) 3121 return rc; 3122 3123 return bnxt_hwrm_port_led_cfg(bp, false); 3124 } 3125 3126 static uint32_t 3127 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 3128 { 3129 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 3130 struct bnxt_cp_ring_info *cpr; 3131 uint32_t desc = 0, raw_cons, cp_ring_size; 3132 struct bnxt_rx_queue *rxq; 3133 struct rx_pkt_cmpl *rxcmp; 3134 int rc; 3135 3136 rc = is_bnxt_in_error(bp); 3137 if (rc) 3138 return rc; 3139 3140 rxq = dev->data->rx_queues[rx_queue_id]; 3141 cpr = rxq->cp_ring; 3142 raw_cons = cpr->cp_raw_cons; 3143 cp_ring_size = cpr->cp_ring_struct->ring_size; 3144 3145 while (1) { 3146 uint32_t agg_cnt, cons, cmpl_type; 3147 3148 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3149 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3150 3151 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size)) 3152 break; 3153 3154 cmpl_type = CMP_TYPE(rxcmp); 3155 3156 switch (cmpl_type) { 3157 case CMPL_BASE_TYPE_RX_L2: 3158 case CMPL_BASE_TYPE_RX_L2_V2: 3159 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3160 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3161 desc++; 3162 break; 3163 3164 case CMPL_BASE_TYPE_RX_TPA_END: 3165 if (BNXT_CHIP_P5(rxq->bp)) { 3166 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3167 3168 p5_tpa_end = (void *)rxcmp; 3169 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3170 } else { 3171 struct rx_tpa_end_cmpl *tpa_end; 3172 3173 tpa_end = (void *)rxcmp; 3174 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3175 } 3176 3177 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3178 desc++; 3179 break; 3180 3181 default: 3182 raw_cons += CMP_LEN(cmpl_type); 3183 } 3184 } 3185 3186 return desc; 3187 } 3188 3189 static int 3190 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 3191 { 3192 struct bnxt_rx_queue *rxq = rx_queue; 3193 struct bnxt_cp_ring_info *cpr; 3194 struct bnxt_rx_ring_info *rxr; 3195 uint32_t desc, raw_cons, cp_ring_size; 3196 struct bnxt *bp = rxq->bp; 3197 struct rx_pkt_cmpl *rxcmp; 3198 int rc; 3199 3200 rc = is_bnxt_in_error(bp); 3201 if (rc) 3202 return rc; 3203 3204 if (offset >= rxq->nb_rx_desc) 3205 return -EINVAL; 3206 3207 rxr = rxq->rx_ring; 3208 cpr = rxq->cp_ring; 3209 cp_ring_size = cpr->cp_ring_struct->ring_size; 3210 3211 /* 3212 * For the vector receive case, the completion at the requested 3213 * offset can be indexed directly. 3214 */ 3215 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 3216 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) { 3217 struct rx_pkt_cmpl *rxcmp; 3218 uint32_t cons; 3219 3220 /* Check status of completion descriptor. */ 3221 raw_cons = cpr->cp_raw_cons + 3222 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2); 3223 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3224 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3225 3226 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size)) 3227 return RTE_ETH_RX_DESC_DONE; 3228 3229 /* Check whether rx desc has an mbuf attached. */ 3230 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2); 3231 if (cons >= rxq->rxrearm_start && 3232 cons < rxq->rxrearm_start + rxq->rxrearm_nb) { 3233 return RTE_ETH_RX_DESC_UNAVAIL; 3234 } 3235 3236 return RTE_ETH_RX_DESC_AVAIL; 3237 } 3238 #endif 3239 3240 /* 3241 * For the non-vector receive case, scan the completion ring to 3242 * locate the completion descriptor for the requested offset. 3243 */ 3244 raw_cons = cpr->cp_raw_cons; 3245 desc = 0; 3246 while (1) { 3247 uint32_t agg_cnt, cons, cmpl_type; 3248 3249 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3250 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3251 3252 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size)) 3253 break; 3254 3255 cmpl_type = CMP_TYPE(rxcmp); 3256 3257 switch (cmpl_type) { 3258 case CMPL_BASE_TYPE_RX_L2: 3259 case CMPL_BASE_TYPE_RX_L2_V2: 3260 if (desc == offset) { 3261 cons = rxcmp->opaque; 3262 if (rxr->rx_buf_ring[cons]) 3263 return RTE_ETH_RX_DESC_DONE; 3264 else 3265 return RTE_ETH_RX_DESC_UNAVAIL; 3266 } 3267 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3268 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3269 desc++; 3270 break; 3271 3272 case CMPL_BASE_TYPE_RX_TPA_END: 3273 if (desc == offset) 3274 return RTE_ETH_RX_DESC_DONE; 3275 3276 if (BNXT_CHIP_P5(rxq->bp)) { 3277 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3278 3279 p5_tpa_end = (void *)rxcmp; 3280 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3281 } else { 3282 struct rx_tpa_end_cmpl *tpa_end; 3283 3284 tpa_end = (void *)rxcmp; 3285 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3286 } 3287 3288 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3289 desc++; 3290 break; 3291 3292 default: 3293 raw_cons += CMP_LEN(cmpl_type); 3294 } 3295 } 3296 3297 return RTE_ETH_RX_DESC_AVAIL; 3298 } 3299 3300 static int 3301 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 3302 { 3303 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 3304 struct bnxt_cp_ring_info *cpr = txq->cp_ring; 3305 uint32_t ring_mask, raw_cons, nb_tx_pkts = 0; 3306 struct cmpl_base *cp_desc_ring; 3307 int rc; 3308 3309 rc = is_bnxt_in_error(txq->bp); 3310 if (rc) 3311 return rc; 3312 3313 if (offset >= txq->nb_tx_desc) 3314 return -EINVAL; 3315 3316 /* Return "desc done" if descriptor is available for use. */ 3317 if (bnxt_tx_bds_in_hw(txq) <= offset) 3318 return RTE_ETH_TX_DESC_DONE; 3319 3320 raw_cons = cpr->cp_raw_cons; 3321 cp_desc_ring = cpr->cp_desc_ring; 3322 ring_mask = cpr->cp_ring_struct->ring_mask; 3323 3324 /* Check to see if hw has posted a completion for the descriptor. */ 3325 while (1) { 3326 struct tx_cmpl *txcmp; 3327 uint32_t cons; 3328 3329 cons = RING_CMPL(ring_mask, raw_cons); 3330 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons]; 3331 3332 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1)) 3333 break; 3334 3335 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2) 3336 nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque); 3337 3338 if (nb_tx_pkts > offset) 3339 return RTE_ETH_TX_DESC_DONE; 3340 3341 raw_cons = NEXT_RAW_CMP(raw_cons); 3342 } 3343 3344 /* Descriptor is pending transmit, not yet completed by hardware. */ 3345 return RTE_ETH_TX_DESC_FULL; 3346 } 3347 3348 int 3349 bnxt_flow_ops_get_op(struct rte_eth_dev *dev, 3350 const struct rte_flow_ops **ops) 3351 { 3352 struct bnxt *bp = dev->data->dev_private; 3353 int ret = 0; 3354 3355 if (!bp) 3356 return -EIO; 3357 3358 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) { 3359 struct bnxt_representor *vfr = dev->data->dev_private; 3360 bp = vfr->parent_dev->data->dev_private; 3361 /* parent is deleted while children are still valid */ 3362 if (!bp) { 3363 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n", 3364 dev->data->port_id); 3365 return -EIO; 3366 } 3367 } 3368 3369 ret = is_bnxt_in_error(bp); 3370 if (ret) 3371 return ret; 3372 3373 /* PMD supports thread-safe flow operations. rte_flow API 3374 * functions can avoid mutex for multi-thread safety. 3375 */ 3376 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 3377 3378 if (BNXT_TRUFLOW_EN(bp)) 3379 *ops = &bnxt_ulp_rte_flow_ops; 3380 else 3381 *ops = &bnxt_flow_ops; 3382 3383 return ret; 3384 } 3385 3386 static const uint32_t * 3387 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3388 { 3389 static const uint32_t ptypes[] = { 3390 RTE_PTYPE_L2_ETHER_VLAN, 3391 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3392 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3393 RTE_PTYPE_L4_ICMP, 3394 RTE_PTYPE_L4_TCP, 3395 RTE_PTYPE_L4_UDP, 3396 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3397 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3398 RTE_PTYPE_INNER_L4_ICMP, 3399 RTE_PTYPE_INNER_L4_TCP, 3400 RTE_PTYPE_INNER_L4_UDP, 3401 RTE_PTYPE_UNKNOWN 3402 }; 3403 3404 if (!dev->rx_pkt_burst) 3405 return NULL; 3406 3407 return ptypes; 3408 } 3409 3410 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3411 int reg_win) 3412 { 3413 uint32_t reg_base = *reg_arr & 0xfffff000; 3414 uint32_t win_off; 3415 int i; 3416 3417 for (i = 0; i < count; i++) { 3418 if ((reg_arr[i] & 0xfffff000) != reg_base) 3419 return -ERANGE; 3420 } 3421 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3422 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3423 return 0; 3424 } 3425 3426 static int bnxt_map_ptp_regs(struct bnxt *bp) 3427 { 3428 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3429 uint32_t *reg_arr; 3430 int rc, i; 3431 3432 reg_arr = ptp->rx_regs; 3433 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3434 if (rc) 3435 return rc; 3436 3437 reg_arr = ptp->tx_regs; 3438 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3439 if (rc) 3440 return rc; 3441 3442 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3443 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3444 3445 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3446 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3447 3448 return 0; 3449 } 3450 3451 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3452 { 3453 rte_write32(0, (uint8_t *)bp->bar0 + 3454 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3455 rte_write32(0, (uint8_t *)bp->bar0 + 3456 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3457 } 3458 3459 static uint64_t bnxt_cc_read(struct bnxt *bp) 3460 { 3461 uint64_t ns; 3462 3463 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3464 BNXT_GRCPF_REG_SYNC_TIME)); 3465 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3466 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3467 return ns; 3468 } 3469 3470 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3471 { 3472 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3473 uint32_t fifo; 3474 3475 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3476 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3477 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3478 return -EAGAIN; 3479 3480 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3481 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3482 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3483 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3484 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3485 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3486 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]); 3487 3488 return 0; 3489 } 3490 3491 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts) 3492 { 3493 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3494 struct bnxt_pf_info *pf = bp->pf; 3495 uint16_t port_id; 3496 int i = 0; 3497 uint32_t fifo; 3498 3499 if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5)) 3500 return -EINVAL; 3501 3502 port_id = pf->port_id; 3503 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3504 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3505 while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) { 3506 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3507 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3508 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3509 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3510 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3511 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3512 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3513 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3514 i++; 3515 } 3516 3517 if (i >= BNXT_PTP_RX_PND_CNT) 3518 return -EBUSY; 3519 3520 return 0; 3521 } 3522 3523 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3524 { 3525 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3526 struct bnxt_pf_info *pf = bp->pf; 3527 uint16_t port_id; 3528 uint32_t fifo; 3529 3530 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3531 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3532 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3533 return -EAGAIN; 3534 3535 port_id = pf->port_id; 3536 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3537 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3538 3539 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3540 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3541 if (fifo & BNXT_PTP_RX_FIFO_PENDING) 3542 return bnxt_clr_rx_ts(bp, ts); 3543 3544 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3545 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3546 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3547 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3548 3549 return 0; 3550 } 3551 3552 static int 3553 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3554 { 3555 uint64_t ns; 3556 struct bnxt *bp = dev->data->dev_private; 3557 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3558 3559 if (!ptp) 3560 return -ENOTSUP; 3561 3562 ns = rte_timespec_to_ns(ts); 3563 /* Set the timecounters to a new value. */ 3564 ptp->tc.nsec = ns; 3565 ptp->tx_tstamp_tc.nsec = ns; 3566 ptp->rx_tstamp_tc.nsec = ns; 3567 3568 return 0; 3569 } 3570 3571 static int 3572 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3573 { 3574 struct bnxt *bp = dev->data->dev_private; 3575 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3576 uint64_t ns, systime_cycles = 0; 3577 int rc = 0; 3578 3579 if (!ptp) 3580 return -ENOTSUP; 3581 3582 if (BNXT_CHIP_P5(bp)) 3583 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3584 &systime_cycles); 3585 else 3586 systime_cycles = bnxt_cc_read(bp); 3587 3588 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3589 *ts = rte_ns_to_timespec(ns); 3590 3591 return rc; 3592 } 3593 static int 3594 bnxt_timesync_enable(struct rte_eth_dev *dev) 3595 { 3596 struct bnxt *bp = dev->data->dev_private; 3597 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3598 uint32_t shift = 0; 3599 int rc; 3600 3601 if (!ptp) 3602 return -ENOTSUP; 3603 3604 ptp->rx_filter = 1; 3605 ptp->tx_tstamp_en = 1; 3606 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3607 3608 rc = bnxt_hwrm_ptp_cfg(bp); 3609 if (rc) 3610 return rc; 3611 3612 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3613 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3614 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3615 3616 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3617 ptp->tc.cc_shift = shift; 3618 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3619 3620 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3621 ptp->rx_tstamp_tc.cc_shift = shift; 3622 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3623 3624 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3625 ptp->tx_tstamp_tc.cc_shift = shift; 3626 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3627 3628 if (!BNXT_CHIP_P5(bp)) 3629 bnxt_map_ptp_regs(bp); 3630 else 3631 rc = bnxt_ptp_start(bp); 3632 3633 return rc; 3634 } 3635 3636 static int 3637 bnxt_timesync_disable(struct rte_eth_dev *dev) 3638 { 3639 struct bnxt *bp = dev->data->dev_private; 3640 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3641 3642 if (!ptp) 3643 return -ENOTSUP; 3644 3645 ptp->rx_filter = 0; 3646 ptp->tx_tstamp_en = 0; 3647 ptp->rxctl = 0; 3648 3649 bnxt_hwrm_ptp_cfg(bp); 3650 3651 if (!BNXT_CHIP_P5(bp)) 3652 bnxt_unmap_ptp_regs(bp); 3653 else 3654 bnxt_ptp_stop(bp); 3655 3656 return 0; 3657 } 3658 3659 static int 3660 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3661 struct timespec *timestamp, 3662 uint32_t flags __rte_unused) 3663 { 3664 struct bnxt *bp = dev->data->dev_private; 3665 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3666 uint64_t rx_tstamp_cycles = 0; 3667 uint64_t ns; 3668 3669 if (!ptp) 3670 return -ENOTSUP; 3671 3672 if (BNXT_CHIP_P5(bp)) 3673 rx_tstamp_cycles = ptp->rx_timestamp; 3674 else 3675 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3676 3677 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3678 *timestamp = rte_ns_to_timespec(ns); 3679 return 0; 3680 } 3681 3682 static int 3683 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3684 struct timespec *timestamp) 3685 { 3686 struct bnxt *bp = dev->data->dev_private; 3687 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3688 uint64_t tx_tstamp_cycles = 0; 3689 uint64_t ns; 3690 int rc = 0; 3691 3692 if (!ptp) 3693 return -ENOTSUP; 3694 3695 if (BNXT_CHIP_P5(bp)) 3696 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3697 &tx_tstamp_cycles); 3698 else 3699 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3700 3701 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3702 *timestamp = rte_ns_to_timespec(ns); 3703 3704 return rc; 3705 } 3706 3707 static int 3708 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3709 { 3710 struct bnxt *bp = dev->data->dev_private; 3711 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3712 3713 if (!ptp) 3714 return -ENOTSUP; 3715 3716 ptp->tc.nsec += delta; 3717 ptp->tx_tstamp_tc.nsec += delta; 3718 ptp->rx_tstamp_tc.nsec += delta; 3719 3720 return 0; 3721 } 3722 3723 static int 3724 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3725 { 3726 struct bnxt *bp = dev->data->dev_private; 3727 int rc; 3728 uint32_t dir_entries; 3729 uint32_t entry_length; 3730 3731 rc = is_bnxt_in_error(bp); 3732 if (rc) 3733 return rc; 3734 3735 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 3736 bp->pdev->addr.domain, bp->pdev->addr.bus, 3737 bp->pdev->addr.devid, bp->pdev->addr.function); 3738 3739 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3740 if (rc != 0) 3741 return rc; 3742 3743 return dir_entries * entry_length; 3744 } 3745 3746 static int 3747 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3748 struct rte_dev_eeprom_info *in_eeprom) 3749 { 3750 struct bnxt *bp = dev->data->dev_private; 3751 uint32_t index; 3752 uint32_t offset; 3753 int rc; 3754 3755 rc = is_bnxt_in_error(bp); 3756 if (rc) 3757 return rc; 3758 3759 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3760 bp->pdev->addr.domain, bp->pdev->addr.bus, 3761 bp->pdev->addr.devid, bp->pdev->addr.function, 3762 in_eeprom->offset, in_eeprom->length); 3763 3764 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3765 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3766 in_eeprom->data); 3767 3768 index = in_eeprom->offset >> 24; 3769 offset = in_eeprom->offset & 0xffffff; 3770 3771 if (index != 0) 3772 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3773 in_eeprom->length, in_eeprom->data); 3774 3775 return 0; 3776 } 3777 3778 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3779 { 3780 switch (dir_type) { 3781 case BNX_DIR_TYPE_CHIMP_PATCH: 3782 case BNX_DIR_TYPE_BOOTCODE: 3783 case BNX_DIR_TYPE_BOOTCODE_2: 3784 case BNX_DIR_TYPE_APE_FW: 3785 case BNX_DIR_TYPE_APE_PATCH: 3786 case BNX_DIR_TYPE_KONG_FW: 3787 case BNX_DIR_TYPE_KONG_PATCH: 3788 case BNX_DIR_TYPE_BONO_FW: 3789 case BNX_DIR_TYPE_BONO_PATCH: 3790 /* FALLTHROUGH */ 3791 return true; 3792 } 3793 3794 return false; 3795 } 3796 3797 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3798 { 3799 switch (dir_type) { 3800 case BNX_DIR_TYPE_AVS: 3801 case BNX_DIR_TYPE_EXP_ROM_MBA: 3802 case BNX_DIR_TYPE_PCIE: 3803 case BNX_DIR_TYPE_TSCF_UCODE: 3804 case BNX_DIR_TYPE_EXT_PHY: 3805 case BNX_DIR_TYPE_CCM: 3806 case BNX_DIR_TYPE_ISCSI_BOOT: 3807 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3808 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3809 /* FALLTHROUGH */ 3810 return true; 3811 } 3812 3813 return false; 3814 } 3815 3816 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3817 { 3818 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3819 bnxt_dir_type_is_other_exec_format(dir_type); 3820 } 3821 3822 static int 3823 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3824 struct rte_dev_eeprom_info *in_eeprom) 3825 { 3826 struct bnxt *bp = dev->data->dev_private; 3827 uint8_t index, dir_op; 3828 uint16_t type, ext, ordinal, attr; 3829 int rc; 3830 3831 rc = is_bnxt_in_error(bp); 3832 if (rc) 3833 return rc; 3834 3835 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3836 bp->pdev->addr.domain, bp->pdev->addr.bus, 3837 bp->pdev->addr.devid, bp->pdev->addr.function, 3838 in_eeprom->offset, in_eeprom->length); 3839 3840 if (!BNXT_PF(bp)) { 3841 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3842 return -EINVAL; 3843 } 3844 3845 type = in_eeprom->magic >> 16; 3846 3847 if (type == 0xffff) { /* special value for directory operations */ 3848 index = in_eeprom->magic & 0xff; 3849 dir_op = in_eeprom->magic >> 8; 3850 if (index == 0) 3851 return -EINVAL; 3852 switch (dir_op) { 3853 case 0x0e: /* erase */ 3854 if (in_eeprom->offset != ~in_eeprom->magic) 3855 return -EINVAL; 3856 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3857 default: 3858 return -EINVAL; 3859 } 3860 } 3861 3862 /* Create or re-write an NVM item: */ 3863 if (bnxt_dir_type_is_executable(type) == true) 3864 return -EOPNOTSUPP; 3865 ext = in_eeprom->magic & 0xffff; 3866 ordinal = in_eeprom->offset >> 16; 3867 attr = in_eeprom->offset & 0xffff; 3868 3869 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3870 in_eeprom->data, in_eeprom->length); 3871 } 3872 3873 static int bnxt_get_module_info(struct rte_eth_dev *dev, 3874 struct rte_eth_dev_module_info *modinfo) 3875 { 3876 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1]; 3877 struct bnxt *bp = dev->data->dev_private; 3878 int rc; 3879 3880 /* No point in going further if phy status indicates 3881 * module is not inserted or if it is powered down or 3882 * if it is of type 10GBase-T 3883 */ 3884 if (bp->link_info->module_status > 3885 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) { 3886 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n", 3887 dev->data->port_id); 3888 return -ENOTSUP; 3889 } 3890 3891 /* This feature is not supported in older firmware versions */ 3892 if (bp->hwrm_spec_code < 0x10202) { 3893 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n", 3894 dev->data->port_id); 3895 return -ENOTSUP; 3896 } 3897 3898 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3899 SFF_DIAG_SUPPORT_OFFSET + 1, 3900 module_info); 3901 3902 if (rc) 3903 return rc; 3904 3905 switch (module_info[0]) { 3906 case SFF_MODULE_ID_SFP: 3907 modinfo->type = RTE_ETH_MODULE_SFF_8472; 3908 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 3909 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0) 3910 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN; 3911 break; 3912 case SFF_MODULE_ID_QSFP: 3913 case SFF_MODULE_ID_QSFP_PLUS: 3914 modinfo->type = RTE_ETH_MODULE_SFF_8436; 3915 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN; 3916 break; 3917 case SFF_MODULE_ID_QSFP28: 3918 modinfo->type = RTE_ETH_MODULE_SFF_8636; 3919 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 3920 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) 3921 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN; 3922 break; 3923 default: 3924 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id); 3925 return -ENOTSUP; 3926 } 3927 3928 PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n", 3929 dev->data->port_id, modinfo->type, modinfo->eeprom_len); 3930 3931 return 0; 3932 } 3933 3934 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev, 3935 struct rte_dev_eeprom_info *info) 3936 { 3937 uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 }; 3938 uint32_t offset = info->offset, length = info->length; 3939 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1]; 3940 struct bnxt *bp = dev->data->dev_private; 3941 uint8_t *data = info->data; 3942 uint8_t page = offset >> 7; 3943 uint8_t max_pages = 2; 3944 uint8_t opt_pages; 3945 int rc; 3946 3947 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3948 SFF_DIAG_SUPPORT_OFFSET + 1, 3949 module_info); 3950 if (rc) 3951 return rc; 3952 3953 switch (module_info[0]) { 3954 case SFF_MODULE_ID_SFP: 3955 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0; 3956 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) { 3957 pg_addr[2] = I2C_DEV_ADDR_A2; 3958 pg_addr[3] = I2C_DEV_ADDR_A2; 3959 max_pages = 4; 3960 } 3961 break; 3962 case SFF_MODULE_ID_QSFP28: 3963 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 3964 SFF8636_OPT_PAGES_OFFSET, 3965 1, &opt_pages); 3966 if (rc) 3967 return rc; 3968 3969 if (opt_pages & SFF8636_PAGE1_MASK) { 3970 pg_addr[2] = I2C_DEV_ADDR_A0; 3971 max_pages = 3; 3972 } 3973 if (opt_pages & SFF8636_PAGE2_MASK) { 3974 pg_addr[3] = I2C_DEV_ADDR_A0; 3975 max_pages = 4; 3976 } 3977 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) { 3978 pg_addr[4] = I2C_DEV_ADDR_A0; 3979 max_pages = 5; 3980 } 3981 break; 3982 default: 3983 break; 3984 } 3985 3986 memset(data, 0, length); 3987 3988 offset &= 0xff; 3989 while (length && page < max_pages) { 3990 uint8_t raw_page = page ? page - 1 : 0; 3991 uint16_t chunk; 3992 3993 if (pg_addr[page] == I2C_DEV_ADDR_A2) 3994 raw_page = 0; 3995 else if (page) 3996 offset |= 0x80; 3997 chunk = RTE_MIN(length, 256 - offset); 3998 3999 if (pg_addr[page]) { 4000 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page], 4001 raw_page, offset, 4002 chunk, data); 4003 if (rc) 4004 return rc; 4005 } 4006 4007 data += chunk; 4008 length -= chunk; 4009 offset = 0; 4010 page += 1 + (chunk > 128); 4011 } 4012 4013 return length ? -EINVAL : 0; 4014 } 4015 4016 /* 4017 * Initialization 4018 */ 4019 4020 static const struct eth_dev_ops bnxt_dev_ops = { 4021 .dev_infos_get = bnxt_dev_info_get_op, 4022 .dev_close = bnxt_dev_close_op, 4023 .dev_configure = bnxt_dev_configure_op, 4024 .dev_start = bnxt_dev_start_op, 4025 .dev_stop = bnxt_dev_stop_op, 4026 .dev_set_link_up = bnxt_dev_set_link_up_op, 4027 .dev_set_link_down = bnxt_dev_set_link_down_op, 4028 .stats_get = bnxt_stats_get_op, 4029 .stats_reset = bnxt_stats_reset_op, 4030 .rx_queue_setup = bnxt_rx_queue_setup_op, 4031 .rx_queue_release = bnxt_rx_queue_release_op, 4032 .tx_queue_setup = bnxt_tx_queue_setup_op, 4033 .tx_queue_release = bnxt_tx_queue_release_op, 4034 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 4035 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 4036 .reta_update = bnxt_reta_update_op, 4037 .reta_query = bnxt_reta_query_op, 4038 .rss_hash_update = bnxt_rss_hash_update_op, 4039 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 4040 .link_update = bnxt_link_update_op, 4041 .promiscuous_enable = bnxt_promiscuous_enable_op, 4042 .promiscuous_disable = bnxt_promiscuous_disable_op, 4043 .allmulticast_enable = bnxt_allmulticast_enable_op, 4044 .allmulticast_disable = bnxt_allmulticast_disable_op, 4045 .mac_addr_add = bnxt_mac_addr_add_op, 4046 .mac_addr_remove = bnxt_mac_addr_remove_op, 4047 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 4048 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 4049 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 4050 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 4051 .vlan_filter_set = bnxt_vlan_filter_set_op, 4052 .vlan_offload_set = bnxt_vlan_offload_set_op, 4053 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 4054 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 4055 .mtu_set = bnxt_mtu_set_op, 4056 .mac_addr_set = bnxt_set_default_mac_addr_op, 4057 .xstats_get = bnxt_dev_xstats_get_op, 4058 .xstats_get_names = bnxt_dev_xstats_get_names_op, 4059 .xstats_reset = bnxt_dev_xstats_reset_op, 4060 .fw_version_get = bnxt_fw_version_get, 4061 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 4062 .rxq_info_get = bnxt_rxq_info_get_op, 4063 .txq_info_get = bnxt_txq_info_get_op, 4064 .rx_burst_mode_get = bnxt_rx_burst_mode_get, 4065 .tx_burst_mode_get = bnxt_tx_burst_mode_get, 4066 .dev_led_on = bnxt_dev_led_on_op, 4067 .dev_led_off = bnxt_dev_led_off_op, 4068 .rx_queue_start = bnxt_rx_queue_start, 4069 .rx_queue_stop = bnxt_rx_queue_stop, 4070 .tx_queue_start = bnxt_tx_queue_start, 4071 .tx_queue_stop = bnxt_tx_queue_stop, 4072 .flow_ops_get = bnxt_flow_ops_get_op, 4073 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 4074 .get_eeprom_length = bnxt_get_eeprom_length_op, 4075 .get_eeprom = bnxt_get_eeprom_op, 4076 .set_eeprom = bnxt_set_eeprom_op, 4077 .get_module_info = bnxt_get_module_info, 4078 .get_module_eeprom = bnxt_get_module_eeprom, 4079 .timesync_enable = bnxt_timesync_enable, 4080 .timesync_disable = bnxt_timesync_disable, 4081 .timesync_read_time = bnxt_timesync_read_time, 4082 .timesync_write_time = bnxt_timesync_write_time, 4083 .timesync_adjust_time = bnxt_timesync_adjust_time, 4084 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 4085 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 4086 }; 4087 4088 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 4089 { 4090 uint32_t offset; 4091 4092 /* Only pre-map the reset GRC registers using window 3 */ 4093 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 4094 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 4095 4096 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 4097 4098 return offset; 4099 } 4100 4101 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 4102 { 4103 struct bnxt_error_recovery_info *info = bp->recovery_info; 4104 uint32_t reg_base = 0xffffffff; 4105 int i; 4106 4107 /* Only pre-map the monitoring GRC registers using window 2 */ 4108 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 4109 uint32_t reg = info->status_regs[i]; 4110 4111 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 4112 continue; 4113 4114 if (reg_base == 0xffffffff) 4115 reg_base = reg & 0xfffff000; 4116 if ((reg & 0xfffff000) != reg_base) 4117 return -ERANGE; 4118 4119 /* Use mask 0xffc as the Lower 2 bits indicates 4120 * address space location 4121 */ 4122 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 4123 (reg & 0xffc); 4124 } 4125 4126 if (reg_base == 0xffffffff) 4127 return 0; 4128 4129 rte_write32(reg_base, (uint8_t *)bp->bar0 + 4130 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4131 4132 return 0; 4133 } 4134 4135 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 4136 { 4137 struct bnxt_error_recovery_info *info = bp->recovery_info; 4138 uint32_t delay = info->delay_after_reset[index]; 4139 uint32_t val = info->reset_reg_val[index]; 4140 uint32_t reg = info->reset_reg[index]; 4141 uint32_t type, offset; 4142 int ret; 4143 4144 type = BNXT_FW_STATUS_REG_TYPE(reg); 4145 offset = BNXT_FW_STATUS_REG_OFF(reg); 4146 4147 switch (type) { 4148 case BNXT_FW_STATUS_REG_TYPE_CFG: 4149 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 4150 if (ret < 0) { 4151 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x", 4152 val, offset); 4153 return; 4154 } 4155 break; 4156 case BNXT_FW_STATUS_REG_TYPE_GRC: 4157 offset = bnxt_map_reset_regs(bp, offset); 4158 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4159 break; 4160 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4161 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4162 break; 4163 } 4164 /* wait on a specific interval of time until core reset is complete */ 4165 if (delay) 4166 rte_delay_ms(delay); 4167 } 4168 4169 static void bnxt_dev_cleanup(struct bnxt *bp) 4170 { 4171 bp->eth_dev->data->dev_link.link_status = 0; 4172 bp->link_info->link_up = 0; 4173 if (bp->eth_dev->data->dev_started) 4174 bnxt_dev_stop(bp->eth_dev); 4175 4176 bnxt_uninit_resources(bp, true); 4177 } 4178 4179 static int 4180 bnxt_check_fw_reset_done(struct bnxt *bp) 4181 { 4182 int timeout = bp->fw_reset_max_msecs; 4183 uint16_t val = 0; 4184 int rc; 4185 4186 do { 4187 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 4188 if (rc < 0) { 4189 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 4190 return rc; 4191 } 4192 if (val != 0xffff) 4193 break; 4194 rte_delay_ms(1); 4195 } while (timeout--); 4196 4197 if (val == 0xffff) { 4198 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); 4199 return -1; 4200 } 4201 4202 return 0; 4203 } 4204 4205 static int bnxt_restore_vlan_filters(struct bnxt *bp) 4206 { 4207 struct rte_eth_dev *dev = bp->eth_dev; 4208 struct rte_vlan_filter_conf *vfc; 4209 int vidx, vbit, rc; 4210 uint16_t vlan_id; 4211 4212 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 4213 vfc = &dev->data->vlan_filter_conf; 4214 vidx = vlan_id / 64; 4215 vbit = vlan_id % 64; 4216 4217 /* Each bit corresponds to a VLAN id */ 4218 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 4219 rc = bnxt_add_vlan_filter(bp, vlan_id); 4220 if (rc) 4221 return rc; 4222 } 4223 } 4224 4225 return 0; 4226 } 4227 4228 static int bnxt_restore_mac_filters(struct bnxt *bp) 4229 { 4230 struct rte_eth_dev *dev = bp->eth_dev; 4231 struct rte_eth_dev_info dev_info; 4232 struct rte_ether_addr *addr; 4233 uint64_t pool_mask; 4234 uint32_t pool = 0; 4235 uint32_t i; 4236 int rc; 4237 4238 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4239 return 0; 4240 4241 rc = bnxt_dev_info_get_op(dev, &dev_info); 4242 if (rc) 4243 return rc; 4244 4245 /* replay MAC address configuration */ 4246 for (i = 1; i < dev_info.max_mac_addrs; i++) { 4247 addr = &dev->data->mac_addrs[i]; 4248 4249 /* skip zero address */ 4250 if (rte_is_zero_ether_addr(addr)) 4251 continue; 4252 4253 pool = 0; 4254 pool_mask = dev->data->mac_pool_sel[i]; 4255 4256 do { 4257 if (pool_mask & 1ULL) { 4258 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 4259 if (rc) 4260 return rc; 4261 } 4262 pool_mask >>= 1; 4263 pool++; 4264 } while (pool_mask); 4265 } 4266 4267 return 0; 4268 } 4269 4270 static int bnxt_restore_filters(struct bnxt *bp) 4271 { 4272 struct rte_eth_dev *dev = bp->eth_dev; 4273 int ret = 0; 4274 4275 if (dev->data->all_multicast) { 4276 ret = bnxt_allmulticast_enable_op(dev); 4277 if (ret) 4278 return ret; 4279 } 4280 if (dev->data->promiscuous) { 4281 ret = bnxt_promiscuous_enable_op(dev); 4282 if (ret) 4283 return ret; 4284 } 4285 4286 ret = bnxt_restore_mac_filters(bp); 4287 if (ret) 4288 return ret; 4289 4290 ret = bnxt_restore_vlan_filters(bp); 4291 /* TODO restore other filters as well */ 4292 return ret; 4293 } 4294 4295 static int bnxt_check_fw_ready(struct bnxt *bp) 4296 { 4297 int timeout = bp->fw_reset_max_msecs; 4298 int rc = 0; 4299 4300 do { 4301 rc = bnxt_hwrm_poll_ver_get(bp); 4302 if (rc == 0) 4303 break; 4304 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 4305 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 4306 } while (rc && timeout > 0); 4307 4308 if (rc) 4309 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 4310 4311 return rc; 4312 } 4313 4314 static void bnxt_dev_recover(void *arg) 4315 { 4316 struct bnxt *bp = arg; 4317 int rc = 0; 4318 4319 pthread_mutex_lock(&bp->err_recovery_lock); 4320 4321 if (!bp->fw_reset_min_msecs) { 4322 rc = bnxt_check_fw_reset_done(bp); 4323 if (rc) 4324 goto err; 4325 } 4326 4327 /* Clear Error flag so that device re-init should happen */ 4328 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 4329 4330 rc = bnxt_check_fw_ready(bp); 4331 if (rc) 4332 goto err; 4333 4334 rc = bnxt_init_resources(bp, true); 4335 if (rc) { 4336 PMD_DRV_LOG(ERR, 4337 "Failed to initialize resources after reset\n"); 4338 goto err; 4339 } 4340 /* clear reset flag as the device is initialized now */ 4341 bp->flags &= ~BNXT_FLAG_FW_RESET; 4342 4343 rc = bnxt_dev_start_op(bp->eth_dev); 4344 if (rc) { 4345 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 4346 goto err_start; 4347 } 4348 4349 rc = bnxt_restore_filters(bp); 4350 if (rc) 4351 goto err_start; 4352 4353 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 4354 pthread_mutex_unlock(&bp->err_recovery_lock); 4355 4356 return; 4357 err_start: 4358 bnxt_dev_stop(bp->eth_dev); 4359 err: 4360 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4361 bnxt_uninit_resources(bp, false); 4362 if (bp->eth_dev->data->dev_conf.intr_conf.rmv) 4363 rte_eth_dev_callback_process(bp->eth_dev, 4364 RTE_ETH_EVENT_INTR_RMV, 4365 NULL); 4366 pthread_mutex_unlock(&bp->err_recovery_lock); 4367 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 4368 } 4369 4370 void bnxt_dev_reset_and_resume(void *arg) 4371 { 4372 struct bnxt *bp = arg; 4373 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; 4374 uint16_t val = 0; 4375 int rc; 4376 4377 bnxt_dev_cleanup(bp); 4378 4379 bnxt_wait_for_device_shutdown(bp); 4380 4381 /* During some fatal firmware error conditions, the PCI config space 4382 * register 0x2e which normally contains the subsystem ID will become 4383 * 0xffff. This register will revert back to the normal value after 4384 * the chip has completed core reset. If we detect this condition, 4385 * we can poll this config register immediately for the value to revert. 4386 */ 4387 if (bp->flags & BNXT_FLAG_FATAL_ERROR) { 4388 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 4389 if (rc < 0) { 4390 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 4391 return; 4392 } 4393 if (val == 0xffff) { 4394 bp->fw_reset_min_msecs = 0; 4395 us = 1; 4396 } 4397 } 4398 4399 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); 4400 if (rc) 4401 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 4402 } 4403 4404 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 4405 { 4406 struct bnxt_error_recovery_info *info = bp->recovery_info; 4407 uint32_t reg = info->status_regs[index]; 4408 uint32_t type, offset, val = 0; 4409 int ret = 0; 4410 4411 type = BNXT_FW_STATUS_REG_TYPE(reg); 4412 offset = BNXT_FW_STATUS_REG_OFF(reg); 4413 4414 switch (type) { 4415 case BNXT_FW_STATUS_REG_TYPE_CFG: 4416 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 4417 if (ret < 0) 4418 PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x", 4419 offset); 4420 break; 4421 case BNXT_FW_STATUS_REG_TYPE_GRC: 4422 offset = info->mapped_status_regs[index]; 4423 /* FALLTHROUGH */ 4424 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4425 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4426 offset)); 4427 break; 4428 } 4429 4430 return val; 4431 } 4432 4433 static int bnxt_fw_reset_all(struct bnxt *bp) 4434 { 4435 struct bnxt_error_recovery_info *info = bp->recovery_info; 4436 uint32_t i; 4437 int rc = 0; 4438 4439 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4440 /* Reset through master function driver */ 4441 for (i = 0; i < info->reg_array_cnt; i++) 4442 bnxt_write_fw_reset_reg(bp, i); 4443 /* Wait for time specified by FW after triggering reset */ 4444 rte_delay_ms(info->master_func_wait_period_after_reset); 4445 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 4446 /* Reset with the help of Kong processor */ 4447 rc = bnxt_hwrm_fw_reset(bp); 4448 if (rc) 4449 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 4450 } 4451 4452 return rc; 4453 } 4454 4455 static void bnxt_fw_reset_cb(void *arg) 4456 { 4457 struct bnxt *bp = arg; 4458 struct bnxt_error_recovery_info *info = bp->recovery_info; 4459 int rc = 0; 4460 4461 /* Only Master function can do FW reset */ 4462 if (bnxt_is_master_func(bp) && 4463 bnxt_is_recovery_enabled(bp)) { 4464 rc = bnxt_fw_reset_all(bp); 4465 if (rc) { 4466 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 4467 return; 4468 } 4469 } 4470 4471 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 4472 * EXCEPTION_FATAL_ASYNC event to all the functions 4473 * (including MASTER FUNC). After receiving this Async, all the active 4474 * drivers should treat this case as FW initiated recovery 4475 */ 4476 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4477 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 4478 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 4479 4480 /* To recover from error */ 4481 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 4482 (void *)bp); 4483 } 4484 } 4485 4486 /* Driver should poll FW heartbeat, reset_counter with the frequency 4487 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 4488 * When the driver detects heartbeat stop or change in reset_counter, 4489 * it has to trigger a reset to recover from the error condition. 4490 * A “master PF” is the function who will have the privilege to 4491 * initiate the chimp reset. The master PF will be elected by the 4492 * firmware and will be notified through async message. 4493 */ 4494 static void bnxt_check_fw_health(void *arg) 4495 { 4496 struct bnxt *bp = arg; 4497 struct bnxt_error_recovery_info *info = bp->recovery_info; 4498 uint32_t val = 0, wait_msec; 4499 4500 if (!info || !bnxt_is_recovery_enabled(bp) || 4501 is_bnxt_in_error(bp)) 4502 return; 4503 4504 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4505 if (val == info->last_heart_beat) 4506 goto reset; 4507 4508 info->last_heart_beat = val; 4509 4510 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4511 if (val != info->last_reset_counter) 4512 goto reset; 4513 4514 info->last_reset_counter = val; 4515 4516 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4517 bnxt_check_fw_health, (void *)bp); 4518 4519 return; 4520 reset: 4521 /* Stop DMA to/from device */ 4522 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4523 bp->flags |= BNXT_FLAG_FW_RESET; 4524 4525 bnxt_stop_rxtx(bp); 4526 4527 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4528 4529 if (bnxt_is_master_func(bp)) 4530 wait_msec = info->master_func_wait_period; 4531 else 4532 wait_msec = info->normal_func_wait_period; 4533 4534 rte_eal_alarm_set(US_PER_MS * wait_msec, 4535 bnxt_fw_reset_cb, (void *)bp); 4536 } 4537 4538 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4539 { 4540 uint32_t polling_freq; 4541 4542 pthread_mutex_lock(&bp->health_check_lock); 4543 4544 if (!bnxt_is_recovery_enabled(bp)) 4545 goto done; 4546 4547 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4548 goto done; 4549 4550 polling_freq = bp->recovery_info->driver_polling_freq; 4551 4552 rte_eal_alarm_set(US_PER_MS * polling_freq, 4553 bnxt_check_fw_health, (void *)bp); 4554 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4555 4556 done: 4557 pthread_mutex_unlock(&bp->health_check_lock); 4558 } 4559 4560 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4561 { 4562 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4563 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4564 } 4565 4566 static bool bnxt_vf_pciid(uint16_t device_id) 4567 { 4568 switch (device_id) { 4569 case BROADCOM_DEV_ID_57304_VF: 4570 case BROADCOM_DEV_ID_57406_VF: 4571 case BROADCOM_DEV_ID_5731X_VF: 4572 case BROADCOM_DEV_ID_5741X_VF: 4573 case BROADCOM_DEV_ID_57414_VF: 4574 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4575 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4576 case BROADCOM_DEV_ID_58802_VF: 4577 case BROADCOM_DEV_ID_57500_VF1: 4578 case BROADCOM_DEV_ID_57500_VF2: 4579 case BROADCOM_DEV_ID_58818_VF: 4580 /* FALLTHROUGH */ 4581 return true; 4582 default: 4583 return false; 4584 } 4585 } 4586 4587 /* Phase 5 device */ 4588 static bool bnxt_p5_device(uint16_t device_id) 4589 { 4590 switch (device_id) { 4591 case BROADCOM_DEV_ID_57508: 4592 case BROADCOM_DEV_ID_57504: 4593 case BROADCOM_DEV_ID_57502: 4594 case BROADCOM_DEV_ID_57508_MF1: 4595 case BROADCOM_DEV_ID_57504_MF1: 4596 case BROADCOM_DEV_ID_57502_MF1: 4597 case BROADCOM_DEV_ID_57508_MF2: 4598 case BROADCOM_DEV_ID_57504_MF2: 4599 case BROADCOM_DEV_ID_57502_MF2: 4600 case BROADCOM_DEV_ID_57500_VF1: 4601 case BROADCOM_DEV_ID_57500_VF2: 4602 case BROADCOM_DEV_ID_58812: 4603 case BROADCOM_DEV_ID_58814: 4604 case BROADCOM_DEV_ID_58818: 4605 case BROADCOM_DEV_ID_58818_VF: 4606 /* FALLTHROUGH */ 4607 return true; 4608 default: 4609 return false; 4610 } 4611 } 4612 4613 bool bnxt_stratus_device(struct bnxt *bp) 4614 { 4615 uint16_t device_id = bp->pdev->id.device_id; 4616 4617 switch (device_id) { 4618 case BROADCOM_DEV_ID_STRATUS_NIC: 4619 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4620 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4621 /* FALLTHROUGH */ 4622 return true; 4623 default: 4624 return false; 4625 } 4626 } 4627 4628 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev) 4629 { 4630 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4631 struct bnxt *bp = eth_dev->data->dev_private; 4632 4633 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4634 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4635 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4636 if (!bp->bar0 || !bp->doorbell_base) { 4637 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4638 return -ENODEV; 4639 } 4640 4641 bp->eth_dev = eth_dev; 4642 bp->pdev = pci_dev; 4643 4644 return 0; 4645 } 4646 4647 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4648 struct bnxt_ctx_pg_info *ctx_pg, 4649 uint32_t mem_size, 4650 const char *suffix, 4651 uint16_t idx) 4652 { 4653 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4654 const struct rte_memzone *mz = NULL; 4655 char mz_name[RTE_MEMZONE_NAMESIZE]; 4656 rte_iova_t mz_phys_addr; 4657 uint64_t valid_bits = 0; 4658 uint32_t sz; 4659 int i; 4660 4661 if (!mem_size) 4662 return 0; 4663 4664 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4665 BNXT_PAGE_SIZE; 4666 rmem->page_size = BNXT_PAGE_SIZE; 4667 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4668 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4669 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4670 4671 valid_bits = PTU_PTE_VALID; 4672 4673 if (rmem->nr_pages > 1) { 4674 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4675 "bnxt_ctx_pg_tbl%s_%x_%d", 4676 suffix, idx, bp->eth_dev->data->port_id); 4677 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4678 mz = rte_memzone_lookup(mz_name); 4679 if (!mz) { 4680 mz = rte_memzone_reserve_aligned(mz_name, 4681 rmem->nr_pages * 8, 4682 bp->eth_dev->device->numa_node, 4683 RTE_MEMZONE_2MB | 4684 RTE_MEMZONE_SIZE_HINT_ONLY | 4685 RTE_MEMZONE_IOVA_CONTIG, 4686 BNXT_PAGE_SIZE); 4687 if (mz == NULL) 4688 return -ENOMEM; 4689 } 4690 4691 memset(mz->addr, 0, mz->len); 4692 mz_phys_addr = mz->iova; 4693 4694 rmem->pg_tbl = mz->addr; 4695 rmem->pg_tbl_map = mz_phys_addr; 4696 rmem->pg_tbl_mz = mz; 4697 } 4698 4699 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4700 suffix, idx, bp->eth_dev->data->port_id); 4701 mz = rte_memzone_lookup(mz_name); 4702 if (!mz) { 4703 mz = rte_memzone_reserve_aligned(mz_name, 4704 mem_size, 4705 bp->eth_dev->device->numa_node, 4706 RTE_MEMZONE_1GB | 4707 RTE_MEMZONE_SIZE_HINT_ONLY | 4708 RTE_MEMZONE_IOVA_CONTIG, 4709 BNXT_PAGE_SIZE); 4710 if (mz == NULL) 4711 return -ENOMEM; 4712 } 4713 4714 memset(mz->addr, 0, mz->len); 4715 mz_phys_addr = mz->iova; 4716 4717 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4718 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4719 rmem->dma_arr[i] = mz_phys_addr + sz; 4720 4721 if (rmem->nr_pages > 1) { 4722 if (i == rmem->nr_pages - 2 && 4723 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4724 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4725 else if (i == rmem->nr_pages - 1 && 4726 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4727 valid_bits |= PTU_PTE_LAST; 4728 4729 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4730 valid_bits); 4731 } 4732 } 4733 4734 rmem->mz = mz; 4735 if (rmem->vmem_size) 4736 rmem->vmem = (void **)mz->addr; 4737 rmem->dma_arr[0] = mz_phys_addr; 4738 return 0; 4739 } 4740 4741 static void bnxt_free_ctx_mem(struct bnxt *bp) 4742 { 4743 int i; 4744 4745 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4746 return; 4747 4748 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4749 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4750 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4751 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4752 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4753 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4754 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4755 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4756 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4757 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4758 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4759 4760 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) { 4761 if (bp->ctx->tqm_mem[i]) 4762 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4763 } 4764 4765 rte_free(bp->ctx); 4766 bp->ctx = NULL; 4767 } 4768 4769 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4770 4771 #define min_t(type, x, y) ({ \ 4772 type __min1 = (x); \ 4773 type __min2 = (y); \ 4774 __min1 < __min2 ? __min1 : __min2; }) 4775 4776 #define max_t(type, x, y) ({ \ 4777 type __max1 = (x); \ 4778 type __max2 = (y); \ 4779 __max1 > __max2 ? __max1 : __max2; }) 4780 4781 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4782 4783 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4784 { 4785 struct bnxt_ctx_pg_info *ctx_pg; 4786 struct bnxt_ctx_mem_info *ctx; 4787 uint32_t mem_size, ena, entries; 4788 uint32_t entries_sp, min; 4789 int i, rc; 4790 4791 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4792 if (rc) { 4793 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4794 return rc; 4795 } 4796 ctx = bp->ctx; 4797 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4798 return 0; 4799 4800 ctx_pg = &ctx->qp_mem; 4801 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4802 if (ctx->qp_entry_size) { 4803 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4804 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4805 if (rc) 4806 return rc; 4807 } 4808 4809 ctx_pg = &ctx->srq_mem; 4810 ctx_pg->entries = ctx->srq_max_l2_entries; 4811 if (ctx->srq_entry_size) { 4812 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4813 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4814 if (rc) 4815 return rc; 4816 } 4817 4818 ctx_pg = &ctx->cq_mem; 4819 ctx_pg->entries = ctx->cq_max_l2_entries; 4820 if (ctx->cq_entry_size) { 4821 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4822 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4823 if (rc) 4824 return rc; 4825 } 4826 4827 ctx_pg = &ctx->vnic_mem; 4828 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4829 ctx->vnic_max_ring_table_entries; 4830 if (ctx->vnic_entry_size) { 4831 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4832 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4833 if (rc) 4834 return rc; 4835 } 4836 4837 ctx_pg = &ctx->stat_mem; 4838 ctx_pg->entries = ctx->stat_max_entries; 4839 if (ctx->stat_entry_size) { 4840 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4841 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4842 if (rc) 4843 return rc; 4844 } 4845 4846 min = ctx->tqm_min_entries_per_ring; 4847 4848 entries_sp = ctx->qp_max_l2_entries + 4849 ctx->vnic_max_vnic_entries + 4850 2 * ctx->qp_min_qp1_entries + min; 4851 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple); 4852 4853 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries; 4854 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4855 entries = clamp_t(uint32_t, entries, min, 4856 ctx->tqm_max_entries_per_ring); 4857 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 4858 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7. 4859 * i > 8 is other ext rings. 4860 */ 4861 ctx_pg = ctx->tqm_mem[i]; 4862 ctx_pg->entries = i ? entries : entries_sp; 4863 if (ctx->tqm_entry_size) { 4864 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4865 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, 4866 "tqm_mem", i); 4867 if (rc) 4868 return rc; 4869 } 4870 if (i < BNXT_MAX_TQM_LEGACY_RINGS) 4871 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4872 else 4873 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8; 4874 } 4875 4876 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4877 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4878 if (rc) 4879 PMD_DRV_LOG(ERR, 4880 "Failed to configure context mem: rc = %d\n", rc); 4881 else 4882 ctx->flags |= BNXT_CTX_FLAG_INITED; 4883 4884 return rc; 4885 } 4886 4887 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4888 { 4889 struct rte_pci_device *pci_dev = bp->pdev; 4890 char mz_name[RTE_MEMZONE_NAMESIZE]; 4891 const struct rte_memzone *mz = NULL; 4892 uint32_t total_alloc_len; 4893 rte_iova_t mz_phys_addr; 4894 4895 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4896 return 0; 4897 4898 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4899 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4900 pci_dev->addr.bus, pci_dev->addr.devid, 4901 pci_dev->addr.function, "rx_port_stats"); 4902 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4903 mz = rte_memzone_lookup(mz_name); 4904 total_alloc_len = 4905 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4906 sizeof(struct rx_port_stats_ext) + 512); 4907 if (!mz) { 4908 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4909 SOCKET_ID_ANY, 4910 RTE_MEMZONE_2MB | 4911 RTE_MEMZONE_SIZE_HINT_ONLY | 4912 RTE_MEMZONE_IOVA_CONTIG); 4913 if (mz == NULL) 4914 return -ENOMEM; 4915 } 4916 memset(mz->addr, 0, mz->len); 4917 mz_phys_addr = mz->iova; 4918 4919 bp->rx_mem_zone = (const void *)mz; 4920 bp->hw_rx_port_stats = mz->addr; 4921 bp->hw_rx_port_stats_map = mz_phys_addr; 4922 4923 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4924 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4925 pci_dev->addr.bus, pci_dev->addr.devid, 4926 pci_dev->addr.function, "tx_port_stats"); 4927 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4928 mz = rte_memzone_lookup(mz_name); 4929 total_alloc_len = 4930 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4931 sizeof(struct tx_port_stats_ext) + 512); 4932 if (!mz) { 4933 mz = rte_memzone_reserve(mz_name, 4934 total_alloc_len, 4935 SOCKET_ID_ANY, 4936 RTE_MEMZONE_2MB | 4937 RTE_MEMZONE_SIZE_HINT_ONLY | 4938 RTE_MEMZONE_IOVA_CONTIG); 4939 if (mz == NULL) 4940 return -ENOMEM; 4941 } 4942 memset(mz->addr, 0, mz->len); 4943 mz_phys_addr = mz->iova; 4944 4945 bp->tx_mem_zone = (const void *)mz; 4946 bp->hw_tx_port_stats = mz->addr; 4947 bp->hw_tx_port_stats_map = mz_phys_addr; 4948 bp->flags |= BNXT_FLAG_PORT_STATS; 4949 4950 /* Display extended statistics if FW supports it */ 4951 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4952 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4953 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4954 return 0; 4955 4956 bp->hw_rx_port_stats_ext = (void *) 4957 ((uint8_t *)bp->hw_rx_port_stats + 4958 sizeof(struct rx_port_stats)); 4959 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4960 sizeof(struct rx_port_stats); 4961 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4962 4963 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4964 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4965 bp->hw_tx_port_stats_ext = (void *) 4966 ((uint8_t *)bp->hw_tx_port_stats + 4967 sizeof(struct tx_port_stats)); 4968 bp->hw_tx_port_stats_ext_map = 4969 bp->hw_tx_port_stats_map + 4970 sizeof(struct tx_port_stats); 4971 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4972 } 4973 4974 return 0; 4975 } 4976 4977 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4978 { 4979 struct bnxt *bp = eth_dev->data->dev_private; 4980 int rc = 0; 4981 4982 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4983 RTE_ETHER_ADDR_LEN * 4984 bp->max_l2_ctx, 4985 0); 4986 if (eth_dev->data->mac_addrs == NULL) { 4987 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4988 return -ENOMEM; 4989 } 4990 4991 if (!BNXT_HAS_DFLT_MAC_SET(bp)) { 4992 if (BNXT_PF(bp)) 4993 return -EINVAL; 4994 4995 /* Generate a random MAC address, if none was assigned by PF */ 4996 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 4997 bnxt_eth_hw_addr_random(bp->mac_addr); 4998 PMD_DRV_LOG(INFO, 4999 "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n", 5000 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 5001 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 5002 5003 rc = bnxt_hwrm_set_mac(bp); 5004 if (rc) 5005 return rc; 5006 } 5007 5008 /* Copy the permanent MAC from the FUNC_QCAPS response */ 5009 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 5010 5011 return rc; 5012 } 5013 5014 static int bnxt_restore_dflt_mac(struct bnxt *bp) 5015 { 5016 int rc = 0; 5017 5018 /* MAC is already configured in FW */ 5019 if (BNXT_HAS_DFLT_MAC_SET(bp)) 5020 return 0; 5021 5022 /* Restore the old MAC configured */ 5023 rc = bnxt_hwrm_set_mac(bp); 5024 if (rc) 5025 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 5026 5027 return rc; 5028 } 5029 5030 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 5031 { 5032 if (!BNXT_PF(bp)) 5033 return; 5034 5035 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd)); 5036 5037 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN)) 5038 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG); 5039 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG); 5040 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG); 5041 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC); 5042 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); 5043 } 5044 5045 struct bnxt * 5046 bnxt_get_bp(uint16_t port) 5047 { 5048 struct bnxt *bp; 5049 struct rte_eth_dev *dev; 5050 5051 if (!rte_eth_dev_is_valid_port(port)) { 5052 PMD_DRV_LOG(ERR, "Invalid port %d\n", port); 5053 return NULL; 5054 } 5055 5056 dev = &rte_eth_devices[port]; 5057 if (!is_bnxt_supported(dev)) { 5058 PMD_DRV_LOG(ERR, "Device %d not supported\n", port); 5059 return NULL; 5060 } 5061 5062 bp = (struct bnxt *)dev->data->dev_private; 5063 if (!BNXT_TRUFLOW_EN(bp)) { 5064 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); 5065 return NULL; 5066 } 5067 5068 return bp; 5069 } 5070 5071 uint16_t 5072 bnxt_get_svif(uint16_t port_id, bool func_svif, 5073 enum bnxt_ulp_intf_type type) 5074 { 5075 struct rte_eth_dev *eth_dev; 5076 struct bnxt *bp; 5077 5078 eth_dev = &rte_eth_devices[port_id]; 5079 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5080 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5081 if (!vfr) 5082 return 0; 5083 5084 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5085 return vfr->svif; 5086 5087 eth_dev = vfr->parent_dev; 5088 } 5089 5090 bp = eth_dev->data->dev_private; 5091 5092 return func_svif ? bp->func_svif : bp->port_svif; 5093 } 5094 5095 void 5096 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, 5097 uint8_t *mac, uint8_t *parent_mac) 5098 { 5099 struct rte_eth_dev *eth_dev; 5100 struct bnxt *bp; 5101 5102 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && 5103 type != BNXT_ULP_INTF_TYPE_PF) 5104 return; 5105 5106 eth_dev = &rte_eth_devices[port]; 5107 bp = eth_dev->data->dev_private; 5108 memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); 5109 5110 if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) 5111 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); 5112 } 5113 5114 uint16_t 5115 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 5116 { 5117 struct rte_eth_dev *eth_dev; 5118 struct bnxt *bp; 5119 5120 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) 5121 return 0; 5122 5123 eth_dev = &rte_eth_devices[port]; 5124 bp = eth_dev->data->dev_private; 5125 5126 return bp->parent->vnic; 5127 } 5128 uint16_t 5129 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 5130 { 5131 struct rte_eth_dev *eth_dev; 5132 struct bnxt_vnic_info *vnic; 5133 struct bnxt *bp; 5134 5135 eth_dev = &rte_eth_devices[port]; 5136 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5137 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5138 if (!vfr) 5139 return 0; 5140 5141 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5142 return vfr->dflt_vnic_id; 5143 5144 eth_dev = vfr->parent_dev; 5145 } 5146 5147 bp = eth_dev->data->dev_private; 5148 5149 vnic = BNXT_GET_DEFAULT_VNIC(bp); 5150 5151 return vnic->fw_vnic_id; 5152 } 5153 5154 uint16_t 5155 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) 5156 { 5157 struct rte_eth_dev *eth_dev; 5158 struct bnxt *bp; 5159 5160 eth_dev = &rte_eth_devices[port]; 5161 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5162 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5163 if (!vfr) 5164 return 0; 5165 5166 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5167 return vfr->fw_fid; 5168 5169 eth_dev = vfr->parent_dev; 5170 } 5171 5172 bp = eth_dev->data->dev_private; 5173 5174 return bp->fw_fid; 5175 } 5176 5177 enum bnxt_ulp_intf_type 5178 bnxt_get_interface_type(uint16_t port) 5179 { 5180 struct rte_eth_dev *eth_dev; 5181 struct bnxt *bp; 5182 5183 eth_dev = &rte_eth_devices[port]; 5184 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) 5185 return BNXT_ULP_INTF_TYPE_VF_REP; 5186 5187 bp = eth_dev->data->dev_private; 5188 if (BNXT_PF(bp)) 5189 return BNXT_ULP_INTF_TYPE_PF; 5190 else if (BNXT_VF_IS_TRUSTED(bp)) 5191 return BNXT_ULP_INTF_TYPE_TRUSTED_VF; 5192 else if (BNXT_VF(bp)) 5193 return BNXT_ULP_INTF_TYPE_VF; 5194 5195 return BNXT_ULP_INTF_TYPE_INVALID; 5196 } 5197 5198 uint16_t 5199 bnxt_get_phy_port_id(uint16_t port_id) 5200 { 5201 struct bnxt_representor *vfr; 5202 struct rte_eth_dev *eth_dev; 5203 struct bnxt *bp; 5204 5205 eth_dev = &rte_eth_devices[port_id]; 5206 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5207 vfr = eth_dev->data->dev_private; 5208 if (!vfr) 5209 return 0; 5210 5211 eth_dev = vfr->parent_dev; 5212 } 5213 5214 bp = eth_dev->data->dev_private; 5215 5216 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; 5217 } 5218 5219 uint16_t 5220 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) 5221 { 5222 struct rte_eth_dev *eth_dev; 5223 struct bnxt *bp; 5224 5225 eth_dev = &rte_eth_devices[port_id]; 5226 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5227 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5228 if (!vfr) 5229 return 0; 5230 5231 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5232 return vfr->fw_fid - 1; 5233 5234 eth_dev = vfr->parent_dev; 5235 } 5236 5237 bp = eth_dev->data->dev_private; 5238 5239 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; 5240 } 5241 5242 uint16_t 5243 bnxt_get_vport(uint16_t port_id) 5244 { 5245 return (1 << bnxt_get_phy_port_id(port_id)); 5246 } 5247 5248 static void bnxt_alloc_error_recovery_info(struct bnxt *bp) 5249 { 5250 struct bnxt_error_recovery_info *info = bp->recovery_info; 5251 5252 if (info) { 5253 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)) 5254 memset(info, 0, sizeof(*info)); 5255 return; 5256 } 5257 5258 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 5259 return; 5260 5261 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5262 sizeof(*info), 0); 5263 if (!info) 5264 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5265 5266 bp->recovery_info = info; 5267 } 5268 5269 static void bnxt_check_fw_status(struct bnxt *bp) 5270 { 5271 uint32_t fw_status; 5272 5273 if (!(bp->recovery_info && 5274 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))) 5275 return; 5276 5277 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG); 5278 if (fw_status != BNXT_FW_STATUS_HEALTHY) 5279 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n", 5280 fw_status); 5281 } 5282 5283 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) 5284 { 5285 struct bnxt_error_recovery_info *info = bp->recovery_info; 5286 uint32_t status_loc; 5287 uint32_t sig_ver; 5288 5289 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 + 5290 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5291 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5292 BNXT_GRCP_WINDOW_2_BASE + 5293 offsetof(struct hcomm_status, 5294 sig_ver))); 5295 /* If the signature is absent, then FW does not support this feature */ 5296 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) != 5297 HCOMM_STATUS_SIGNATURE_VAL) 5298 return 0; 5299 5300 if (!info) { 5301 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5302 sizeof(*info), 0); 5303 if (!info) 5304 return -ENOMEM; 5305 bp->recovery_info = info; 5306 } else { 5307 memset(info, 0, sizeof(*info)); 5308 } 5309 5310 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5311 BNXT_GRCP_WINDOW_2_BASE + 5312 offsetof(struct hcomm_status, 5313 fw_status_loc))); 5314 5315 /* Only pre-map the FW health status GRC register */ 5316 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC) 5317 return 0; 5318 5319 info->status_regs[BNXT_FW_STATUS_REG] = status_loc; 5320 info->mapped_status_regs[BNXT_FW_STATUS_REG] = 5321 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK); 5322 5323 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 + 5324 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5325 5326 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS; 5327 5328 return 0; 5329 } 5330 5331 /* This function gets the FW version along with the 5332 * capabilities(MAX and current) of the function, vnic, 5333 * error recovery, phy and other chip related info 5334 */ 5335 static int bnxt_get_config(struct bnxt *bp) 5336 { 5337 uint16_t mtu; 5338 int rc = 0; 5339 5340 bp->fw_cap = 0; 5341 5342 rc = bnxt_map_hcomm_fw_status_reg(bp); 5343 if (rc) 5344 return rc; 5345 5346 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT); 5347 if (rc) { 5348 bnxt_check_fw_status(bp); 5349 return rc; 5350 } 5351 5352 rc = bnxt_hwrm_func_reset(bp); 5353 if (rc) 5354 return -EIO; 5355 5356 rc = bnxt_hwrm_vnic_qcaps(bp); 5357 if (rc) 5358 return rc; 5359 5360 rc = bnxt_hwrm_queue_qportcfg(bp); 5361 if (rc) 5362 return rc; 5363 5364 /* Get the MAX capabilities for this function. 5365 * This function also allocates context memory for TQM rings and 5366 * informs the firmware about this allocated backing store memory. 5367 */ 5368 rc = bnxt_hwrm_func_qcaps(bp); 5369 if (rc) 5370 return rc; 5371 5372 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 5373 if (rc) 5374 return rc; 5375 5376 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 5377 if (rc) 5378 return rc; 5379 5380 bnxt_hwrm_port_mac_qcfg(bp); 5381 5382 bnxt_hwrm_parent_pf_qcfg(bp); 5383 5384 bnxt_hwrm_port_phy_qcaps(bp); 5385 5386 bnxt_alloc_error_recovery_info(bp); 5387 /* Get the adapter error recovery support info */ 5388 rc = bnxt_hwrm_error_recovery_qcfg(bp); 5389 if (rc) 5390 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5391 5392 bnxt_hwrm_port_led_qcaps(bp); 5393 5394 return 0; 5395 } 5396 5397 static int 5398 bnxt_init_locks(struct bnxt *bp) 5399 { 5400 int err; 5401 5402 err = pthread_mutex_init(&bp->flow_lock, NULL); 5403 if (err) { 5404 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 5405 return err; 5406 } 5407 5408 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 5409 if (err) { 5410 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 5411 return err; 5412 } 5413 5414 err = pthread_mutex_init(&bp->health_check_lock, NULL); 5415 if (err) { 5416 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n"); 5417 return err; 5418 } 5419 5420 err = pthread_mutex_init(&bp->err_recovery_lock, NULL); 5421 if (err) 5422 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n"); 5423 5424 return err; 5425 } 5426 5427 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 5428 { 5429 int rc = 0; 5430 5431 rc = bnxt_get_config(bp); 5432 if (rc) 5433 return rc; 5434 5435 if (!reconfig_dev) { 5436 rc = bnxt_setup_mac_addr(bp->eth_dev); 5437 if (rc) 5438 return rc; 5439 } else { 5440 rc = bnxt_restore_dflt_mac(bp); 5441 if (rc) 5442 return rc; 5443 } 5444 5445 bnxt_config_vf_req_fwd(bp); 5446 5447 rc = bnxt_hwrm_func_driver_register(bp); 5448 if (rc) { 5449 PMD_DRV_LOG(ERR, "Failed to register driver"); 5450 return -EBUSY; 5451 } 5452 5453 if (BNXT_PF(bp)) { 5454 if (bp->pdev->max_vfs) { 5455 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 5456 if (rc) { 5457 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 5458 return rc; 5459 } 5460 } else { 5461 rc = bnxt_hwrm_allocate_pf_only(bp); 5462 if (rc) { 5463 PMD_DRV_LOG(ERR, 5464 "Failed to allocate PF resources"); 5465 return rc; 5466 } 5467 } 5468 } 5469 5470 rc = bnxt_alloc_mem(bp, reconfig_dev); 5471 if (rc) 5472 return rc; 5473 5474 rc = bnxt_setup_int(bp); 5475 if (rc) 5476 return rc; 5477 5478 rc = bnxt_request_int(bp); 5479 if (rc) 5480 return rc; 5481 5482 rc = bnxt_init_ctx_mem(bp); 5483 if (rc) { 5484 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n"); 5485 return rc; 5486 } 5487 5488 return 0; 5489 } 5490 5491 static int 5492 bnxt_parse_devarg_accum_stats(__rte_unused const char *key, 5493 const char *value, void *opaque_arg) 5494 { 5495 struct bnxt *bp = opaque_arg; 5496 unsigned long accum_stats; 5497 char *end = NULL; 5498 5499 if (!value || !opaque_arg) { 5500 PMD_DRV_LOG(ERR, 5501 "Invalid parameter passed to accum-stats devargs.\n"); 5502 return -EINVAL; 5503 } 5504 5505 accum_stats = strtoul(value, &end, 10); 5506 if (end == NULL || *end != '\0' || 5507 (accum_stats == ULONG_MAX && errno == ERANGE)) { 5508 PMD_DRV_LOG(ERR, 5509 "Invalid parameter passed to accum-stats devargs.\n"); 5510 return -EINVAL; 5511 } 5512 5513 if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) { 5514 PMD_DRV_LOG(ERR, 5515 "Invalid value passed to accum-stats devargs.\n"); 5516 return -EINVAL; 5517 } 5518 5519 if (accum_stats) { 5520 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN; 5521 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n"); 5522 } else { 5523 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN; 5524 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n"); 5525 } 5526 5527 return 0; 5528 } 5529 5530 static int 5531 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, 5532 const char *value, void *opaque_arg) 5533 { 5534 struct bnxt *bp = opaque_arg; 5535 unsigned long flow_xstat; 5536 char *end = NULL; 5537 5538 if (!value || !opaque_arg) { 5539 PMD_DRV_LOG(ERR, 5540 "Invalid parameter passed to flow_xstat devarg.\n"); 5541 return -EINVAL; 5542 } 5543 5544 flow_xstat = strtoul(value, &end, 10); 5545 if (end == NULL || *end != '\0' || 5546 (flow_xstat == ULONG_MAX && errno == ERANGE)) { 5547 PMD_DRV_LOG(ERR, 5548 "Invalid parameter passed to flow_xstat devarg.\n"); 5549 return -EINVAL; 5550 } 5551 5552 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) { 5553 PMD_DRV_LOG(ERR, 5554 "Invalid value passed to flow_xstat devarg.\n"); 5555 return -EINVAL; 5556 } 5557 5558 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN; 5559 if (BNXT_FLOW_XSTATS_EN(bp)) 5560 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n"); 5561 5562 return 0; 5563 } 5564 5565 static int 5566 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, 5567 const char *value, void *opaque_arg) 5568 { 5569 struct bnxt *bp = opaque_arg; 5570 unsigned long max_num_kflows; 5571 char *end = NULL; 5572 5573 if (!value || !opaque_arg) { 5574 PMD_DRV_LOG(ERR, 5575 "Invalid parameter passed to max_num_kflows devarg.\n"); 5576 return -EINVAL; 5577 } 5578 5579 max_num_kflows = strtoul(value, &end, 10); 5580 if (end == NULL || *end != '\0' || 5581 (max_num_kflows == ULONG_MAX && errno == ERANGE)) { 5582 PMD_DRV_LOG(ERR, 5583 "Invalid parameter passed to max_num_kflows devarg.\n"); 5584 return -EINVAL; 5585 } 5586 5587 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) { 5588 PMD_DRV_LOG(ERR, 5589 "Invalid value passed to max_num_kflows devarg.\n"); 5590 return -EINVAL; 5591 } 5592 5593 bp->max_num_kflows = max_num_kflows; 5594 if (bp->max_num_kflows) 5595 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n", 5596 max_num_kflows); 5597 5598 return 0; 5599 } 5600 5601 static int 5602 bnxt_parse_devarg_app_id(__rte_unused const char *key, 5603 const char *value, void *opaque_arg) 5604 { 5605 struct bnxt *bp = opaque_arg; 5606 unsigned long app_id; 5607 char *end = NULL; 5608 5609 if (!value || !opaque_arg) { 5610 PMD_DRV_LOG(ERR, 5611 "Invalid parameter passed to app-id " 5612 "devargs.\n"); 5613 return -EINVAL; 5614 } 5615 5616 app_id = strtoul(value, &end, 10); 5617 if (end == NULL || *end != '\0' || 5618 (app_id == ULONG_MAX && errno == ERANGE)) { 5619 PMD_DRV_LOG(ERR, 5620 "Invalid parameter passed to app_id " 5621 "devargs.\n"); 5622 return -EINVAL; 5623 } 5624 5625 if (BNXT_DEVARG_APP_ID_INVALID(app_id)) { 5626 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n", 5627 (uint16_t)app_id); 5628 return -EINVAL; 5629 } 5630 5631 bp->app_id = app_id; 5632 PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id); 5633 5634 return 0; 5635 } 5636 5637 static int 5638 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key, 5639 const char *value, void *opaque_arg) 5640 { 5641 struct bnxt_representor *vfr_bp = opaque_arg; 5642 unsigned long rep_is_pf; 5643 char *end = NULL; 5644 5645 if (!value || !opaque_arg) { 5646 PMD_DRV_LOG(ERR, 5647 "Invalid parameter passed to rep_is_pf devargs.\n"); 5648 return -EINVAL; 5649 } 5650 5651 rep_is_pf = strtoul(value, &end, 10); 5652 if (end == NULL || *end != '\0' || 5653 (rep_is_pf == ULONG_MAX && errno == ERANGE)) { 5654 PMD_DRV_LOG(ERR, 5655 "Invalid parameter passed to rep_is_pf devargs.\n"); 5656 return -EINVAL; 5657 } 5658 5659 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) { 5660 PMD_DRV_LOG(ERR, 5661 "Invalid value passed to rep_is_pf devargs.\n"); 5662 return -EINVAL; 5663 } 5664 5665 vfr_bp->flags |= rep_is_pf; 5666 if (BNXT_REP_PF(vfr_bp)) 5667 PMD_DRV_LOG(INFO, "PF representor\n"); 5668 else 5669 PMD_DRV_LOG(INFO, "VF representor\n"); 5670 5671 return 0; 5672 } 5673 5674 static int 5675 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key, 5676 const char *value, void *opaque_arg) 5677 { 5678 struct bnxt_representor *vfr_bp = opaque_arg; 5679 unsigned long rep_based_pf; 5680 char *end = NULL; 5681 5682 if (!value || !opaque_arg) { 5683 PMD_DRV_LOG(ERR, 5684 "Invalid parameter passed to rep_based_pf " 5685 "devargs.\n"); 5686 return -EINVAL; 5687 } 5688 5689 rep_based_pf = strtoul(value, &end, 10); 5690 if (end == NULL || *end != '\0' || 5691 (rep_based_pf == ULONG_MAX && errno == ERANGE)) { 5692 PMD_DRV_LOG(ERR, 5693 "Invalid parameter passed to rep_based_pf " 5694 "devargs.\n"); 5695 return -EINVAL; 5696 } 5697 5698 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) { 5699 PMD_DRV_LOG(ERR, 5700 "Invalid value passed to rep_based_pf devargs.\n"); 5701 return -EINVAL; 5702 } 5703 5704 vfr_bp->rep_based_pf = rep_based_pf; 5705 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID; 5706 5707 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf); 5708 5709 return 0; 5710 } 5711 5712 static int 5713 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key, 5714 const char *value, void *opaque_arg) 5715 { 5716 struct bnxt_representor *vfr_bp = opaque_arg; 5717 unsigned long rep_q_r2f; 5718 char *end = NULL; 5719 5720 if (!value || !opaque_arg) { 5721 PMD_DRV_LOG(ERR, 5722 "Invalid parameter passed to rep_q_r2f " 5723 "devargs.\n"); 5724 return -EINVAL; 5725 } 5726 5727 rep_q_r2f = strtoul(value, &end, 10); 5728 if (end == NULL || *end != '\0' || 5729 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) { 5730 PMD_DRV_LOG(ERR, 5731 "Invalid parameter passed to rep_q_r2f " 5732 "devargs.\n"); 5733 return -EINVAL; 5734 } 5735 5736 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) { 5737 PMD_DRV_LOG(ERR, 5738 "Invalid value passed to rep_q_r2f devargs.\n"); 5739 return -EINVAL; 5740 } 5741 5742 vfr_bp->rep_q_r2f = rep_q_r2f; 5743 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID; 5744 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f); 5745 5746 return 0; 5747 } 5748 5749 static int 5750 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key, 5751 const char *value, void *opaque_arg) 5752 { 5753 struct bnxt_representor *vfr_bp = opaque_arg; 5754 unsigned long rep_q_f2r; 5755 char *end = NULL; 5756 5757 if (!value || !opaque_arg) { 5758 PMD_DRV_LOG(ERR, 5759 "Invalid parameter passed to rep_q_f2r " 5760 "devargs.\n"); 5761 return -EINVAL; 5762 } 5763 5764 rep_q_f2r = strtoul(value, &end, 10); 5765 if (end == NULL || *end != '\0' || 5766 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) { 5767 PMD_DRV_LOG(ERR, 5768 "Invalid parameter passed to rep_q_f2r " 5769 "devargs.\n"); 5770 return -EINVAL; 5771 } 5772 5773 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) { 5774 PMD_DRV_LOG(ERR, 5775 "Invalid value passed to rep_q_f2r devargs.\n"); 5776 return -EINVAL; 5777 } 5778 5779 vfr_bp->rep_q_f2r = rep_q_f2r; 5780 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID; 5781 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r); 5782 5783 return 0; 5784 } 5785 5786 static int 5787 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key, 5788 const char *value, void *opaque_arg) 5789 { 5790 struct bnxt_representor *vfr_bp = opaque_arg; 5791 unsigned long rep_fc_r2f; 5792 char *end = NULL; 5793 5794 if (!value || !opaque_arg) { 5795 PMD_DRV_LOG(ERR, 5796 "Invalid parameter passed to rep_fc_r2f " 5797 "devargs.\n"); 5798 return -EINVAL; 5799 } 5800 5801 rep_fc_r2f = strtoul(value, &end, 10); 5802 if (end == NULL || *end != '\0' || 5803 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) { 5804 PMD_DRV_LOG(ERR, 5805 "Invalid parameter passed to rep_fc_r2f " 5806 "devargs.\n"); 5807 return -EINVAL; 5808 } 5809 5810 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) { 5811 PMD_DRV_LOG(ERR, 5812 "Invalid value passed to rep_fc_r2f devargs.\n"); 5813 return -EINVAL; 5814 } 5815 5816 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID; 5817 vfr_bp->rep_fc_r2f = rep_fc_r2f; 5818 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f); 5819 5820 return 0; 5821 } 5822 5823 static int 5824 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key, 5825 const char *value, void *opaque_arg) 5826 { 5827 struct bnxt_representor *vfr_bp = opaque_arg; 5828 unsigned long rep_fc_f2r; 5829 char *end = NULL; 5830 5831 if (!value || !opaque_arg) { 5832 PMD_DRV_LOG(ERR, 5833 "Invalid parameter passed to rep_fc_f2r " 5834 "devargs.\n"); 5835 return -EINVAL; 5836 } 5837 5838 rep_fc_f2r = strtoul(value, &end, 10); 5839 if (end == NULL || *end != '\0' || 5840 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) { 5841 PMD_DRV_LOG(ERR, 5842 "Invalid parameter passed to rep_fc_f2r " 5843 "devargs.\n"); 5844 return -EINVAL; 5845 } 5846 5847 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) { 5848 PMD_DRV_LOG(ERR, 5849 "Invalid value passed to rep_fc_f2r devargs.\n"); 5850 return -EINVAL; 5851 } 5852 5853 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID; 5854 vfr_bp->rep_fc_f2r = rep_fc_f2r; 5855 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r); 5856 5857 return 0; 5858 } 5859 5860 static int 5861 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) 5862 { 5863 struct rte_kvargs *kvlist; 5864 int ret; 5865 5866 if (devargs == NULL) 5867 return 0; 5868 5869 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); 5870 if (kvlist == NULL) 5871 return -EINVAL; 5872 5873 /* 5874 * Handler for "flow_xstat" devarg. 5875 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1" 5876 */ 5877 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, 5878 bnxt_parse_devarg_flow_xstat, bp); 5879 if (ret) 5880 goto err; 5881 5882 /* 5883 * Handler for "accum-stats" devarg. 5884 * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1" 5885 */ 5886 rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS, 5887 bnxt_parse_devarg_accum_stats, bp); 5888 /* 5889 * Handler for "max_num_kflows" devarg. 5890 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" 5891 */ 5892 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, 5893 bnxt_parse_devarg_max_num_kflows, bp); 5894 if (ret) 5895 goto err; 5896 5897 err: 5898 /* 5899 * Handler for "app-id" devarg. 5900 * Invoked as for ex: "-a 000:00:0d.0,app-id=1" 5901 */ 5902 rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID, 5903 bnxt_parse_devarg_app_id, bp); 5904 5905 rte_kvargs_free(kvlist); 5906 return ret; 5907 } 5908 5909 static int bnxt_alloc_switch_domain(struct bnxt *bp) 5910 { 5911 int rc = 0; 5912 5913 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 5914 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id); 5915 if (rc) 5916 PMD_DRV_LOG(ERR, 5917 "Failed to alloc switch domain: %d\n", rc); 5918 else 5919 PMD_DRV_LOG(INFO, 5920 "Switch domain allocated %d\n", 5921 bp->switch_domain_id); 5922 } 5923 5924 return rc; 5925 } 5926 5927 /* Allocate and initialize various fields in bnxt struct that 5928 * need to be allocated/destroyed only once in the lifetime of the driver 5929 */ 5930 static int bnxt_drv_init(struct rte_eth_dev *eth_dev) 5931 { 5932 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5933 struct bnxt *bp = eth_dev->data->dev_private; 5934 int rc = 0; 5935 5936 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 5937 5938 if (bnxt_vf_pciid(pci_dev->id.device_id)) 5939 bp->flags |= BNXT_FLAG_VF; 5940 5941 if (bnxt_p5_device(pci_dev->id.device_id)) 5942 bp->flags |= BNXT_FLAG_CHIP_P5; 5943 5944 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 5945 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 5946 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 5947 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 5948 bp->flags |= BNXT_FLAG_STINGRAY; 5949 5950 if (BNXT_TRUFLOW_EN(bp)) { 5951 /* extra mbuf field is required to store CFA code from mark */ 5952 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = { 5953 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME, 5954 .size = sizeof(bnxt_cfa_code_dynfield_t), 5955 .align = __alignof__(bnxt_cfa_code_dynfield_t), 5956 }; 5957 bnxt_cfa_code_dynfield_offset = 5958 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc); 5959 if (bnxt_cfa_code_dynfield_offset < 0) { 5960 PMD_DRV_LOG(ERR, 5961 "Failed to register mbuf field for TruFlow mark\n"); 5962 return -rte_errno; 5963 } 5964 } 5965 5966 rc = bnxt_map_pci_bars(eth_dev); 5967 if (rc) { 5968 PMD_DRV_LOG(ERR, 5969 "Failed to initialize board rc: %x\n", rc); 5970 return rc; 5971 } 5972 5973 rc = bnxt_alloc_pf_info(bp); 5974 if (rc) 5975 return rc; 5976 5977 rc = bnxt_alloc_link_info(bp); 5978 if (rc) 5979 return rc; 5980 5981 rc = bnxt_alloc_parent_info(bp); 5982 if (rc) 5983 return rc; 5984 5985 rc = bnxt_alloc_hwrm_resources(bp); 5986 if (rc) { 5987 PMD_DRV_LOG(ERR, 5988 "Failed to allocate response buffer rc: %x\n", rc); 5989 return rc; 5990 } 5991 rc = bnxt_alloc_leds_info(bp); 5992 if (rc) 5993 return rc; 5994 5995 rc = bnxt_alloc_cos_queues(bp); 5996 if (rc) 5997 return rc; 5998 5999 rc = bnxt_init_locks(bp); 6000 if (rc) 6001 return rc; 6002 6003 rc = bnxt_alloc_switch_domain(bp); 6004 if (rc) 6005 return rc; 6006 6007 return rc; 6008 } 6009 6010 static int 6011 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) 6012 { 6013 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 6014 static int version_printed; 6015 struct bnxt *bp; 6016 int rc; 6017 6018 if (version_printed++ == 0) 6019 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 6020 6021 eth_dev->dev_ops = &bnxt_dev_ops; 6022 eth_dev->rx_queue_count = bnxt_rx_queue_count_op; 6023 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; 6024 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; 6025 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 6026 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 6027 6028 /* 6029 * For secondary processes, we don't initialise any further 6030 * as primary has already done this work. 6031 */ 6032 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 6033 return 0; 6034 6035 rte_eth_copy_pci_info(eth_dev, pci_dev); 6036 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 6037 6038 bp = eth_dev->data->dev_private; 6039 6040 /* Parse dev arguments passed on when starting the DPDK application. */ 6041 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs); 6042 if (rc) 6043 goto error_free; 6044 6045 rc = bnxt_drv_init(eth_dev); 6046 if (rc) 6047 goto error_free; 6048 6049 rc = bnxt_init_resources(bp, false); 6050 if (rc) 6051 goto error_free; 6052 6053 rc = bnxt_alloc_stats_mem(bp); 6054 if (rc) 6055 goto error_free; 6056 6057 PMD_DRV_LOG(INFO, 6058 "Found %s device at mem %" PRIX64 ", node addr %pM\n", 6059 DRV_MODULE_NAME, 6060 pci_dev->mem_resource[0].phys_addr, 6061 pci_dev->mem_resource[0].addr); 6062 6063 return 0; 6064 6065 error_free: 6066 bnxt_dev_uninit(eth_dev); 6067 return rc; 6068 } 6069 6070 6071 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx) 6072 { 6073 if (!ctx) 6074 return; 6075 6076 if (ctx->va) 6077 rte_free(ctx->va); 6078 6079 ctx->va = NULL; 6080 ctx->dma = RTE_BAD_IOVA; 6081 ctx->ctx_id = BNXT_CTX_VAL_INVAL; 6082 } 6083 6084 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp) 6085 { 6086 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 6087 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 6088 bp->flow_stat->rx_fc_out_tbl.ctx_id, 6089 bp->flow_stat->max_fc, 6090 false); 6091 6092 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 6093 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 6094 bp->flow_stat->tx_fc_out_tbl.ctx_id, 6095 bp->flow_stat->max_fc, 6096 false); 6097 6098 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6099 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id); 6100 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6101 6102 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6103 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id); 6104 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6105 6106 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6107 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id); 6108 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6109 6110 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6111 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id); 6112 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6113 } 6114 6115 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp) 6116 { 6117 bnxt_unregister_fc_ctx_mem(bp); 6118 6119 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl); 6120 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl); 6121 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl); 6122 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl); 6123 } 6124 6125 static void bnxt_uninit_ctx_mem(struct bnxt *bp) 6126 { 6127 if (BNXT_FLOW_XSTATS_EN(bp)) 6128 bnxt_uninit_fc_ctx_mem(bp); 6129 } 6130 6131 static void 6132 bnxt_free_error_recovery_info(struct bnxt *bp) 6133 { 6134 rte_free(bp->recovery_info); 6135 bp->recovery_info = NULL; 6136 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 6137 } 6138 6139 static int 6140 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 6141 { 6142 int rc; 6143 6144 bnxt_free_int(bp); 6145 bnxt_free_mem(bp, reconfig_dev); 6146 6147 bnxt_hwrm_func_buf_unrgtr(bp); 6148 if (bp->pf != NULL) { 6149 rte_free(bp->pf->vf_req_buf); 6150 bp->pf->vf_req_buf = NULL; 6151 } 6152 6153 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 6154 bp->flags &= ~BNXT_FLAG_REGISTERED; 6155 bnxt_free_ctx_mem(bp); 6156 if (!reconfig_dev) { 6157 bnxt_free_hwrm_resources(bp); 6158 bnxt_free_error_recovery_info(bp); 6159 } 6160 6161 bnxt_uninit_ctx_mem(bp); 6162 6163 bnxt_free_flow_stats_info(bp); 6164 if (bp->rep_info != NULL) 6165 bnxt_free_switch_domain(bp); 6166 bnxt_free_rep_info(bp); 6167 rte_free(bp->ptp_cfg); 6168 bp->ptp_cfg = NULL; 6169 return rc; 6170 } 6171 6172 static int 6173 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 6174 { 6175 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 6176 return -EPERM; 6177 6178 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 6179 6180 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 6181 bnxt_dev_close_op(eth_dev); 6182 6183 return 0; 6184 } 6185 6186 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev) 6187 { 6188 struct bnxt *bp = eth_dev->data->dev_private; 6189 struct rte_eth_dev *vf_rep_eth_dev; 6190 int ret = 0, i; 6191 6192 if (!bp) 6193 return -EINVAL; 6194 6195 for (i = 0; i < bp->num_reps; i++) { 6196 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev; 6197 if (!vf_rep_eth_dev) 6198 continue; 6199 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n", 6200 vf_rep_eth_dev->data->port_id); 6201 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit); 6202 } 6203 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", 6204 eth_dev->data->port_id); 6205 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit); 6206 6207 return ret; 6208 } 6209 6210 static void bnxt_free_rep_info(struct bnxt *bp) 6211 { 6212 rte_free(bp->rep_info); 6213 bp->rep_info = NULL; 6214 rte_free(bp->cfa_code_map); 6215 bp->cfa_code_map = NULL; 6216 } 6217 6218 static int bnxt_init_rep_info(struct bnxt *bp) 6219 { 6220 int i = 0, rc; 6221 6222 if (bp->rep_info) 6223 return 0; 6224 6225 bp->rep_info = rte_zmalloc("bnxt_rep_info", 6226 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, 6227 0); 6228 if (!bp->rep_info) { 6229 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); 6230 return -ENOMEM; 6231 } 6232 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map", 6233 sizeof(*bp->cfa_code_map) * 6234 BNXT_MAX_CFA_CODE, 0); 6235 if (!bp->cfa_code_map) { 6236 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n"); 6237 bnxt_free_rep_info(bp); 6238 return -ENOMEM; 6239 } 6240 6241 for (i = 0; i < BNXT_MAX_CFA_CODE; i++) 6242 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID; 6243 6244 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL); 6245 if (rc) { 6246 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n"); 6247 bnxt_free_rep_info(bp); 6248 return rc; 6249 } 6250 6251 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL); 6252 if (rc) { 6253 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n"); 6254 bnxt_free_rep_info(bp); 6255 return rc; 6256 } 6257 6258 return rc; 6259 } 6260 6261 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, 6262 struct rte_eth_devargs *eth_da, 6263 struct rte_eth_dev *backing_eth_dev, 6264 const char *dev_args) 6265 { 6266 struct rte_eth_dev *vf_rep_eth_dev; 6267 char name[RTE_ETH_NAME_MAX_LEN]; 6268 struct bnxt *backing_bp; 6269 uint16_t num_rep; 6270 int i, ret = 0; 6271 struct rte_kvargs *kvlist = NULL; 6272 6273 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) 6274 return 0; 6275 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) { 6276 PMD_DRV_LOG(ERR, "unsupported representor type %d\n", 6277 eth_da->type); 6278 return -ENOTSUP; 6279 } 6280 num_rep = eth_da->nb_representor_ports; 6281 if (num_rep > BNXT_MAX_VF_REPS) { 6282 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", 6283 num_rep, BNXT_MAX_VF_REPS); 6284 return -EINVAL; 6285 } 6286 6287 if (num_rep >= RTE_MAX_ETHPORTS) { 6288 PMD_DRV_LOG(ERR, 6289 "nb_representor_ports = %d > %d MAX ETHPORTS\n", 6290 num_rep, RTE_MAX_ETHPORTS); 6291 return -EINVAL; 6292 } 6293 6294 backing_bp = backing_eth_dev->data->dev_private; 6295 6296 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { 6297 PMD_DRV_LOG(ERR, 6298 "Not a PF or trusted VF. No Representor support\n"); 6299 /* Returning an error is not an option. 6300 * Applications are not handling this correctly 6301 */ 6302 return 0; 6303 } 6304 6305 if (bnxt_init_rep_info(backing_bp)) 6306 return 0; 6307 6308 for (i = 0; i < num_rep; i++) { 6309 struct bnxt_representor representor = { 6310 .vf_id = eth_da->representor_ports[i], 6311 .switch_domain_id = backing_bp->switch_domain_id, 6312 .parent_dev = backing_eth_dev 6313 }; 6314 6315 if (representor.vf_id >= BNXT_MAX_VF_REPS) { 6316 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", 6317 representor.vf_id, BNXT_MAX_VF_REPS); 6318 continue; 6319 } 6320 6321 /* representor port net_bdf_port */ 6322 snprintf(name, sizeof(name), "net_%s_representor_%d", 6323 pci_dev->device.name, eth_da->representor_ports[i]); 6324 6325 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args); 6326 if (kvlist) { 6327 /* 6328 * Handler for "rep_is_pf" devarg. 6329 * Invoked as for ex: "-a 000:00:0d.0, 6330 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6331 */ 6332 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF, 6333 bnxt_parse_devarg_rep_is_pf, 6334 (void *)&representor); 6335 if (ret) { 6336 ret = -EINVAL; 6337 goto err; 6338 } 6339 /* 6340 * Handler for "rep_based_pf" devarg. 6341 * Invoked as for ex: "-a 000:00:0d.0, 6342 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6343 */ 6344 ret = rte_kvargs_process(kvlist, 6345 BNXT_DEVARG_REP_BASED_PF, 6346 bnxt_parse_devarg_rep_based_pf, 6347 (void *)&representor); 6348 if (ret) { 6349 ret = -EINVAL; 6350 goto err; 6351 } 6352 /* 6353 * Handler for "rep_based_pf" devarg. 6354 * Invoked as for ex: "-a 000:00:0d.0, 6355 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6356 */ 6357 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F, 6358 bnxt_parse_devarg_rep_q_r2f, 6359 (void *)&representor); 6360 if (ret) { 6361 ret = -EINVAL; 6362 goto err; 6363 } 6364 /* 6365 * Handler for "rep_based_pf" devarg. 6366 * Invoked as for ex: "-a 000:00:0d.0, 6367 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6368 */ 6369 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R, 6370 bnxt_parse_devarg_rep_q_f2r, 6371 (void *)&representor); 6372 if (ret) { 6373 ret = -EINVAL; 6374 goto err; 6375 } 6376 /* 6377 * Handler for "rep_based_pf" devarg. 6378 * Invoked as for ex: "-a 000:00:0d.0, 6379 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6380 */ 6381 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F, 6382 bnxt_parse_devarg_rep_fc_r2f, 6383 (void *)&representor); 6384 if (ret) { 6385 ret = -EINVAL; 6386 goto err; 6387 } 6388 /* 6389 * Handler for "rep_based_pf" devarg. 6390 * Invoked as for ex: "-a 000:00:0d.0, 6391 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6392 */ 6393 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R, 6394 bnxt_parse_devarg_rep_fc_f2r, 6395 (void *)&representor); 6396 if (ret) { 6397 ret = -EINVAL; 6398 goto err; 6399 } 6400 } 6401 6402 ret = rte_eth_dev_create(&pci_dev->device, name, 6403 sizeof(struct bnxt_representor), 6404 NULL, NULL, 6405 bnxt_representor_init, 6406 &representor); 6407 if (ret) { 6408 PMD_DRV_LOG(ERR, "failed to create bnxt vf " 6409 "representor %s.", name); 6410 goto err; 6411 } 6412 6413 vf_rep_eth_dev = rte_eth_dev_allocated(name); 6414 if (!vf_rep_eth_dev) { 6415 PMD_DRV_LOG(ERR, "Failed to find the eth_dev" 6416 " for VF-Rep: %s.", name); 6417 ret = -ENODEV; 6418 goto err; 6419 } 6420 6421 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n", 6422 backing_eth_dev->data->port_id); 6423 backing_bp->rep_info[representor.vf_id].vfr_eth_dev = 6424 vf_rep_eth_dev; 6425 backing_bp->num_reps++; 6426 6427 } 6428 6429 rte_kvargs_free(kvlist); 6430 return 0; 6431 6432 err: 6433 /* If num_rep > 1, then rollback already created 6434 * ports, since we'll be failing the probe anyway 6435 */ 6436 if (num_rep > 1) 6437 bnxt_pci_remove_dev_with_reps(backing_eth_dev); 6438 rte_errno = -ret; 6439 rte_kvargs_free(kvlist); 6440 6441 return ret; 6442 } 6443 6444 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 6445 struct rte_pci_device *pci_dev) 6446 { 6447 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 6448 struct rte_eth_dev *backing_eth_dev; 6449 uint16_t num_rep; 6450 int ret = 0; 6451 6452 if (pci_dev->device.devargs) { 6453 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, 6454 ð_da); 6455 if (ret) 6456 return ret; 6457 } 6458 6459 num_rep = eth_da.nb_representor_ports; 6460 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n", 6461 num_rep); 6462 6463 /* We could come here after first level of probe is already invoked 6464 * as part of an application bringup(OVS-DPDK vswitchd), so first check 6465 * for already allocated eth_dev for the backing device (PF/Trusted VF) 6466 */ 6467 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6468 if (backing_eth_dev == NULL) { 6469 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 6470 sizeof(struct bnxt), 6471 eth_dev_pci_specific_init, pci_dev, 6472 bnxt_dev_init, NULL); 6473 6474 if (ret || !num_rep) 6475 return ret; 6476 6477 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6478 } 6479 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n", 6480 backing_eth_dev->data->port_id); 6481 6482 if (!num_rep) 6483 return ret; 6484 6485 /* probe representor ports now */ 6486 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev, 6487 pci_dev->device.devargs->args); 6488 6489 return ret; 6490 } 6491 6492 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 6493 { 6494 struct rte_eth_dev *eth_dev; 6495 6496 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6497 if (!eth_dev) 6498 return 0; /* Invoked typically only by OVS-DPDK, by the 6499 * time it comes here the eth_dev is already 6500 * deleted by rte_eth_dev_close(), so returning 6501 * +ve value will at least help in proper cleanup 6502 */ 6503 6504 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id); 6505 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 6506 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 6507 return rte_eth_dev_destroy(eth_dev, 6508 bnxt_representor_uninit); 6509 else 6510 return rte_eth_dev_destroy(eth_dev, 6511 bnxt_dev_uninit); 6512 } else { 6513 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 6514 } 6515 } 6516 6517 static struct rte_pci_driver bnxt_rte_pmd = { 6518 .id_table = bnxt_pci_id_map, 6519 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 6520 RTE_PCI_DRV_INTR_RMV | 6521 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs 6522 * and OVS-DPDK 6523 */ 6524 .probe = bnxt_pci_probe, 6525 .remove = bnxt_pci_remove, 6526 }; 6527 6528 static bool 6529 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 6530 { 6531 if (strcmp(dev->device->driver->name, drv->driver.name)) 6532 return false; 6533 6534 return true; 6535 } 6536 6537 bool is_bnxt_supported(struct rte_eth_dev *dev) 6538 { 6539 return is_device_supported(dev, &bnxt_rte_pmd); 6540 } 6541 6542 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE); 6543 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 6544 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 6545 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 6546