1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <rte_ethdev_driver.h> 11 #include <rte_ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 16 #include "bnxt.h" 17 #include "bnxt_filter.h" 18 #include "bnxt_hwrm.h" 19 #include "bnxt_irq.h" 20 #include "bnxt_ring.h" 21 #include "bnxt_rxq.h" 22 #include "bnxt_rxr.h" 23 #include "bnxt_stats.h" 24 #include "bnxt_txq.h" 25 #include "bnxt_txr.h" 26 #include "bnxt_vnic.h" 27 #include "hsi_struct_def_dpdk.h" 28 #include "bnxt_nvm_defs.h" 29 30 #define DRV_MODULE_NAME "bnxt" 31 static const char bnxt_version[] = 32 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 33 int bnxt_logtype_driver; 34 35 /* 36 * The set of PCI devices this driver supports 37 */ 38 static const struct rte_pci_id bnxt_pci_id_map[] = { 39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 92 { .vendor_id = 0, /* sentinel */ }, 93 }; 94 95 #define BNXT_ETH_RSS_SUPPORT ( \ 96 ETH_RSS_IPV4 | \ 97 ETH_RSS_NONFRAG_IPV4_TCP | \ 98 ETH_RSS_NONFRAG_IPV4_UDP | \ 99 ETH_RSS_IPV6 | \ 100 ETH_RSS_NONFRAG_IPV6_TCP | \ 101 ETH_RSS_NONFRAG_IPV6_UDP) 102 103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 104 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 105 DEV_TX_OFFLOAD_TCP_CKSUM | \ 106 DEV_TX_OFFLOAD_UDP_CKSUM | \ 107 DEV_TX_OFFLOAD_TCP_TSO | \ 108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 113 DEV_TX_OFFLOAD_QINQ_INSERT | \ 114 DEV_TX_OFFLOAD_MULTI_SEGS) 115 116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 117 DEV_RX_OFFLOAD_VLAN_STRIP | \ 118 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 119 DEV_RX_OFFLOAD_UDP_CKSUM | \ 120 DEV_RX_OFFLOAD_TCP_CKSUM | \ 121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 122 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 123 DEV_RX_OFFLOAD_KEEP_CRC | \ 124 DEV_RX_OFFLOAD_VLAN_EXTEND | \ 125 DEV_RX_OFFLOAD_TCP_LRO | \ 126 DEV_RX_OFFLOAD_SCATTER | \ 127 DEV_RX_OFFLOAD_RSS_HASH) 128 129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 134 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 135 136 int is_bnxt_in_error(struct bnxt *bp) 137 { 138 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 139 return -EIO; 140 if (bp->flags & BNXT_FLAG_FW_RESET) 141 return -EBUSY; 142 143 return 0; 144 } 145 146 /***********************/ 147 148 /* 149 * High level utility functions 150 */ 151 152 uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 153 { 154 if (!BNXT_CHIP_THOR(bp)) 155 return 1; 156 157 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings, 158 BNXT_RSS_ENTRIES_PER_CTX_THOR) / 159 BNXT_RSS_ENTRIES_PER_CTX_THOR; 160 } 161 162 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 163 { 164 if (!BNXT_CHIP_THOR(bp)) 165 return HW_HASH_INDEX_SIZE; 166 167 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR; 168 } 169 170 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 171 { 172 bnxt_free_filter_mem(bp); 173 bnxt_free_vnic_attributes(bp); 174 bnxt_free_vnic_mem(bp); 175 176 /* tx/rx rings are configured as part of *_queue_setup callbacks. 177 * If the number of rings change across fw update, 178 * we don't have much choice except to warn the user. 179 */ 180 if (!reconfig) { 181 bnxt_free_stats(bp); 182 bnxt_free_tx_rings(bp); 183 bnxt_free_rx_rings(bp); 184 } 185 bnxt_free_async_cp_ring(bp); 186 bnxt_free_rxtx_nq_ring(bp); 187 188 rte_free(bp->grp_info); 189 bp->grp_info = NULL; 190 } 191 192 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 193 { 194 int rc; 195 196 rc = bnxt_alloc_ring_grps(bp); 197 if (rc) 198 goto alloc_mem_err; 199 200 rc = bnxt_alloc_async_ring_struct(bp); 201 if (rc) 202 goto alloc_mem_err; 203 204 rc = bnxt_alloc_vnic_mem(bp); 205 if (rc) 206 goto alloc_mem_err; 207 208 rc = bnxt_alloc_vnic_attributes(bp); 209 if (rc) 210 goto alloc_mem_err; 211 212 rc = bnxt_alloc_filter_mem(bp); 213 if (rc) 214 goto alloc_mem_err; 215 216 rc = bnxt_alloc_async_cp_ring(bp); 217 if (rc) 218 goto alloc_mem_err; 219 220 rc = bnxt_alloc_rxtx_nq_ring(bp); 221 if (rc) 222 goto alloc_mem_err; 223 224 return 0; 225 226 alloc_mem_err: 227 bnxt_free_mem(bp, reconfig); 228 return rc; 229 } 230 231 static int bnxt_init_chip(struct bnxt *bp) 232 { 233 struct bnxt_rx_queue *rxq; 234 struct rte_eth_link new; 235 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 236 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 237 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 238 uint64_t rx_offloads = dev_conf->rxmode.offloads; 239 uint32_t intr_vector = 0; 240 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 241 uint32_t vec = BNXT_MISC_VEC_ID; 242 unsigned int i, j; 243 int rc; 244 245 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 246 bp->eth_dev->data->dev_conf.rxmode.offloads |= 247 DEV_RX_OFFLOAD_JUMBO_FRAME; 248 bp->flags |= BNXT_FLAG_JUMBO; 249 } else { 250 bp->eth_dev->data->dev_conf.rxmode.offloads &= 251 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 252 bp->flags &= ~BNXT_FLAG_JUMBO; 253 } 254 255 /* THOR does not support ring groups. 256 * But we will use the array to save RSS context IDs. 257 */ 258 if (BNXT_CHIP_THOR(bp)) 259 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR; 260 261 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 262 if (rc) { 263 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 264 goto err_out; 265 } 266 267 rc = bnxt_alloc_hwrm_rings(bp); 268 if (rc) { 269 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 270 goto err_out; 271 } 272 273 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 274 if (rc) { 275 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 276 goto err_out; 277 } 278 279 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 280 goto skip_cosq_cfg; 281 282 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 283 if (bp->rx_cos_queue[i].id != 0xff) { 284 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 285 286 if (!vnic) { 287 PMD_DRV_LOG(ERR, 288 "Num pools more than FW profile\n"); 289 rc = -EINVAL; 290 goto err_out; 291 } 292 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 293 bp->rx_cosq_cnt++; 294 } 295 } 296 297 skip_cosq_cfg: 298 rc = bnxt_mq_rx_configure(bp); 299 if (rc) { 300 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 301 goto err_out; 302 } 303 304 /* VNIC configuration */ 305 for (i = 0; i < bp->nr_vnics; i++) { 306 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 307 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 308 309 rc = bnxt_vnic_grp_alloc(bp, vnic); 310 if (rc) 311 goto err_out; 312 313 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 314 i, vnic, vnic->fw_grp_ids); 315 316 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 317 if (rc) { 318 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n", 319 i, rc); 320 goto err_out; 321 } 322 323 /* Alloc RSS context only if RSS mode is enabled */ 324 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 325 int j, nr_ctxs = bnxt_rss_ctxts(bp); 326 327 rc = 0; 328 for (j = 0; j < nr_ctxs; j++) { 329 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 330 if (rc) 331 break; 332 } 333 if (rc) { 334 PMD_DRV_LOG(ERR, 335 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 336 i, j, rc); 337 goto err_out; 338 } 339 vnic->num_lb_ctxts = nr_ctxs; 340 } 341 342 /* 343 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 344 * setting is not available at this time, it will not be 345 * configured correctly in the CFA. 346 */ 347 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 348 vnic->vlan_strip = true; 349 else 350 vnic->vlan_strip = false; 351 352 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 353 if (rc) { 354 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 355 i, rc); 356 goto err_out; 357 } 358 359 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 360 if (rc) { 361 PMD_DRV_LOG(ERR, 362 "HWRM vnic %d filter failure rc: %x\n", 363 i, rc); 364 goto err_out; 365 } 366 367 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 368 rxq = bp->eth_dev->data->rx_queues[j]; 369 370 PMD_DRV_LOG(DEBUG, 371 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 372 j, rxq->vnic, rxq->vnic->fw_grp_ids); 373 374 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 375 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 376 } 377 378 rc = bnxt_vnic_rss_configure(bp, vnic); 379 if (rc) { 380 PMD_DRV_LOG(ERR, 381 "HWRM vnic set RSS failure rc: %x\n", rc); 382 goto err_out; 383 } 384 385 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 386 387 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 388 DEV_RX_OFFLOAD_TCP_LRO) 389 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 390 else 391 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 392 } 393 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 394 if (rc) { 395 PMD_DRV_LOG(ERR, 396 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 397 goto err_out; 398 } 399 400 /* check and configure queue intr-vector mapping */ 401 if ((rte_intr_cap_multiple(intr_handle) || 402 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 403 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 404 intr_vector = bp->eth_dev->data->nb_rx_queues; 405 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 406 if (intr_vector > bp->rx_cp_nr_rings) { 407 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 408 bp->rx_cp_nr_rings); 409 return -ENOTSUP; 410 } 411 rc = rte_intr_efd_enable(intr_handle, intr_vector); 412 if (rc) 413 return rc; 414 } 415 416 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 417 intr_handle->intr_vec = 418 rte_zmalloc("intr_vec", 419 bp->eth_dev->data->nb_rx_queues * 420 sizeof(int), 0); 421 if (intr_handle->intr_vec == NULL) { 422 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 423 " intr_vec", bp->eth_dev->data->nb_rx_queues); 424 rc = -ENOMEM; 425 goto err_disable; 426 } 427 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 428 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 429 intr_handle->intr_vec, intr_handle->nb_efd, 430 intr_handle->max_intr); 431 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 432 queue_id++) { 433 intr_handle->intr_vec[queue_id] = 434 vec + BNXT_RX_VEC_START; 435 if (vec < base + intr_handle->nb_efd - 1) 436 vec++; 437 } 438 } 439 440 /* enable uio/vfio intr/eventfd mapping */ 441 rc = rte_intr_enable(intr_handle); 442 if (rc) 443 goto err_free; 444 445 rc = bnxt_get_hwrm_link_config(bp, &new); 446 if (rc) { 447 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc); 448 goto err_free; 449 } 450 451 if (!bp->link_info.link_up) { 452 rc = bnxt_set_hwrm_link_config(bp, true); 453 if (rc) { 454 PMD_DRV_LOG(ERR, 455 "HWRM link config failure rc: %x\n", rc); 456 goto err_free; 457 } 458 } 459 bnxt_print_link_info(bp->eth_dev); 460 461 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 462 if (!bp->mark_table) 463 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 464 465 return 0; 466 467 err_free: 468 rte_free(intr_handle->intr_vec); 469 err_disable: 470 rte_intr_efd_disable(intr_handle); 471 err_out: 472 /* Some of the error status returned by FW may not be from errno.h */ 473 if (rc > 0) 474 rc = -EIO; 475 476 return rc; 477 } 478 479 static int bnxt_shutdown_nic(struct bnxt *bp) 480 { 481 bnxt_free_all_hwrm_resources(bp); 482 bnxt_free_all_filters(bp); 483 bnxt_free_all_vnics(bp); 484 return 0; 485 } 486 487 /* 488 * Device configuration and status function 489 */ 490 491 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 492 struct rte_eth_dev_info *dev_info) 493 { 494 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 495 struct bnxt *bp = eth_dev->data->dev_private; 496 uint16_t max_vnics, i, j, vpool, vrxq; 497 unsigned int max_rx_rings; 498 int rc; 499 500 rc = is_bnxt_in_error(bp); 501 if (rc) 502 return rc; 503 504 /* MAC Specifics */ 505 dev_info->max_mac_addrs = bp->max_l2_ctx; 506 dev_info->max_hash_mac_addrs = 0; 507 508 /* PF/VF specifics */ 509 if (BNXT_PF(bp)) 510 dev_info->max_vfs = pdev->max_vfs; 511 512 max_rx_rings = BNXT_MAX_RINGS(bp); 513 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 514 dev_info->max_rx_queues = max_rx_rings; 515 dev_info->max_tx_queues = max_rx_rings; 516 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 517 dev_info->hash_key_size = 40; 518 max_vnics = bp->max_vnics; 519 520 /* MTU specifics */ 521 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 522 dev_info->max_mtu = BNXT_MAX_MTU; 523 524 /* Fast path specifics */ 525 dev_info->min_rx_bufsize = 1; 526 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 527 528 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 529 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 530 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 531 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT; 532 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 533 534 /* *INDENT-OFF* */ 535 dev_info->default_rxconf = (struct rte_eth_rxconf) { 536 .rx_thresh = { 537 .pthresh = 8, 538 .hthresh = 8, 539 .wthresh = 0, 540 }, 541 .rx_free_thresh = 32, 542 /* If no descriptors available, pkts are dropped by default */ 543 .rx_drop_en = 1, 544 }; 545 546 dev_info->default_txconf = (struct rte_eth_txconf) { 547 .tx_thresh = { 548 .pthresh = 32, 549 .hthresh = 0, 550 .wthresh = 0, 551 }, 552 .tx_free_thresh = 32, 553 .tx_rs_thresh = 32, 554 }; 555 eth_dev->data->dev_conf.intr_conf.lsc = 1; 556 557 eth_dev->data->dev_conf.intr_conf.rxq = 1; 558 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 559 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 560 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 561 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 562 563 /* *INDENT-ON* */ 564 565 /* 566 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 567 * need further investigation. 568 */ 569 570 /* VMDq resources */ 571 vpool = 64; /* ETH_64_POOLS */ 572 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 573 for (i = 0; i < 4; vpool >>= 1, i++) { 574 if (max_vnics > vpool) { 575 for (j = 0; j < 5; vrxq >>= 1, j++) { 576 if (dev_info->max_rx_queues > vrxq) { 577 if (vpool > vrxq) 578 vpool = vrxq; 579 goto found; 580 } 581 } 582 /* Not enough resources to support VMDq */ 583 break; 584 } 585 } 586 /* Not enough resources to support VMDq */ 587 vpool = 0; 588 vrxq = 0; 589 found: 590 dev_info->max_vmdq_pools = vpool; 591 dev_info->vmdq_queue_num = vrxq; 592 593 dev_info->vmdq_pool_base = 0; 594 dev_info->vmdq_queue_base = 0; 595 596 return 0; 597 } 598 599 /* Configure the device based on the configuration provided */ 600 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 601 { 602 struct bnxt *bp = eth_dev->data->dev_private; 603 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 604 int rc; 605 606 bp->rx_queues = (void *)eth_dev->data->rx_queues; 607 bp->tx_queues = (void *)eth_dev->data->tx_queues; 608 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 609 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 610 611 rc = is_bnxt_in_error(bp); 612 if (rc) 613 return rc; 614 615 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 616 rc = bnxt_hwrm_check_vf_rings(bp); 617 if (rc) { 618 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 619 return -ENOSPC; 620 } 621 622 /* If a resource has already been allocated - in this case 623 * it is the async completion ring, free it. Reallocate it after 624 * resource reservation. This will ensure the resource counts 625 * are calculated correctly. 626 */ 627 628 pthread_mutex_lock(&bp->def_cp_lock); 629 630 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 631 bnxt_disable_int(bp); 632 bnxt_free_cp_ring(bp, bp->async_cp_ring); 633 } 634 635 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 636 if (rc) { 637 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 638 pthread_mutex_unlock(&bp->def_cp_lock); 639 return -ENOSPC; 640 } 641 642 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 643 rc = bnxt_alloc_async_cp_ring(bp); 644 if (rc) { 645 pthread_mutex_unlock(&bp->def_cp_lock); 646 return rc; 647 } 648 bnxt_enable_int(bp); 649 } 650 651 pthread_mutex_unlock(&bp->def_cp_lock); 652 } else { 653 /* legacy driver needs to get updated values */ 654 rc = bnxt_hwrm_func_qcaps(bp); 655 if (rc) { 656 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc); 657 return rc; 658 } 659 } 660 661 /* Inherit new configurations */ 662 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 663 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 664 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 665 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 666 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 667 bp->max_stat_ctx) 668 goto resource_error; 669 670 if (BNXT_HAS_RING_GRPS(bp) && 671 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 672 goto resource_error; 673 674 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 675 bp->max_vnics < eth_dev->data->nb_rx_queues) 676 goto resource_error; 677 678 bp->rx_cp_nr_rings = bp->rx_nr_rings; 679 bp->tx_cp_nr_rings = bp->tx_nr_rings; 680 681 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 682 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; 683 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 684 685 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 686 eth_dev->data->mtu = 687 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 688 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 689 BNXT_NUM_VLANS; 690 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 691 } 692 return 0; 693 694 resource_error: 695 PMD_DRV_LOG(ERR, 696 "Insufficient resources to support requested config\n"); 697 PMD_DRV_LOG(ERR, 698 "Num Queues Requested: Tx %d, Rx %d\n", 699 eth_dev->data->nb_tx_queues, 700 eth_dev->data->nb_rx_queues); 701 PMD_DRV_LOG(ERR, 702 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 703 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 704 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 705 return -ENOSPC; 706 } 707 708 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 709 { 710 struct rte_eth_link *link = ð_dev->data->dev_link; 711 712 if (link->link_status) 713 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 714 eth_dev->data->port_id, 715 (uint32_t)link->link_speed, 716 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 717 ("full-duplex") : ("half-duplex\n")); 718 else 719 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 720 eth_dev->data->port_id); 721 } 722 723 /* 724 * Determine whether the current configuration requires support for scattered 725 * receive; return 1 if scattered receive is required and 0 if not. 726 */ 727 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 728 { 729 uint16_t buf_size; 730 int i; 731 732 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 733 return 1; 734 735 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 736 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 737 738 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 739 RTE_PKTMBUF_HEADROOM); 740 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 741 return 1; 742 } 743 return 0; 744 } 745 746 static eth_rx_burst_t 747 bnxt_receive_function(struct rte_eth_dev *eth_dev) 748 { 749 struct bnxt *bp = eth_dev->data->dev_private; 750 751 #ifdef RTE_ARCH_X86 752 #ifndef RTE_LIBRTE_IEEE1588 753 /* 754 * Vector mode receive can be enabled only if scatter rx is not 755 * in use and rx offloads are limited to VLAN stripping and 756 * CRC stripping. 757 */ 758 if (!eth_dev->data->scattered_rx && 759 !(eth_dev->data->dev_conf.rxmode.offloads & 760 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 761 DEV_RX_OFFLOAD_KEEP_CRC | 762 DEV_RX_OFFLOAD_JUMBO_FRAME | 763 DEV_RX_OFFLOAD_IPV4_CKSUM | 764 DEV_RX_OFFLOAD_UDP_CKSUM | 765 DEV_RX_OFFLOAD_TCP_CKSUM | 766 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 767 DEV_RX_OFFLOAD_RSS_HASH | 768 DEV_RX_OFFLOAD_VLAN_FILTER))) { 769 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 770 eth_dev->data->port_id); 771 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 772 return bnxt_recv_pkts_vec; 773 } 774 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 775 eth_dev->data->port_id); 776 PMD_DRV_LOG(INFO, 777 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 778 eth_dev->data->port_id, 779 eth_dev->data->scattered_rx, 780 eth_dev->data->dev_conf.rxmode.offloads); 781 #endif 782 #endif 783 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 784 return bnxt_recv_pkts; 785 } 786 787 static eth_tx_burst_t 788 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) 789 { 790 #ifdef RTE_ARCH_X86 791 #ifndef RTE_LIBRTE_IEEE1588 792 /* 793 * Vector mode transmit can be enabled only if not using scatter rx 794 * or tx offloads. 795 */ 796 if (!eth_dev->data->scattered_rx && 797 !eth_dev->data->dev_conf.txmode.offloads) { 798 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 799 eth_dev->data->port_id); 800 return bnxt_xmit_pkts_vec; 801 } 802 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 803 eth_dev->data->port_id); 804 PMD_DRV_LOG(INFO, 805 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 806 eth_dev->data->port_id, 807 eth_dev->data->scattered_rx, 808 eth_dev->data->dev_conf.txmode.offloads); 809 #endif 810 #endif 811 return bnxt_xmit_pkts; 812 } 813 814 static int bnxt_handle_if_change_status(struct bnxt *bp) 815 { 816 int rc; 817 818 /* Since fw has undergone a reset and lost all contexts, 819 * set fatal flag to not issue hwrm during cleanup 820 */ 821 bp->flags |= BNXT_FLAG_FATAL_ERROR; 822 bnxt_uninit_resources(bp, true); 823 824 /* clear fatal flag so that re-init happens */ 825 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 826 rc = bnxt_init_resources(bp, true); 827 828 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 829 830 return rc; 831 } 832 833 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 834 { 835 struct bnxt *bp = eth_dev->data->dev_private; 836 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 837 int vlan_mask = 0; 838 int rc; 839 840 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 841 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 842 return -EINVAL; 843 } 844 845 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) { 846 PMD_DRV_LOG(ERR, 847 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 848 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 849 } 850 851 rc = bnxt_hwrm_if_change(bp, 1); 852 if (!rc) { 853 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 854 rc = bnxt_handle_if_change_status(bp); 855 if (rc) 856 return rc; 857 } 858 } 859 bnxt_enable_int(bp); 860 861 rc = bnxt_init_chip(bp); 862 if (rc) 863 goto error; 864 865 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 866 867 bnxt_link_update(eth_dev, 1, ETH_LINK_UP); 868 869 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 870 vlan_mask |= ETH_VLAN_FILTER_MASK; 871 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 872 vlan_mask |= ETH_VLAN_STRIP_MASK; 873 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 874 if (rc) 875 goto error; 876 877 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 878 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 879 880 bp->flags |= BNXT_FLAG_INIT_DONE; 881 eth_dev->data->dev_started = 1; 882 bp->dev_stopped = 0; 883 pthread_mutex_lock(&bp->def_cp_lock); 884 bnxt_schedule_fw_health_check(bp); 885 pthread_mutex_unlock(&bp->def_cp_lock); 886 return 0; 887 888 error: 889 bnxt_hwrm_if_change(bp, 0); 890 bnxt_shutdown_nic(bp); 891 bnxt_free_tx_mbufs(bp); 892 bnxt_free_rx_mbufs(bp); 893 return rc; 894 } 895 896 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 897 { 898 struct bnxt *bp = eth_dev->data->dev_private; 899 int rc = 0; 900 901 if (!bp->link_info.link_up) 902 rc = bnxt_set_hwrm_link_config(bp, true); 903 if (!rc) 904 eth_dev->data->dev_link.link_status = 1; 905 906 bnxt_print_link_info(eth_dev); 907 return rc; 908 } 909 910 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 911 { 912 struct bnxt *bp = eth_dev->data->dev_private; 913 914 eth_dev->data->dev_link.link_status = 0; 915 bnxt_set_hwrm_link_config(bp, false); 916 bp->link_info.link_up = 0; 917 918 return 0; 919 } 920 921 /* Unload the driver, release resources */ 922 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 923 { 924 struct bnxt *bp = eth_dev->data->dev_private; 925 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 926 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 927 928 eth_dev->data->dev_started = 0; 929 /* Prevent crashes when queues are still in use */ 930 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 931 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 932 933 bnxt_disable_int(bp); 934 935 /* disable uio/vfio intr/eventfd mapping */ 936 rte_intr_disable(intr_handle); 937 938 bnxt_cancel_fw_health_check(bp); 939 940 bp->flags &= ~BNXT_FLAG_INIT_DONE; 941 if (bp->eth_dev->data->dev_started) { 942 /* TBD: STOP HW queues DMA */ 943 eth_dev->data->dev_link.link_status = 0; 944 } 945 bnxt_dev_set_link_down_op(eth_dev); 946 947 /* Wait for link to be reset and the async notification to process. 948 * During reset recovery, there is no need to wait 949 */ 950 if (!is_bnxt_in_error(bp)) 951 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN); 952 953 /* Clean queue intr-vector mapping */ 954 rte_intr_efd_disable(intr_handle); 955 if (intr_handle->intr_vec != NULL) { 956 rte_free(intr_handle->intr_vec); 957 intr_handle->intr_vec = NULL; 958 } 959 960 bnxt_hwrm_port_clr_stats(bp); 961 bnxt_free_tx_mbufs(bp); 962 bnxt_free_rx_mbufs(bp); 963 /* Process any remaining notifications in default completion queue */ 964 bnxt_int_handler(eth_dev); 965 bnxt_shutdown_nic(bp); 966 bnxt_hwrm_if_change(bp, 0); 967 memset(bp->mark_table, 0, BNXT_MARK_TABLE_SZ); 968 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 969 bp->dev_stopped = 1; 970 bp->rx_cosq_cnt = 0; 971 } 972 973 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 974 { 975 struct bnxt *bp = eth_dev->data->dev_private; 976 977 if (bp->dev_stopped == 0) 978 bnxt_dev_stop_op(eth_dev); 979 980 if (eth_dev->data->mac_addrs != NULL) { 981 rte_free(eth_dev->data->mac_addrs); 982 eth_dev->data->mac_addrs = NULL; 983 } 984 if (bp->grp_info != NULL) { 985 rte_free(bp->grp_info); 986 bp->grp_info = NULL; 987 } 988 989 rte_free(bp->mark_table); 990 bp->mark_table = NULL; 991 992 bnxt_dev_uninit(eth_dev); 993 } 994 995 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 996 uint32_t index) 997 { 998 struct bnxt *bp = eth_dev->data->dev_private; 999 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1000 struct bnxt_vnic_info *vnic; 1001 struct bnxt_filter_info *filter, *temp_filter; 1002 uint32_t i; 1003 1004 if (is_bnxt_in_error(bp)) 1005 return; 1006 1007 /* 1008 * Loop through all VNICs from the specified filter flow pools to 1009 * remove the corresponding MAC addr filter 1010 */ 1011 for (i = 0; i < bp->nr_vnics; i++) { 1012 if (!(pool_mask & (1ULL << i))) 1013 continue; 1014 1015 vnic = &bp->vnic_info[i]; 1016 filter = STAILQ_FIRST(&vnic->filter); 1017 while (filter) { 1018 temp_filter = STAILQ_NEXT(filter, next); 1019 if (filter->mac_index == index) { 1020 STAILQ_REMOVE(&vnic->filter, filter, 1021 bnxt_filter_info, next); 1022 bnxt_hwrm_clear_l2_filter(bp, filter); 1023 bnxt_free_filter(bp, filter); 1024 } 1025 filter = temp_filter; 1026 } 1027 } 1028 } 1029 1030 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1031 struct rte_ether_addr *mac_addr, uint32_t index, 1032 uint32_t pool) 1033 { 1034 struct bnxt_filter_info *filter; 1035 int rc = 0; 1036 1037 /* Attach requested MAC address to the new l2_filter */ 1038 STAILQ_FOREACH(filter, &vnic->filter, next) { 1039 if (filter->mac_index == index) { 1040 PMD_DRV_LOG(DEBUG, 1041 "MAC addr already existed for pool %d\n", 1042 pool); 1043 return 0; 1044 } 1045 } 1046 1047 filter = bnxt_alloc_filter(bp); 1048 if (!filter) { 1049 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1050 return -ENODEV; 1051 } 1052 1053 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1054 * if the MAC that's been programmed now is a different one, then, 1055 * copy that addr to filter->l2_addr 1056 */ 1057 if (mac_addr) 1058 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1059 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1060 1061 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1062 if (!rc) { 1063 filter->mac_index = index; 1064 if (filter->mac_index == 0) 1065 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1066 else 1067 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1068 } else { 1069 bnxt_free_filter(bp, filter); 1070 } 1071 1072 return rc; 1073 } 1074 1075 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1076 struct rte_ether_addr *mac_addr, 1077 uint32_t index, uint32_t pool) 1078 { 1079 struct bnxt *bp = eth_dev->data->dev_private; 1080 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1081 int rc = 0; 1082 1083 rc = is_bnxt_in_error(bp); 1084 if (rc) 1085 return rc; 1086 1087 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) { 1088 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1089 return -ENOTSUP; 1090 } 1091 1092 if (!vnic) { 1093 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1094 return -EINVAL; 1095 } 1096 1097 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1098 1099 return rc; 1100 } 1101 1102 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 1103 bool exp_link_status) 1104 { 1105 int rc = 0; 1106 struct bnxt *bp = eth_dev->data->dev_private; 1107 struct rte_eth_link new; 1108 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT : 1109 BNXT_LINK_DOWN_WAIT_CNT; 1110 1111 rc = is_bnxt_in_error(bp); 1112 if (rc) 1113 return rc; 1114 1115 memset(&new, 0, sizeof(new)); 1116 do { 1117 /* Retrieve link info from hardware */ 1118 rc = bnxt_get_hwrm_link_config(bp, &new); 1119 if (rc) { 1120 new.link_speed = ETH_LINK_SPEED_100M; 1121 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1122 PMD_DRV_LOG(ERR, 1123 "Failed to retrieve link rc = 0x%x!\n", rc); 1124 goto out; 1125 } 1126 1127 if (!wait_to_complete || new.link_status == exp_link_status) 1128 break; 1129 1130 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1131 } while (cnt--); 1132 1133 out: 1134 /* Timed out or success */ 1135 if (new.link_status != eth_dev->data->dev_link.link_status || 1136 new.link_speed != eth_dev->data->dev_link.link_speed) { 1137 rte_eth_linkstatus_set(eth_dev, &new); 1138 1139 _rte_eth_dev_callback_process(eth_dev, 1140 RTE_ETH_EVENT_INTR_LSC, 1141 NULL); 1142 1143 bnxt_print_link_info(eth_dev); 1144 } 1145 1146 return rc; 1147 } 1148 1149 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 1150 int wait_to_complete) 1151 { 1152 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP); 1153 } 1154 1155 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1156 { 1157 struct bnxt *bp = eth_dev->data->dev_private; 1158 struct bnxt_vnic_info *vnic; 1159 uint32_t old_flags; 1160 int rc; 1161 1162 rc = is_bnxt_in_error(bp); 1163 if (rc) 1164 return rc; 1165 1166 if (bp->vnic_info == NULL) 1167 return 0; 1168 1169 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1170 1171 old_flags = vnic->flags; 1172 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1173 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1174 if (rc != 0) 1175 vnic->flags = old_flags; 1176 1177 return rc; 1178 } 1179 1180 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1181 { 1182 struct bnxt *bp = eth_dev->data->dev_private; 1183 struct bnxt_vnic_info *vnic; 1184 uint32_t old_flags; 1185 int rc; 1186 1187 rc = is_bnxt_in_error(bp); 1188 if (rc) 1189 return rc; 1190 1191 if (bp->vnic_info == NULL) 1192 return 0; 1193 1194 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1195 1196 old_flags = vnic->flags; 1197 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1198 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1199 if (rc != 0) 1200 vnic->flags = old_flags; 1201 1202 return rc; 1203 } 1204 1205 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1206 { 1207 struct bnxt *bp = eth_dev->data->dev_private; 1208 struct bnxt_vnic_info *vnic; 1209 uint32_t old_flags; 1210 int rc; 1211 1212 rc = is_bnxt_in_error(bp); 1213 if (rc) 1214 return rc; 1215 1216 if (bp->vnic_info == NULL) 1217 return 0; 1218 1219 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1220 1221 old_flags = vnic->flags; 1222 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1223 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1224 if (rc != 0) 1225 vnic->flags = old_flags; 1226 1227 return rc; 1228 } 1229 1230 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1231 { 1232 struct bnxt *bp = eth_dev->data->dev_private; 1233 struct bnxt_vnic_info *vnic; 1234 uint32_t old_flags; 1235 int rc; 1236 1237 rc = is_bnxt_in_error(bp); 1238 if (rc) 1239 return rc; 1240 1241 if (bp->vnic_info == NULL) 1242 return 0; 1243 1244 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1245 1246 old_flags = vnic->flags; 1247 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1248 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1249 if (rc != 0) 1250 vnic->flags = old_flags; 1251 1252 return rc; 1253 } 1254 1255 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1256 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1257 { 1258 if (qid >= bp->rx_nr_rings) 1259 return NULL; 1260 1261 return bp->eth_dev->data->rx_queues[qid]; 1262 } 1263 1264 /* Return rxq corresponding to a given rss table ring/group ID. */ 1265 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1266 { 1267 struct bnxt_rx_queue *rxq; 1268 unsigned int i; 1269 1270 if (!BNXT_HAS_RING_GRPS(bp)) { 1271 for (i = 0; i < bp->rx_nr_rings; i++) { 1272 rxq = bp->eth_dev->data->rx_queues[i]; 1273 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1274 return rxq->index; 1275 } 1276 } else { 1277 for (i = 0; i < bp->rx_nr_rings; i++) { 1278 if (bp->grp_info[i].fw_grp_id == fwr) 1279 return i; 1280 } 1281 } 1282 1283 return INVALID_HW_RING_ID; 1284 } 1285 1286 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1287 struct rte_eth_rss_reta_entry64 *reta_conf, 1288 uint16_t reta_size) 1289 { 1290 struct bnxt *bp = eth_dev->data->dev_private; 1291 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1292 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1293 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1294 uint16_t idx, sft; 1295 int i, rc; 1296 1297 rc = is_bnxt_in_error(bp); 1298 if (rc) 1299 return rc; 1300 1301 if (!vnic->rss_table) 1302 return -EINVAL; 1303 1304 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1305 return -EINVAL; 1306 1307 if (reta_size != tbl_size) { 1308 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1309 "(%d) must equal the size supported by the hardware " 1310 "(%d)\n", reta_size, tbl_size); 1311 return -EINVAL; 1312 } 1313 1314 for (i = 0; i < reta_size; i++) { 1315 struct bnxt_rx_queue *rxq; 1316 1317 idx = i / RTE_RETA_GROUP_SIZE; 1318 sft = i % RTE_RETA_GROUP_SIZE; 1319 1320 if (!(reta_conf[idx].mask & (1ULL << sft))) 1321 continue; 1322 1323 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1324 if (!rxq) { 1325 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1326 return -EINVAL; 1327 } 1328 1329 if (BNXT_CHIP_THOR(bp)) { 1330 vnic->rss_table[i * 2] = 1331 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1332 vnic->rss_table[i * 2 + 1] = 1333 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1334 } else { 1335 vnic->rss_table[i] = 1336 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1337 } 1338 } 1339 1340 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1341 return 0; 1342 } 1343 1344 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1345 struct rte_eth_rss_reta_entry64 *reta_conf, 1346 uint16_t reta_size) 1347 { 1348 struct bnxt *bp = eth_dev->data->dev_private; 1349 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1350 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1351 uint16_t idx, sft, i; 1352 int rc; 1353 1354 rc = is_bnxt_in_error(bp); 1355 if (rc) 1356 return rc; 1357 1358 /* Retrieve from the default VNIC */ 1359 if (!vnic) 1360 return -EINVAL; 1361 if (!vnic->rss_table) 1362 return -EINVAL; 1363 1364 if (reta_size != tbl_size) { 1365 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1366 "(%d) must equal the size supported by the hardware " 1367 "(%d)\n", reta_size, tbl_size); 1368 return -EINVAL; 1369 } 1370 1371 for (idx = 0, i = 0; i < reta_size; i++) { 1372 idx = i / RTE_RETA_GROUP_SIZE; 1373 sft = i % RTE_RETA_GROUP_SIZE; 1374 1375 if (reta_conf[idx].mask & (1ULL << sft)) { 1376 uint16_t qid; 1377 1378 if (BNXT_CHIP_THOR(bp)) 1379 qid = bnxt_rss_to_qid(bp, 1380 vnic->rss_table[i * 2]); 1381 else 1382 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 1383 1384 if (qid == INVALID_HW_RING_ID) { 1385 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 1386 return -EINVAL; 1387 } 1388 reta_conf[idx].reta[sft] = qid; 1389 } 1390 } 1391 1392 return 0; 1393 } 1394 1395 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 1396 struct rte_eth_rss_conf *rss_conf) 1397 { 1398 struct bnxt *bp = eth_dev->data->dev_private; 1399 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1400 struct bnxt_vnic_info *vnic; 1401 int rc; 1402 1403 rc = is_bnxt_in_error(bp); 1404 if (rc) 1405 return rc; 1406 1407 /* 1408 * If RSS enablement were different than dev_configure, 1409 * then return -EINVAL 1410 */ 1411 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 1412 if (!rss_conf->rss_hf) 1413 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 1414 } else { 1415 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 1416 return -EINVAL; 1417 } 1418 1419 bp->flags |= BNXT_FLAG_UPDATE_HASH; 1420 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf)); 1421 1422 /* Update the default RSS VNIC(s) */ 1423 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1424 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 1425 1426 /* 1427 * If hashkey is not specified, use the previously configured 1428 * hashkey 1429 */ 1430 if (!rss_conf->rss_key) 1431 goto rss_config; 1432 1433 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 1434 PMD_DRV_LOG(ERR, 1435 "Invalid hashkey length, should be 16 bytes\n"); 1436 return -EINVAL; 1437 } 1438 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 1439 1440 rss_config: 1441 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1442 return 0; 1443 } 1444 1445 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 1446 struct rte_eth_rss_conf *rss_conf) 1447 { 1448 struct bnxt *bp = eth_dev->data->dev_private; 1449 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1450 int len, rc; 1451 uint32_t hash_types; 1452 1453 rc = is_bnxt_in_error(bp); 1454 if (rc) 1455 return rc; 1456 1457 /* RSS configuration is the same for all VNICs */ 1458 if (vnic && vnic->rss_hash_key) { 1459 if (rss_conf->rss_key) { 1460 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 1461 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 1462 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 1463 } 1464 1465 hash_types = vnic->hash_type; 1466 rss_conf->rss_hf = 0; 1467 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 1468 rss_conf->rss_hf |= ETH_RSS_IPV4; 1469 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 1470 } 1471 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 1472 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 1473 hash_types &= 1474 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1475 } 1476 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 1477 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 1478 hash_types &= 1479 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1480 } 1481 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 1482 rss_conf->rss_hf |= ETH_RSS_IPV6; 1483 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1484 } 1485 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 1486 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 1487 hash_types &= 1488 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1489 } 1490 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 1491 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 1492 hash_types &= 1493 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1494 } 1495 if (hash_types) { 1496 PMD_DRV_LOG(ERR, 1497 "Unknwon RSS config from firmware (%08x), RSS disabled", 1498 vnic->hash_type); 1499 return -ENOTSUP; 1500 } 1501 } else { 1502 rss_conf->rss_hf = 0; 1503 } 1504 return 0; 1505 } 1506 1507 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 1508 struct rte_eth_fc_conf *fc_conf) 1509 { 1510 struct bnxt *bp = dev->data->dev_private; 1511 struct rte_eth_link link_info; 1512 int rc; 1513 1514 rc = is_bnxt_in_error(bp); 1515 if (rc) 1516 return rc; 1517 1518 rc = bnxt_get_hwrm_link_config(bp, &link_info); 1519 if (rc) 1520 return rc; 1521 1522 memset(fc_conf, 0, sizeof(*fc_conf)); 1523 if (bp->link_info.auto_pause) 1524 fc_conf->autoneg = 1; 1525 switch (bp->link_info.pause) { 1526 case 0: 1527 fc_conf->mode = RTE_FC_NONE; 1528 break; 1529 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 1530 fc_conf->mode = RTE_FC_TX_PAUSE; 1531 break; 1532 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 1533 fc_conf->mode = RTE_FC_RX_PAUSE; 1534 break; 1535 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 1536 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 1537 fc_conf->mode = RTE_FC_FULL; 1538 break; 1539 } 1540 return 0; 1541 } 1542 1543 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 1544 struct rte_eth_fc_conf *fc_conf) 1545 { 1546 struct bnxt *bp = dev->data->dev_private; 1547 int rc; 1548 1549 rc = is_bnxt_in_error(bp); 1550 if (rc) 1551 return rc; 1552 1553 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1554 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 1555 return -ENOTSUP; 1556 } 1557 1558 switch (fc_conf->mode) { 1559 case RTE_FC_NONE: 1560 bp->link_info.auto_pause = 0; 1561 bp->link_info.force_pause = 0; 1562 break; 1563 case RTE_FC_RX_PAUSE: 1564 if (fc_conf->autoneg) { 1565 bp->link_info.auto_pause = 1566 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1567 bp->link_info.force_pause = 0; 1568 } else { 1569 bp->link_info.auto_pause = 0; 1570 bp->link_info.force_pause = 1571 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1572 } 1573 break; 1574 case RTE_FC_TX_PAUSE: 1575 if (fc_conf->autoneg) { 1576 bp->link_info.auto_pause = 1577 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 1578 bp->link_info.force_pause = 0; 1579 } else { 1580 bp->link_info.auto_pause = 0; 1581 bp->link_info.force_pause = 1582 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 1583 } 1584 break; 1585 case RTE_FC_FULL: 1586 if (fc_conf->autoneg) { 1587 bp->link_info.auto_pause = 1588 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 1589 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1590 bp->link_info.force_pause = 0; 1591 } else { 1592 bp->link_info.auto_pause = 0; 1593 bp->link_info.force_pause = 1594 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 1595 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1596 } 1597 break; 1598 } 1599 return bnxt_set_hwrm_link_config(bp, true); 1600 } 1601 1602 /* Add UDP tunneling port */ 1603 static int 1604 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 1605 struct rte_eth_udp_tunnel *udp_tunnel) 1606 { 1607 struct bnxt *bp = eth_dev->data->dev_private; 1608 uint16_t tunnel_type = 0; 1609 int rc = 0; 1610 1611 rc = is_bnxt_in_error(bp); 1612 if (rc) 1613 return rc; 1614 1615 switch (udp_tunnel->prot_type) { 1616 case RTE_TUNNEL_TYPE_VXLAN: 1617 if (bp->vxlan_port_cnt) { 1618 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1619 udp_tunnel->udp_port); 1620 if (bp->vxlan_port != udp_tunnel->udp_port) { 1621 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1622 return -ENOSPC; 1623 } 1624 bp->vxlan_port_cnt++; 1625 return 0; 1626 } 1627 tunnel_type = 1628 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 1629 bp->vxlan_port_cnt++; 1630 break; 1631 case RTE_TUNNEL_TYPE_GENEVE: 1632 if (bp->geneve_port_cnt) { 1633 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1634 udp_tunnel->udp_port); 1635 if (bp->geneve_port != udp_tunnel->udp_port) { 1636 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1637 return -ENOSPC; 1638 } 1639 bp->geneve_port_cnt++; 1640 return 0; 1641 } 1642 tunnel_type = 1643 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 1644 bp->geneve_port_cnt++; 1645 break; 1646 default: 1647 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1648 return -ENOTSUP; 1649 } 1650 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 1651 tunnel_type); 1652 return rc; 1653 } 1654 1655 static int 1656 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 1657 struct rte_eth_udp_tunnel *udp_tunnel) 1658 { 1659 struct bnxt *bp = eth_dev->data->dev_private; 1660 uint16_t tunnel_type = 0; 1661 uint16_t port = 0; 1662 int rc = 0; 1663 1664 rc = is_bnxt_in_error(bp); 1665 if (rc) 1666 return rc; 1667 1668 switch (udp_tunnel->prot_type) { 1669 case RTE_TUNNEL_TYPE_VXLAN: 1670 if (!bp->vxlan_port_cnt) { 1671 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1672 return -EINVAL; 1673 } 1674 if (bp->vxlan_port != udp_tunnel->udp_port) { 1675 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1676 udp_tunnel->udp_port, bp->vxlan_port); 1677 return -EINVAL; 1678 } 1679 if (--bp->vxlan_port_cnt) 1680 return 0; 1681 1682 tunnel_type = 1683 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 1684 port = bp->vxlan_fw_dst_port_id; 1685 break; 1686 case RTE_TUNNEL_TYPE_GENEVE: 1687 if (!bp->geneve_port_cnt) { 1688 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1689 return -EINVAL; 1690 } 1691 if (bp->geneve_port != udp_tunnel->udp_port) { 1692 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1693 udp_tunnel->udp_port, bp->geneve_port); 1694 return -EINVAL; 1695 } 1696 if (--bp->geneve_port_cnt) 1697 return 0; 1698 1699 tunnel_type = 1700 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 1701 port = bp->geneve_fw_dst_port_id; 1702 break; 1703 default: 1704 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1705 return -ENOTSUP; 1706 } 1707 1708 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 1709 if (!rc) { 1710 if (tunnel_type == 1711 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) 1712 bp->vxlan_port = 0; 1713 if (tunnel_type == 1714 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) 1715 bp->geneve_port = 0; 1716 } 1717 return rc; 1718 } 1719 1720 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1721 { 1722 struct bnxt_filter_info *filter; 1723 struct bnxt_vnic_info *vnic; 1724 int rc = 0; 1725 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 1726 1727 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1728 filter = STAILQ_FIRST(&vnic->filter); 1729 while (filter) { 1730 /* Search for this matching MAC+VLAN filter */ 1731 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 1732 /* Delete the filter */ 1733 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 1734 if (rc) 1735 return rc; 1736 STAILQ_REMOVE(&vnic->filter, filter, 1737 bnxt_filter_info, next); 1738 bnxt_free_filter(bp, filter); 1739 PMD_DRV_LOG(INFO, 1740 "Deleted vlan filter for %d\n", 1741 vlan_id); 1742 return 0; 1743 } 1744 filter = STAILQ_NEXT(filter, next); 1745 } 1746 return -ENOENT; 1747 } 1748 1749 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1750 { 1751 struct bnxt_filter_info *filter; 1752 struct bnxt_vnic_info *vnic; 1753 int rc = 0; 1754 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 1755 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 1756 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 1757 1758 /* Implementation notes on the use of VNIC in this command: 1759 * 1760 * By default, these filters belong to default vnic for the function. 1761 * Once these filters are set up, only destination VNIC can be modified. 1762 * If the destination VNIC is not specified in this command, 1763 * then the HWRM shall only create an l2 context id. 1764 */ 1765 1766 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1767 filter = STAILQ_FIRST(&vnic->filter); 1768 /* Check if the VLAN has already been added */ 1769 while (filter) { 1770 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 1771 return -EEXIST; 1772 1773 filter = STAILQ_NEXT(filter, next); 1774 } 1775 1776 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 1777 * command to create MAC+VLAN filter with the right flags, enables set. 1778 */ 1779 filter = bnxt_alloc_filter(bp); 1780 if (!filter) { 1781 PMD_DRV_LOG(ERR, 1782 "MAC/VLAN filter alloc failed\n"); 1783 return -ENOMEM; 1784 } 1785 /* MAC + VLAN ID filter */ 1786 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 1787 * untagged packets are received 1788 * 1789 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 1790 * packets and only the programmed vlan's packets are received 1791 */ 1792 filter->l2_ivlan = vlan_id; 1793 filter->l2_ivlan_mask = 0x0FFF; 1794 filter->enables |= en; 1795 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1796 1797 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1798 if (rc) { 1799 /* Free the newly allocated filter as we were 1800 * not able to create the filter in hardware. 1801 */ 1802 bnxt_free_filter(bp, filter); 1803 return rc; 1804 } 1805 1806 filter->mac_index = 0; 1807 /* Add this new filter to the list */ 1808 if (vlan_id == 0) 1809 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1810 else 1811 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1812 1813 PMD_DRV_LOG(INFO, 1814 "Added Vlan filter for %d\n", vlan_id); 1815 return rc; 1816 } 1817 1818 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 1819 uint16_t vlan_id, int on) 1820 { 1821 struct bnxt *bp = eth_dev->data->dev_private; 1822 int rc; 1823 1824 rc = is_bnxt_in_error(bp); 1825 if (rc) 1826 return rc; 1827 1828 /* These operations apply to ALL existing MAC/VLAN filters */ 1829 if (on) 1830 return bnxt_add_vlan_filter(bp, vlan_id); 1831 else 1832 return bnxt_del_vlan_filter(bp, vlan_id); 1833 } 1834 1835 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 1836 struct bnxt_vnic_info *vnic) 1837 { 1838 struct bnxt_filter_info *filter; 1839 int rc; 1840 1841 filter = STAILQ_FIRST(&vnic->filter); 1842 while (filter) { 1843 if (filter->mac_index == 0 && 1844 !memcmp(filter->l2_addr, bp->mac_addr, 1845 RTE_ETHER_ADDR_LEN)) { 1846 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 1847 if (!rc) { 1848 STAILQ_REMOVE(&vnic->filter, filter, 1849 bnxt_filter_info, next); 1850 bnxt_free_filter(bp, filter); 1851 } 1852 return rc; 1853 } 1854 filter = STAILQ_NEXT(filter, next); 1855 } 1856 return 0; 1857 } 1858 1859 static int 1860 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 1861 { 1862 struct bnxt *bp = dev->data->dev_private; 1863 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1864 struct bnxt_vnic_info *vnic; 1865 unsigned int i; 1866 int rc; 1867 1868 rc = is_bnxt_in_error(bp); 1869 if (rc) 1870 return rc; 1871 1872 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1873 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 1874 /* Remove any VLAN filters programmed */ 1875 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 1876 bnxt_del_vlan_filter(bp, i); 1877 1878 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 1879 if (rc) 1880 return rc; 1881 } else { 1882 /* Default filter will allow packets that match the 1883 * dest mac. So, it has to be deleted, otherwise, we 1884 * will endup receiving vlan packets for which the 1885 * filter is not programmed, when hw-vlan-filter 1886 * configuration is ON 1887 */ 1888 bnxt_del_dflt_mac_filter(bp, vnic); 1889 /* This filter will allow only untagged packets */ 1890 bnxt_add_vlan_filter(bp, 0); 1891 } 1892 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 1893 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 1894 1895 if (mask & ETH_VLAN_STRIP_MASK) { 1896 /* Enable or disable VLAN stripping */ 1897 for (i = 0; i < bp->nr_vnics; i++) { 1898 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1899 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1900 vnic->vlan_strip = true; 1901 else 1902 vnic->vlan_strip = false; 1903 bnxt_hwrm_vnic_cfg(bp, vnic); 1904 } 1905 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 1906 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 1907 } 1908 1909 if (mask & ETH_VLAN_EXTEND_MASK) { 1910 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 1911 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 1912 else 1913 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 1914 } 1915 1916 return 0; 1917 } 1918 1919 static int 1920 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 1921 uint16_t tpid) 1922 { 1923 struct bnxt *bp = dev->data->dev_private; 1924 int qinq = dev->data->dev_conf.rxmode.offloads & 1925 DEV_RX_OFFLOAD_VLAN_EXTEND; 1926 1927 if (vlan_type != ETH_VLAN_TYPE_INNER && 1928 vlan_type != ETH_VLAN_TYPE_OUTER) { 1929 PMD_DRV_LOG(ERR, 1930 "Unsupported vlan type."); 1931 return -EINVAL; 1932 } 1933 if (!qinq) { 1934 PMD_DRV_LOG(ERR, 1935 "QinQ not enabled. Needs to be ON as we can " 1936 "accelerate only outer vlan\n"); 1937 return -EINVAL; 1938 } 1939 1940 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 1941 switch (tpid) { 1942 case RTE_ETHER_TYPE_QINQ: 1943 bp->outer_tpid_bd = 1944 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 1945 break; 1946 case RTE_ETHER_TYPE_VLAN: 1947 bp->outer_tpid_bd = 1948 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 1949 break; 1950 case 0x9100: 1951 bp->outer_tpid_bd = 1952 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 1953 break; 1954 case 0x9200: 1955 bp->outer_tpid_bd = 1956 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 1957 break; 1958 case 0x9300: 1959 bp->outer_tpid_bd = 1960 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 1961 break; 1962 default: 1963 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 1964 return -EINVAL; 1965 } 1966 bp->outer_tpid_bd |= tpid; 1967 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 1968 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 1969 PMD_DRV_LOG(ERR, 1970 "Can accelerate only outer vlan in QinQ\n"); 1971 return -EINVAL; 1972 } 1973 1974 return 0; 1975 } 1976 1977 static int 1978 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 1979 struct rte_ether_addr *addr) 1980 { 1981 struct bnxt *bp = dev->data->dev_private; 1982 /* Default Filter is tied to VNIC 0 */ 1983 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1984 struct bnxt_filter_info *filter; 1985 int rc; 1986 1987 rc = is_bnxt_in_error(bp); 1988 if (rc) 1989 return rc; 1990 1991 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 1992 return -EPERM; 1993 1994 if (rte_is_zero_ether_addr(addr)) 1995 return -EINVAL; 1996 1997 STAILQ_FOREACH(filter, &vnic->filter, next) { 1998 /* Default Filter is at Index 0 */ 1999 if (filter->mac_index != 0) 2000 continue; 2001 2002 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN); 2003 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN); 2004 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX | 2005 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2006 filter->enables |= 2007 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR | 2008 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK; 2009 2010 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2011 if (rc) { 2012 memcpy(filter->l2_addr, bp->mac_addr, 2013 RTE_ETHER_ADDR_LEN); 2014 return rc; 2015 } 2016 2017 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2018 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2019 return 0; 2020 } 2021 2022 return 0; 2023 } 2024 2025 static int 2026 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2027 struct rte_ether_addr *mc_addr_set, 2028 uint32_t nb_mc_addr) 2029 { 2030 struct bnxt *bp = eth_dev->data->dev_private; 2031 char *mc_addr_list = (char *)mc_addr_set; 2032 struct bnxt_vnic_info *vnic; 2033 uint32_t off = 0, i = 0; 2034 int rc; 2035 2036 rc = is_bnxt_in_error(bp); 2037 if (rc) 2038 return rc; 2039 2040 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2041 2042 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2043 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2044 goto allmulti; 2045 } 2046 2047 /* TODO Check for Duplicate mcast addresses */ 2048 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2049 for (i = 0; i < nb_mc_addr; i++) { 2050 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2051 RTE_ETHER_ADDR_LEN); 2052 off += RTE_ETHER_ADDR_LEN; 2053 } 2054 2055 vnic->mc_addr_cnt = i; 2056 if (vnic->mc_addr_cnt) 2057 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2058 else 2059 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2060 2061 allmulti: 2062 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2063 } 2064 2065 static int 2066 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2067 { 2068 struct bnxt *bp = dev->data->dev_private; 2069 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2070 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2071 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2072 int ret; 2073 2074 ret = snprintf(fw_version, fw_size, "%d.%d.%d", 2075 fw_major, fw_minor, fw_updt); 2076 2077 ret += 1; /* add the size of '\0' */ 2078 if (fw_size < (uint32_t)ret) 2079 return ret; 2080 else 2081 return 0; 2082 } 2083 2084 static void 2085 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2086 struct rte_eth_rxq_info *qinfo) 2087 { 2088 struct bnxt *bp = dev->data->dev_private; 2089 struct bnxt_rx_queue *rxq; 2090 2091 if (is_bnxt_in_error(bp)) 2092 return; 2093 2094 rxq = dev->data->rx_queues[queue_id]; 2095 2096 qinfo->mp = rxq->mb_pool; 2097 qinfo->scattered_rx = dev->data->scattered_rx; 2098 qinfo->nb_desc = rxq->nb_rx_desc; 2099 2100 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2101 qinfo->conf.rx_drop_en = 0; 2102 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2103 } 2104 2105 static void 2106 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2107 struct rte_eth_txq_info *qinfo) 2108 { 2109 struct bnxt *bp = dev->data->dev_private; 2110 struct bnxt_tx_queue *txq; 2111 2112 if (is_bnxt_in_error(bp)) 2113 return; 2114 2115 txq = dev->data->tx_queues[queue_id]; 2116 2117 qinfo->nb_desc = txq->nb_tx_desc; 2118 2119 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2120 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2121 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2122 2123 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2124 qinfo->conf.tx_rs_thresh = 0; 2125 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2126 } 2127 2128 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 2129 { 2130 struct bnxt *bp = eth_dev->data->dev_private; 2131 uint32_t new_pkt_size; 2132 uint32_t rc = 0; 2133 uint32_t i; 2134 2135 rc = is_bnxt_in_error(bp); 2136 if (rc) 2137 return rc; 2138 2139 /* Exit if receive queues are not configured yet */ 2140 if (!eth_dev->data->nb_rx_queues) 2141 return rc; 2142 2143 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 2144 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 2145 2146 #ifdef RTE_ARCH_X86 2147 /* 2148 * If vector-mode tx/rx is active, disallow any MTU change that would 2149 * require scattered receive support. 2150 */ 2151 if (eth_dev->data->dev_started && 2152 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec || 2153 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) && 2154 (new_pkt_size > 2155 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 2156 PMD_DRV_LOG(ERR, 2157 "MTU change would require scattered rx support. "); 2158 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 2159 return -EINVAL; 2160 } 2161 #endif 2162 2163 if (new_mtu > RTE_ETHER_MTU) { 2164 bp->flags |= BNXT_FLAG_JUMBO; 2165 bp->eth_dev->data->dev_conf.rxmode.offloads |= 2166 DEV_RX_OFFLOAD_JUMBO_FRAME; 2167 } else { 2168 bp->eth_dev->data->dev_conf.rxmode.offloads &= 2169 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2170 bp->flags &= ~BNXT_FLAG_JUMBO; 2171 } 2172 2173 /* Is there a change in mtu setting? */ 2174 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) 2175 return rc; 2176 2177 for (i = 0; i < bp->nr_vnics; i++) { 2178 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2179 uint16_t size = 0; 2180 2181 vnic->mru = BNXT_VNIC_MRU(new_mtu); 2182 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 2183 if (rc) 2184 break; 2185 2186 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 2187 size -= RTE_PKTMBUF_HEADROOM; 2188 2189 if (size < new_mtu) { 2190 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 2191 if (rc) 2192 return rc; 2193 } 2194 } 2195 2196 if (!rc) 2197 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 2198 2199 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 2200 2201 return rc; 2202 } 2203 2204 static int 2205 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 2206 { 2207 struct bnxt *bp = dev->data->dev_private; 2208 uint16_t vlan = bp->vlan; 2209 int rc; 2210 2211 rc = is_bnxt_in_error(bp); 2212 if (rc) 2213 return rc; 2214 2215 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2216 PMD_DRV_LOG(ERR, 2217 "PVID cannot be modified for this function\n"); 2218 return -ENOTSUP; 2219 } 2220 bp->vlan = on ? pvid : 0; 2221 2222 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 2223 if (rc) 2224 bp->vlan = vlan; 2225 return rc; 2226 } 2227 2228 static int 2229 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 2230 { 2231 struct bnxt *bp = dev->data->dev_private; 2232 int rc; 2233 2234 rc = is_bnxt_in_error(bp); 2235 if (rc) 2236 return rc; 2237 2238 return bnxt_hwrm_port_led_cfg(bp, true); 2239 } 2240 2241 static int 2242 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 2243 { 2244 struct bnxt *bp = dev->data->dev_private; 2245 int rc; 2246 2247 rc = is_bnxt_in_error(bp); 2248 if (rc) 2249 return rc; 2250 2251 return bnxt_hwrm_port_led_cfg(bp, false); 2252 } 2253 2254 static uint32_t 2255 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 2256 { 2257 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2258 uint32_t desc = 0, raw_cons = 0, cons; 2259 struct bnxt_cp_ring_info *cpr; 2260 struct bnxt_rx_queue *rxq; 2261 struct rx_pkt_cmpl *rxcmp; 2262 int rc; 2263 2264 rc = is_bnxt_in_error(bp); 2265 if (rc) 2266 return rc; 2267 2268 rxq = dev->data->rx_queues[rx_queue_id]; 2269 cpr = rxq->cp_ring; 2270 raw_cons = cpr->cp_raw_cons; 2271 2272 while (1) { 2273 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 2274 rte_prefetch0(&cpr->cp_desc_ring[cons]); 2275 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2276 2277 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) { 2278 break; 2279 } else { 2280 raw_cons++; 2281 desc++; 2282 } 2283 } 2284 2285 return desc; 2286 } 2287 2288 static int 2289 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 2290 { 2291 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 2292 struct bnxt_rx_ring_info *rxr; 2293 struct bnxt_cp_ring_info *cpr; 2294 struct bnxt_sw_rx_bd *rx_buf; 2295 struct rx_pkt_cmpl *rxcmp; 2296 uint32_t cons, cp_cons; 2297 int rc; 2298 2299 if (!rxq) 2300 return -EINVAL; 2301 2302 rc = is_bnxt_in_error(rxq->bp); 2303 if (rc) 2304 return rc; 2305 2306 cpr = rxq->cp_ring; 2307 rxr = rxq->rx_ring; 2308 2309 if (offset >= rxq->nb_rx_desc) 2310 return -EINVAL; 2311 2312 cons = RING_CMP(cpr->cp_ring_struct, offset); 2313 cp_cons = cpr->cp_raw_cons; 2314 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2315 2316 if (cons > cp_cons) { 2317 if (CMPL_VALID(rxcmp, cpr->valid)) 2318 return RTE_ETH_RX_DESC_DONE; 2319 } else { 2320 if (CMPL_VALID(rxcmp, !cpr->valid)) 2321 return RTE_ETH_RX_DESC_DONE; 2322 } 2323 rx_buf = &rxr->rx_buf_ring[cons]; 2324 if (rx_buf->mbuf == NULL) 2325 return RTE_ETH_RX_DESC_UNAVAIL; 2326 2327 2328 return RTE_ETH_RX_DESC_AVAIL; 2329 } 2330 2331 static int 2332 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 2333 { 2334 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 2335 struct bnxt_tx_ring_info *txr; 2336 struct bnxt_cp_ring_info *cpr; 2337 struct bnxt_sw_tx_bd *tx_buf; 2338 struct tx_pkt_cmpl *txcmp; 2339 uint32_t cons, cp_cons; 2340 int rc; 2341 2342 if (!txq) 2343 return -EINVAL; 2344 2345 rc = is_bnxt_in_error(txq->bp); 2346 if (rc) 2347 return rc; 2348 2349 cpr = txq->cp_ring; 2350 txr = txq->tx_ring; 2351 2352 if (offset >= txq->nb_tx_desc) 2353 return -EINVAL; 2354 2355 cons = RING_CMP(cpr->cp_ring_struct, offset); 2356 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2357 cp_cons = cpr->cp_raw_cons; 2358 2359 if (cons > cp_cons) { 2360 if (CMPL_VALID(txcmp, cpr->valid)) 2361 return RTE_ETH_TX_DESC_UNAVAIL; 2362 } else { 2363 if (CMPL_VALID(txcmp, !cpr->valid)) 2364 return RTE_ETH_TX_DESC_UNAVAIL; 2365 } 2366 tx_buf = &txr->tx_buf_ring[cons]; 2367 if (tx_buf->mbuf == NULL) 2368 return RTE_ETH_TX_DESC_DONE; 2369 2370 return RTE_ETH_TX_DESC_FULL; 2371 } 2372 2373 static struct bnxt_filter_info * 2374 bnxt_match_and_validate_ether_filter(struct bnxt *bp, 2375 struct rte_eth_ethertype_filter *efilter, 2376 struct bnxt_vnic_info *vnic0, 2377 struct bnxt_vnic_info *vnic, 2378 int *ret) 2379 { 2380 struct bnxt_filter_info *mfilter = NULL; 2381 int match = 0; 2382 *ret = 0; 2383 2384 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 || 2385 efilter->ether_type == RTE_ETHER_TYPE_IPV6) { 2386 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in" 2387 " ethertype filter.", efilter->ether_type); 2388 *ret = -EINVAL; 2389 goto exit; 2390 } 2391 if (efilter->queue >= bp->rx_nr_rings) { 2392 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2393 *ret = -EINVAL; 2394 goto exit; 2395 } 2396 2397 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 2398 vnic = &bp->vnic_info[efilter->queue]; 2399 if (vnic == NULL) { 2400 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2401 *ret = -EINVAL; 2402 goto exit; 2403 } 2404 2405 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2406 STAILQ_FOREACH(mfilter, &vnic0->filter, next) { 2407 if ((!memcmp(efilter->mac_addr.addr_bytes, 2408 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2409 mfilter->flags == 2410 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP && 2411 mfilter->ethertype == efilter->ether_type)) { 2412 match = 1; 2413 break; 2414 } 2415 } 2416 } else { 2417 STAILQ_FOREACH(mfilter, &vnic->filter, next) 2418 if ((!memcmp(efilter->mac_addr.addr_bytes, 2419 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2420 mfilter->ethertype == efilter->ether_type && 2421 mfilter->flags == 2422 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) { 2423 match = 1; 2424 break; 2425 } 2426 } 2427 2428 if (match) 2429 *ret = -EEXIST; 2430 2431 exit: 2432 return mfilter; 2433 } 2434 2435 static int 2436 bnxt_ethertype_filter(struct rte_eth_dev *dev, 2437 enum rte_filter_op filter_op, 2438 void *arg) 2439 { 2440 struct bnxt *bp = dev->data->dev_private; 2441 struct rte_eth_ethertype_filter *efilter = 2442 (struct rte_eth_ethertype_filter *)arg; 2443 struct bnxt_filter_info *bfilter, *filter1; 2444 struct bnxt_vnic_info *vnic, *vnic0; 2445 int ret; 2446 2447 if (filter_op == RTE_ETH_FILTER_NOP) 2448 return 0; 2449 2450 if (arg == NULL) { 2451 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2452 filter_op); 2453 return -EINVAL; 2454 } 2455 2456 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 2457 vnic = &bp->vnic_info[efilter->queue]; 2458 2459 switch (filter_op) { 2460 case RTE_ETH_FILTER_ADD: 2461 bnxt_match_and_validate_ether_filter(bp, efilter, 2462 vnic0, vnic, &ret); 2463 if (ret < 0) 2464 return ret; 2465 2466 bfilter = bnxt_get_unused_filter(bp); 2467 if (bfilter == NULL) { 2468 PMD_DRV_LOG(ERR, 2469 "Not enough resources for a new filter.\n"); 2470 return -ENOMEM; 2471 } 2472 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2473 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes, 2474 RTE_ETHER_ADDR_LEN); 2475 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes, 2476 RTE_ETHER_ADDR_LEN); 2477 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2478 bfilter->ethertype = efilter->ether_type; 2479 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2480 2481 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0); 2482 if (filter1 == NULL) { 2483 ret = -EINVAL; 2484 goto cleanup; 2485 } 2486 bfilter->enables |= 2487 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2488 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2489 2490 bfilter->dst_id = vnic->fw_vnic_id; 2491 2492 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2493 bfilter->flags = 2494 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2495 } 2496 2497 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2498 if (ret) 2499 goto cleanup; 2500 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2501 break; 2502 case RTE_ETH_FILTER_DELETE: 2503 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter, 2504 vnic0, vnic, &ret); 2505 if (ret == -EEXIST) { 2506 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1); 2507 2508 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info, 2509 next); 2510 bnxt_free_filter(bp, filter1); 2511 } else if (ret == 0) { 2512 PMD_DRV_LOG(ERR, "No matching filter found\n"); 2513 } 2514 break; 2515 default: 2516 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2517 ret = -EINVAL; 2518 goto error; 2519 } 2520 return ret; 2521 cleanup: 2522 bnxt_free_filter(bp, bfilter); 2523 error: 2524 return ret; 2525 } 2526 2527 static inline int 2528 parse_ntuple_filter(struct bnxt *bp, 2529 struct rte_eth_ntuple_filter *nfilter, 2530 struct bnxt_filter_info *bfilter) 2531 { 2532 uint32_t en = 0; 2533 2534 if (nfilter->queue >= bp->rx_nr_rings) { 2535 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue); 2536 return -EINVAL; 2537 } 2538 2539 switch (nfilter->dst_port_mask) { 2540 case UINT16_MAX: 2541 bfilter->dst_port_mask = -1; 2542 bfilter->dst_port = nfilter->dst_port; 2543 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT | 2544 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2545 break; 2546 default: 2547 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 2548 return -EINVAL; 2549 } 2550 2551 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2552 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2553 2554 switch (nfilter->proto_mask) { 2555 case UINT8_MAX: 2556 if (nfilter->proto == 17) /* IPPROTO_UDP */ 2557 bfilter->ip_protocol = 17; 2558 else if (nfilter->proto == 6) /* IPPROTO_TCP */ 2559 bfilter->ip_protocol = 6; 2560 else 2561 return -EINVAL; 2562 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2563 break; 2564 default: 2565 PMD_DRV_LOG(ERR, "invalid protocol mask."); 2566 return -EINVAL; 2567 } 2568 2569 switch (nfilter->dst_ip_mask) { 2570 case UINT32_MAX: 2571 bfilter->dst_ipaddr_mask[0] = -1; 2572 bfilter->dst_ipaddr[0] = nfilter->dst_ip; 2573 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR | 2574 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2575 break; 2576 default: 2577 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 2578 return -EINVAL; 2579 } 2580 2581 switch (nfilter->src_ip_mask) { 2582 case UINT32_MAX: 2583 bfilter->src_ipaddr_mask[0] = -1; 2584 bfilter->src_ipaddr[0] = nfilter->src_ip; 2585 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR | 2586 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2587 break; 2588 default: 2589 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 2590 return -EINVAL; 2591 } 2592 2593 switch (nfilter->src_port_mask) { 2594 case UINT16_MAX: 2595 bfilter->src_port_mask = -1; 2596 bfilter->src_port = nfilter->src_port; 2597 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT | 2598 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2599 break; 2600 default: 2601 PMD_DRV_LOG(ERR, "invalid src_port mask."); 2602 return -EINVAL; 2603 } 2604 2605 bfilter->enables = en; 2606 return 0; 2607 } 2608 2609 static struct bnxt_filter_info* 2610 bnxt_match_ntuple_filter(struct bnxt *bp, 2611 struct bnxt_filter_info *bfilter, 2612 struct bnxt_vnic_info **mvnic) 2613 { 2614 struct bnxt_filter_info *mfilter = NULL; 2615 int i; 2616 2617 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2618 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2619 STAILQ_FOREACH(mfilter, &vnic->filter, next) { 2620 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] && 2621 bfilter->src_ipaddr_mask[0] == 2622 mfilter->src_ipaddr_mask[0] && 2623 bfilter->src_port == mfilter->src_port && 2624 bfilter->src_port_mask == mfilter->src_port_mask && 2625 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] && 2626 bfilter->dst_ipaddr_mask[0] == 2627 mfilter->dst_ipaddr_mask[0] && 2628 bfilter->dst_port == mfilter->dst_port && 2629 bfilter->dst_port_mask == mfilter->dst_port_mask && 2630 bfilter->flags == mfilter->flags && 2631 bfilter->enables == mfilter->enables) { 2632 if (mvnic) 2633 *mvnic = vnic; 2634 return mfilter; 2635 } 2636 } 2637 } 2638 return NULL; 2639 } 2640 2641 static int 2642 bnxt_cfg_ntuple_filter(struct bnxt *bp, 2643 struct rte_eth_ntuple_filter *nfilter, 2644 enum rte_filter_op filter_op) 2645 { 2646 struct bnxt_filter_info *bfilter, *mfilter, *filter1; 2647 struct bnxt_vnic_info *vnic, *vnic0, *mvnic; 2648 int ret; 2649 2650 if (nfilter->flags != RTE_5TUPLE_FLAGS) { 2651 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 2652 return -EINVAL; 2653 } 2654 2655 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) { 2656 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n"); 2657 return -EINVAL; 2658 } 2659 2660 bfilter = bnxt_get_unused_filter(bp); 2661 if (bfilter == NULL) { 2662 PMD_DRV_LOG(ERR, 2663 "Not enough resources for a new filter.\n"); 2664 return -ENOMEM; 2665 } 2666 ret = parse_ntuple_filter(bp, nfilter, bfilter); 2667 if (ret < 0) 2668 goto free_filter; 2669 2670 vnic = &bp->vnic_info[nfilter->queue]; 2671 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 2672 filter1 = STAILQ_FIRST(&vnic0->filter); 2673 if (filter1 == NULL) { 2674 ret = -EINVAL; 2675 goto free_filter; 2676 } 2677 2678 bfilter->dst_id = vnic->fw_vnic_id; 2679 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2680 bfilter->enables |= 2681 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2682 bfilter->ethertype = 0x800; 2683 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2684 2685 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic); 2686 2687 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2688 bfilter->dst_id == mfilter->dst_id) { 2689 PMD_DRV_LOG(ERR, "filter exists.\n"); 2690 ret = -EEXIST; 2691 goto free_filter; 2692 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2693 bfilter->dst_id != mfilter->dst_id) { 2694 mfilter->dst_id = vnic->fw_vnic_id; 2695 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter); 2696 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next); 2697 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next); 2698 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n"); 2699 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n"); 2700 goto free_filter; 2701 } 2702 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2703 PMD_DRV_LOG(ERR, "filter doesn't exist."); 2704 ret = -ENOENT; 2705 goto free_filter; 2706 } 2707 2708 if (filter_op == RTE_ETH_FILTER_ADD) { 2709 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2710 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2711 if (ret) 2712 goto free_filter; 2713 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2714 } else { 2715 if (mfilter == NULL) { 2716 /* This should not happen. But for Coverity! */ 2717 ret = -ENOENT; 2718 goto free_filter; 2719 } 2720 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter); 2721 2722 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next); 2723 bnxt_free_filter(bp, mfilter); 2724 bnxt_free_filter(bp, bfilter); 2725 } 2726 2727 return 0; 2728 free_filter: 2729 bnxt_free_filter(bp, bfilter); 2730 return ret; 2731 } 2732 2733 static int 2734 bnxt_ntuple_filter(struct rte_eth_dev *dev, 2735 enum rte_filter_op filter_op, 2736 void *arg) 2737 { 2738 struct bnxt *bp = dev->data->dev_private; 2739 int ret; 2740 2741 if (filter_op == RTE_ETH_FILTER_NOP) 2742 return 0; 2743 2744 if (arg == NULL) { 2745 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2746 filter_op); 2747 return -EINVAL; 2748 } 2749 2750 switch (filter_op) { 2751 case RTE_ETH_FILTER_ADD: 2752 ret = bnxt_cfg_ntuple_filter(bp, 2753 (struct rte_eth_ntuple_filter *)arg, 2754 filter_op); 2755 break; 2756 case RTE_ETH_FILTER_DELETE: 2757 ret = bnxt_cfg_ntuple_filter(bp, 2758 (struct rte_eth_ntuple_filter *)arg, 2759 filter_op); 2760 break; 2761 default: 2762 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2763 ret = -EINVAL; 2764 break; 2765 } 2766 return ret; 2767 } 2768 2769 static int 2770 bnxt_parse_fdir_filter(struct bnxt *bp, 2771 struct rte_eth_fdir_filter *fdir, 2772 struct bnxt_filter_info *filter) 2773 { 2774 enum rte_fdir_mode fdir_mode = 2775 bp->eth_dev->data->dev_conf.fdir_conf.mode; 2776 struct bnxt_vnic_info *vnic0, *vnic; 2777 struct bnxt_filter_info *filter1; 2778 uint32_t en = 0; 2779 int i; 2780 2781 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 2782 return -EINVAL; 2783 2784 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci; 2785 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID; 2786 2787 switch (fdir->input.flow_type) { 2788 case RTE_ETH_FLOW_IPV4: 2789 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 2790 /* FALLTHROUGH */ 2791 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip; 2792 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2793 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip; 2794 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2795 filter->ip_protocol = fdir->input.flow.ip4_flow.proto; 2796 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2797 filter->ip_addr_type = 2798 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2799 filter->src_ipaddr_mask[0] = 0xffffffff; 2800 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2801 filter->dst_ipaddr_mask[0] = 0xffffffff; 2802 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2803 filter->ethertype = 0x800; 2804 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2805 break; 2806 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 2807 filter->src_port = fdir->input.flow.tcp4_flow.src_port; 2808 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2809 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port; 2810 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2811 filter->dst_port_mask = 0xffff; 2812 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2813 filter->src_port_mask = 0xffff; 2814 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2815 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip; 2816 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2817 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip; 2818 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2819 filter->ip_protocol = 6; 2820 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2821 filter->ip_addr_type = 2822 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2823 filter->src_ipaddr_mask[0] = 0xffffffff; 2824 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2825 filter->dst_ipaddr_mask[0] = 0xffffffff; 2826 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2827 filter->ethertype = 0x800; 2828 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2829 break; 2830 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 2831 filter->src_port = fdir->input.flow.udp4_flow.src_port; 2832 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2833 filter->dst_port = fdir->input.flow.udp4_flow.dst_port; 2834 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2835 filter->dst_port_mask = 0xffff; 2836 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2837 filter->src_port_mask = 0xffff; 2838 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2839 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip; 2840 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2841 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip; 2842 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2843 filter->ip_protocol = 17; 2844 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2845 filter->ip_addr_type = 2846 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2847 filter->src_ipaddr_mask[0] = 0xffffffff; 2848 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2849 filter->dst_ipaddr_mask[0] = 0xffffffff; 2850 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2851 filter->ethertype = 0x800; 2852 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2853 break; 2854 case RTE_ETH_FLOW_IPV6: 2855 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 2856 /* FALLTHROUGH */ 2857 filter->ip_addr_type = 2858 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2859 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto; 2860 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2861 rte_memcpy(filter->src_ipaddr, 2862 fdir->input.flow.ipv6_flow.src_ip, 16); 2863 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2864 rte_memcpy(filter->dst_ipaddr, 2865 fdir->input.flow.ipv6_flow.dst_ip, 16); 2866 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2867 memset(filter->dst_ipaddr_mask, 0xff, 16); 2868 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2869 memset(filter->src_ipaddr_mask, 0xff, 16); 2870 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2871 filter->ethertype = 0x86dd; 2872 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2873 break; 2874 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 2875 filter->src_port = fdir->input.flow.tcp6_flow.src_port; 2876 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2877 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port; 2878 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2879 filter->dst_port_mask = 0xffff; 2880 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2881 filter->src_port_mask = 0xffff; 2882 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2883 filter->ip_addr_type = 2884 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2885 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto; 2886 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2887 rte_memcpy(filter->src_ipaddr, 2888 fdir->input.flow.tcp6_flow.ip.src_ip, 16); 2889 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2890 rte_memcpy(filter->dst_ipaddr, 2891 fdir->input.flow.tcp6_flow.ip.dst_ip, 16); 2892 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2893 memset(filter->dst_ipaddr_mask, 0xff, 16); 2894 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2895 memset(filter->src_ipaddr_mask, 0xff, 16); 2896 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2897 filter->ethertype = 0x86dd; 2898 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2899 break; 2900 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 2901 filter->src_port = fdir->input.flow.udp6_flow.src_port; 2902 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2903 filter->dst_port = fdir->input.flow.udp6_flow.dst_port; 2904 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2905 filter->dst_port_mask = 0xffff; 2906 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2907 filter->src_port_mask = 0xffff; 2908 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2909 filter->ip_addr_type = 2910 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2911 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto; 2912 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2913 rte_memcpy(filter->src_ipaddr, 2914 fdir->input.flow.udp6_flow.ip.src_ip, 16); 2915 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2916 rte_memcpy(filter->dst_ipaddr, 2917 fdir->input.flow.udp6_flow.ip.dst_ip, 16); 2918 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2919 memset(filter->dst_ipaddr_mask, 0xff, 16); 2920 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2921 memset(filter->src_ipaddr_mask, 0xff, 16); 2922 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2923 filter->ethertype = 0x86dd; 2924 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2925 break; 2926 case RTE_ETH_FLOW_L2_PAYLOAD: 2927 filter->ethertype = fdir->input.flow.l2_flow.ether_type; 2928 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2929 break; 2930 case RTE_ETH_FLOW_VXLAN: 2931 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2932 return -EINVAL; 2933 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2934 filter->tunnel_type = 2935 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN; 2936 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2937 break; 2938 case RTE_ETH_FLOW_NVGRE: 2939 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2940 return -EINVAL; 2941 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2942 filter->tunnel_type = 2943 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE; 2944 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2945 break; 2946 case RTE_ETH_FLOW_UNKNOWN: 2947 case RTE_ETH_FLOW_RAW: 2948 case RTE_ETH_FLOW_FRAG_IPV4: 2949 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 2950 case RTE_ETH_FLOW_FRAG_IPV6: 2951 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 2952 case RTE_ETH_FLOW_IPV6_EX: 2953 case RTE_ETH_FLOW_IPV6_TCP_EX: 2954 case RTE_ETH_FLOW_IPV6_UDP_EX: 2955 case RTE_ETH_FLOW_GENEVE: 2956 /* FALLTHROUGH */ 2957 default: 2958 return -EINVAL; 2959 } 2960 2961 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 2962 vnic = &bp->vnic_info[fdir->action.rx_queue]; 2963 if (vnic == NULL) { 2964 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue); 2965 return -EINVAL; 2966 } 2967 2968 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 2969 rte_memcpy(filter->dst_macaddr, 2970 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6); 2971 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2972 } 2973 2974 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) { 2975 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2976 filter1 = STAILQ_FIRST(&vnic0->filter); 2977 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0); 2978 } else { 2979 filter->dst_id = vnic->fw_vnic_id; 2980 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 2981 if (filter->dst_macaddr[i] == 0x00) 2982 filter1 = STAILQ_FIRST(&vnic0->filter); 2983 else 2984 filter1 = bnxt_get_l2_filter(bp, filter, vnic); 2985 } 2986 2987 if (filter1 == NULL) 2988 return -EINVAL; 2989 2990 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2991 filter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2992 2993 filter->enables = en; 2994 2995 return 0; 2996 } 2997 2998 static struct bnxt_filter_info * 2999 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf, 3000 struct bnxt_vnic_info **mvnic) 3001 { 3002 struct bnxt_filter_info *mf = NULL; 3003 int i; 3004 3005 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3006 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3007 3008 STAILQ_FOREACH(mf, &vnic->filter, next) { 3009 if (mf->filter_type == nf->filter_type && 3010 mf->flags == nf->flags && 3011 mf->src_port == nf->src_port && 3012 mf->src_port_mask == nf->src_port_mask && 3013 mf->dst_port == nf->dst_port && 3014 mf->dst_port_mask == nf->dst_port_mask && 3015 mf->ip_protocol == nf->ip_protocol && 3016 mf->ip_addr_type == nf->ip_addr_type && 3017 mf->ethertype == nf->ethertype && 3018 mf->vni == nf->vni && 3019 mf->tunnel_type == nf->tunnel_type && 3020 mf->l2_ovlan == nf->l2_ovlan && 3021 mf->l2_ovlan_mask == nf->l2_ovlan_mask && 3022 mf->l2_ivlan == nf->l2_ivlan && 3023 mf->l2_ivlan_mask == nf->l2_ivlan_mask && 3024 !memcmp(mf->l2_addr, nf->l2_addr, 3025 RTE_ETHER_ADDR_LEN) && 3026 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask, 3027 RTE_ETHER_ADDR_LEN) && 3028 !memcmp(mf->src_macaddr, nf->src_macaddr, 3029 RTE_ETHER_ADDR_LEN) && 3030 !memcmp(mf->dst_macaddr, nf->dst_macaddr, 3031 RTE_ETHER_ADDR_LEN) && 3032 !memcmp(mf->src_ipaddr, nf->src_ipaddr, 3033 sizeof(nf->src_ipaddr)) && 3034 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask, 3035 sizeof(nf->src_ipaddr_mask)) && 3036 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr, 3037 sizeof(nf->dst_ipaddr)) && 3038 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask, 3039 sizeof(nf->dst_ipaddr_mask))) { 3040 if (mvnic) 3041 *mvnic = vnic; 3042 return mf; 3043 } 3044 } 3045 } 3046 return NULL; 3047 } 3048 3049 static int 3050 bnxt_fdir_filter(struct rte_eth_dev *dev, 3051 enum rte_filter_op filter_op, 3052 void *arg) 3053 { 3054 struct bnxt *bp = dev->data->dev_private; 3055 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg; 3056 struct bnxt_filter_info *filter, *match; 3057 struct bnxt_vnic_info *vnic, *mvnic; 3058 int ret = 0, i; 3059 3060 if (filter_op == RTE_ETH_FILTER_NOP) 3061 return 0; 3062 3063 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 3064 return -EINVAL; 3065 3066 switch (filter_op) { 3067 case RTE_ETH_FILTER_ADD: 3068 case RTE_ETH_FILTER_DELETE: 3069 /* FALLTHROUGH */ 3070 filter = bnxt_get_unused_filter(bp); 3071 if (filter == NULL) { 3072 PMD_DRV_LOG(ERR, 3073 "Not enough resources for a new flow.\n"); 3074 return -ENOMEM; 3075 } 3076 3077 ret = bnxt_parse_fdir_filter(bp, fdir, filter); 3078 if (ret != 0) 3079 goto free_filter; 3080 filter->filter_type = HWRM_CFA_NTUPLE_FILTER; 3081 3082 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3083 vnic = &bp->vnic_info[0]; 3084 else 3085 vnic = &bp->vnic_info[fdir->action.rx_queue]; 3086 3087 match = bnxt_match_fdir(bp, filter, &mvnic); 3088 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { 3089 if (match->dst_id == vnic->fw_vnic_id) { 3090 PMD_DRV_LOG(ERR, "Flow already exists.\n"); 3091 ret = -EEXIST; 3092 goto free_filter; 3093 } else { 3094 match->dst_id = vnic->fw_vnic_id; 3095 ret = bnxt_hwrm_set_ntuple_filter(bp, 3096 match->dst_id, 3097 match); 3098 STAILQ_REMOVE(&mvnic->filter, match, 3099 bnxt_filter_info, next); 3100 STAILQ_INSERT_TAIL(&vnic->filter, match, next); 3101 PMD_DRV_LOG(ERR, 3102 "Filter with matching pattern exist\n"); 3103 PMD_DRV_LOG(ERR, 3104 "Updated it to new destination q\n"); 3105 goto free_filter; 3106 } 3107 } 3108 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 3109 PMD_DRV_LOG(ERR, "Flow does not exist.\n"); 3110 ret = -ENOENT; 3111 goto free_filter; 3112 } 3113 3114 if (filter_op == RTE_ETH_FILTER_ADD) { 3115 ret = bnxt_hwrm_set_ntuple_filter(bp, 3116 filter->dst_id, 3117 filter); 3118 if (ret) 3119 goto free_filter; 3120 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 3121 } else { 3122 ret = bnxt_hwrm_clear_ntuple_filter(bp, match); 3123 STAILQ_REMOVE(&vnic->filter, match, 3124 bnxt_filter_info, next); 3125 bnxt_free_filter(bp, match); 3126 bnxt_free_filter(bp, filter); 3127 } 3128 break; 3129 case RTE_ETH_FILTER_FLUSH: 3130 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3131 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3132 3133 STAILQ_FOREACH(filter, &vnic->filter, next) { 3134 if (filter->filter_type == 3135 HWRM_CFA_NTUPLE_FILTER) { 3136 ret = 3137 bnxt_hwrm_clear_ntuple_filter(bp, 3138 filter); 3139 STAILQ_REMOVE(&vnic->filter, filter, 3140 bnxt_filter_info, next); 3141 } 3142 } 3143 } 3144 return ret; 3145 case RTE_ETH_FILTER_UPDATE: 3146 case RTE_ETH_FILTER_STATS: 3147 case RTE_ETH_FILTER_INFO: 3148 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op); 3149 break; 3150 default: 3151 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 3152 ret = -EINVAL; 3153 break; 3154 } 3155 return ret; 3156 3157 free_filter: 3158 bnxt_free_filter(bp, filter); 3159 return ret; 3160 } 3161 3162 static int 3163 bnxt_filter_ctrl_op(struct rte_eth_dev *dev, 3164 enum rte_filter_type filter_type, 3165 enum rte_filter_op filter_op, void *arg) 3166 { 3167 int ret = 0; 3168 3169 ret = is_bnxt_in_error(dev->data->dev_private); 3170 if (ret) 3171 return ret; 3172 3173 switch (filter_type) { 3174 case RTE_ETH_FILTER_TUNNEL: 3175 PMD_DRV_LOG(ERR, 3176 "filter type: %d: To be implemented\n", filter_type); 3177 break; 3178 case RTE_ETH_FILTER_FDIR: 3179 ret = bnxt_fdir_filter(dev, filter_op, arg); 3180 break; 3181 case RTE_ETH_FILTER_NTUPLE: 3182 ret = bnxt_ntuple_filter(dev, filter_op, arg); 3183 break; 3184 case RTE_ETH_FILTER_ETHERTYPE: 3185 ret = bnxt_ethertype_filter(dev, filter_op, arg); 3186 break; 3187 case RTE_ETH_FILTER_GENERIC: 3188 if (filter_op != RTE_ETH_FILTER_GET) 3189 return -EINVAL; 3190 *(const void **)arg = &bnxt_flow_ops; 3191 break; 3192 default: 3193 PMD_DRV_LOG(ERR, 3194 "Filter type (%d) not supported", filter_type); 3195 ret = -EINVAL; 3196 break; 3197 } 3198 return ret; 3199 } 3200 3201 static const uint32_t * 3202 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3203 { 3204 static const uint32_t ptypes[] = { 3205 RTE_PTYPE_L2_ETHER_VLAN, 3206 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3207 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3208 RTE_PTYPE_L4_ICMP, 3209 RTE_PTYPE_L4_TCP, 3210 RTE_PTYPE_L4_UDP, 3211 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3212 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3213 RTE_PTYPE_INNER_L4_ICMP, 3214 RTE_PTYPE_INNER_L4_TCP, 3215 RTE_PTYPE_INNER_L4_UDP, 3216 RTE_PTYPE_UNKNOWN 3217 }; 3218 3219 if (!dev->rx_pkt_burst) 3220 return NULL; 3221 3222 return ptypes; 3223 } 3224 3225 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3226 int reg_win) 3227 { 3228 uint32_t reg_base = *reg_arr & 0xfffff000; 3229 uint32_t win_off; 3230 int i; 3231 3232 for (i = 0; i < count; i++) { 3233 if ((reg_arr[i] & 0xfffff000) != reg_base) 3234 return -ERANGE; 3235 } 3236 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3237 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3238 return 0; 3239 } 3240 3241 static int bnxt_map_ptp_regs(struct bnxt *bp) 3242 { 3243 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3244 uint32_t *reg_arr; 3245 int rc, i; 3246 3247 reg_arr = ptp->rx_regs; 3248 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3249 if (rc) 3250 return rc; 3251 3252 reg_arr = ptp->tx_regs; 3253 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3254 if (rc) 3255 return rc; 3256 3257 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3258 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3259 3260 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3261 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3262 3263 return 0; 3264 } 3265 3266 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3267 { 3268 rte_write32(0, (uint8_t *)bp->bar0 + 3269 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3270 rte_write32(0, (uint8_t *)bp->bar0 + 3271 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3272 } 3273 3274 static uint64_t bnxt_cc_read(struct bnxt *bp) 3275 { 3276 uint64_t ns; 3277 3278 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3279 BNXT_GRCPF_REG_SYNC_TIME)); 3280 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3281 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3282 return ns; 3283 } 3284 3285 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3286 { 3287 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3288 uint32_t fifo; 3289 3290 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3291 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3292 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3293 return -EAGAIN; 3294 3295 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3296 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3297 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3298 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3299 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3300 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3301 3302 return 0; 3303 } 3304 3305 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3306 { 3307 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3308 struct bnxt_pf_info *pf = &bp->pf; 3309 uint16_t port_id; 3310 uint32_t fifo; 3311 3312 if (!ptp) 3313 return -ENODEV; 3314 3315 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3316 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3317 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3318 return -EAGAIN; 3319 3320 port_id = pf->port_id; 3321 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3322 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3323 3324 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3325 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3326 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 3327 /* bnxt_clr_rx_ts(bp); TBD */ 3328 return -EBUSY; 3329 } 3330 3331 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3332 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3333 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3334 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3335 3336 return 0; 3337 } 3338 3339 static int 3340 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3341 { 3342 uint64_t ns; 3343 struct bnxt *bp = dev->data->dev_private; 3344 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3345 3346 if (!ptp) 3347 return 0; 3348 3349 ns = rte_timespec_to_ns(ts); 3350 /* Set the timecounters to a new value. */ 3351 ptp->tc.nsec = ns; 3352 3353 return 0; 3354 } 3355 3356 static int 3357 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3358 { 3359 struct bnxt *bp = dev->data->dev_private; 3360 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3361 uint64_t ns, systime_cycles = 0; 3362 int rc = 0; 3363 3364 if (!ptp) 3365 return 0; 3366 3367 if (BNXT_CHIP_THOR(bp)) 3368 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3369 &systime_cycles); 3370 else 3371 systime_cycles = bnxt_cc_read(bp); 3372 3373 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3374 *ts = rte_ns_to_timespec(ns); 3375 3376 return rc; 3377 } 3378 static int 3379 bnxt_timesync_enable(struct rte_eth_dev *dev) 3380 { 3381 struct bnxt *bp = dev->data->dev_private; 3382 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3383 uint32_t shift = 0; 3384 int rc; 3385 3386 if (!ptp) 3387 return 0; 3388 3389 ptp->rx_filter = 1; 3390 ptp->tx_tstamp_en = 1; 3391 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3392 3393 rc = bnxt_hwrm_ptp_cfg(bp); 3394 if (rc) 3395 return rc; 3396 3397 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3398 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3399 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3400 3401 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3402 ptp->tc.cc_shift = shift; 3403 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3404 3405 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3406 ptp->rx_tstamp_tc.cc_shift = shift; 3407 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3408 3409 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3410 ptp->tx_tstamp_tc.cc_shift = shift; 3411 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3412 3413 if (!BNXT_CHIP_THOR(bp)) 3414 bnxt_map_ptp_regs(bp); 3415 3416 return 0; 3417 } 3418 3419 static int 3420 bnxt_timesync_disable(struct rte_eth_dev *dev) 3421 { 3422 struct bnxt *bp = dev->data->dev_private; 3423 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3424 3425 if (!ptp) 3426 return 0; 3427 3428 ptp->rx_filter = 0; 3429 ptp->tx_tstamp_en = 0; 3430 ptp->rxctl = 0; 3431 3432 bnxt_hwrm_ptp_cfg(bp); 3433 3434 if (!BNXT_CHIP_THOR(bp)) 3435 bnxt_unmap_ptp_regs(bp); 3436 3437 return 0; 3438 } 3439 3440 static int 3441 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3442 struct timespec *timestamp, 3443 uint32_t flags __rte_unused) 3444 { 3445 struct bnxt *bp = dev->data->dev_private; 3446 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3447 uint64_t rx_tstamp_cycles = 0; 3448 uint64_t ns; 3449 3450 if (!ptp) 3451 return 0; 3452 3453 if (BNXT_CHIP_THOR(bp)) 3454 rx_tstamp_cycles = ptp->rx_timestamp; 3455 else 3456 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3457 3458 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3459 *timestamp = rte_ns_to_timespec(ns); 3460 return 0; 3461 } 3462 3463 static int 3464 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3465 struct timespec *timestamp) 3466 { 3467 struct bnxt *bp = dev->data->dev_private; 3468 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3469 uint64_t tx_tstamp_cycles = 0; 3470 uint64_t ns; 3471 int rc = 0; 3472 3473 if (!ptp) 3474 return 0; 3475 3476 if (BNXT_CHIP_THOR(bp)) 3477 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3478 &tx_tstamp_cycles); 3479 else 3480 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3481 3482 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3483 *timestamp = rte_ns_to_timespec(ns); 3484 3485 return rc; 3486 } 3487 3488 static int 3489 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3490 { 3491 struct bnxt *bp = dev->data->dev_private; 3492 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3493 3494 if (!ptp) 3495 return 0; 3496 3497 ptp->tc.nsec += delta; 3498 3499 return 0; 3500 } 3501 3502 static int 3503 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3504 { 3505 struct bnxt *bp = dev->data->dev_private; 3506 int rc; 3507 uint32_t dir_entries; 3508 uint32_t entry_length; 3509 3510 rc = is_bnxt_in_error(bp); 3511 if (rc) 3512 return rc; 3513 3514 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n", 3515 bp->pdev->addr.domain, bp->pdev->addr.bus, 3516 bp->pdev->addr.devid, bp->pdev->addr.function); 3517 3518 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3519 if (rc != 0) 3520 return rc; 3521 3522 return dir_entries * entry_length; 3523 } 3524 3525 static int 3526 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3527 struct rte_dev_eeprom_info *in_eeprom) 3528 { 3529 struct bnxt *bp = dev->data->dev_private; 3530 uint32_t index; 3531 uint32_t offset; 3532 int rc; 3533 3534 rc = is_bnxt_in_error(bp); 3535 if (rc) 3536 return rc; 3537 3538 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 3539 "len = %d\n", bp->pdev->addr.domain, 3540 bp->pdev->addr.bus, bp->pdev->addr.devid, 3541 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 3542 3543 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3544 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3545 in_eeprom->data); 3546 3547 index = in_eeprom->offset >> 24; 3548 offset = in_eeprom->offset & 0xffffff; 3549 3550 if (index != 0) 3551 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3552 in_eeprom->length, in_eeprom->data); 3553 3554 return 0; 3555 } 3556 3557 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3558 { 3559 switch (dir_type) { 3560 case BNX_DIR_TYPE_CHIMP_PATCH: 3561 case BNX_DIR_TYPE_BOOTCODE: 3562 case BNX_DIR_TYPE_BOOTCODE_2: 3563 case BNX_DIR_TYPE_APE_FW: 3564 case BNX_DIR_TYPE_APE_PATCH: 3565 case BNX_DIR_TYPE_KONG_FW: 3566 case BNX_DIR_TYPE_KONG_PATCH: 3567 case BNX_DIR_TYPE_BONO_FW: 3568 case BNX_DIR_TYPE_BONO_PATCH: 3569 /* FALLTHROUGH */ 3570 return true; 3571 } 3572 3573 return false; 3574 } 3575 3576 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3577 { 3578 switch (dir_type) { 3579 case BNX_DIR_TYPE_AVS: 3580 case BNX_DIR_TYPE_EXP_ROM_MBA: 3581 case BNX_DIR_TYPE_PCIE: 3582 case BNX_DIR_TYPE_TSCF_UCODE: 3583 case BNX_DIR_TYPE_EXT_PHY: 3584 case BNX_DIR_TYPE_CCM: 3585 case BNX_DIR_TYPE_ISCSI_BOOT: 3586 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3587 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3588 /* FALLTHROUGH */ 3589 return true; 3590 } 3591 3592 return false; 3593 } 3594 3595 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3596 { 3597 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3598 bnxt_dir_type_is_other_exec_format(dir_type); 3599 } 3600 3601 static int 3602 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3603 struct rte_dev_eeprom_info *in_eeprom) 3604 { 3605 struct bnxt *bp = dev->data->dev_private; 3606 uint8_t index, dir_op; 3607 uint16_t type, ext, ordinal, attr; 3608 int rc; 3609 3610 rc = is_bnxt_in_error(bp); 3611 if (rc) 3612 return rc; 3613 3614 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 3615 "len = %d\n", bp->pdev->addr.domain, 3616 bp->pdev->addr.bus, bp->pdev->addr.devid, 3617 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 3618 3619 if (!BNXT_PF(bp)) { 3620 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3621 return -EINVAL; 3622 } 3623 3624 type = in_eeprom->magic >> 16; 3625 3626 if (type == 0xffff) { /* special value for directory operations */ 3627 index = in_eeprom->magic & 0xff; 3628 dir_op = in_eeprom->magic >> 8; 3629 if (index == 0) 3630 return -EINVAL; 3631 switch (dir_op) { 3632 case 0x0e: /* erase */ 3633 if (in_eeprom->offset != ~in_eeprom->magic) 3634 return -EINVAL; 3635 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3636 default: 3637 return -EINVAL; 3638 } 3639 } 3640 3641 /* Create or re-write an NVM item: */ 3642 if (bnxt_dir_type_is_executable(type) == true) 3643 return -EOPNOTSUPP; 3644 ext = in_eeprom->magic & 0xffff; 3645 ordinal = in_eeprom->offset >> 16; 3646 attr = in_eeprom->offset & 0xffff; 3647 3648 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3649 in_eeprom->data, in_eeprom->length); 3650 } 3651 3652 /* 3653 * Initialization 3654 */ 3655 3656 static const struct eth_dev_ops bnxt_dev_ops = { 3657 .dev_infos_get = bnxt_dev_info_get_op, 3658 .dev_close = bnxt_dev_close_op, 3659 .dev_configure = bnxt_dev_configure_op, 3660 .dev_start = bnxt_dev_start_op, 3661 .dev_stop = bnxt_dev_stop_op, 3662 .dev_set_link_up = bnxt_dev_set_link_up_op, 3663 .dev_set_link_down = bnxt_dev_set_link_down_op, 3664 .stats_get = bnxt_stats_get_op, 3665 .stats_reset = bnxt_stats_reset_op, 3666 .rx_queue_setup = bnxt_rx_queue_setup_op, 3667 .rx_queue_release = bnxt_rx_queue_release_op, 3668 .tx_queue_setup = bnxt_tx_queue_setup_op, 3669 .tx_queue_release = bnxt_tx_queue_release_op, 3670 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3671 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3672 .reta_update = bnxt_reta_update_op, 3673 .reta_query = bnxt_reta_query_op, 3674 .rss_hash_update = bnxt_rss_hash_update_op, 3675 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3676 .link_update = bnxt_link_update_op, 3677 .promiscuous_enable = bnxt_promiscuous_enable_op, 3678 .promiscuous_disable = bnxt_promiscuous_disable_op, 3679 .allmulticast_enable = bnxt_allmulticast_enable_op, 3680 .allmulticast_disable = bnxt_allmulticast_disable_op, 3681 .mac_addr_add = bnxt_mac_addr_add_op, 3682 .mac_addr_remove = bnxt_mac_addr_remove_op, 3683 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3684 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3685 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3686 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3687 .vlan_filter_set = bnxt_vlan_filter_set_op, 3688 .vlan_offload_set = bnxt_vlan_offload_set_op, 3689 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 3690 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3691 .mtu_set = bnxt_mtu_set_op, 3692 .mac_addr_set = bnxt_set_default_mac_addr_op, 3693 .xstats_get = bnxt_dev_xstats_get_op, 3694 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3695 .xstats_reset = bnxt_dev_xstats_reset_op, 3696 .fw_version_get = bnxt_fw_version_get, 3697 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3698 .rxq_info_get = bnxt_rxq_info_get_op, 3699 .txq_info_get = bnxt_txq_info_get_op, 3700 .dev_led_on = bnxt_dev_led_on_op, 3701 .dev_led_off = bnxt_dev_led_off_op, 3702 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op, 3703 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op, 3704 .rx_queue_count = bnxt_rx_queue_count_op, 3705 .rx_descriptor_status = bnxt_rx_descriptor_status_op, 3706 .tx_descriptor_status = bnxt_tx_descriptor_status_op, 3707 .rx_queue_start = bnxt_rx_queue_start, 3708 .rx_queue_stop = bnxt_rx_queue_stop, 3709 .tx_queue_start = bnxt_tx_queue_start, 3710 .tx_queue_stop = bnxt_tx_queue_stop, 3711 .filter_ctrl = bnxt_filter_ctrl_op, 3712 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3713 .get_eeprom_length = bnxt_get_eeprom_length_op, 3714 .get_eeprom = bnxt_get_eeprom_op, 3715 .set_eeprom = bnxt_set_eeprom_op, 3716 .timesync_enable = bnxt_timesync_enable, 3717 .timesync_disable = bnxt_timesync_disable, 3718 .timesync_read_time = bnxt_timesync_read_time, 3719 .timesync_write_time = bnxt_timesync_write_time, 3720 .timesync_adjust_time = bnxt_timesync_adjust_time, 3721 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3722 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3723 }; 3724 3725 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 3726 { 3727 uint32_t offset; 3728 3729 /* Only pre-map the reset GRC registers using window 3 */ 3730 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 3731 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 3732 3733 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 3734 3735 return offset; 3736 } 3737 3738 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 3739 { 3740 struct bnxt_error_recovery_info *info = bp->recovery_info; 3741 uint32_t reg_base = 0xffffffff; 3742 int i; 3743 3744 /* Only pre-map the monitoring GRC registers using window 2 */ 3745 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 3746 uint32_t reg = info->status_regs[i]; 3747 3748 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 3749 continue; 3750 3751 if (reg_base == 0xffffffff) 3752 reg_base = reg & 0xfffff000; 3753 if ((reg & 0xfffff000) != reg_base) 3754 return -ERANGE; 3755 3756 /* Use mask 0xffc as the Lower 2 bits indicates 3757 * address space location 3758 */ 3759 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 3760 (reg & 0xffc); 3761 } 3762 3763 if (reg_base == 0xffffffff) 3764 return 0; 3765 3766 rte_write32(reg_base, (uint8_t *)bp->bar0 + 3767 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 3768 3769 return 0; 3770 } 3771 3772 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 3773 { 3774 struct bnxt_error_recovery_info *info = bp->recovery_info; 3775 uint32_t delay = info->delay_after_reset[index]; 3776 uint32_t val = info->reset_reg_val[index]; 3777 uint32_t reg = info->reset_reg[index]; 3778 uint32_t type, offset; 3779 3780 type = BNXT_FW_STATUS_REG_TYPE(reg); 3781 offset = BNXT_FW_STATUS_REG_OFF(reg); 3782 3783 switch (type) { 3784 case BNXT_FW_STATUS_REG_TYPE_CFG: 3785 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 3786 break; 3787 case BNXT_FW_STATUS_REG_TYPE_GRC: 3788 offset = bnxt_map_reset_regs(bp, offset); 3789 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3790 break; 3791 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3792 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3793 break; 3794 } 3795 /* wait on a specific interval of time until core reset is complete */ 3796 if (delay) 3797 rte_delay_ms(delay); 3798 } 3799 3800 static void bnxt_dev_cleanup(struct bnxt *bp) 3801 { 3802 bnxt_set_hwrm_link_config(bp, false); 3803 bp->link_info.link_up = 0; 3804 if (bp->dev_stopped == 0) 3805 bnxt_dev_stop_op(bp->eth_dev); 3806 3807 bnxt_uninit_resources(bp, true); 3808 } 3809 3810 static int bnxt_restore_vlan_filters(struct bnxt *bp) 3811 { 3812 struct rte_eth_dev *dev = bp->eth_dev; 3813 struct rte_vlan_filter_conf *vfc; 3814 int vidx, vbit, rc; 3815 uint16_t vlan_id; 3816 3817 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 3818 vfc = &dev->data->vlan_filter_conf; 3819 vidx = vlan_id / 64; 3820 vbit = vlan_id % 64; 3821 3822 /* Each bit corresponds to a VLAN id */ 3823 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 3824 rc = bnxt_add_vlan_filter(bp, vlan_id); 3825 if (rc) 3826 return rc; 3827 } 3828 } 3829 3830 return 0; 3831 } 3832 3833 static int bnxt_restore_mac_filters(struct bnxt *bp) 3834 { 3835 struct rte_eth_dev *dev = bp->eth_dev; 3836 struct rte_eth_dev_info dev_info; 3837 struct rte_ether_addr *addr; 3838 uint64_t pool_mask; 3839 uint32_t pool = 0; 3840 uint16_t i; 3841 int rc; 3842 3843 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) 3844 return 0; 3845 3846 rc = bnxt_dev_info_get_op(dev, &dev_info); 3847 if (rc) 3848 return rc; 3849 3850 /* replay MAC address configuration */ 3851 for (i = 1; i < dev_info.max_mac_addrs; i++) { 3852 addr = &dev->data->mac_addrs[i]; 3853 3854 /* skip zero address */ 3855 if (rte_is_zero_ether_addr(addr)) 3856 continue; 3857 3858 pool = 0; 3859 pool_mask = dev->data->mac_pool_sel[i]; 3860 3861 do { 3862 if (pool_mask & 1ULL) { 3863 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 3864 if (rc) 3865 return rc; 3866 } 3867 pool_mask >>= 1; 3868 pool++; 3869 } while (pool_mask); 3870 } 3871 3872 return 0; 3873 } 3874 3875 static int bnxt_restore_filters(struct bnxt *bp) 3876 { 3877 struct rte_eth_dev *dev = bp->eth_dev; 3878 int ret = 0; 3879 3880 if (dev->data->all_multicast) 3881 ret = bnxt_allmulticast_enable_op(dev); 3882 if (dev->data->promiscuous) 3883 ret = bnxt_promiscuous_enable_op(dev); 3884 3885 ret = bnxt_restore_mac_filters(bp); 3886 if (ret) 3887 return ret; 3888 3889 ret = bnxt_restore_vlan_filters(bp); 3890 /* TODO restore other filters as well */ 3891 return ret; 3892 } 3893 3894 static void bnxt_dev_recover(void *arg) 3895 { 3896 struct bnxt *bp = arg; 3897 int timeout = bp->fw_reset_max_msecs; 3898 int rc = 0; 3899 3900 /* Clear Error flag so that device re-init should happen */ 3901 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 3902 3903 do { 3904 rc = bnxt_hwrm_ver_get(bp); 3905 if (rc == 0) 3906 break; 3907 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 3908 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 3909 } while (rc && timeout); 3910 3911 if (rc) { 3912 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 3913 goto err; 3914 } 3915 3916 rc = bnxt_init_resources(bp, true); 3917 if (rc) { 3918 PMD_DRV_LOG(ERR, 3919 "Failed to initialize resources after reset\n"); 3920 goto err; 3921 } 3922 /* clear reset flag as the device is initialized now */ 3923 bp->flags &= ~BNXT_FLAG_FW_RESET; 3924 3925 rc = bnxt_dev_start_op(bp->eth_dev); 3926 if (rc) { 3927 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 3928 goto err; 3929 } 3930 3931 rc = bnxt_restore_filters(bp); 3932 if (rc) 3933 goto err; 3934 3935 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 3936 return; 3937 err: 3938 bp->flags |= BNXT_FLAG_FATAL_ERROR; 3939 bnxt_uninit_resources(bp, false); 3940 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 3941 } 3942 3943 void bnxt_dev_reset_and_resume(void *arg) 3944 { 3945 struct bnxt *bp = arg; 3946 int rc; 3947 3948 bnxt_dev_cleanup(bp); 3949 3950 bnxt_wait_for_device_shutdown(bp); 3951 3952 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, 3953 bnxt_dev_recover, (void *)bp); 3954 if (rc) 3955 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 3956 } 3957 3958 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 3959 { 3960 struct bnxt_error_recovery_info *info = bp->recovery_info; 3961 uint32_t reg = info->status_regs[index]; 3962 uint32_t type, offset, val = 0; 3963 3964 type = BNXT_FW_STATUS_REG_TYPE(reg); 3965 offset = BNXT_FW_STATUS_REG_OFF(reg); 3966 3967 switch (type) { 3968 case BNXT_FW_STATUS_REG_TYPE_CFG: 3969 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 3970 break; 3971 case BNXT_FW_STATUS_REG_TYPE_GRC: 3972 offset = info->mapped_status_regs[index]; 3973 /* FALLTHROUGH */ 3974 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3975 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3976 offset)); 3977 break; 3978 } 3979 3980 return val; 3981 } 3982 3983 static int bnxt_fw_reset_all(struct bnxt *bp) 3984 { 3985 struct bnxt_error_recovery_info *info = bp->recovery_info; 3986 uint32_t i; 3987 int rc = 0; 3988 3989 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 3990 /* Reset through master function driver */ 3991 for (i = 0; i < info->reg_array_cnt; i++) 3992 bnxt_write_fw_reset_reg(bp, i); 3993 /* Wait for time specified by FW after triggering reset */ 3994 rte_delay_ms(info->master_func_wait_period_after_reset); 3995 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 3996 /* Reset with the help of Kong processor */ 3997 rc = bnxt_hwrm_fw_reset(bp); 3998 if (rc) 3999 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 4000 } 4001 4002 return rc; 4003 } 4004 4005 static void bnxt_fw_reset_cb(void *arg) 4006 { 4007 struct bnxt *bp = arg; 4008 struct bnxt_error_recovery_info *info = bp->recovery_info; 4009 int rc = 0; 4010 4011 /* Only Master function can do FW reset */ 4012 if (bnxt_is_master_func(bp) && 4013 bnxt_is_recovery_enabled(bp)) { 4014 rc = bnxt_fw_reset_all(bp); 4015 if (rc) { 4016 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 4017 return; 4018 } 4019 } 4020 4021 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 4022 * EXCEPTION_FATAL_ASYNC event to all the functions 4023 * (including MASTER FUNC). After receiving this Async, all the active 4024 * drivers should treat this case as FW initiated recovery 4025 */ 4026 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4027 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 4028 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 4029 4030 /* To recover from error */ 4031 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 4032 (void *)bp); 4033 } 4034 } 4035 4036 /* Driver should poll FW heartbeat, reset_counter with the frequency 4037 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 4038 * When the driver detects heartbeat stop or change in reset_counter, 4039 * it has to trigger a reset to recover from the error condition. 4040 * A “master PF” is the function who will have the privilege to 4041 * initiate the chimp reset. The master PF will be elected by the 4042 * firmware and will be notified through async message. 4043 */ 4044 static void bnxt_check_fw_health(void *arg) 4045 { 4046 struct bnxt *bp = arg; 4047 struct bnxt_error_recovery_info *info = bp->recovery_info; 4048 uint32_t val = 0, wait_msec; 4049 4050 if (!info || !bnxt_is_recovery_enabled(bp) || 4051 is_bnxt_in_error(bp)) 4052 return; 4053 4054 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4055 if (val == info->last_heart_beat) 4056 goto reset; 4057 4058 info->last_heart_beat = val; 4059 4060 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4061 if (val != info->last_reset_counter) 4062 goto reset; 4063 4064 info->last_reset_counter = val; 4065 4066 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4067 bnxt_check_fw_health, (void *)bp); 4068 4069 return; 4070 reset: 4071 /* Stop DMA to/from device */ 4072 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4073 bp->flags |= BNXT_FLAG_FW_RESET; 4074 4075 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4076 4077 if (bnxt_is_master_func(bp)) 4078 wait_msec = info->master_func_wait_period; 4079 else 4080 wait_msec = info->normal_func_wait_period; 4081 4082 rte_eal_alarm_set(US_PER_MS * wait_msec, 4083 bnxt_fw_reset_cb, (void *)bp); 4084 } 4085 4086 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4087 { 4088 uint32_t polling_freq; 4089 4090 if (!bnxt_is_recovery_enabled(bp)) 4091 return; 4092 4093 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4094 return; 4095 4096 polling_freq = bp->recovery_info->driver_polling_freq; 4097 4098 rte_eal_alarm_set(US_PER_MS * polling_freq, 4099 bnxt_check_fw_health, (void *)bp); 4100 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4101 } 4102 4103 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4104 { 4105 if (!bnxt_is_recovery_enabled(bp)) 4106 return; 4107 4108 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4109 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4110 } 4111 4112 static bool bnxt_vf_pciid(uint16_t device_id) 4113 { 4114 switch (device_id) { 4115 case BROADCOM_DEV_ID_57304_VF: 4116 case BROADCOM_DEV_ID_57406_VF: 4117 case BROADCOM_DEV_ID_5731X_VF: 4118 case BROADCOM_DEV_ID_5741X_VF: 4119 case BROADCOM_DEV_ID_57414_VF: 4120 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4121 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4122 case BROADCOM_DEV_ID_58802_VF: 4123 case BROADCOM_DEV_ID_57500_VF1: 4124 case BROADCOM_DEV_ID_57500_VF2: 4125 /* FALLTHROUGH */ 4126 return true; 4127 default: 4128 return false; 4129 } 4130 } 4131 4132 static bool bnxt_thor_device(uint16_t device_id) 4133 { 4134 switch (device_id) { 4135 case BROADCOM_DEV_ID_57508: 4136 case BROADCOM_DEV_ID_57504: 4137 case BROADCOM_DEV_ID_57502: 4138 case BROADCOM_DEV_ID_57508_MF1: 4139 case BROADCOM_DEV_ID_57504_MF1: 4140 case BROADCOM_DEV_ID_57502_MF1: 4141 case BROADCOM_DEV_ID_57508_MF2: 4142 case BROADCOM_DEV_ID_57504_MF2: 4143 case BROADCOM_DEV_ID_57502_MF2: 4144 case BROADCOM_DEV_ID_57500_VF1: 4145 case BROADCOM_DEV_ID_57500_VF2: 4146 /* FALLTHROUGH */ 4147 return true; 4148 default: 4149 return false; 4150 } 4151 } 4152 4153 bool bnxt_stratus_device(struct bnxt *bp) 4154 { 4155 uint16_t device_id = bp->pdev->id.device_id; 4156 4157 switch (device_id) { 4158 case BROADCOM_DEV_ID_STRATUS_NIC: 4159 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4160 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4161 /* FALLTHROUGH */ 4162 return true; 4163 default: 4164 return false; 4165 } 4166 } 4167 4168 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 4169 { 4170 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4171 struct bnxt *bp = eth_dev->data->dev_private; 4172 4173 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4174 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4175 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4176 if (!bp->bar0 || !bp->doorbell_base) { 4177 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4178 return -ENODEV; 4179 } 4180 4181 bp->eth_dev = eth_dev; 4182 bp->pdev = pci_dev; 4183 4184 return 0; 4185 } 4186 4187 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4188 struct bnxt_ctx_pg_info *ctx_pg, 4189 uint32_t mem_size, 4190 const char *suffix, 4191 uint16_t idx) 4192 { 4193 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4194 const struct rte_memzone *mz = NULL; 4195 char mz_name[RTE_MEMZONE_NAMESIZE]; 4196 rte_iova_t mz_phys_addr; 4197 uint64_t valid_bits = 0; 4198 uint32_t sz; 4199 int i; 4200 4201 if (!mem_size) 4202 return 0; 4203 4204 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4205 BNXT_PAGE_SIZE; 4206 rmem->page_size = BNXT_PAGE_SIZE; 4207 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4208 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4209 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4210 4211 valid_bits = PTU_PTE_VALID; 4212 4213 if (rmem->nr_pages > 1) { 4214 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4215 "bnxt_ctx_pg_tbl%s_%x_%d", 4216 suffix, idx, bp->eth_dev->data->port_id); 4217 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4218 mz = rte_memzone_lookup(mz_name); 4219 if (!mz) { 4220 mz = rte_memzone_reserve_aligned(mz_name, 4221 rmem->nr_pages * 8, 4222 SOCKET_ID_ANY, 4223 RTE_MEMZONE_2MB | 4224 RTE_MEMZONE_SIZE_HINT_ONLY | 4225 RTE_MEMZONE_IOVA_CONTIG, 4226 BNXT_PAGE_SIZE); 4227 if (mz == NULL) 4228 return -ENOMEM; 4229 } 4230 4231 memset(mz->addr, 0, mz->len); 4232 mz_phys_addr = mz->iova; 4233 if ((unsigned long)mz->addr == mz_phys_addr) { 4234 PMD_DRV_LOG(DEBUG, 4235 "physical address same as virtual\n"); 4236 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n"); 4237 mz_phys_addr = rte_mem_virt2iova(mz->addr); 4238 if (mz_phys_addr == RTE_BAD_IOVA) { 4239 PMD_DRV_LOG(ERR, 4240 "unable to map addr to phys memory\n"); 4241 return -ENOMEM; 4242 } 4243 } 4244 rte_mem_lock_page(((char *)mz->addr)); 4245 4246 rmem->pg_tbl = mz->addr; 4247 rmem->pg_tbl_map = mz_phys_addr; 4248 rmem->pg_tbl_mz = mz; 4249 } 4250 4251 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4252 suffix, idx, bp->eth_dev->data->port_id); 4253 mz = rte_memzone_lookup(mz_name); 4254 if (!mz) { 4255 mz = rte_memzone_reserve_aligned(mz_name, 4256 mem_size, 4257 SOCKET_ID_ANY, 4258 RTE_MEMZONE_1GB | 4259 RTE_MEMZONE_SIZE_HINT_ONLY | 4260 RTE_MEMZONE_IOVA_CONTIG, 4261 BNXT_PAGE_SIZE); 4262 if (mz == NULL) 4263 return -ENOMEM; 4264 } 4265 4266 memset(mz->addr, 0, mz->len); 4267 mz_phys_addr = mz->iova; 4268 if ((unsigned long)mz->addr == mz_phys_addr) { 4269 PMD_DRV_LOG(DEBUG, 4270 "Memzone physical address same as virtual.\n"); 4271 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n"); 4272 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE) 4273 rte_mem_lock_page(((char *)mz->addr) + sz); 4274 mz_phys_addr = rte_mem_virt2iova(mz->addr); 4275 if (mz_phys_addr == RTE_BAD_IOVA) { 4276 PMD_DRV_LOG(ERR, 4277 "unable to map addr to phys memory\n"); 4278 return -ENOMEM; 4279 } 4280 } 4281 4282 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4283 rte_mem_lock_page(((char *)mz->addr) + sz); 4284 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4285 rmem->dma_arr[i] = mz_phys_addr + sz; 4286 4287 if (rmem->nr_pages > 1) { 4288 if (i == rmem->nr_pages - 2 && 4289 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4290 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4291 else if (i == rmem->nr_pages - 1 && 4292 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4293 valid_bits |= PTU_PTE_LAST; 4294 4295 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4296 valid_bits); 4297 } 4298 } 4299 4300 rmem->mz = mz; 4301 if (rmem->vmem_size) 4302 rmem->vmem = (void **)mz->addr; 4303 rmem->dma_arr[0] = mz_phys_addr; 4304 return 0; 4305 } 4306 4307 static void bnxt_free_ctx_mem(struct bnxt *bp) 4308 { 4309 int i; 4310 4311 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4312 return; 4313 4314 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4315 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4316 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4317 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4318 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4319 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4320 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4321 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4322 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4323 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4324 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4325 4326 for (i = 0; i < BNXT_MAX_Q; i++) { 4327 if (bp->ctx->tqm_mem[i]) 4328 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4329 } 4330 4331 rte_free(bp->ctx); 4332 bp->ctx = NULL; 4333 } 4334 4335 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4336 4337 #define min_t(type, x, y) ({ \ 4338 type __min1 = (x); \ 4339 type __min2 = (y); \ 4340 __min1 < __min2 ? __min1 : __min2; }) 4341 4342 #define max_t(type, x, y) ({ \ 4343 type __max1 = (x); \ 4344 type __max2 = (y); \ 4345 __max1 > __max2 ? __max1 : __max2; }) 4346 4347 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4348 4349 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4350 { 4351 struct bnxt_ctx_pg_info *ctx_pg; 4352 struct bnxt_ctx_mem_info *ctx; 4353 uint32_t mem_size, ena, entries; 4354 int i, rc; 4355 4356 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4357 if (rc) { 4358 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4359 return rc; 4360 } 4361 ctx = bp->ctx; 4362 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4363 return 0; 4364 4365 ctx_pg = &ctx->qp_mem; 4366 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4367 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4368 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4369 if (rc) 4370 return rc; 4371 4372 ctx_pg = &ctx->srq_mem; 4373 ctx_pg->entries = ctx->srq_max_l2_entries; 4374 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4375 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4376 if (rc) 4377 return rc; 4378 4379 ctx_pg = &ctx->cq_mem; 4380 ctx_pg->entries = ctx->cq_max_l2_entries; 4381 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4382 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4383 if (rc) 4384 return rc; 4385 4386 ctx_pg = &ctx->vnic_mem; 4387 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4388 ctx->vnic_max_ring_table_entries; 4389 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4390 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4391 if (rc) 4392 return rc; 4393 4394 ctx_pg = &ctx->stat_mem; 4395 ctx_pg->entries = ctx->stat_max_entries; 4396 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4397 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4398 if (rc) 4399 return rc; 4400 4401 entries = ctx->qp_max_l2_entries + 4402 ctx->vnic_max_vnic_entries + 4403 ctx->tqm_min_entries_per_ring; 4404 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4405 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring, 4406 ctx->tqm_max_entries_per_ring); 4407 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) { 4408 ctx_pg = ctx->tqm_mem[i]; 4409 /* use min tqm entries for now. */ 4410 ctx_pg->entries = entries; 4411 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4412 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i); 4413 if (rc) 4414 return rc; 4415 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4416 } 4417 4418 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4419 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4420 if (rc) 4421 PMD_DRV_LOG(ERR, 4422 "Failed to configure context mem: rc = %d\n", rc); 4423 else 4424 ctx->flags |= BNXT_CTX_FLAG_INITED; 4425 4426 return rc; 4427 } 4428 4429 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4430 { 4431 struct rte_pci_device *pci_dev = bp->pdev; 4432 char mz_name[RTE_MEMZONE_NAMESIZE]; 4433 const struct rte_memzone *mz = NULL; 4434 uint32_t total_alloc_len; 4435 rte_iova_t mz_phys_addr; 4436 4437 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4438 return 0; 4439 4440 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4441 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4442 pci_dev->addr.bus, pci_dev->addr.devid, 4443 pci_dev->addr.function, "rx_port_stats"); 4444 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4445 mz = rte_memzone_lookup(mz_name); 4446 total_alloc_len = 4447 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4448 sizeof(struct rx_port_stats_ext) + 512); 4449 if (!mz) { 4450 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4451 SOCKET_ID_ANY, 4452 RTE_MEMZONE_2MB | 4453 RTE_MEMZONE_SIZE_HINT_ONLY | 4454 RTE_MEMZONE_IOVA_CONTIG); 4455 if (mz == NULL) 4456 return -ENOMEM; 4457 } 4458 memset(mz->addr, 0, mz->len); 4459 mz_phys_addr = mz->iova; 4460 if ((unsigned long)mz->addr == mz_phys_addr) { 4461 PMD_DRV_LOG(DEBUG, 4462 "Memzone physical address same as virtual.\n"); 4463 PMD_DRV_LOG(DEBUG, 4464 "Using rte_mem_virt2iova()\n"); 4465 mz_phys_addr = rte_mem_virt2iova(mz->addr); 4466 if (mz_phys_addr == RTE_BAD_IOVA) { 4467 PMD_DRV_LOG(ERR, 4468 "Can't map address to physical memory\n"); 4469 return -ENOMEM; 4470 } 4471 } 4472 4473 bp->rx_mem_zone = (const void *)mz; 4474 bp->hw_rx_port_stats = mz->addr; 4475 bp->hw_rx_port_stats_map = mz_phys_addr; 4476 4477 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4478 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4479 pci_dev->addr.bus, pci_dev->addr.devid, 4480 pci_dev->addr.function, "tx_port_stats"); 4481 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4482 mz = rte_memzone_lookup(mz_name); 4483 total_alloc_len = 4484 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4485 sizeof(struct tx_port_stats_ext) + 512); 4486 if (!mz) { 4487 mz = rte_memzone_reserve(mz_name, 4488 total_alloc_len, 4489 SOCKET_ID_ANY, 4490 RTE_MEMZONE_2MB | 4491 RTE_MEMZONE_SIZE_HINT_ONLY | 4492 RTE_MEMZONE_IOVA_CONTIG); 4493 if (mz == NULL) 4494 return -ENOMEM; 4495 } 4496 memset(mz->addr, 0, mz->len); 4497 mz_phys_addr = mz->iova; 4498 if ((unsigned long)mz->addr == mz_phys_addr) { 4499 PMD_DRV_LOG(DEBUG, 4500 "Memzone physical address same as virtual\n"); 4501 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n"); 4502 mz_phys_addr = rte_mem_virt2iova(mz->addr); 4503 if (mz_phys_addr == RTE_BAD_IOVA) { 4504 PMD_DRV_LOG(ERR, 4505 "Can't map address to physical memory\n"); 4506 return -ENOMEM; 4507 } 4508 } 4509 4510 bp->tx_mem_zone = (const void *)mz; 4511 bp->hw_tx_port_stats = mz->addr; 4512 bp->hw_tx_port_stats_map = mz_phys_addr; 4513 bp->flags |= BNXT_FLAG_PORT_STATS; 4514 4515 /* Display extended statistics if FW supports it */ 4516 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4517 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4518 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4519 return 0; 4520 4521 bp->hw_rx_port_stats_ext = (void *) 4522 ((uint8_t *)bp->hw_rx_port_stats + 4523 sizeof(struct rx_port_stats)); 4524 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4525 sizeof(struct rx_port_stats); 4526 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4527 4528 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4529 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4530 bp->hw_tx_port_stats_ext = (void *) 4531 ((uint8_t *)bp->hw_tx_port_stats + 4532 sizeof(struct tx_port_stats)); 4533 bp->hw_tx_port_stats_ext_map = 4534 bp->hw_tx_port_stats_map + 4535 sizeof(struct tx_port_stats); 4536 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4537 } 4538 4539 return 0; 4540 } 4541 4542 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4543 { 4544 struct bnxt *bp = eth_dev->data->dev_private; 4545 int rc = 0; 4546 4547 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4548 RTE_ETHER_ADDR_LEN * 4549 bp->max_l2_ctx, 4550 0); 4551 if (eth_dev->data->mac_addrs == NULL) { 4552 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4553 return -ENOMEM; 4554 } 4555 4556 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) { 4557 if (BNXT_PF(bp)) 4558 return -EINVAL; 4559 4560 /* Generate a random MAC address, if none was assigned by PF */ 4561 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 4562 bnxt_eth_hw_addr_random(bp->mac_addr); 4563 PMD_DRV_LOG(INFO, 4564 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 4565 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 4566 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 4567 4568 rc = bnxt_hwrm_set_mac(bp); 4569 if (!rc) 4570 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr, 4571 RTE_ETHER_ADDR_LEN); 4572 return rc; 4573 } 4574 4575 /* Copy the permanent MAC from the FUNC_QCAPS response */ 4576 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN); 4577 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 4578 4579 return rc; 4580 } 4581 4582 static int bnxt_restore_dflt_mac(struct bnxt *bp) 4583 { 4584 int rc = 0; 4585 4586 /* MAC is already configured in FW */ 4587 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) 4588 return 0; 4589 4590 /* Restore the old MAC configured */ 4591 rc = bnxt_hwrm_set_mac(bp); 4592 if (rc) 4593 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 4594 4595 return rc; 4596 } 4597 4598 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 4599 { 4600 if (!BNXT_PF(bp)) 4601 return; 4602 4603 #define ALLOW_FUNC(x) \ 4604 { \ 4605 uint32_t arg = (x); \ 4606 bp->pf.vf_req_fwd[((arg) >> 5)] &= \ 4607 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \ 4608 } 4609 4610 /* Forward all requests if firmware is new enough */ 4611 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) && 4612 (bp->fw_ver < ((20 << 24) | (7 << 16)))) || 4613 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) { 4614 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd)); 4615 } else { 4616 PMD_DRV_LOG(WARNING, 4617 "Firmware too old for VF mailbox functionality\n"); 4618 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd)); 4619 } 4620 4621 /* 4622 * The following are used for driver cleanup. If we disallow these, 4623 * VF drivers can't clean up cleanly. 4624 */ 4625 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR); 4626 ALLOW_FUNC(HWRM_VNIC_FREE); 4627 ALLOW_FUNC(HWRM_RING_FREE); 4628 ALLOW_FUNC(HWRM_RING_GRP_FREE); 4629 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE); 4630 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE); 4631 ALLOW_FUNC(HWRM_STAT_CTX_FREE); 4632 ALLOW_FUNC(HWRM_PORT_PHY_QCFG); 4633 ALLOW_FUNC(HWRM_VNIC_TPA_CFG); 4634 } 4635 4636 static int bnxt_init_fw(struct bnxt *bp) 4637 { 4638 uint16_t mtu; 4639 int rc = 0; 4640 4641 bp->fw_cap = 0; 4642 4643 rc = bnxt_hwrm_ver_get(bp); 4644 if (rc) 4645 return rc; 4646 4647 rc = bnxt_hwrm_func_reset(bp); 4648 if (rc) 4649 return -EIO; 4650 4651 rc = bnxt_hwrm_vnic_qcaps(bp); 4652 if (rc) 4653 return rc; 4654 4655 rc = bnxt_hwrm_queue_qportcfg(bp); 4656 if (rc) 4657 return rc; 4658 4659 /* Get the MAX capabilities for this function. 4660 * This function also allocates context memory for TQM rings and 4661 * informs the firmware about this allocated backing store memory. 4662 */ 4663 rc = bnxt_hwrm_func_qcaps(bp); 4664 if (rc) 4665 return rc; 4666 4667 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 4668 if (rc) 4669 return rc; 4670 4671 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 4672 if (rc) 4673 return rc; 4674 4675 /* Get the adapter error recovery support info */ 4676 rc = bnxt_hwrm_error_recovery_qcfg(bp); 4677 if (rc) 4678 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 4679 4680 bnxt_hwrm_port_led_qcaps(bp); 4681 4682 return 0; 4683 } 4684 4685 static int 4686 bnxt_init_locks(struct bnxt *bp) 4687 { 4688 int err; 4689 4690 err = pthread_mutex_init(&bp->flow_lock, NULL); 4691 if (err) { 4692 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 4693 return err; 4694 } 4695 4696 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 4697 if (err) 4698 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 4699 return err; 4700 } 4701 4702 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 4703 { 4704 int rc; 4705 4706 rc = bnxt_init_fw(bp); 4707 if (rc) 4708 return rc; 4709 4710 if (!reconfig_dev) { 4711 rc = bnxt_setup_mac_addr(bp->eth_dev); 4712 if (rc) 4713 return rc; 4714 } else { 4715 rc = bnxt_restore_dflt_mac(bp); 4716 if (rc) 4717 return rc; 4718 } 4719 4720 bnxt_config_vf_req_fwd(bp); 4721 4722 rc = bnxt_hwrm_func_driver_register(bp); 4723 if (rc) { 4724 PMD_DRV_LOG(ERR, "Failed to register driver"); 4725 return -EBUSY; 4726 } 4727 4728 if (BNXT_PF(bp)) { 4729 if (bp->pdev->max_vfs) { 4730 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 4731 if (rc) { 4732 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 4733 return rc; 4734 } 4735 } else { 4736 rc = bnxt_hwrm_allocate_pf_only(bp); 4737 if (rc) { 4738 PMD_DRV_LOG(ERR, 4739 "Failed to allocate PF resources"); 4740 return rc; 4741 } 4742 } 4743 } 4744 4745 rc = bnxt_alloc_mem(bp, reconfig_dev); 4746 if (rc) 4747 return rc; 4748 4749 rc = bnxt_setup_int(bp); 4750 if (rc) 4751 return rc; 4752 4753 rc = bnxt_request_int(bp); 4754 if (rc) 4755 return rc; 4756 4757 rc = bnxt_init_locks(bp); 4758 if (rc) 4759 return rc; 4760 4761 return 0; 4762 } 4763 4764 static int 4765 bnxt_dev_init(struct rte_eth_dev *eth_dev) 4766 { 4767 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4768 static int version_printed; 4769 struct bnxt *bp; 4770 int rc; 4771 4772 if (version_printed++ == 0) 4773 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 4774 4775 eth_dev->dev_ops = &bnxt_dev_ops; 4776 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 4777 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 4778 4779 /* 4780 * For secondary processes, we don't initialise any further 4781 * as primary has already done this work. 4782 */ 4783 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 4784 return 0; 4785 4786 rte_eth_copy_pci_info(eth_dev, pci_dev); 4787 4788 bp = eth_dev->data->dev_private; 4789 4790 bp->dev_stopped = 1; 4791 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 4792 4793 if (bnxt_vf_pciid(pci_dev->id.device_id)) 4794 bp->flags |= BNXT_FLAG_VF; 4795 4796 if (bnxt_thor_device(pci_dev->id.device_id)) 4797 bp->flags |= BNXT_FLAG_THOR_CHIP; 4798 4799 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 4800 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 4801 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 4802 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 4803 bp->flags |= BNXT_FLAG_STINGRAY; 4804 4805 rc = bnxt_init_board(eth_dev); 4806 if (rc) { 4807 PMD_DRV_LOG(ERR, 4808 "Failed to initialize board rc: %x\n", rc); 4809 return rc; 4810 } 4811 4812 rc = bnxt_alloc_hwrm_resources(bp); 4813 if (rc) { 4814 PMD_DRV_LOG(ERR, 4815 "Failed to allocate hwrm resource rc: %x\n", rc); 4816 goto error_free; 4817 } 4818 rc = bnxt_init_resources(bp, false); 4819 if (rc) 4820 goto error_free; 4821 4822 rc = bnxt_alloc_stats_mem(bp); 4823 if (rc) 4824 goto error_free; 4825 4826 PMD_DRV_LOG(INFO, 4827 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", 4828 pci_dev->mem_resource[0].phys_addr, 4829 pci_dev->mem_resource[0].addr); 4830 4831 return 0; 4832 4833 error_free: 4834 bnxt_dev_uninit(eth_dev); 4835 return rc; 4836 } 4837 4838 static void 4839 bnxt_uninit_locks(struct bnxt *bp) 4840 { 4841 pthread_mutex_destroy(&bp->flow_lock); 4842 pthread_mutex_destroy(&bp->def_cp_lock); 4843 } 4844 4845 static int 4846 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 4847 { 4848 int rc; 4849 4850 bnxt_free_int(bp); 4851 bnxt_free_mem(bp, reconfig_dev); 4852 bnxt_hwrm_func_buf_unrgtr(bp); 4853 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 4854 bp->flags &= ~BNXT_FLAG_REGISTERED; 4855 bnxt_free_ctx_mem(bp); 4856 if (!reconfig_dev) { 4857 bnxt_free_hwrm_resources(bp); 4858 4859 if (bp->recovery_info != NULL) { 4860 rte_free(bp->recovery_info); 4861 bp->recovery_info = NULL; 4862 } 4863 } 4864 4865 bnxt_uninit_locks(bp); 4866 rte_free(bp->ptp_cfg); 4867 bp->ptp_cfg = NULL; 4868 return rc; 4869 } 4870 4871 static int 4872 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 4873 { 4874 struct bnxt *bp = eth_dev->data->dev_private; 4875 int rc; 4876 4877 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 4878 return -EPERM; 4879 4880 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 4881 4882 rc = bnxt_uninit_resources(bp, false); 4883 4884 if (bp->tx_mem_zone) { 4885 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 4886 bp->tx_mem_zone = NULL; 4887 } 4888 4889 if (bp->rx_mem_zone) { 4890 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 4891 bp->rx_mem_zone = NULL; 4892 } 4893 4894 if (bp->dev_stopped == 0) 4895 bnxt_dev_close_op(eth_dev); 4896 if (bp->pf.vf_info) 4897 rte_free(bp->pf.vf_info); 4898 eth_dev->dev_ops = NULL; 4899 eth_dev->rx_pkt_burst = NULL; 4900 eth_dev->tx_pkt_burst = NULL; 4901 4902 return rc; 4903 } 4904 4905 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 4906 struct rte_pci_device *pci_dev) 4907 { 4908 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt), 4909 bnxt_dev_init); 4910 } 4911 4912 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 4913 { 4914 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 4915 return rte_eth_dev_pci_generic_remove(pci_dev, 4916 bnxt_dev_uninit); 4917 else 4918 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 4919 } 4920 4921 static struct rte_pci_driver bnxt_rte_pmd = { 4922 .id_table = bnxt_pci_id_map, 4923 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 4924 .probe = bnxt_pci_probe, 4925 .remove = bnxt_pci_remove, 4926 }; 4927 4928 static bool 4929 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 4930 { 4931 if (strcmp(dev->device->driver->name, drv->driver.name)) 4932 return false; 4933 4934 return true; 4935 } 4936 4937 bool is_bnxt_supported(struct rte_eth_dev *dev) 4938 { 4939 return is_device_supported(dev, &bnxt_rte_pmd); 4940 } 4941 4942 RTE_INIT(bnxt_init_log) 4943 { 4944 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver"); 4945 if (bnxt_logtype_driver >= 0) 4946 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE); 4947 } 4948 4949 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 4950 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 4951 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 4952