1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <rte_ethdev_driver.h> 11 #include <rte_ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 15 #include "bnxt.h" 16 #include "bnxt_cpr.h" 17 #include "bnxt_filter.h" 18 #include "bnxt_hwrm.h" 19 #include "bnxt_irq.h" 20 #include "bnxt_ring.h" 21 #include "bnxt_rxq.h" 22 #include "bnxt_rxr.h" 23 #include "bnxt_stats.h" 24 #include "bnxt_txq.h" 25 #include "bnxt_txr.h" 26 #include "bnxt_vnic.h" 27 #include "hsi_struct_def_dpdk.h" 28 #include "bnxt_nvm_defs.h" 29 #include "bnxt_util.h" 30 31 #define DRV_MODULE_NAME "bnxt" 32 static const char bnxt_version[] = 33 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 34 int bnxt_logtype_driver; 35 36 #define PCI_VENDOR_ID_BROADCOM 0x14E4 37 38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 41 #define BROADCOM_DEV_ID_57414_VF 0x16c1 42 #define BROADCOM_DEV_ID_57301 0x16c8 43 #define BROADCOM_DEV_ID_57302 0x16c9 44 #define BROADCOM_DEV_ID_57304_PF 0x16ca 45 #define BROADCOM_DEV_ID_57304_VF 0x16cb 46 #define BROADCOM_DEV_ID_57417_MF 0x16cc 47 #define BROADCOM_DEV_ID_NS2 0x16cd 48 #define BROADCOM_DEV_ID_57311 0x16ce 49 #define BROADCOM_DEV_ID_57312 0x16cf 50 #define BROADCOM_DEV_ID_57402 0x16d0 51 #define BROADCOM_DEV_ID_57404 0x16d1 52 #define BROADCOM_DEV_ID_57406_PF 0x16d2 53 #define BROADCOM_DEV_ID_57406_VF 0x16d3 54 #define BROADCOM_DEV_ID_57402_MF 0x16d4 55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5 56 #define BROADCOM_DEV_ID_57412 0x16d6 57 #define BROADCOM_DEV_ID_57414 0x16d7 58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 61 #define BROADCOM_DEV_ID_57412_MF 0x16de 62 #define BROADCOM_DEV_ID_57314 0x16df 63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 68 #define BROADCOM_DEV_ID_57404_MF 0x16e7 69 #define BROADCOM_DEV_ID_57406_MF 0x16e8 70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9 71 #define BROADCOM_DEV_ID_57407_MF 0x16ea 72 #define BROADCOM_DEV_ID_57414_MF 0x16ec 73 #define BROADCOM_DEV_ID_57416_MF 0x16ee 74 #define BROADCOM_DEV_ID_57508 0x1750 75 #define BROADCOM_DEV_ID_57504 0x1751 76 #define BROADCOM_DEV_ID_57502 0x1752 77 #define BROADCOM_DEV_ID_57500_VF1 0x1806 78 #define BROADCOM_DEV_ID_57500_VF2 0x1807 79 #define BROADCOM_DEV_ID_58802 0xd802 80 #define BROADCOM_DEV_ID_58804 0xd804 81 #define BROADCOM_DEV_ID_58808 0x16f0 82 #define BROADCOM_DEV_ID_58802_VF 0xd800 83 84 static const struct rte_pci_id bnxt_pci_id_map[] = { 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 86 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 88 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, 101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, 102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, 103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, 105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, 111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, 112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 132 { .vendor_id = 0, /* sentinel */ }, 133 }; 134 135 #define BNXT_ETH_RSS_SUPPORT ( \ 136 ETH_RSS_IPV4 | \ 137 ETH_RSS_NONFRAG_IPV4_TCP | \ 138 ETH_RSS_NONFRAG_IPV4_UDP | \ 139 ETH_RSS_IPV6 | \ 140 ETH_RSS_NONFRAG_IPV6_TCP | \ 141 ETH_RSS_NONFRAG_IPV6_UDP) 142 143 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 144 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 145 DEV_TX_OFFLOAD_TCP_CKSUM | \ 146 DEV_TX_OFFLOAD_UDP_CKSUM | \ 147 DEV_TX_OFFLOAD_TCP_TSO | \ 148 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 149 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 150 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 151 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 152 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 153 DEV_TX_OFFLOAD_MULTI_SEGS) 154 155 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 156 DEV_RX_OFFLOAD_VLAN_STRIP | \ 157 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 158 DEV_RX_OFFLOAD_UDP_CKSUM | \ 159 DEV_RX_OFFLOAD_TCP_CKSUM | \ 160 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 161 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 162 DEV_RX_OFFLOAD_KEEP_CRC | \ 163 DEV_RX_OFFLOAD_TCP_LRO) 164 165 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 166 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 167 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 168 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 169 170 /***********************/ 171 172 /* 173 * High level utility functions 174 */ 175 176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 177 { 178 if (!BNXT_CHIP_THOR(bp)) 179 return 1; 180 181 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings, 182 BNXT_RSS_ENTRIES_PER_CTX_THOR) / 183 BNXT_RSS_ENTRIES_PER_CTX_THOR; 184 } 185 186 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 187 { 188 if (!BNXT_CHIP_THOR(bp)) 189 return HW_HASH_INDEX_SIZE; 190 191 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR; 192 } 193 194 static void bnxt_free_mem(struct bnxt *bp) 195 { 196 bnxt_free_filter_mem(bp); 197 bnxt_free_vnic_attributes(bp); 198 bnxt_free_vnic_mem(bp); 199 200 bnxt_free_stats(bp); 201 bnxt_free_tx_rings(bp); 202 bnxt_free_rx_rings(bp); 203 bnxt_free_async_cp_ring(bp); 204 } 205 206 static int bnxt_alloc_mem(struct bnxt *bp) 207 { 208 int rc; 209 210 rc = bnxt_alloc_async_ring_struct(bp); 211 if (rc) 212 goto alloc_mem_err; 213 214 rc = bnxt_alloc_vnic_mem(bp); 215 if (rc) 216 goto alloc_mem_err; 217 218 rc = bnxt_alloc_vnic_attributes(bp); 219 if (rc) 220 goto alloc_mem_err; 221 222 rc = bnxt_alloc_filter_mem(bp); 223 if (rc) 224 goto alloc_mem_err; 225 226 rc = bnxt_alloc_async_cp_ring(bp); 227 if (rc) 228 goto alloc_mem_err; 229 230 return 0; 231 232 alloc_mem_err: 233 bnxt_free_mem(bp); 234 return rc; 235 } 236 237 static int bnxt_init_chip(struct bnxt *bp) 238 { 239 struct bnxt_rx_queue *rxq; 240 struct rte_eth_link new; 241 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 242 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 243 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 244 uint64_t rx_offloads = dev_conf->rxmode.offloads; 245 uint32_t intr_vector = 0; 246 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 247 uint32_t vec = BNXT_MISC_VEC_ID; 248 unsigned int i, j; 249 int rc; 250 251 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 252 bp->eth_dev->data->dev_conf.rxmode.offloads |= 253 DEV_RX_OFFLOAD_JUMBO_FRAME; 254 bp->flags |= BNXT_FLAG_JUMBO; 255 } else { 256 bp->eth_dev->data->dev_conf.rxmode.offloads &= 257 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 258 bp->flags &= ~BNXT_FLAG_JUMBO; 259 } 260 261 /* THOR does not support ring groups. 262 * But we will use the array to save RSS context IDs. 263 */ 264 if (BNXT_CHIP_THOR(bp)) 265 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR; 266 267 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 268 if (rc) { 269 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 270 goto err_out; 271 } 272 273 rc = bnxt_alloc_hwrm_rings(bp); 274 if (rc) { 275 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 276 goto err_out; 277 } 278 279 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 280 if (rc) { 281 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 282 goto err_out; 283 } 284 285 rc = bnxt_mq_rx_configure(bp); 286 if (rc) { 287 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 288 goto err_out; 289 } 290 291 /* VNIC configuration */ 292 for (i = 0; i < bp->nr_vnics; i++) { 293 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 294 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 295 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps; 296 297 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0); 298 if (!vnic->fw_grp_ids) { 299 PMD_DRV_LOG(ERR, 300 "Failed to alloc %d bytes for group ids\n", 301 size); 302 rc = -ENOMEM; 303 goto err_out; 304 } 305 memset(vnic->fw_grp_ids, -1, size); 306 307 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 308 i, vnic, vnic->fw_grp_ids); 309 310 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 311 if (rc) { 312 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n", 313 i, rc); 314 goto err_out; 315 } 316 317 /* Alloc RSS context only if RSS mode is enabled */ 318 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 319 int j, nr_ctxs = bnxt_rss_ctxts(bp); 320 321 rc = 0; 322 for (j = 0; j < nr_ctxs; j++) { 323 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 324 if (rc) 325 break; 326 } 327 if (rc) { 328 PMD_DRV_LOG(ERR, 329 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 330 i, j, rc); 331 goto err_out; 332 } 333 vnic->num_lb_ctxts = nr_ctxs; 334 } 335 336 /* 337 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 338 * setting is not available at this time, it will not be 339 * configured correctly in the CFA. 340 */ 341 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 342 vnic->vlan_strip = true; 343 else 344 vnic->vlan_strip = false; 345 346 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 347 if (rc) { 348 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 349 i, rc); 350 goto err_out; 351 } 352 353 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 354 if (rc) { 355 PMD_DRV_LOG(ERR, 356 "HWRM vnic %d filter failure rc: %x\n", 357 i, rc); 358 goto err_out; 359 } 360 361 for (j = 0; j < bp->rx_nr_rings; j++) { 362 rxq = bp->eth_dev->data->rx_queues[j]; 363 364 PMD_DRV_LOG(DEBUG, 365 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 366 j, rxq->vnic, rxq->vnic->fw_grp_ids); 367 368 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 369 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 370 } 371 372 rc = bnxt_vnic_rss_configure(bp, vnic); 373 if (rc) { 374 PMD_DRV_LOG(ERR, 375 "HWRM vnic set RSS failure rc: %x\n", rc); 376 goto err_out; 377 } 378 379 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 380 381 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 382 DEV_RX_OFFLOAD_TCP_LRO) 383 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 384 else 385 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 386 } 387 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 388 if (rc) { 389 PMD_DRV_LOG(ERR, 390 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 391 goto err_out; 392 } 393 394 /* check and configure queue intr-vector mapping */ 395 if ((rte_intr_cap_multiple(intr_handle) || 396 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 397 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 398 intr_vector = bp->eth_dev->data->nb_rx_queues; 399 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 400 if (intr_vector > bp->rx_cp_nr_rings) { 401 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 402 bp->rx_cp_nr_rings); 403 return -ENOTSUP; 404 } 405 rc = rte_intr_efd_enable(intr_handle, intr_vector); 406 if (rc) 407 return rc; 408 } 409 410 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 411 intr_handle->intr_vec = 412 rte_zmalloc("intr_vec", 413 bp->eth_dev->data->nb_rx_queues * 414 sizeof(int), 0); 415 if (intr_handle->intr_vec == NULL) { 416 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 417 " intr_vec", bp->eth_dev->data->nb_rx_queues); 418 rc = -ENOMEM; 419 goto err_disable; 420 } 421 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 422 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 423 intr_handle->intr_vec, intr_handle->nb_efd, 424 intr_handle->max_intr); 425 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 426 queue_id++) { 427 intr_handle->intr_vec[queue_id] = 428 vec + BNXT_RX_VEC_START; 429 if (vec < base + intr_handle->nb_efd - 1) 430 vec++; 431 } 432 } 433 434 /* enable uio/vfio intr/eventfd mapping */ 435 rc = rte_intr_enable(intr_handle); 436 if (rc) 437 goto err_free; 438 439 rc = bnxt_get_hwrm_link_config(bp, &new); 440 if (rc) { 441 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc); 442 goto err_free; 443 } 444 445 if (!bp->link_info.link_up) { 446 rc = bnxt_set_hwrm_link_config(bp, true); 447 if (rc) { 448 PMD_DRV_LOG(ERR, 449 "HWRM link config failure rc: %x\n", rc); 450 goto err_free; 451 } 452 } 453 bnxt_print_link_info(bp->eth_dev); 454 455 return 0; 456 457 err_free: 458 rte_free(intr_handle->intr_vec); 459 err_disable: 460 rte_intr_efd_disable(intr_handle); 461 err_out: 462 /* Some of the error status returned by FW may not be from errno.h */ 463 if (rc > 0) 464 rc = -EIO; 465 466 return rc; 467 } 468 469 static int bnxt_shutdown_nic(struct bnxt *bp) 470 { 471 bnxt_free_all_hwrm_resources(bp); 472 bnxt_free_all_filters(bp); 473 bnxt_free_all_vnics(bp); 474 return 0; 475 } 476 477 static int bnxt_init_nic(struct bnxt *bp) 478 { 479 int rc; 480 481 if (BNXT_HAS_RING_GRPS(bp)) { 482 rc = bnxt_init_ring_grps(bp); 483 if (rc) 484 return rc; 485 } 486 487 bnxt_init_vnics(bp); 488 bnxt_init_filters(bp); 489 490 return 0; 491 } 492 493 /* 494 * Device configuration and status function 495 */ 496 497 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 498 struct rte_eth_dev_info *dev_info) 499 { 500 struct bnxt *bp = eth_dev->data->dev_private; 501 uint16_t max_vnics, i, j, vpool, vrxq; 502 unsigned int max_rx_rings; 503 504 /* MAC Specifics */ 505 dev_info->max_mac_addrs = bp->max_l2_ctx; 506 dev_info->max_hash_mac_addrs = 0; 507 508 /* PF/VF specifics */ 509 if (BNXT_PF(bp)) 510 dev_info->max_vfs = bp->pdev->max_vfs; 511 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx); 512 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 513 dev_info->max_rx_queues = max_rx_rings; 514 dev_info->max_tx_queues = max_rx_rings; 515 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 516 dev_info->hash_key_size = 40; 517 max_vnics = bp->max_vnics; 518 519 /* Fast path specifics */ 520 dev_info->min_rx_bufsize = 1; 521 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN + 522 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; 523 524 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 525 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 526 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 527 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT; 528 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 529 530 /* *INDENT-OFF* */ 531 dev_info->default_rxconf = (struct rte_eth_rxconf) { 532 .rx_thresh = { 533 .pthresh = 8, 534 .hthresh = 8, 535 .wthresh = 0, 536 }, 537 .rx_free_thresh = 32, 538 /* If no descriptors available, pkts are dropped by default */ 539 .rx_drop_en = 1, 540 }; 541 542 dev_info->default_txconf = (struct rte_eth_txconf) { 543 .tx_thresh = { 544 .pthresh = 32, 545 .hthresh = 0, 546 .wthresh = 0, 547 }, 548 .tx_free_thresh = 32, 549 .tx_rs_thresh = 32, 550 }; 551 eth_dev->data->dev_conf.intr_conf.lsc = 1; 552 553 eth_dev->data->dev_conf.intr_conf.rxq = 1; 554 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 555 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 556 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 557 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 558 559 /* *INDENT-ON* */ 560 561 /* 562 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 563 * need further investigation. 564 */ 565 566 /* VMDq resources */ 567 vpool = 64; /* ETH_64_POOLS */ 568 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 569 for (i = 0; i < 4; vpool >>= 1, i++) { 570 if (max_vnics > vpool) { 571 for (j = 0; j < 5; vrxq >>= 1, j++) { 572 if (dev_info->max_rx_queues > vrxq) { 573 if (vpool > vrxq) 574 vpool = vrxq; 575 goto found; 576 } 577 } 578 /* Not enough resources to support VMDq */ 579 break; 580 } 581 } 582 /* Not enough resources to support VMDq */ 583 vpool = 0; 584 vrxq = 0; 585 found: 586 dev_info->max_vmdq_pools = vpool; 587 dev_info->vmdq_queue_num = vrxq; 588 589 dev_info->vmdq_pool_base = 0; 590 dev_info->vmdq_queue_base = 0; 591 } 592 593 /* Configure the device based on the configuration provided */ 594 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 595 { 596 struct bnxt *bp = eth_dev->data->dev_private; 597 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 598 int rc; 599 600 bp->rx_queues = (void *)eth_dev->data->rx_queues; 601 bp->tx_queues = (void *)eth_dev->data->tx_queues; 602 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 603 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 604 605 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 606 rc = bnxt_hwrm_check_vf_rings(bp); 607 if (rc) { 608 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 609 return -ENOSPC; 610 } 611 612 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 613 if (rc) { 614 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 615 return -ENOSPC; 616 } 617 } else { 618 /* legacy driver needs to get updated values */ 619 rc = bnxt_hwrm_func_qcaps(bp); 620 if (rc) { 621 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc); 622 return rc; 623 } 624 } 625 626 /* Inherit new configurations */ 627 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 628 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 629 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 630 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 631 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 632 bp->max_stat_ctx) 633 goto resource_error; 634 635 if (BNXT_HAS_RING_GRPS(bp) && 636 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 637 goto resource_error; 638 639 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 640 bp->max_vnics < eth_dev->data->nb_rx_queues) 641 goto resource_error; 642 643 bp->rx_cp_nr_rings = bp->rx_nr_rings; 644 bp->tx_cp_nr_rings = bp->tx_nr_rings; 645 646 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 647 eth_dev->data->mtu = 648 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 649 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 650 BNXT_NUM_VLANS; 651 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 652 } 653 return 0; 654 655 resource_error: 656 PMD_DRV_LOG(ERR, 657 "Insufficient resources to support requested config\n"); 658 PMD_DRV_LOG(ERR, 659 "Num Queues Requested: Tx %d, Rx %d\n", 660 eth_dev->data->nb_tx_queues, 661 eth_dev->data->nb_rx_queues); 662 PMD_DRV_LOG(ERR, 663 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 664 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 665 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 666 return -ENOSPC; 667 } 668 669 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 670 { 671 struct rte_eth_link *link = ð_dev->data->dev_link; 672 673 if (link->link_status) 674 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 675 eth_dev->data->port_id, 676 (uint32_t)link->link_speed, 677 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 678 ("full-duplex") : ("half-duplex\n")); 679 else 680 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 681 eth_dev->data->port_id); 682 } 683 684 /* 685 * Determine whether the current configuration requires support for scattered 686 * receive; return 1 if scattered receive is required and 0 if not. 687 */ 688 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 689 { 690 uint16_t buf_size; 691 int i; 692 693 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 694 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 695 696 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 697 RTE_PKTMBUF_HEADROOM); 698 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 699 return 1; 700 } 701 return 0; 702 } 703 704 static eth_rx_burst_t 705 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev) 706 { 707 #ifdef RTE_ARCH_X86 708 /* 709 * Vector mode receive can be enabled only if scatter rx is not 710 * in use and rx offloads are limited to VLAN stripping and 711 * CRC stripping. 712 */ 713 if (!eth_dev->data->scattered_rx && 714 !(eth_dev->data->dev_conf.rxmode.offloads & 715 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 716 DEV_RX_OFFLOAD_KEEP_CRC | 717 DEV_RX_OFFLOAD_JUMBO_FRAME | 718 DEV_RX_OFFLOAD_IPV4_CKSUM | 719 DEV_RX_OFFLOAD_UDP_CKSUM | 720 DEV_RX_OFFLOAD_TCP_CKSUM | 721 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 722 DEV_RX_OFFLOAD_VLAN_FILTER))) { 723 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 724 eth_dev->data->port_id); 725 return bnxt_recv_pkts_vec; 726 } 727 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 728 eth_dev->data->port_id); 729 PMD_DRV_LOG(INFO, 730 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 731 eth_dev->data->port_id, 732 eth_dev->data->scattered_rx, 733 eth_dev->data->dev_conf.rxmode.offloads); 734 #endif 735 return bnxt_recv_pkts; 736 } 737 738 static eth_tx_burst_t 739 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) 740 { 741 #ifdef RTE_ARCH_X86 742 /* 743 * Vector mode transmit can be enabled only if not using scatter rx 744 * or tx offloads. 745 */ 746 if (!eth_dev->data->scattered_rx && 747 !eth_dev->data->dev_conf.txmode.offloads) { 748 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 749 eth_dev->data->port_id); 750 return bnxt_xmit_pkts_vec; 751 } 752 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 753 eth_dev->data->port_id); 754 PMD_DRV_LOG(INFO, 755 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 756 eth_dev->data->port_id, 757 eth_dev->data->scattered_rx, 758 eth_dev->data->dev_conf.txmode.offloads); 759 #endif 760 return bnxt_xmit_pkts; 761 } 762 763 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 764 { 765 struct bnxt *bp = eth_dev->data->dev_private; 766 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 767 int vlan_mask = 0; 768 int rc; 769 770 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) { 771 PMD_DRV_LOG(ERR, 772 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 773 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 774 } 775 776 rc = bnxt_init_chip(bp); 777 if (rc) 778 goto error; 779 780 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 781 782 bnxt_link_update_op(eth_dev, 1); 783 784 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 785 vlan_mask |= ETH_VLAN_FILTER_MASK; 786 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 787 vlan_mask |= ETH_VLAN_STRIP_MASK; 788 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 789 if (rc) 790 goto error; 791 792 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 793 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 794 bnxt_enable_int(bp); 795 bp->flags |= BNXT_FLAG_INIT_DONE; 796 bp->dev_stopped = 0; 797 return 0; 798 799 error: 800 bnxt_shutdown_nic(bp); 801 bnxt_free_tx_mbufs(bp); 802 bnxt_free_rx_mbufs(bp); 803 return rc; 804 } 805 806 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 807 { 808 struct bnxt *bp = eth_dev->data->dev_private; 809 int rc = 0; 810 811 if (!bp->link_info.link_up) 812 rc = bnxt_set_hwrm_link_config(bp, true); 813 if (!rc) 814 eth_dev->data->dev_link.link_status = 1; 815 816 bnxt_print_link_info(eth_dev); 817 return 0; 818 } 819 820 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 821 { 822 struct bnxt *bp = eth_dev->data->dev_private; 823 824 eth_dev->data->dev_link.link_status = 0; 825 bnxt_set_hwrm_link_config(bp, false); 826 bp->link_info.link_up = 0; 827 828 return 0; 829 } 830 831 /* Unload the driver, release resources */ 832 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 833 { 834 struct bnxt *bp = eth_dev->data->dev_private; 835 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 836 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 837 838 bnxt_disable_int(bp); 839 840 /* disable uio/vfio intr/eventfd mapping */ 841 rte_intr_disable(intr_handle); 842 843 bp->flags &= ~BNXT_FLAG_INIT_DONE; 844 if (bp->eth_dev->data->dev_started) { 845 /* TBD: STOP HW queues DMA */ 846 eth_dev->data->dev_link.link_status = 0; 847 } 848 bnxt_set_hwrm_link_config(bp, false); 849 850 /* Clean queue intr-vector mapping */ 851 rte_intr_efd_disable(intr_handle); 852 if (intr_handle->intr_vec != NULL) { 853 rte_free(intr_handle->intr_vec); 854 intr_handle->intr_vec = NULL; 855 } 856 857 bnxt_hwrm_port_clr_stats(bp); 858 bnxt_free_tx_mbufs(bp); 859 bnxt_free_rx_mbufs(bp); 860 bnxt_shutdown_nic(bp); 861 bp->dev_stopped = 1; 862 } 863 864 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 865 { 866 struct bnxt *bp = eth_dev->data->dev_private; 867 868 if (bp->dev_stopped == 0) 869 bnxt_dev_stop_op(eth_dev); 870 871 if (eth_dev->data->mac_addrs != NULL) { 872 rte_free(eth_dev->data->mac_addrs); 873 eth_dev->data->mac_addrs = NULL; 874 } 875 if (bp->grp_info != NULL) { 876 rte_free(bp->grp_info); 877 bp->grp_info = NULL; 878 } 879 880 bnxt_dev_uninit(eth_dev); 881 } 882 883 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 884 uint32_t index) 885 { 886 struct bnxt *bp = eth_dev->data->dev_private; 887 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 888 struct bnxt_vnic_info *vnic; 889 struct bnxt_filter_info *filter, *temp_filter; 890 uint32_t i; 891 892 /* 893 * Loop through all VNICs from the specified filter flow pools to 894 * remove the corresponding MAC addr filter 895 */ 896 for (i = 0; i < bp->nr_vnics; i++) { 897 if (!(pool_mask & (1ULL << i))) 898 continue; 899 900 vnic = &bp->vnic_info[i]; 901 filter = STAILQ_FIRST(&vnic->filter); 902 while (filter) { 903 temp_filter = STAILQ_NEXT(filter, next); 904 if (filter->mac_index == index) { 905 STAILQ_REMOVE(&vnic->filter, filter, 906 bnxt_filter_info, next); 907 bnxt_hwrm_clear_l2_filter(bp, filter); 908 filter->mac_index = INVALID_MAC_INDEX; 909 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN); 910 STAILQ_INSERT_TAIL(&bp->free_filter_list, 911 filter, next); 912 } 913 filter = temp_filter; 914 } 915 } 916 } 917 918 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 919 struct rte_ether_addr *mac_addr, 920 uint32_t index, uint32_t pool) 921 { 922 struct bnxt *bp = eth_dev->data->dev_private; 923 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 924 struct bnxt_filter_info *filter; 925 int rc = 0; 926 927 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) { 928 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 929 return -ENOTSUP; 930 } 931 932 if (!vnic) { 933 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 934 return -EINVAL; 935 } 936 /* Attach requested MAC address to the new l2_filter */ 937 STAILQ_FOREACH(filter, &vnic->filter, next) { 938 if (filter->mac_index == index) { 939 PMD_DRV_LOG(ERR, 940 "MAC addr already existed for pool %d\n", pool); 941 return 0; 942 } 943 } 944 filter = bnxt_alloc_filter(bp); 945 if (!filter) { 946 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 947 return -ENODEV; 948 } 949 950 filter->mac_index = index; 951 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 952 953 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 954 if (!rc) { 955 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 956 } else { 957 filter->mac_index = INVALID_MAC_INDEX; 958 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN); 959 bnxt_free_filter(bp, filter); 960 } 961 962 return rc; 963 } 964 965 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 966 { 967 int rc = 0; 968 struct bnxt *bp = eth_dev->data->dev_private; 969 struct rte_eth_link new; 970 unsigned int cnt = BNXT_LINK_WAIT_CNT; 971 972 memset(&new, 0, sizeof(new)); 973 do { 974 /* Retrieve link info from hardware */ 975 rc = bnxt_get_hwrm_link_config(bp, &new); 976 if (rc) { 977 new.link_speed = ETH_LINK_SPEED_100M; 978 new.link_duplex = ETH_LINK_FULL_DUPLEX; 979 PMD_DRV_LOG(ERR, 980 "Failed to retrieve link rc = 0x%x!\n", rc); 981 goto out; 982 } 983 984 if (!wait_to_complete || new.link_status) 985 break; 986 987 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 988 } while (cnt--); 989 990 out: 991 /* Timed out or success */ 992 if (new.link_status != eth_dev->data->dev_link.link_status || 993 new.link_speed != eth_dev->data->dev_link.link_speed) { 994 memcpy(ð_dev->data->dev_link, &new, 995 sizeof(struct rte_eth_link)); 996 997 _rte_eth_dev_callback_process(eth_dev, 998 RTE_ETH_EVENT_INTR_LSC, 999 NULL); 1000 1001 bnxt_print_link_info(eth_dev); 1002 } 1003 1004 return rc; 1005 } 1006 1007 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1008 { 1009 struct bnxt *bp = eth_dev->data->dev_private; 1010 struct bnxt_vnic_info *vnic; 1011 1012 if (bp->vnic_info == NULL) 1013 return; 1014 1015 vnic = &bp->vnic_info[0]; 1016 1017 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1018 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1019 } 1020 1021 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1022 { 1023 struct bnxt *bp = eth_dev->data->dev_private; 1024 struct bnxt_vnic_info *vnic; 1025 1026 if (bp->vnic_info == NULL) 1027 return; 1028 1029 vnic = &bp->vnic_info[0]; 1030 1031 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1032 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1033 } 1034 1035 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1036 { 1037 struct bnxt *bp = eth_dev->data->dev_private; 1038 struct bnxt_vnic_info *vnic; 1039 1040 if (bp->vnic_info == NULL) 1041 return; 1042 1043 vnic = &bp->vnic_info[0]; 1044 1045 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1046 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1047 } 1048 1049 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1050 { 1051 struct bnxt *bp = eth_dev->data->dev_private; 1052 struct bnxt_vnic_info *vnic; 1053 1054 if (bp->vnic_info == NULL) 1055 return; 1056 1057 vnic = &bp->vnic_info[0]; 1058 1059 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1060 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1061 } 1062 1063 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1064 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1065 { 1066 if (qid >= bp->rx_nr_rings) 1067 return NULL; 1068 1069 return bp->eth_dev->data->rx_queues[qid]; 1070 } 1071 1072 /* Return rxq corresponding to a given rss table ring/group ID. */ 1073 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1074 { 1075 struct bnxt_rx_queue *rxq; 1076 unsigned int i; 1077 1078 if (!BNXT_HAS_RING_GRPS(bp)) { 1079 for (i = 0; i < bp->rx_nr_rings; i++) { 1080 rxq = bp->eth_dev->data->rx_queues[i]; 1081 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1082 return rxq->index; 1083 } 1084 } else { 1085 for (i = 0; i < bp->rx_nr_rings; i++) { 1086 if (bp->grp_info[i].fw_grp_id == fwr) 1087 return i; 1088 } 1089 } 1090 1091 return INVALID_HW_RING_ID; 1092 } 1093 1094 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1095 struct rte_eth_rss_reta_entry64 *reta_conf, 1096 uint16_t reta_size) 1097 { 1098 struct bnxt *bp = eth_dev->data->dev_private; 1099 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1100 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1101 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1102 uint16_t idx, sft; 1103 int i; 1104 1105 if (!vnic->rss_table) 1106 return -EINVAL; 1107 1108 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1109 return -EINVAL; 1110 1111 if (reta_size != tbl_size) { 1112 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1113 "(%d) must equal the size supported by the hardware " 1114 "(%d)\n", reta_size, tbl_size); 1115 return -EINVAL; 1116 } 1117 1118 for (i = 0; i < reta_size; i++) { 1119 struct bnxt_rx_queue *rxq; 1120 1121 idx = i / RTE_RETA_GROUP_SIZE; 1122 sft = i % RTE_RETA_GROUP_SIZE; 1123 1124 if (!(reta_conf[idx].mask & (1ULL << sft))) 1125 continue; 1126 1127 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1128 if (!rxq) { 1129 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1130 return -EINVAL; 1131 } 1132 1133 if (BNXT_CHIP_THOR(bp)) { 1134 vnic->rss_table[i * 2] = 1135 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1136 vnic->rss_table[i * 2 + 1] = 1137 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1138 } else { 1139 vnic->rss_table[i] = 1140 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1141 } 1142 1143 vnic->rss_table[i] = 1144 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1145 } 1146 1147 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1148 return 0; 1149 } 1150 1151 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1152 struct rte_eth_rss_reta_entry64 *reta_conf, 1153 uint16_t reta_size) 1154 { 1155 struct bnxt *bp = eth_dev->data->dev_private; 1156 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1157 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1158 uint16_t idx, sft, i; 1159 1160 /* Retrieve from the default VNIC */ 1161 if (!vnic) 1162 return -EINVAL; 1163 if (!vnic->rss_table) 1164 return -EINVAL; 1165 1166 if (reta_size != tbl_size) { 1167 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1168 "(%d) must equal the size supported by the hardware " 1169 "(%d)\n", reta_size, tbl_size); 1170 return -EINVAL; 1171 } 1172 1173 for (idx = 0, i = 0; i < reta_size; i++) { 1174 idx = i / RTE_RETA_GROUP_SIZE; 1175 sft = i % RTE_RETA_GROUP_SIZE; 1176 1177 if (reta_conf[idx].mask & (1ULL << sft)) { 1178 uint16_t qid; 1179 1180 if (BNXT_CHIP_THOR(bp)) 1181 qid = bnxt_rss_to_qid(bp, 1182 vnic->rss_table[i * 2]); 1183 else 1184 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 1185 1186 if (qid == INVALID_HW_RING_ID) { 1187 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 1188 return -EINVAL; 1189 } 1190 reta_conf[idx].reta[sft] = qid; 1191 } 1192 } 1193 1194 return 0; 1195 } 1196 1197 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 1198 struct rte_eth_rss_conf *rss_conf) 1199 { 1200 struct bnxt *bp = eth_dev->data->dev_private; 1201 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1202 struct bnxt_vnic_info *vnic; 1203 uint16_t hash_type = 0; 1204 unsigned int i; 1205 1206 /* 1207 * If RSS enablement were different than dev_configure, 1208 * then return -EINVAL 1209 */ 1210 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 1211 if (!rss_conf->rss_hf) 1212 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 1213 } else { 1214 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 1215 return -EINVAL; 1216 } 1217 1218 bp->flags |= BNXT_FLAG_UPDATE_HASH; 1219 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf)); 1220 1221 if (rss_conf->rss_hf & ETH_RSS_IPV4) 1222 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 1223 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 1224 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1225 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 1226 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1227 if (rss_conf->rss_hf & ETH_RSS_IPV6) 1228 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1229 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 1230 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1231 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 1232 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1233 1234 /* Update the RSS VNIC(s) */ 1235 for (i = 0; i < bp->nr_vnics; i++) { 1236 vnic = &bp->vnic_info[i]; 1237 vnic->hash_type = hash_type; 1238 1239 /* 1240 * Use the supplied key if the key length is 1241 * acceptable and the rss_key is not NULL 1242 */ 1243 if (rss_conf->rss_key && 1244 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE) 1245 memcpy(vnic->rss_hash_key, rss_conf->rss_key, 1246 rss_conf->rss_key_len); 1247 1248 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1249 } 1250 return 0; 1251 } 1252 1253 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 1254 struct rte_eth_rss_conf *rss_conf) 1255 { 1256 struct bnxt *bp = eth_dev->data->dev_private; 1257 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1258 int len; 1259 uint32_t hash_types; 1260 1261 /* RSS configuration is the same for all VNICs */ 1262 if (vnic && vnic->rss_hash_key) { 1263 if (rss_conf->rss_key) { 1264 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 1265 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 1266 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 1267 } 1268 1269 hash_types = vnic->hash_type; 1270 rss_conf->rss_hf = 0; 1271 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 1272 rss_conf->rss_hf |= ETH_RSS_IPV4; 1273 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 1274 } 1275 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 1276 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 1277 hash_types &= 1278 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1279 } 1280 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 1281 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 1282 hash_types &= 1283 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1284 } 1285 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 1286 rss_conf->rss_hf |= ETH_RSS_IPV6; 1287 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1288 } 1289 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 1290 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 1291 hash_types &= 1292 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1293 } 1294 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 1295 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 1296 hash_types &= 1297 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1298 } 1299 if (hash_types) { 1300 PMD_DRV_LOG(ERR, 1301 "Unknwon RSS config from firmware (%08x), RSS disabled", 1302 vnic->hash_type); 1303 return -ENOTSUP; 1304 } 1305 } else { 1306 rss_conf->rss_hf = 0; 1307 } 1308 return 0; 1309 } 1310 1311 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 1312 struct rte_eth_fc_conf *fc_conf) 1313 { 1314 struct bnxt *bp = dev->data->dev_private; 1315 struct rte_eth_link link_info; 1316 int rc; 1317 1318 rc = bnxt_get_hwrm_link_config(bp, &link_info); 1319 if (rc) 1320 return rc; 1321 1322 memset(fc_conf, 0, sizeof(*fc_conf)); 1323 if (bp->link_info.auto_pause) 1324 fc_conf->autoneg = 1; 1325 switch (bp->link_info.pause) { 1326 case 0: 1327 fc_conf->mode = RTE_FC_NONE; 1328 break; 1329 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 1330 fc_conf->mode = RTE_FC_TX_PAUSE; 1331 break; 1332 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 1333 fc_conf->mode = RTE_FC_RX_PAUSE; 1334 break; 1335 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 1336 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 1337 fc_conf->mode = RTE_FC_FULL; 1338 break; 1339 } 1340 return 0; 1341 } 1342 1343 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 1344 struct rte_eth_fc_conf *fc_conf) 1345 { 1346 struct bnxt *bp = dev->data->dev_private; 1347 1348 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1349 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 1350 return -ENOTSUP; 1351 } 1352 1353 switch (fc_conf->mode) { 1354 case RTE_FC_NONE: 1355 bp->link_info.auto_pause = 0; 1356 bp->link_info.force_pause = 0; 1357 break; 1358 case RTE_FC_RX_PAUSE: 1359 if (fc_conf->autoneg) { 1360 bp->link_info.auto_pause = 1361 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1362 bp->link_info.force_pause = 0; 1363 } else { 1364 bp->link_info.auto_pause = 0; 1365 bp->link_info.force_pause = 1366 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1367 } 1368 break; 1369 case RTE_FC_TX_PAUSE: 1370 if (fc_conf->autoneg) { 1371 bp->link_info.auto_pause = 1372 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 1373 bp->link_info.force_pause = 0; 1374 } else { 1375 bp->link_info.auto_pause = 0; 1376 bp->link_info.force_pause = 1377 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 1378 } 1379 break; 1380 case RTE_FC_FULL: 1381 if (fc_conf->autoneg) { 1382 bp->link_info.auto_pause = 1383 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 1384 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1385 bp->link_info.force_pause = 0; 1386 } else { 1387 bp->link_info.auto_pause = 0; 1388 bp->link_info.force_pause = 1389 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 1390 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1391 } 1392 break; 1393 } 1394 return bnxt_set_hwrm_link_config(bp, true); 1395 } 1396 1397 /* Add UDP tunneling port */ 1398 static int 1399 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 1400 struct rte_eth_udp_tunnel *udp_tunnel) 1401 { 1402 struct bnxt *bp = eth_dev->data->dev_private; 1403 uint16_t tunnel_type = 0; 1404 int rc = 0; 1405 1406 switch (udp_tunnel->prot_type) { 1407 case RTE_TUNNEL_TYPE_VXLAN: 1408 if (bp->vxlan_port_cnt) { 1409 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1410 udp_tunnel->udp_port); 1411 if (bp->vxlan_port != udp_tunnel->udp_port) { 1412 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1413 return -ENOSPC; 1414 } 1415 bp->vxlan_port_cnt++; 1416 return 0; 1417 } 1418 tunnel_type = 1419 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 1420 bp->vxlan_port_cnt++; 1421 break; 1422 case RTE_TUNNEL_TYPE_GENEVE: 1423 if (bp->geneve_port_cnt) { 1424 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1425 udp_tunnel->udp_port); 1426 if (bp->geneve_port != udp_tunnel->udp_port) { 1427 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1428 return -ENOSPC; 1429 } 1430 bp->geneve_port_cnt++; 1431 return 0; 1432 } 1433 tunnel_type = 1434 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 1435 bp->geneve_port_cnt++; 1436 break; 1437 default: 1438 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1439 return -ENOTSUP; 1440 } 1441 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 1442 tunnel_type); 1443 return rc; 1444 } 1445 1446 static int 1447 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 1448 struct rte_eth_udp_tunnel *udp_tunnel) 1449 { 1450 struct bnxt *bp = eth_dev->data->dev_private; 1451 uint16_t tunnel_type = 0; 1452 uint16_t port = 0; 1453 int rc = 0; 1454 1455 switch (udp_tunnel->prot_type) { 1456 case RTE_TUNNEL_TYPE_VXLAN: 1457 if (!bp->vxlan_port_cnt) { 1458 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1459 return -EINVAL; 1460 } 1461 if (bp->vxlan_port != udp_tunnel->udp_port) { 1462 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1463 udp_tunnel->udp_port, bp->vxlan_port); 1464 return -EINVAL; 1465 } 1466 if (--bp->vxlan_port_cnt) 1467 return 0; 1468 1469 tunnel_type = 1470 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 1471 port = bp->vxlan_fw_dst_port_id; 1472 break; 1473 case RTE_TUNNEL_TYPE_GENEVE: 1474 if (!bp->geneve_port_cnt) { 1475 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1476 return -EINVAL; 1477 } 1478 if (bp->geneve_port != udp_tunnel->udp_port) { 1479 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1480 udp_tunnel->udp_port, bp->geneve_port); 1481 return -EINVAL; 1482 } 1483 if (--bp->geneve_port_cnt) 1484 return 0; 1485 1486 tunnel_type = 1487 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 1488 port = bp->geneve_fw_dst_port_id; 1489 break; 1490 default: 1491 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1492 return -ENOTSUP; 1493 } 1494 1495 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 1496 if (!rc) { 1497 if (tunnel_type == 1498 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) 1499 bp->vxlan_port = 0; 1500 if (tunnel_type == 1501 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) 1502 bp->geneve_port = 0; 1503 } 1504 return rc; 1505 } 1506 1507 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1508 { 1509 struct bnxt_filter_info *filter; 1510 struct bnxt_vnic_info *vnic; 1511 int rc = 0; 1512 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 1513 1514 /* if VLAN exists && VLAN matches vlan_id 1515 * remove the MAC+VLAN filter 1516 * add a new MAC only filter 1517 * else 1518 * VLAN filter doesn't exist, just skip and continue 1519 */ 1520 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1521 filter = STAILQ_FIRST(&vnic->filter); 1522 while (filter) { 1523 /* Search for this matching MAC+VLAN filter */ 1524 if (filter->enables & chk && filter->l2_ivlan == vlan_id && 1525 !memcmp(filter->l2_addr, 1526 bp->mac_addr, 1527 RTE_ETHER_ADDR_LEN)) { 1528 /* Delete the filter */ 1529 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 1530 if (rc) 1531 return rc; 1532 STAILQ_REMOVE(&vnic->filter, filter, 1533 bnxt_filter_info, next); 1534 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next); 1535 1536 PMD_DRV_LOG(INFO, 1537 "Del Vlan filter for %d\n", 1538 vlan_id); 1539 return rc; 1540 } 1541 filter = STAILQ_NEXT(filter, next); 1542 } 1543 return -ENOENT; 1544 } 1545 1546 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1547 { 1548 struct bnxt_filter_info *filter; 1549 struct bnxt_vnic_info *vnic; 1550 int rc = 0; 1551 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 1552 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 1553 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 1554 1555 /* Implementation notes on the use of VNIC in this command: 1556 * 1557 * By default, these filters belong to default vnic for the function. 1558 * Once these filters are set up, only destination VNIC can be modified. 1559 * If the destination VNIC is not specified in this command, 1560 * then the HWRM shall only create an l2 context id. 1561 */ 1562 1563 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1564 filter = STAILQ_FIRST(&vnic->filter); 1565 /* Check if the VLAN has already been added */ 1566 while (filter) { 1567 if (filter->enables & chk && filter->l2_ivlan == vlan_id && 1568 !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN)) 1569 return -EEXIST; 1570 1571 filter = STAILQ_NEXT(filter, next); 1572 } 1573 1574 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 1575 * command to create MAC+VLAN filter with the right flags, enables set. 1576 */ 1577 filter = bnxt_alloc_filter(bp); 1578 if (!filter) { 1579 PMD_DRV_LOG(ERR, 1580 "MAC/VLAN filter alloc failed\n"); 1581 return -ENOMEM; 1582 } 1583 /* MAC + VLAN ID filter */ 1584 filter->l2_ivlan = vlan_id; 1585 filter->l2_ivlan_mask = 0x0FFF; 1586 filter->enables |= en; 1587 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1588 if (rc) { 1589 /* Free the newly allocated filter as we were 1590 * not able to create the filter in hardware. 1591 */ 1592 filter->fw_l2_filter_id = UINT64_MAX; 1593 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next); 1594 return rc; 1595 } 1596 1597 /* Add this new filter to the list */ 1598 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1599 PMD_DRV_LOG(INFO, 1600 "Added Vlan filter for %d\n", vlan_id); 1601 return rc; 1602 } 1603 1604 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 1605 uint16_t vlan_id, int on) 1606 { 1607 struct bnxt *bp = eth_dev->data->dev_private; 1608 1609 /* These operations apply to ALL existing MAC/VLAN filters */ 1610 if (on) 1611 return bnxt_add_vlan_filter(bp, vlan_id); 1612 else 1613 return bnxt_del_vlan_filter(bp, vlan_id); 1614 } 1615 1616 static int 1617 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 1618 { 1619 struct bnxt *bp = dev->data->dev_private; 1620 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1621 unsigned int i; 1622 1623 if (mask & ETH_VLAN_FILTER_MASK) { 1624 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 1625 /* Remove any VLAN filters programmed */ 1626 for (i = 0; i < 4095; i++) 1627 bnxt_del_vlan_filter(bp, i); 1628 } 1629 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 1630 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 1631 } 1632 1633 if (mask & ETH_VLAN_STRIP_MASK) { 1634 /* Enable or disable VLAN stripping */ 1635 for (i = 0; i < bp->nr_vnics; i++) { 1636 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1637 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1638 vnic->vlan_strip = true; 1639 else 1640 vnic->vlan_strip = false; 1641 bnxt_hwrm_vnic_cfg(bp, vnic); 1642 } 1643 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 1644 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 1645 } 1646 1647 if (mask & ETH_VLAN_EXTEND_MASK) 1648 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n"); 1649 1650 return 0; 1651 } 1652 1653 static int 1654 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 1655 struct rte_ether_addr *addr) 1656 { 1657 struct bnxt *bp = dev->data->dev_private; 1658 /* Default Filter is tied to VNIC 0 */ 1659 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1660 struct bnxt_filter_info *filter; 1661 int rc; 1662 1663 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 1664 return -EPERM; 1665 1666 if (rte_is_zero_ether_addr(addr)) 1667 return -EINVAL; 1668 1669 STAILQ_FOREACH(filter, &vnic->filter, next) { 1670 /* Default Filter is at Index 0 */ 1671 if (filter->mac_index != 0) 1672 continue; 1673 1674 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN); 1675 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN); 1676 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX; 1677 filter->enables |= 1678 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR | 1679 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK; 1680 1681 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1682 if (rc) 1683 return rc; 1684 1685 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 1686 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 1687 return 0; 1688 } 1689 1690 return 0; 1691 } 1692 1693 static int 1694 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 1695 struct rte_ether_addr *mc_addr_set, 1696 uint32_t nb_mc_addr) 1697 { 1698 struct bnxt *bp = eth_dev->data->dev_private; 1699 char *mc_addr_list = (char *)mc_addr_set; 1700 struct bnxt_vnic_info *vnic; 1701 uint32_t off = 0, i = 0; 1702 1703 vnic = &bp->vnic_info[0]; 1704 1705 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 1706 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1707 goto allmulti; 1708 } 1709 1710 /* TODO Check for Duplicate mcast addresses */ 1711 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1712 for (i = 0; i < nb_mc_addr; i++) { 1713 memcpy(vnic->mc_list + off, &mc_addr_list[i], 1714 RTE_ETHER_ADDR_LEN); 1715 off += RTE_ETHER_ADDR_LEN; 1716 } 1717 1718 vnic->mc_addr_cnt = i; 1719 1720 allmulti: 1721 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1722 } 1723 1724 static int 1725 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 1726 { 1727 struct bnxt *bp = dev->data->dev_private; 1728 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 1729 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 1730 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 1731 int ret; 1732 1733 ret = snprintf(fw_version, fw_size, "%d.%d.%d", 1734 fw_major, fw_minor, fw_updt); 1735 1736 ret += 1; /* add the size of '\0' */ 1737 if (fw_size < (uint32_t)ret) 1738 return ret; 1739 else 1740 return 0; 1741 } 1742 1743 static void 1744 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 1745 struct rte_eth_rxq_info *qinfo) 1746 { 1747 struct bnxt_rx_queue *rxq; 1748 1749 rxq = dev->data->rx_queues[queue_id]; 1750 1751 qinfo->mp = rxq->mb_pool; 1752 qinfo->scattered_rx = dev->data->scattered_rx; 1753 qinfo->nb_desc = rxq->nb_rx_desc; 1754 1755 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 1756 qinfo->conf.rx_drop_en = 0; 1757 qinfo->conf.rx_deferred_start = 0; 1758 } 1759 1760 static void 1761 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 1762 struct rte_eth_txq_info *qinfo) 1763 { 1764 struct bnxt_tx_queue *txq; 1765 1766 txq = dev->data->tx_queues[queue_id]; 1767 1768 qinfo->nb_desc = txq->nb_tx_desc; 1769 1770 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 1771 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 1772 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 1773 1774 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 1775 qinfo->conf.tx_rs_thresh = 0; 1776 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1777 } 1778 1779 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 1780 { 1781 struct bnxt *bp = eth_dev->data->dev_private; 1782 struct rte_eth_dev_info dev_info; 1783 uint32_t new_pkt_size; 1784 uint32_t rc = 0; 1785 uint32_t i; 1786 1787 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 1788 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 1789 1790 bnxt_dev_info_get_op(eth_dev, &dev_info); 1791 1792 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) { 1793 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n", 1794 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU); 1795 return -EINVAL; 1796 } 1797 1798 #ifdef RTE_ARCH_X86 1799 /* 1800 * If vector-mode tx/rx is active, disallow any MTU change that would 1801 * require scattered receive support. 1802 */ 1803 if (eth_dev->data->dev_started && 1804 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec || 1805 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) && 1806 (new_pkt_size > 1807 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 1808 PMD_DRV_LOG(ERR, 1809 "MTU change would require scattered rx support. "); 1810 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 1811 return -EINVAL; 1812 } 1813 #endif 1814 1815 if (new_mtu > RTE_ETHER_MTU) { 1816 bp->flags |= BNXT_FLAG_JUMBO; 1817 bp->eth_dev->data->dev_conf.rxmode.offloads |= 1818 DEV_RX_OFFLOAD_JUMBO_FRAME; 1819 } else { 1820 bp->eth_dev->data->dev_conf.rxmode.offloads &= 1821 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1822 bp->flags &= ~BNXT_FLAG_JUMBO; 1823 } 1824 1825 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 1826 1827 eth_dev->data->mtu = new_mtu; 1828 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu); 1829 1830 for (i = 0; i < bp->nr_vnics; i++) { 1831 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1832 uint16_t size = 0; 1833 1834 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN + 1835 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; 1836 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 1837 if (rc) 1838 break; 1839 1840 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 1841 size -= RTE_PKTMBUF_HEADROOM; 1842 1843 if (size < new_mtu) { 1844 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 1845 if (rc) 1846 return rc; 1847 } 1848 } 1849 1850 return rc; 1851 } 1852 1853 static int 1854 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 1855 { 1856 struct bnxt *bp = dev->data->dev_private; 1857 uint16_t vlan = bp->vlan; 1858 int rc; 1859 1860 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1861 PMD_DRV_LOG(ERR, 1862 "PVID cannot be modified for this function\n"); 1863 return -ENOTSUP; 1864 } 1865 bp->vlan = on ? pvid : 0; 1866 1867 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 1868 if (rc) 1869 bp->vlan = vlan; 1870 return rc; 1871 } 1872 1873 static int 1874 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 1875 { 1876 struct bnxt *bp = dev->data->dev_private; 1877 1878 return bnxt_hwrm_port_led_cfg(bp, true); 1879 } 1880 1881 static int 1882 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 1883 { 1884 struct bnxt *bp = dev->data->dev_private; 1885 1886 return bnxt_hwrm_port_led_cfg(bp, false); 1887 } 1888 1889 static uint32_t 1890 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1891 { 1892 uint32_t desc = 0, raw_cons = 0, cons; 1893 struct bnxt_cp_ring_info *cpr; 1894 struct bnxt_rx_queue *rxq; 1895 struct rx_pkt_cmpl *rxcmp; 1896 uint16_t cmp_type; 1897 uint8_t cmp = 1; 1898 bool valid; 1899 1900 rxq = dev->data->rx_queues[rx_queue_id]; 1901 cpr = rxq->cp_ring; 1902 valid = cpr->valid; 1903 1904 while (raw_cons < rxq->nb_rx_desc) { 1905 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 1906 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1907 1908 if (!CMPL_VALID(rxcmp, valid)) 1909 goto nothing_to_do; 1910 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid); 1911 cmp_type = CMP_TYPE(rxcmp); 1912 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) { 1913 cmp = (rte_le_to_cpu_32( 1914 ((struct rx_tpa_end_cmpl *) 1915 (rxcmp))->agg_bufs_v1) & 1916 RX_TPA_END_CMPL_AGG_BUFS_MASK) >> 1917 RX_TPA_END_CMPL_AGG_BUFS_SFT; 1918 desc++; 1919 } else if (cmp_type == 0x11) { 1920 desc++; 1921 cmp = (rxcmp->agg_bufs_v1 & 1922 RX_PKT_CMPL_AGG_BUFS_MASK) >> 1923 RX_PKT_CMPL_AGG_BUFS_SFT; 1924 } else { 1925 cmp = 1; 1926 } 1927 nothing_to_do: 1928 raw_cons += cmp ? cmp : 2; 1929 } 1930 1931 return desc; 1932 } 1933 1934 static int 1935 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 1936 { 1937 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 1938 struct bnxt_rx_ring_info *rxr; 1939 struct bnxt_cp_ring_info *cpr; 1940 struct bnxt_sw_rx_bd *rx_buf; 1941 struct rx_pkt_cmpl *rxcmp; 1942 uint32_t cons, cp_cons; 1943 1944 if (!rxq) 1945 return -EINVAL; 1946 1947 cpr = rxq->cp_ring; 1948 rxr = rxq->rx_ring; 1949 1950 if (offset >= rxq->nb_rx_desc) 1951 return -EINVAL; 1952 1953 cons = RING_CMP(cpr->cp_ring_struct, offset); 1954 cp_cons = cpr->cp_raw_cons; 1955 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1956 1957 if (cons > cp_cons) { 1958 if (CMPL_VALID(rxcmp, cpr->valid)) 1959 return RTE_ETH_RX_DESC_DONE; 1960 } else { 1961 if (CMPL_VALID(rxcmp, !cpr->valid)) 1962 return RTE_ETH_RX_DESC_DONE; 1963 } 1964 rx_buf = &rxr->rx_buf_ring[cons]; 1965 if (rx_buf->mbuf == NULL) 1966 return RTE_ETH_RX_DESC_UNAVAIL; 1967 1968 1969 return RTE_ETH_RX_DESC_AVAIL; 1970 } 1971 1972 static int 1973 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 1974 { 1975 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 1976 struct bnxt_tx_ring_info *txr; 1977 struct bnxt_cp_ring_info *cpr; 1978 struct bnxt_sw_tx_bd *tx_buf; 1979 struct tx_pkt_cmpl *txcmp; 1980 uint32_t cons, cp_cons; 1981 1982 if (!txq) 1983 return -EINVAL; 1984 1985 cpr = txq->cp_ring; 1986 txr = txq->tx_ring; 1987 1988 if (offset >= txq->nb_tx_desc) 1989 return -EINVAL; 1990 1991 cons = RING_CMP(cpr->cp_ring_struct, offset); 1992 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1993 cp_cons = cpr->cp_raw_cons; 1994 1995 if (cons > cp_cons) { 1996 if (CMPL_VALID(txcmp, cpr->valid)) 1997 return RTE_ETH_TX_DESC_UNAVAIL; 1998 } else { 1999 if (CMPL_VALID(txcmp, !cpr->valid)) 2000 return RTE_ETH_TX_DESC_UNAVAIL; 2001 } 2002 tx_buf = &txr->tx_buf_ring[cons]; 2003 if (tx_buf->mbuf == NULL) 2004 return RTE_ETH_TX_DESC_DONE; 2005 2006 return RTE_ETH_TX_DESC_FULL; 2007 } 2008 2009 static struct bnxt_filter_info * 2010 bnxt_match_and_validate_ether_filter(struct bnxt *bp, 2011 struct rte_eth_ethertype_filter *efilter, 2012 struct bnxt_vnic_info *vnic0, 2013 struct bnxt_vnic_info *vnic, 2014 int *ret) 2015 { 2016 struct bnxt_filter_info *mfilter = NULL; 2017 int match = 0; 2018 *ret = 0; 2019 2020 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 || 2021 efilter->ether_type == RTE_ETHER_TYPE_IPV6) { 2022 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in" 2023 " ethertype filter.", efilter->ether_type); 2024 *ret = -EINVAL; 2025 goto exit; 2026 } 2027 if (efilter->queue >= bp->rx_nr_rings) { 2028 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2029 *ret = -EINVAL; 2030 goto exit; 2031 } 2032 2033 vnic0 = &bp->vnic_info[0]; 2034 vnic = &bp->vnic_info[efilter->queue]; 2035 if (vnic == NULL) { 2036 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2037 *ret = -EINVAL; 2038 goto exit; 2039 } 2040 2041 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2042 STAILQ_FOREACH(mfilter, &vnic0->filter, next) { 2043 if ((!memcmp(efilter->mac_addr.addr_bytes, 2044 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2045 mfilter->flags == 2046 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP && 2047 mfilter->ethertype == efilter->ether_type)) { 2048 match = 1; 2049 break; 2050 } 2051 } 2052 } else { 2053 STAILQ_FOREACH(mfilter, &vnic->filter, next) 2054 if ((!memcmp(efilter->mac_addr.addr_bytes, 2055 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2056 mfilter->ethertype == efilter->ether_type && 2057 mfilter->flags == 2058 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) { 2059 match = 1; 2060 break; 2061 } 2062 } 2063 2064 if (match) 2065 *ret = -EEXIST; 2066 2067 exit: 2068 return mfilter; 2069 } 2070 2071 static int 2072 bnxt_ethertype_filter(struct rte_eth_dev *dev, 2073 enum rte_filter_op filter_op, 2074 void *arg) 2075 { 2076 struct bnxt *bp = dev->data->dev_private; 2077 struct rte_eth_ethertype_filter *efilter = 2078 (struct rte_eth_ethertype_filter *)arg; 2079 struct bnxt_filter_info *bfilter, *filter1; 2080 struct bnxt_vnic_info *vnic, *vnic0; 2081 int ret; 2082 2083 if (filter_op == RTE_ETH_FILTER_NOP) 2084 return 0; 2085 2086 if (arg == NULL) { 2087 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2088 filter_op); 2089 return -EINVAL; 2090 } 2091 2092 vnic0 = &bp->vnic_info[0]; 2093 vnic = &bp->vnic_info[efilter->queue]; 2094 2095 switch (filter_op) { 2096 case RTE_ETH_FILTER_ADD: 2097 bnxt_match_and_validate_ether_filter(bp, efilter, 2098 vnic0, vnic, &ret); 2099 if (ret < 0) 2100 return ret; 2101 2102 bfilter = bnxt_get_unused_filter(bp); 2103 if (bfilter == NULL) { 2104 PMD_DRV_LOG(ERR, 2105 "Not enough resources for a new filter.\n"); 2106 return -ENOMEM; 2107 } 2108 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2109 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes, 2110 RTE_ETHER_ADDR_LEN); 2111 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes, 2112 RTE_ETHER_ADDR_LEN); 2113 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2114 bfilter->ethertype = efilter->ether_type; 2115 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2116 2117 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0); 2118 if (filter1 == NULL) { 2119 ret = -EINVAL; 2120 goto cleanup; 2121 } 2122 bfilter->enables |= 2123 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2124 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2125 2126 bfilter->dst_id = vnic->fw_vnic_id; 2127 2128 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2129 bfilter->flags = 2130 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2131 } 2132 2133 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2134 if (ret) 2135 goto cleanup; 2136 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2137 break; 2138 case RTE_ETH_FILTER_DELETE: 2139 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter, 2140 vnic0, vnic, &ret); 2141 if (ret == -EEXIST) { 2142 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1); 2143 2144 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info, 2145 next); 2146 bnxt_free_filter(bp, filter1); 2147 } else if (ret == 0) { 2148 PMD_DRV_LOG(ERR, "No matching filter found\n"); 2149 } 2150 break; 2151 default: 2152 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2153 ret = -EINVAL; 2154 goto error; 2155 } 2156 return ret; 2157 cleanup: 2158 bnxt_free_filter(bp, bfilter); 2159 error: 2160 return ret; 2161 } 2162 2163 static inline int 2164 parse_ntuple_filter(struct bnxt *bp, 2165 struct rte_eth_ntuple_filter *nfilter, 2166 struct bnxt_filter_info *bfilter) 2167 { 2168 uint32_t en = 0; 2169 2170 if (nfilter->queue >= bp->rx_nr_rings) { 2171 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue); 2172 return -EINVAL; 2173 } 2174 2175 switch (nfilter->dst_port_mask) { 2176 case UINT16_MAX: 2177 bfilter->dst_port_mask = -1; 2178 bfilter->dst_port = nfilter->dst_port; 2179 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT | 2180 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2181 break; 2182 default: 2183 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 2184 return -EINVAL; 2185 } 2186 2187 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2188 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2189 2190 switch (nfilter->proto_mask) { 2191 case UINT8_MAX: 2192 if (nfilter->proto == 17) /* IPPROTO_UDP */ 2193 bfilter->ip_protocol = 17; 2194 else if (nfilter->proto == 6) /* IPPROTO_TCP */ 2195 bfilter->ip_protocol = 6; 2196 else 2197 return -EINVAL; 2198 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2199 break; 2200 default: 2201 PMD_DRV_LOG(ERR, "invalid protocol mask."); 2202 return -EINVAL; 2203 } 2204 2205 switch (nfilter->dst_ip_mask) { 2206 case UINT32_MAX: 2207 bfilter->dst_ipaddr_mask[0] = -1; 2208 bfilter->dst_ipaddr[0] = nfilter->dst_ip; 2209 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR | 2210 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2211 break; 2212 default: 2213 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 2214 return -EINVAL; 2215 } 2216 2217 switch (nfilter->src_ip_mask) { 2218 case UINT32_MAX: 2219 bfilter->src_ipaddr_mask[0] = -1; 2220 bfilter->src_ipaddr[0] = nfilter->src_ip; 2221 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR | 2222 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2223 break; 2224 default: 2225 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 2226 return -EINVAL; 2227 } 2228 2229 switch (nfilter->src_port_mask) { 2230 case UINT16_MAX: 2231 bfilter->src_port_mask = -1; 2232 bfilter->src_port = nfilter->src_port; 2233 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT | 2234 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2235 break; 2236 default: 2237 PMD_DRV_LOG(ERR, "invalid src_port mask."); 2238 return -EINVAL; 2239 } 2240 2241 //TODO Priority 2242 //nfilter->priority = (uint8_t)filter->priority; 2243 2244 bfilter->enables = en; 2245 return 0; 2246 } 2247 2248 static struct bnxt_filter_info* 2249 bnxt_match_ntuple_filter(struct bnxt *bp, 2250 struct bnxt_filter_info *bfilter, 2251 struct bnxt_vnic_info **mvnic) 2252 { 2253 struct bnxt_filter_info *mfilter = NULL; 2254 int i; 2255 2256 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2257 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2258 STAILQ_FOREACH(mfilter, &vnic->filter, next) { 2259 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] && 2260 bfilter->src_ipaddr_mask[0] == 2261 mfilter->src_ipaddr_mask[0] && 2262 bfilter->src_port == mfilter->src_port && 2263 bfilter->src_port_mask == mfilter->src_port_mask && 2264 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] && 2265 bfilter->dst_ipaddr_mask[0] == 2266 mfilter->dst_ipaddr_mask[0] && 2267 bfilter->dst_port == mfilter->dst_port && 2268 bfilter->dst_port_mask == mfilter->dst_port_mask && 2269 bfilter->flags == mfilter->flags && 2270 bfilter->enables == mfilter->enables) { 2271 if (mvnic) 2272 *mvnic = vnic; 2273 return mfilter; 2274 } 2275 } 2276 } 2277 return NULL; 2278 } 2279 2280 static int 2281 bnxt_cfg_ntuple_filter(struct bnxt *bp, 2282 struct rte_eth_ntuple_filter *nfilter, 2283 enum rte_filter_op filter_op) 2284 { 2285 struct bnxt_filter_info *bfilter, *mfilter, *filter1; 2286 struct bnxt_vnic_info *vnic, *vnic0, *mvnic; 2287 int ret; 2288 2289 if (nfilter->flags != RTE_5TUPLE_FLAGS) { 2290 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 2291 return -EINVAL; 2292 } 2293 2294 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) { 2295 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n"); 2296 return -EINVAL; 2297 } 2298 2299 bfilter = bnxt_get_unused_filter(bp); 2300 if (bfilter == NULL) { 2301 PMD_DRV_LOG(ERR, 2302 "Not enough resources for a new filter.\n"); 2303 return -ENOMEM; 2304 } 2305 ret = parse_ntuple_filter(bp, nfilter, bfilter); 2306 if (ret < 0) 2307 goto free_filter; 2308 2309 vnic = &bp->vnic_info[nfilter->queue]; 2310 vnic0 = &bp->vnic_info[0]; 2311 filter1 = STAILQ_FIRST(&vnic0->filter); 2312 if (filter1 == NULL) { 2313 ret = -EINVAL; 2314 goto free_filter; 2315 } 2316 2317 bfilter->dst_id = vnic->fw_vnic_id; 2318 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2319 bfilter->enables |= 2320 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2321 bfilter->ethertype = 0x800; 2322 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2323 2324 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic); 2325 2326 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2327 bfilter->dst_id == mfilter->dst_id) { 2328 PMD_DRV_LOG(ERR, "filter exists.\n"); 2329 ret = -EEXIST; 2330 goto free_filter; 2331 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2332 bfilter->dst_id != mfilter->dst_id) { 2333 mfilter->dst_id = vnic->fw_vnic_id; 2334 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter); 2335 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next); 2336 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next); 2337 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n"); 2338 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n"); 2339 goto free_filter; 2340 } 2341 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2342 PMD_DRV_LOG(ERR, "filter doesn't exist."); 2343 ret = -ENOENT; 2344 goto free_filter; 2345 } 2346 2347 if (filter_op == RTE_ETH_FILTER_ADD) { 2348 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2349 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2350 if (ret) 2351 goto free_filter; 2352 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2353 } else { 2354 if (mfilter == NULL) { 2355 /* This should not happen. But for Coverity! */ 2356 ret = -ENOENT; 2357 goto free_filter; 2358 } 2359 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter); 2360 2361 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next); 2362 bnxt_free_filter(bp, mfilter); 2363 mfilter->fw_l2_filter_id = -1; 2364 bnxt_free_filter(bp, bfilter); 2365 bfilter->fw_l2_filter_id = -1; 2366 } 2367 2368 return 0; 2369 free_filter: 2370 bfilter->fw_l2_filter_id = -1; 2371 bnxt_free_filter(bp, bfilter); 2372 return ret; 2373 } 2374 2375 static int 2376 bnxt_ntuple_filter(struct rte_eth_dev *dev, 2377 enum rte_filter_op filter_op, 2378 void *arg) 2379 { 2380 struct bnxt *bp = dev->data->dev_private; 2381 int ret; 2382 2383 if (filter_op == RTE_ETH_FILTER_NOP) 2384 return 0; 2385 2386 if (arg == NULL) { 2387 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2388 filter_op); 2389 return -EINVAL; 2390 } 2391 2392 switch (filter_op) { 2393 case RTE_ETH_FILTER_ADD: 2394 ret = bnxt_cfg_ntuple_filter(bp, 2395 (struct rte_eth_ntuple_filter *)arg, 2396 filter_op); 2397 break; 2398 case RTE_ETH_FILTER_DELETE: 2399 ret = bnxt_cfg_ntuple_filter(bp, 2400 (struct rte_eth_ntuple_filter *)arg, 2401 filter_op); 2402 break; 2403 default: 2404 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2405 ret = -EINVAL; 2406 break; 2407 } 2408 return ret; 2409 } 2410 2411 static int 2412 bnxt_parse_fdir_filter(struct bnxt *bp, 2413 struct rte_eth_fdir_filter *fdir, 2414 struct bnxt_filter_info *filter) 2415 { 2416 enum rte_fdir_mode fdir_mode = 2417 bp->eth_dev->data->dev_conf.fdir_conf.mode; 2418 struct bnxt_vnic_info *vnic0, *vnic; 2419 struct bnxt_filter_info *filter1; 2420 uint32_t en = 0; 2421 int i; 2422 2423 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 2424 return -EINVAL; 2425 2426 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci; 2427 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID; 2428 2429 switch (fdir->input.flow_type) { 2430 case RTE_ETH_FLOW_IPV4: 2431 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 2432 /* FALLTHROUGH */ 2433 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip; 2434 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2435 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip; 2436 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2437 filter->ip_protocol = fdir->input.flow.ip4_flow.proto; 2438 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2439 filter->ip_addr_type = 2440 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2441 filter->src_ipaddr_mask[0] = 0xffffffff; 2442 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2443 filter->dst_ipaddr_mask[0] = 0xffffffff; 2444 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2445 filter->ethertype = 0x800; 2446 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2447 break; 2448 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 2449 filter->src_port = fdir->input.flow.tcp4_flow.src_port; 2450 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2451 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port; 2452 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2453 filter->dst_port_mask = 0xffff; 2454 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2455 filter->src_port_mask = 0xffff; 2456 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2457 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip; 2458 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2459 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip; 2460 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2461 filter->ip_protocol = 6; 2462 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2463 filter->ip_addr_type = 2464 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2465 filter->src_ipaddr_mask[0] = 0xffffffff; 2466 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2467 filter->dst_ipaddr_mask[0] = 0xffffffff; 2468 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2469 filter->ethertype = 0x800; 2470 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2471 break; 2472 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 2473 filter->src_port = fdir->input.flow.udp4_flow.src_port; 2474 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2475 filter->dst_port = fdir->input.flow.udp4_flow.dst_port; 2476 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2477 filter->dst_port_mask = 0xffff; 2478 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2479 filter->src_port_mask = 0xffff; 2480 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2481 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip; 2482 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2483 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip; 2484 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2485 filter->ip_protocol = 17; 2486 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2487 filter->ip_addr_type = 2488 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2489 filter->src_ipaddr_mask[0] = 0xffffffff; 2490 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2491 filter->dst_ipaddr_mask[0] = 0xffffffff; 2492 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2493 filter->ethertype = 0x800; 2494 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2495 break; 2496 case RTE_ETH_FLOW_IPV6: 2497 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 2498 /* FALLTHROUGH */ 2499 filter->ip_addr_type = 2500 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2501 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto; 2502 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2503 rte_memcpy(filter->src_ipaddr, 2504 fdir->input.flow.ipv6_flow.src_ip, 16); 2505 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2506 rte_memcpy(filter->dst_ipaddr, 2507 fdir->input.flow.ipv6_flow.dst_ip, 16); 2508 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2509 memset(filter->dst_ipaddr_mask, 0xff, 16); 2510 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2511 memset(filter->src_ipaddr_mask, 0xff, 16); 2512 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2513 filter->ethertype = 0x86dd; 2514 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2515 break; 2516 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 2517 filter->src_port = fdir->input.flow.tcp6_flow.src_port; 2518 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2519 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port; 2520 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2521 filter->dst_port_mask = 0xffff; 2522 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2523 filter->src_port_mask = 0xffff; 2524 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2525 filter->ip_addr_type = 2526 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2527 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto; 2528 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2529 rte_memcpy(filter->src_ipaddr, 2530 fdir->input.flow.tcp6_flow.ip.src_ip, 16); 2531 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2532 rte_memcpy(filter->dst_ipaddr, 2533 fdir->input.flow.tcp6_flow.ip.dst_ip, 16); 2534 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2535 memset(filter->dst_ipaddr_mask, 0xff, 16); 2536 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2537 memset(filter->src_ipaddr_mask, 0xff, 16); 2538 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2539 filter->ethertype = 0x86dd; 2540 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2541 break; 2542 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 2543 filter->src_port = fdir->input.flow.udp6_flow.src_port; 2544 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2545 filter->dst_port = fdir->input.flow.udp6_flow.dst_port; 2546 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2547 filter->dst_port_mask = 0xffff; 2548 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2549 filter->src_port_mask = 0xffff; 2550 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2551 filter->ip_addr_type = 2552 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2553 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto; 2554 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2555 rte_memcpy(filter->src_ipaddr, 2556 fdir->input.flow.udp6_flow.ip.src_ip, 16); 2557 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2558 rte_memcpy(filter->dst_ipaddr, 2559 fdir->input.flow.udp6_flow.ip.dst_ip, 16); 2560 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2561 memset(filter->dst_ipaddr_mask, 0xff, 16); 2562 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2563 memset(filter->src_ipaddr_mask, 0xff, 16); 2564 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2565 filter->ethertype = 0x86dd; 2566 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2567 break; 2568 case RTE_ETH_FLOW_L2_PAYLOAD: 2569 filter->ethertype = fdir->input.flow.l2_flow.ether_type; 2570 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2571 break; 2572 case RTE_ETH_FLOW_VXLAN: 2573 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2574 return -EINVAL; 2575 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2576 filter->tunnel_type = 2577 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN; 2578 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2579 break; 2580 case RTE_ETH_FLOW_NVGRE: 2581 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2582 return -EINVAL; 2583 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2584 filter->tunnel_type = 2585 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE; 2586 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2587 break; 2588 case RTE_ETH_FLOW_UNKNOWN: 2589 case RTE_ETH_FLOW_RAW: 2590 case RTE_ETH_FLOW_FRAG_IPV4: 2591 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 2592 case RTE_ETH_FLOW_FRAG_IPV6: 2593 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 2594 case RTE_ETH_FLOW_IPV6_EX: 2595 case RTE_ETH_FLOW_IPV6_TCP_EX: 2596 case RTE_ETH_FLOW_IPV6_UDP_EX: 2597 case RTE_ETH_FLOW_GENEVE: 2598 /* FALLTHROUGH */ 2599 default: 2600 return -EINVAL; 2601 } 2602 2603 vnic0 = &bp->vnic_info[0]; 2604 vnic = &bp->vnic_info[fdir->action.rx_queue]; 2605 if (vnic == NULL) { 2606 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue); 2607 return -EINVAL; 2608 } 2609 2610 2611 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 2612 rte_memcpy(filter->dst_macaddr, 2613 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6); 2614 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2615 } 2616 2617 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) { 2618 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2619 filter1 = STAILQ_FIRST(&vnic0->filter); 2620 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0); 2621 } else { 2622 filter->dst_id = vnic->fw_vnic_id; 2623 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 2624 if (filter->dst_macaddr[i] == 0x00) 2625 filter1 = STAILQ_FIRST(&vnic0->filter); 2626 else 2627 filter1 = bnxt_get_l2_filter(bp, filter, vnic); 2628 } 2629 2630 if (filter1 == NULL) 2631 return -EINVAL; 2632 2633 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2634 filter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2635 2636 filter->enables = en; 2637 2638 return 0; 2639 } 2640 2641 static struct bnxt_filter_info * 2642 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf, 2643 struct bnxt_vnic_info **mvnic) 2644 { 2645 struct bnxt_filter_info *mf = NULL; 2646 int i; 2647 2648 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2649 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2650 2651 STAILQ_FOREACH(mf, &vnic->filter, next) { 2652 if (mf->filter_type == nf->filter_type && 2653 mf->flags == nf->flags && 2654 mf->src_port == nf->src_port && 2655 mf->src_port_mask == nf->src_port_mask && 2656 mf->dst_port == nf->dst_port && 2657 mf->dst_port_mask == nf->dst_port_mask && 2658 mf->ip_protocol == nf->ip_protocol && 2659 mf->ip_addr_type == nf->ip_addr_type && 2660 mf->ethertype == nf->ethertype && 2661 mf->vni == nf->vni && 2662 mf->tunnel_type == nf->tunnel_type && 2663 mf->l2_ovlan == nf->l2_ovlan && 2664 mf->l2_ovlan_mask == nf->l2_ovlan_mask && 2665 mf->l2_ivlan == nf->l2_ivlan && 2666 mf->l2_ivlan_mask == nf->l2_ivlan_mask && 2667 !memcmp(mf->l2_addr, nf->l2_addr, 2668 RTE_ETHER_ADDR_LEN) && 2669 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask, 2670 RTE_ETHER_ADDR_LEN) && 2671 !memcmp(mf->src_macaddr, nf->src_macaddr, 2672 RTE_ETHER_ADDR_LEN) && 2673 !memcmp(mf->dst_macaddr, nf->dst_macaddr, 2674 RTE_ETHER_ADDR_LEN) && 2675 !memcmp(mf->src_ipaddr, nf->src_ipaddr, 2676 sizeof(nf->src_ipaddr)) && 2677 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask, 2678 sizeof(nf->src_ipaddr_mask)) && 2679 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr, 2680 sizeof(nf->dst_ipaddr)) && 2681 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask, 2682 sizeof(nf->dst_ipaddr_mask))) { 2683 if (mvnic) 2684 *mvnic = vnic; 2685 return mf; 2686 } 2687 } 2688 } 2689 return NULL; 2690 } 2691 2692 static int 2693 bnxt_fdir_filter(struct rte_eth_dev *dev, 2694 enum rte_filter_op filter_op, 2695 void *arg) 2696 { 2697 struct bnxt *bp = dev->data->dev_private; 2698 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg; 2699 struct bnxt_filter_info *filter, *match; 2700 struct bnxt_vnic_info *vnic, *mvnic; 2701 int ret = 0, i; 2702 2703 if (filter_op == RTE_ETH_FILTER_NOP) 2704 return 0; 2705 2706 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 2707 return -EINVAL; 2708 2709 switch (filter_op) { 2710 case RTE_ETH_FILTER_ADD: 2711 case RTE_ETH_FILTER_DELETE: 2712 /* FALLTHROUGH */ 2713 filter = bnxt_get_unused_filter(bp); 2714 if (filter == NULL) { 2715 PMD_DRV_LOG(ERR, 2716 "Not enough resources for a new flow.\n"); 2717 return -ENOMEM; 2718 } 2719 2720 ret = bnxt_parse_fdir_filter(bp, fdir, filter); 2721 if (ret != 0) 2722 goto free_filter; 2723 filter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2724 2725 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2726 vnic = &bp->vnic_info[0]; 2727 else 2728 vnic = &bp->vnic_info[fdir->action.rx_queue]; 2729 2730 match = bnxt_match_fdir(bp, filter, &mvnic); 2731 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { 2732 if (match->dst_id == vnic->fw_vnic_id) { 2733 PMD_DRV_LOG(ERR, "Flow already exists.\n"); 2734 ret = -EEXIST; 2735 goto free_filter; 2736 } else { 2737 match->dst_id = vnic->fw_vnic_id; 2738 ret = bnxt_hwrm_set_ntuple_filter(bp, 2739 match->dst_id, 2740 match); 2741 STAILQ_REMOVE(&mvnic->filter, match, 2742 bnxt_filter_info, next); 2743 STAILQ_INSERT_TAIL(&vnic->filter, match, next); 2744 PMD_DRV_LOG(ERR, 2745 "Filter with matching pattern exist\n"); 2746 PMD_DRV_LOG(ERR, 2747 "Updated it to new destination q\n"); 2748 goto free_filter; 2749 } 2750 } 2751 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2752 PMD_DRV_LOG(ERR, "Flow does not exist.\n"); 2753 ret = -ENOENT; 2754 goto free_filter; 2755 } 2756 2757 if (filter_op == RTE_ETH_FILTER_ADD) { 2758 ret = bnxt_hwrm_set_ntuple_filter(bp, 2759 filter->dst_id, 2760 filter); 2761 if (ret) 2762 goto free_filter; 2763 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2764 } else { 2765 ret = bnxt_hwrm_clear_ntuple_filter(bp, match); 2766 STAILQ_REMOVE(&vnic->filter, match, 2767 bnxt_filter_info, next); 2768 bnxt_free_filter(bp, match); 2769 filter->fw_l2_filter_id = -1; 2770 bnxt_free_filter(bp, filter); 2771 } 2772 break; 2773 case RTE_ETH_FILTER_FLUSH: 2774 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2775 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2776 2777 STAILQ_FOREACH(filter, &vnic->filter, next) { 2778 if (filter->filter_type == 2779 HWRM_CFA_NTUPLE_FILTER) { 2780 ret = 2781 bnxt_hwrm_clear_ntuple_filter(bp, 2782 filter); 2783 STAILQ_REMOVE(&vnic->filter, filter, 2784 bnxt_filter_info, next); 2785 } 2786 } 2787 } 2788 return ret; 2789 case RTE_ETH_FILTER_UPDATE: 2790 case RTE_ETH_FILTER_STATS: 2791 case RTE_ETH_FILTER_INFO: 2792 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op); 2793 break; 2794 default: 2795 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 2796 ret = -EINVAL; 2797 break; 2798 } 2799 return ret; 2800 2801 free_filter: 2802 filter->fw_l2_filter_id = -1; 2803 bnxt_free_filter(bp, filter); 2804 return ret; 2805 } 2806 2807 static int 2808 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused, 2809 enum rte_filter_type filter_type, 2810 enum rte_filter_op filter_op, void *arg) 2811 { 2812 int ret = 0; 2813 2814 switch (filter_type) { 2815 case RTE_ETH_FILTER_TUNNEL: 2816 PMD_DRV_LOG(ERR, 2817 "filter type: %d: To be implemented\n", filter_type); 2818 break; 2819 case RTE_ETH_FILTER_FDIR: 2820 ret = bnxt_fdir_filter(dev, filter_op, arg); 2821 break; 2822 case RTE_ETH_FILTER_NTUPLE: 2823 ret = bnxt_ntuple_filter(dev, filter_op, arg); 2824 break; 2825 case RTE_ETH_FILTER_ETHERTYPE: 2826 ret = bnxt_ethertype_filter(dev, filter_op, arg); 2827 break; 2828 case RTE_ETH_FILTER_GENERIC: 2829 if (filter_op != RTE_ETH_FILTER_GET) 2830 return -EINVAL; 2831 *(const void **)arg = &bnxt_flow_ops; 2832 break; 2833 default: 2834 PMD_DRV_LOG(ERR, 2835 "Filter type (%d) not supported", filter_type); 2836 ret = -EINVAL; 2837 break; 2838 } 2839 return ret; 2840 } 2841 2842 static const uint32_t * 2843 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 2844 { 2845 static const uint32_t ptypes[] = { 2846 RTE_PTYPE_L2_ETHER_VLAN, 2847 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 2848 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 2849 RTE_PTYPE_L4_ICMP, 2850 RTE_PTYPE_L4_TCP, 2851 RTE_PTYPE_L4_UDP, 2852 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 2853 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 2854 RTE_PTYPE_INNER_L4_ICMP, 2855 RTE_PTYPE_INNER_L4_TCP, 2856 RTE_PTYPE_INNER_L4_UDP, 2857 RTE_PTYPE_UNKNOWN 2858 }; 2859 2860 if (!dev->rx_pkt_burst) 2861 return NULL; 2862 2863 return ptypes; 2864 } 2865 2866 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 2867 int reg_win) 2868 { 2869 uint32_t reg_base = *reg_arr & 0xfffff000; 2870 uint32_t win_off; 2871 int i; 2872 2873 for (i = 0; i < count; i++) { 2874 if ((reg_arr[i] & 0xfffff000) != reg_base) 2875 return -ERANGE; 2876 } 2877 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 2878 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 2879 return 0; 2880 } 2881 2882 static int bnxt_map_ptp_regs(struct bnxt *bp) 2883 { 2884 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2885 uint32_t *reg_arr; 2886 int rc, i; 2887 2888 reg_arr = ptp->rx_regs; 2889 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 2890 if (rc) 2891 return rc; 2892 2893 reg_arr = ptp->tx_regs; 2894 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 2895 if (rc) 2896 return rc; 2897 2898 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 2899 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 2900 2901 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 2902 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 2903 2904 return 0; 2905 } 2906 2907 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 2908 { 2909 rte_write32(0, (uint8_t *)bp->bar0 + 2910 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 2911 rte_write32(0, (uint8_t *)bp->bar0 + 2912 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 2913 } 2914 2915 static uint64_t bnxt_cc_read(struct bnxt *bp) 2916 { 2917 uint64_t ns; 2918 2919 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2920 BNXT_GRCPF_REG_SYNC_TIME)); 2921 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2922 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 2923 return ns; 2924 } 2925 2926 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 2927 { 2928 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2929 uint32_t fifo; 2930 2931 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2932 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 2933 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 2934 return -EAGAIN; 2935 2936 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2937 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 2938 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2939 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 2940 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2941 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 2942 2943 return 0; 2944 } 2945 2946 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 2947 { 2948 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2949 struct bnxt_pf_info *pf = &bp->pf; 2950 uint16_t port_id; 2951 uint32_t fifo; 2952 2953 if (!ptp) 2954 return -ENODEV; 2955 2956 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2957 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 2958 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 2959 return -EAGAIN; 2960 2961 port_id = pf->port_id; 2962 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 2963 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 2964 2965 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2966 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 2967 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 2968 /* bnxt_clr_rx_ts(bp); TBD */ 2969 return -EBUSY; 2970 } 2971 2972 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2973 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 2974 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2975 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 2976 2977 return 0; 2978 } 2979 2980 static int 2981 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 2982 { 2983 uint64_t ns; 2984 struct bnxt *bp = dev->data->dev_private; 2985 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2986 2987 if (!ptp) 2988 return 0; 2989 2990 ns = rte_timespec_to_ns(ts); 2991 /* Set the timecounters to a new value. */ 2992 ptp->tc.nsec = ns; 2993 2994 return 0; 2995 } 2996 2997 static int 2998 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 2999 { 3000 uint64_t ns, systime_cycles; 3001 struct bnxt *bp = dev->data->dev_private; 3002 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3003 3004 if (!ptp) 3005 return 0; 3006 3007 systime_cycles = bnxt_cc_read(bp); 3008 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3009 *ts = rte_ns_to_timespec(ns); 3010 3011 return 0; 3012 } 3013 static int 3014 bnxt_timesync_enable(struct rte_eth_dev *dev) 3015 { 3016 struct bnxt *bp = dev->data->dev_private; 3017 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3018 uint32_t shift = 0; 3019 3020 if (!ptp) 3021 return 0; 3022 3023 ptp->rx_filter = 1; 3024 ptp->tx_tstamp_en = 1; 3025 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3026 3027 if (!bnxt_hwrm_ptp_cfg(bp)) 3028 bnxt_map_ptp_regs(bp); 3029 3030 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3031 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3032 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3033 3034 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3035 ptp->tc.cc_shift = shift; 3036 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3037 3038 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3039 ptp->rx_tstamp_tc.cc_shift = shift; 3040 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3041 3042 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3043 ptp->tx_tstamp_tc.cc_shift = shift; 3044 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3045 3046 return 0; 3047 } 3048 3049 static int 3050 bnxt_timesync_disable(struct rte_eth_dev *dev) 3051 { 3052 struct bnxt *bp = dev->data->dev_private; 3053 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3054 3055 if (!ptp) 3056 return 0; 3057 3058 ptp->rx_filter = 0; 3059 ptp->tx_tstamp_en = 0; 3060 ptp->rxctl = 0; 3061 3062 bnxt_hwrm_ptp_cfg(bp); 3063 3064 bnxt_unmap_ptp_regs(bp); 3065 3066 return 0; 3067 } 3068 3069 static int 3070 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3071 struct timespec *timestamp, 3072 uint32_t flags __rte_unused) 3073 { 3074 struct bnxt *bp = dev->data->dev_private; 3075 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3076 uint64_t rx_tstamp_cycles = 0; 3077 uint64_t ns; 3078 3079 if (!ptp) 3080 return 0; 3081 3082 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3083 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3084 *timestamp = rte_ns_to_timespec(ns); 3085 return 0; 3086 } 3087 3088 static int 3089 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3090 struct timespec *timestamp) 3091 { 3092 struct bnxt *bp = dev->data->dev_private; 3093 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3094 uint64_t tx_tstamp_cycles = 0; 3095 uint64_t ns; 3096 3097 if (!ptp) 3098 return 0; 3099 3100 bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3101 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3102 *timestamp = rte_ns_to_timespec(ns); 3103 3104 return 0; 3105 } 3106 3107 static int 3108 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3109 { 3110 struct bnxt *bp = dev->data->dev_private; 3111 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3112 3113 if (!ptp) 3114 return 0; 3115 3116 ptp->tc.nsec += delta; 3117 3118 return 0; 3119 } 3120 3121 static int 3122 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3123 { 3124 struct bnxt *bp = dev->data->dev_private; 3125 int rc; 3126 uint32_t dir_entries; 3127 uint32_t entry_length; 3128 3129 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n", 3130 bp->pdev->addr.domain, bp->pdev->addr.bus, 3131 bp->pdev->addr.devid, bp->pdev->addr.function); 3132 3133 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3134 if (rc != 0) 3135 return rc; 3136 3137 return dir_entries * entry_length; 3138 } 3139 3140 static int 3141 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3142 struct rte_dev_eeprom_info *in_eeprom) 3143 { 3144 struct bnxt *bp = dev->data->dev_private; 3145 uint32_t index; 3146 uint32_t offset; 3147 3148 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 3149 "len = %d\n", bp->pdev->addr.domain, 3150 bp->pdev->addr.bus, bp->pdev->addr.devid, 3151 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 3152 3153 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3154 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3155 in_eeprom->data); 3156 3157 index = in_eeprom->offset >> 24; 3158 offset = in_eeprom->offset & 0xffffff; 3159 3160 if (index != 0) 3161 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3162 in_eeprom->length, in_eeprom->data); 3163 3164 return 0; 3165 } 3166 3167 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3168 { 3169 switch (dir_type) { 3170 case BNX_DIR_TYPE_CHIMP_PATCH: 3171 case BNX_DIR_TYPE_BOOTCODE: 3172 case BNX_DIR_TYPE_BOOTCODE_2: 3173 case BNX_DIR_TYPE_APE_FW: 3174 case BNX_DIR_TYPE_APE_PATCH: 3175 case BNX_DIR_TYPE_KONG_FW: 3176 case BNX_DIR_TYPE_KONG_PATCH: 3177 case BNX_DIR_TYPE_BONO_FW: 3178 case BNX_DIR_TYPE_BONO_PATCH: 3179 /* FALLTHROUGH */ 3180 return true; 3181 } 3182 3183 return false; 3184 } 3185 3186 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3187 { 3188 switch (dir_type) { 3189 case BNX_DIR_TYPE_AVS: 3190 case BNX_DIR_TYPE_EXP_ROM_MBA: 3191 case BNX_DIR_TYPE_PCIE: 3192 case BNX_DIR_TYPE_TSCF_UCODE: 3193 case BNX_DIR_TYPE_EXT_PHY: 3194 case BNX_DIR_TYPE_CCM: 3195 case BNX_DIR_TYPE_ISCSI_BOOT: 3196 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3197 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3198 /* FALLTHROUGH */ 3199 return true; 3200 } 3201 3202 return false; 3203 } 3204 3205 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3206 { 3207 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3208 bnxt_dir_type_is_other_exec_format(dir_type); 3209 } 3210 3211 static int 3212 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3213 struct rte_dev_eeprom_info *in_eeprom) 3214 { 3215 struct bnxt *bp = dev->data->dev_private; 3216 uint8_t index, dir_op; 3217 uint16_t type, ext, ordinal, attr; 3218 3219 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 3220 "len = %d\n", bp->pdev->addr.domain, 3221 bp->pdev->addr.bus, bp->pdev->addr.devid, 3222 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 3223 3224 if (!BNXT_PF(bp)) { 3225 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3226 return -EINVAL; 3227 } 3228 3229 type = in_eeprom->magic >> 16; 3230 3231 if (type == 0xffff) { /* special value for directory operations */ 3232 index = in_eeprom->magic & 0xff; 3233 dir_op = in_eeprom->magic >> 8; 3234 if (index == 0) 3235 return -EINVAL; 3236 switch (dir_op) { 3237 case 0x0e: /* erase */ 3238 if (in_eeprom->offset != ~in_eeprom->magic) 3239 return -EINVAL; 3240 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3241 default: 3242 return -EINVAL; 3243 } 3244 } 3245 3246 /* Create or re-write an NVM item: */ 3247 if (bnxt_dir_type_is_executable(type) == true) 3248 return -EOPNOTSUPP; 3249 ext = in_eeprom->magic & 0xffff; 3250 ordinal = in_eeprom->offset >> 16; 3251 attr = in_eeprom->offset & 0xffff; 3252 3253 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3254 in_eeprom->data, in_eeprom->length); 3255 } 3256 3257 /* 3258 * Initialization 3259 */ 3260 3261 static const struct eth_dev_ops bnxt_dev_ops = { 3262 .dev_infos_get = bnxt_dev_info_get_op, 3263 .dev_close = bnxt_dev_close_op, 3264 .dev_configure = bnxt_dev_configure_op, 3265 .dev_start = bnxt_dev_start_op, 3266 .dev_stop = bnxt_dev_stop_op, 3267 .dev_set_link_up = bnxt_dev_set_link_up_op, 3268 .dev_set_link_down = bnxt_dev_set_link_down_op, 3269 .stats_get = bnxt_stats_get_op, 3270 .stats_reset = bnxt_stats_reset_op, 3271 .rx_queue_setup = bnxt_rx_queue_setup_op, 3272 .rx_queue_release = bnxt_rx_queue_release_op, 3273 .tx_queue_setup = bnxt_tx_queue_setup_op, 3274 .tx_queue_release = bnxt_tx_queue_release_op, 3275 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3276 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3277 .reta_update = bnxt_reta_update_op, 3278 .reta_query = bnxt_reta_query_op, 3279 .rss_hash_update = bnxt_rss_hash_update_op, 3280 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3281 .link_update = bnxt_link_update_op, 3282 .promiscuous_enable = bnxt_promiscuous_enable_op, 3283 .promiscuous_disable = bnxt_promiscuous_disable_op, 3284 .allmulticast_enable = bnxt_allmulticast_enable_op, 3285 .allmulticast_disable = bnxt_allmulticast_disable_op, 3286 .mac_addr_add = bnxt_mac_addr_add_op, 3287 .mac_addr_remove = bnxt_mac_addr_remove_op, 3288 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3289 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3290 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3291 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3292 .vlan_filter_set = bnxt_vlan_filter_set_op, 3293 .vlan_offload_set = bnxt_vlan_offload_set_op, 3294 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3295 .mtu_set = bnxt_mtu_set_op, 3296 .mac_addr_set = bnxt_set_default_mac_addr_op, 3297 .xstats_get = bnxt_dev_xstats_get_op, 3298 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3299 .xstats_reset = bnxt_dev_xstats_reset_op, 3300 .fw_version_get = bnxt_fw_version_get, 3301 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3302 .rxq_info_get = bnxt_rxq_info_get_op, 3303 .txq_info_get = bnxt_txq_info_get_op, 3304 .dev_led_on = bnxt_dev_led_on_op, 3305 .dev_led_off = bnxt_dev_led_off_op, 3306 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op, 3307 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op, 3308 .rx_queue_count = bnxt_rx_queue_count_op, 3309 .rx_descriptor_status = bnxt_rx_descriptor_status_op, 3310 .tx_descriptor_status = bnxt_tx_descriptor_status_op, 3311 .rx_queue_start = bnxt_rx_queue_start, 3312 .rx_queue_stop = bnxt_rx_queue_stop, 3313 .tx_queue_start = bnxt_tx_queue_start, 3314 .tx_queue_stop = bnxt_tx_queue_stop, 3315 .filter_ctrl = bnxt_filter_ctrl_op, 3316 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3317 .get_eeprom_length = bnxt_get_eeprom_length_op, 3318 .get_eeprom = bnxt_get_eeprom_op, 3319 .set_eeprom = bnxt_set_eeprom_op, 3320 .timesync_enable = bnxt_timesync_enable, 3321 .timesync_disable = bnxt_timesync_disable, 3322 .timesync_read_time = bnxt_timesync_read_time, 3323 .timesync_write_time = bnxt_timesync_write_time, 3324 .timesync_adjust_time = bnxt_timesync_adjust_time, 3325 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3326 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3327 }; 3328 3329 static bool bnxt_vf_pciid(uint16_t id) 3330 { 3331 if (id == BROADCOM_DEV_ID_57304_VF || 3332 id == BROADCOM_DEV_ID_57406_VF || 3333 id == BROADCOM_DEV_ID_5731X_VF || 3334 id == BROADCOM_DEV_ID_5741X_VF || 3335 id == BROADCOM_DEV_ID_57414_VF || 3336 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 || 3337 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 || 3338 id == BROADCOM_DEV_ID_58802_VF || 3339 id == BROADCOM_DEV_ID_57500_VF1 || 3340 id == BROADCOM_DEV_ID_57500_VF2) 3341 return true; 3342 return false; 3343 } 3344 3345 bool bnxt_stratus_device(struct bnxt *bp) 3346 { 3347 uint16_t id = bp->pdev->id.device_id; 3348 3349 if (id == BROADCOM_DEV_ID_STRATUS_NIC || 3350 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 || 3351 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2) 3352 return true; 3353 return false; 3354 } 3355 3356 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 3357 { 3358 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3359 struct bnxt *bp = eth_dev->data->dev_private; 3360 3361 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 3362 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 3363 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 3364 if (!bp->bar0 || !bp->doorbell_base) { 3365 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 3366 return -ENODEV; 3367 } 3368 3369 bp->eth_dev = eth_dev; 3370 bp->pdev = pci_dev; 3371 3372 return 0; 3373 } 3374 3375 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp, 3376 struct bnxt_ctx_pg_info *ctx_pg, 3377 uint32_t mem_size, 3378 const char *suffix, 3379 uint16_t idx) 3380 { 3381 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 3382 const struct rte_memzone *mz = NULL; 3383 char mz_name[RTE_MEMZONE_NAMESIZE]; 3384 rte_iova_t mz_phys_addr; 3385 uint64_t valid_bits = 0; 3386 uint32_t sz; 3387 int i; 3388 3389 if (!mem_size) 3390 return 0; 3391 3392 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 3393 BNXT_PAGE_SIZE; 3394 rmem->page_size = BNXT_PAGE_SIZE; 3395 rmem->pg_arr = ctx_pg->ctx_pg_arr; 3396 rmem->dma_arr = ctx_pg->ctx_dma_arr; 3397 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 3398 3399 valid_bits = PTU_PTE_VALID; 3400 3401 if (rmem->nr_pages > 1) { 3402 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 3403 "bnxt_ctx_pg_tbl%s_%x_%d", 3404 suffix, idx, bp->eth_dev->data->port_id); 3405 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 3406 mz = rte_memzone_lookup(mz_name); 3407 if (!mz) { 3408 mz = rte_memzone_reserve_aligned(mz_name, 3409 rmem->nr_pages * 8, 3410 SOCKET_ID_ANY, 3411 RTE_MEMZONE_2MB | 3412 RTE_MEMZONE_SIZE_HINT_ONLY | 3413 RTE_MEMZONE_IOVA_CONTIG, 3414 BNXT_PAGE_SIZE); 3415 if (mz == NULL) 3416 return -ENOMEM; 3417 } 3418 3419 memset(mz->addr, 0, mz->len); 3420 mz_phys_addr = mz->iova; 3421 if ((unsigned long)mz->addr == mz_phys_addr) { 3422 PMD_DRV_LOG(WARNING, 3423 "Memzone physical address same as virtual.\n"); 3424 PMD_DRV_LOG(WARNING, 3425 "Using rte_mem_virt2iova()\n"); 3426 mz_phys_addr = rte_mem_virt2iova(mz->addr); 3427 if (mz_phys_addr == RTE_BAD_IOVA) { 3428 PMD_DRV_LOG(ERR, 3429 "unable to map addr to phys memory\n"); 3430 return -ENOMEM; 3431 } 3432 } 3433 rte_mem_lock_page(((char *)mz->addr)); 3434 3435 rmem->pg_tbl = mz->addr; 3436 rmem->pg_tbl_map = mz_phys_addr; 3437 rmem->pg_tbl_mz = mz; 3438 } 3439 3440 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 3441 suffix, idx, bp->eth_dev->data->port_id); 3442 mz = rte_memzone_lookup(mz_name); 3443 if (!mz) { 3444 mz = rte_memzone_reserve_aligned(mz_name, 3445 mem_size, 3446 SOCKET_ID_ANY, 3447 RTE_MEMZONE_1GB | 3448 RTE_MEMZONE_SIZE_HINT_ONLY | 3449 RTE_MEMZONE_IOVA_CONTIG, 3450 BNXT_PAGE_SIZE); 3451 if (mz == NULL) 3452 return -ENOMEM; 3453 } 3454 3455 memset(mz->addr, 0, mz->len); 3456 mz_phys_addr = mz->iova; 3457 if ((unsigned long)mz->addr == mz_phys_addr) { 3458 PMD_DRV_LOG(WARNING, 3459 "Memzone physical address same as virtual.\n"); 3460 PMD_DRV_LOG(WARNING, 3461 "Using rte_mem_virt2iova()\n"); 3462 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE) 3463 rte_mem_lock_page(((char *)mz->addr) + sz); 3464 mz_phys_addr = rte_mem_virt2iova(mz->addr); 3465 if (mz_phys_addr == RTE_BAD_IOVA) { 3466 PMD_DRV_LOG(ERR, 3467 "unable to map addr to phys memory\n"); 3468 return -ENOMEM; 3469 } 3470 } 3471 3472 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 3473 rte_mem_lock_page(((char *)mz->addr) + sz); 3474 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 3475 rmem->dma_arr[i] = mz_phys_addr + sz; 3476 3477 if (rmem->nr_pages > 1) { 3478 if (i == rmem->nr_pages - 2 && 3479 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 3480 valid_bits |= PTU_PTE_NEXT_TO_LAST; 3481 else if (i == rmem->nr_pages - 1 && 3482 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 3483 valid_bits |= PTU_PTE_LAST; 3484 3485 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 3486 valid_bits); 3487 } 3488 } 3489 3490 rmem->mz = mz; 3491 if (rmem->vmem_size) 3492 rmem->vmem = (void **)mz->addr; 3493 rmem->dma_arr[0] = mz_phys_addr; 3494 return 0; 3495 } 3496 3497 static void bnxt_free_ctx_mem(struct bnxt *bp) 3498 { 3499 int i; 3500 3501 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 3502 return; 3503 3504 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 3505 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 3506 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 3507 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 3508 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 3509 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 3510 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 3511 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 3512 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 3513 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 3514 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 3515 3516 for (i = 0; i < BNXT_MAX_Q; i++) { 3517 if (bp->ctx->tqm_mem[i]) 3518 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 3519 } 3520 3521 rte_free(bp->ctx); 3522 bp->ctx = NULL; 3523 } 3524 3525 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 3526 3527 #define min_t(type, x, y) ({ \ 3528 type __min1 = (x); \ 3529 type __min2 = (y); \ 3530 __min1 < __min2 ? __min1 : __min2; }) 3531 3532 #define max_t(type, x, y) ({ \ 3533 type __max1 = (x); \ 3534 type __max2 = (y); \ 3535 __max1 > __max2 ? __max1 : __max2; }) 3536 3537 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 3538 3539 int bnxt_alloc_ctx_mem(struct bnxt *bp) 3540 { 3541 struct bnxt_ctx_pg_info *ctx_pg; 3542 struct bnxt_ctx_mem_info *ctx; 3543 uint32_t mem_size, ena, entries; 3544 int i, rc; 3545 3546 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 3547 if (rc) { 3548 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 3549 return rc; 3550 } 3551 ctx = bp->ctx; 3552 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 3553 return 0; 3554 3555 ctx_pg = &ctx->qp_mem; 3556 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 3557 mem_size = ctx->qp_entry_size * ctx_pg->entries; 3558 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 3559 if (rc) 3560 return rc; 3561 3562 ctx_pg = &ctx->srq_mem; 3563 ctx_pg->entries = ctx->srq_max_l2_entries; 3564 mem_size = ctx->srq_entry_size * ctx_pg->entries; 3565 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 3566 if (rc) 3567 return rc; 3568 3569 ctx_pg = &ctx->cq_mem; 3570 ctx_pg->entries = ctx->cq_max_l2_entries; 3571 mem_size = ctx->cq_entry_size * ctx_pg->entries; 3572 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 3573 if (rc) 3574 return rc; 3575 3576 ctx_pg = &ctx->vnic_mem; 3577 ctx_pg->entries = ctx->vnic_max_vnic_entries + 3578 ctx->vnic_max_ring_table_entries; 3579 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 3580 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 3581 if (rc) 3582 return rc; 3583 3584 ctx_pg = &ctx->stat_mem; 3585 ctx_pg->entries = ctx->stat_max_entries; 3586 mem_size = ctx->stat_entry_size * ctx_pg->entries; 3587 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 3588 if (rc) 3589 return rc; 3590 3591 entries = ctx->qp_max_l2_entries; 3592 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 3593 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring, 3594 ctx->tqm_max_entries_per_ring); 3595 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) { 3596 ctx_pg = ctx->tqm_mem[i]; 3597 /* use min tqm entries for now. */ 3598 ctx_pg->entries = entries; 3599 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 3600 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i); 3601 if (rc) 3602 return rc; 3603 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 3604 } 3605 3606 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 3607 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 3608 if (rc) 3609 PMD_DRV_LOG(ERR, 3610 "Failed to configure context mem: rc = %d\n", rc); 3611 else 3612 ctx->flags |= BNXT_CTX_FLAG_INITED; 3613 3614 return rc; 3615 } 3616 3617 static int bnxt_alloc_stats_mem(struct bnxt *bp) 3618 { 3619 struct rte_pci_device *pci_dev = bp->pdev; 3620 char mz_name[RTE_MEMZONE_NAMESIZE]; 3621 const struct rte_memzone *mz = NULL; 3622 uint32_t total_alloc_len; 3623 rte_iova_t mz_phys_addr; 3624 3625 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 3626 return 0; 3627 3628 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 3629 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 3630 pci_dev->addr.bus, pci_dev->addr.devid, 3631 pci_dev->addr.function, "rx_port_stats"); 3632 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 3633 mz = rte_memzone_lookup(mz_name); 3634 total_alloc_len = 3635 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 3636 sizeof(struct rx_port_stats_ext) + 512); 3637 if (!mz) { 3638 mz = rte_memzone_reserve(mz_name, total_alloc_len, 3639 SOCKET_ID_ANY, 3640 RTE_MEMZONE_2MB | 3641 RTE_MEMZONE_SIZE_HINT_ONLY | 3642 RTE_MEMZONE_IOVA_CONTIG); 3643 if (mz == NULL) 3644 return -ENOMEM; 3645 } 3646 memset(mz->addr, 0, mz->len); 3647 mz_phys_addr = mz->iova; 3648 if ((unsigned long)mz->addr == mz_phys_addr) { 3649 PMD_DRV_LOG(WARNING, 3650 "Memzone physical address same as virtual.\n"); 3651 PMD_DRV_LOG(WARNING, 3652 "Using rte_mem_virt2iova()\n"); 3653 mz_phys_addr = rte_mem_virt2iova(mz->addr); 3654 if (mz_phys_addr == RTE_BAD_IOVA) { 3655 PMD_DRV_LOG(ERR, 3656 "Can't map address to physical memory\n"); 3657 return -ENOMEM; 3658 } 3659 } 3660 3661 bp->rx_mem_zone = (const void *)mz; 3662 bp->hw_rx_port_stats = mz->addr; 3663 bp->hw_rx_port_stats_map = mz_phys_addr; 3664 3665 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 3666 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 3667 pci_dev->addr.bus, pci_dev->addr.devid, 3668 pci_dev->addr.function, "tx_port_stats"); 3669 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 3670 mz = rte_memzone_lookup(mz_name); 3671 total_alloc_len = 3672 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 3673 sizeof(struct tx_port_stats_ext) + 512); 3674 if (!mz) { 3675 mz = rte_memzone_reserve(mz_name, 3676 total_alloc_len, 3677 SOCKET_ID_ANY, 3678 RTE_MEMZONE_2MB | 3679 RTE_MEMZONE_SIZE_HINT_ONLY | 3680 RTE_MEMZONE_IOVA_CONTIG); 3681 if (mz == NULL) 3682 return -ENOMEM; 3683 } 3684 memset(mz->addr, 0, mz->len); 3685 mz_phys_addr = mz->iova; 3686 if ((unsigned long)mz->addr == mz_phys_addr) { 3687 PMD_DRV_LOG(WARNING, 3688 "Memzone physical address same as virtual\n"); 3689 PMD_DRV_LOG(WARNING, 3690 "Using rte_mem_virt2iova()\n"); 3691 mz_phys_addr = rte_mem_virt2iova(mz->addr); 3692 if (mz_phys_addr == RTE_BAD_IOVA) { 3693 PMD_DRV_LOG(ERR, 3694 "Can't map address to physical memory\n"); 3695 return -ENOMEM; 3696 } 3697 } 3698 3699 bp->tx_mem_zone = (const void *)mz; 3700 bp->hw_tx_port_stats = mz->addr; 3701 bp->hw_tx_port_stats_map = mz_phys_addr; 3702 bp->flags |= BNXT_FLAG_PORT_STATS; 3703 3704 /* Display extended statistics if FW supports it */ 3705 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 3706 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 3707 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 3708 return 0; 3709 3710 bp->hw_rx_port_stats_ext = (void *) 3711 ((uint8_t *)bp->hw_rx_port_stats + 3712 sizeof(struct rx_port_stats)); 3713 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 3714 sizeof(struct rx_port_stats); 3715 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 3716 3717 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 3718 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 3719 bp->hw_tx_port_stats_ext = (void *) 3720 ((uint8_t *)bp->hw_tx_port_stats + 3721 sizeof(struct tx_port_stats)); 3722 bp->hw_tx_port_stats_ext_map = 3723 bp->hw_tx_port_stats_map + 3724 sizeof(struct tx_port_stats); 3725 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 3726 } 3727 3728 return 0; 3729 } 3730 3731 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 3732 { 3733 struct bnxt *bp = eth_dev->data->dev_private; 3734 int rc = 0; 3735 3736 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 3737 RTE_ETHER_ADDR_LEN * 3738 bp->max_l2_ctx, 3739 0); 3740 if (eth_dev->data->mac_addrs == NULL) { 3741 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 3742 return -ENOMEM; 3743 } 3744 3745 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) { 3746 if (BNXT_PF(bp)) 3747 return -EINVAL; 3748 3749 /* Generate a random MAC address, if none was assigned by PF */ 3750 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 3751 bnxt_eth_hw_addr_random(bp->mac_addr); 3752 PMD_DRV_LOG(INFO, 3753 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 3754 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 3755 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 3756 3757 rc = bnxt_hwrm_set_mac(bp); 3758 if (!rc) 3759 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr, 3760 RTE_ETHER_ADDR_LEN); 3761 return rc; 3762 } 3763 3764 /* Copy the permanent MAC from the FUNC_QCAPS response */ 3765 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN); 3766 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 3767 3768 return rc; 3769 } 3770 3771 #define ALLOW_FUNC(x) \ 3772 { \ 3773 uint32_t arg = (x); \ 3774 bp->pf.vf_req_fwd[((arg) >> 5)] &= \ 3775 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \ 3776 } 3777 static int 3778 bnxt_dev_init(struct rte_eth_dev *eth_dev) 3779 { 3780 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3781 static int version_printed; 3782 struct bnxt *bp; 3783 uint16_t mtu; 3784 int rc; 3785 3786 if (version_printed++ == 0) 3787 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 3788 3789 rte_eth_copy_pci_info(eth_dev, pci_dev); 3790 3791 bp = eth_dev->data->dev_private; 3792 3793 bp->dev_stopped = 1; 3794 3795 eth_dev->dev_ops = &bnxt_dev_ops; 3796 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 3797 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 3798 3799 /* 3800 * For secondary processes, we don't initialise any further 3801 * as primary has already done this work. 3802 */ 3803 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3804 return 0; 3805 3806 if (bnxt_vf_pciid(pci_dev->id.device_id)) 3807 bp->flags |= BNXT_FLAG_VF; 3808 3809 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 || 3810 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 || 3811 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 || 3812 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 || 3813 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2) 3814 bp->flags |= BNXT_FLAG_THOR_CHIP; 3815 3816 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 3817 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 3818 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 3819 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 3820 bp->flags |= BNXT_FLAG_STINGRAY; 3821 3822 rc = bnxt_init_board(eth_dev); 3823 if (rc) { 3824 PMD_DRV_LOG(ERR, 3825 "Board initialization failed rc: %x\n", rc); 3826 goto error; 3827 } 3828 3829 rc = bnxt_alloc_hwrm_resources(bp); 3830 if (rc) { 3831 PMD_DRV_LOG(ERR, 3832 "hwrm resource allocation failure rc: %x\n", rc); 3833 goto error_free; 3834 } 3835 rc = bnxt_hwrm_ver_get(bp); 3836 if (rc) 3837 goto error_free; 3838 3839 rc = bnxt_hwrm_func_reset(bp); 3840 if (rc) { 3841 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc); 3842 rc = -EIO; 3843 goto error_free; 3844 } 3845 3846 rc = bnxt_hwrm_queue_qportcfg(bp); 3847 if (rc) { 3848 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n"); 3849 goto error_free; 3850 } 3851 /* Get the MAX capabilities for this function */ 3852 rc = bnxt_hwrm_func_qcaps(bp); 3853 if (rc) { 3854 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc); 3855 goto error_free; 3856 } 3857 3858 rc = bnxt_alloc_stats_mem(bp); 3859 if (rc) 3860 goto error_free; 3861 3862 if (bp->max_tx_rings == 0) { 3863 PMD_DRV_LOG(ERR, "No TX rings available!\n"); 3864 rc = -EBUSY; 3865 goto error_free; 3866 } 3867 3868 rc = bnxt_setup_mac_addr(eth_dev); 3869 if (rc) 3870 goto error_free; 3871 3872 /* THOR does not support ring groups. 3873 * But we will use the array to save RSS context IDs. 3874 */ 3875 if (BNXT_CHIP_THOR(bp)) { 3876 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR; 3877 } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) { 3878 /* 1 ring is for default completion ring */ 3879 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n"); 3880 rc = -ENOSPC; 3881 goto error_free; 3882 } 3883 3884 if (BNXT_HAS_RING_GRPS(bp)) { 3885 bp->grp_info = rte_zmalloc("bnxt_grp_info", 3886 sizeof(*bp->grp_info) * 3887 bp->max_ring_grps, 0); 3888 if (!bp->grp_info) { 3889 PMD_DRV_LOG(ERR, 3890 "Failed to alloc %zu bytes for grp info tbl.\n", 3891 sizeof(*bp->grp_info) * bp->max_ring_grps); 3892 rc = -ENOMEM; 3893 goto error_free; 3894 } 3895 } 3896 3897 /* Forward all requests if firmware is new enough */ 3898 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) && 3899 (bp->fw_ver < ((20 << 24) | (7 << 16)))) || 3900 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) { 3901 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd)); 3902 } else { 3903 PMD_DRV_LOG(WARNING, 3904 "Firmware too old for VF mailbox functionality\n"); 3905 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd)); 3906 } 3907 3908 /* 3909 * The following are used for driver cleanup. If we disallow these, 3910 * VF drivers can't clean up cleanly. 3911 */ 3912 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR); 3913 ALLOW_FUNC(HWRM_VNIC_FREE); 3914 ALLOW_FUNC(HWRM_RING_FREE); 3915 ALLOW_FUNC(HWRM_RING_GRP_FREE); 3916 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE); 3917 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE); 3918 ALLOW_FUNC(HWRM_STAT_CTX_FREE); 3919 ALLOW_FUNC(HWRM_PORT_PHY_QCFG); 3920 ALLOW_FUNC(HWRM_VNIC_TPA_CFG); 3921 rc = bnxt_hwrm_func_driver_register(bp); 3922 if (rc) { 3923 PMD_DRV_LOG(ERR, 3924 "Failed to register driver"); 3925 rc = -EBUSY; 3926 goto error_free; 3927 } 3928 3929 PMD_DRV_LOG(INFO, 3930 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n", 3931 pci_dev->mem_resource[0].phys_addr, 3932 pci_dev->mem_resource[0].addr); 3933 3934 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 3935 if (rc) { 3936 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n"); 3937 goto error_free; 3938 } 3939 3940 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU && 3941 mtu != eth_dev->data->mtu) 3942 eth_dev->data->mtu = mtu; 3943 3944 if (BNXT_PF(bp)) { 3945 //if (bp->pf.active_vfs) { 3946 // TODO: Deallocate VF resources? 3947 //} 3948 if (bp->pdev->max_vfs) { 3949 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 3950 if (rc) { 3951 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 3952 goto error_free; 3953 } 3954 } else { 3955 rc = bnxt_hwrm_allocate_pf_only(bp); 3956 if (rc) { 3957 PMD_DRV_LOG(ERR, 3958 "Failed to allocate PF resources\n"); 3959 goto error_free; 3960 } 3961 } 3962 } 3963 3964 bnxt_hwrm_port_led_qcaps(bp); 3965 3966 rc = bnxt_setup_int(bp); 3967 if (rc) 3968 goto error_free; 3969 3970 rc = bnxt_alloc_mem(bp); 3971 if (rc) 3972 goto error_free; 3973 3974 bnxt_init_nic(bp); 3975 3976 rc = bnxt_request_int(bp); 3977 if (rc) 3978 goto error_free; 3979 3980 return 0; 3981 3982 error_free: 3983 bnxt_dev_uninit(eth_dev); 3984 error: 3985 return rc; 3986 } 3987 3988 static int 3989 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 3990 { 3991 struct bnxt *bp = eth_dev->data->dev_private; 3992 int rc; 3993 3994 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3995 return -EPERM; 3996 3997 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 3998 bnxt_disable_int(bp); 3999 bnxt_free_int(bp); 4000 bnxt_free_mem(bp); 4001 4002 bnxt_hwrm_func_buf_unrgtr(bp); 4003 4004 if (bp->grp_info != NULL) { 4005 rte_free(bp->grp_info); 4006 bp->grp_info = NULL; 4007 } 4008 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 4009 bnxt_free_hwrm_resources(bp); 4010 4011 if (bp->tx_mem_zone) { 4012 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 4013 bp->tx_mem_zone = NULL; 4014 } 4015 4016 if (bp->rx_mem_zone) { 4017 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 4018 bp->rx_mem_zone = NULL; 4019 } 4020 4021 if (bp->dev_stopped == 0) 4022 bnxt_dev_close_op(eth_dev); 4023 if (bp->pf.vf_info) 4024 rte_free(bp->pf.vf_info); 4025 bnxt_free_ctx_mem(bp); 4026 eth_dev->dev_ops = NULL; 4027 eth_dev->rx_pkt_burst = NULL; 4028 eth_dev->tx_pkt_burst = NULL; 4029 4030 return rc; 4031 } 4032 4033 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 4034 struct rte_pci_device *pci_dev) 4035 { 4036 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt), 4037 bnxt_dev_init); 4038 } 4039 4040 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 4041 { 4042 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 4043 return rte_eth_dev_pci_generic_remove(pci_dev, 4044 bnxt_dev_uninit); 4045 else 4046 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 4047 } 4048 4049 static struct rte_pci_driver bnxt_rte_pmd = { 4050 .id_table = bnxt_pci_id_map, 4051 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 4052 .probe = bnxt_pci_probe, 4053 .remove = bnxt_pci_remove, 4054 }; 4055 4056 static bool 4057 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 4058 { 4059 if (strcmp(dev->device->driver->name, drv->driver.name)) 4060 return false; 4061 4062 return true; 4063 } 4064 4065 bool is_bnxt_supported(struct rte_eth_dev *dev) 4066 { 4067 return is_device_supported(dev, &bnxt_rte_pmd); 4068 } 4069 4070 RTE_INIT(bnxt_init_log) 4071 { 4072 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver"); 4073 if (bnxt_logtype_driver >= 0) 4074 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE); 4075 } 4076 4077 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 4078 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 4079 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 4080