1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <ethdev_driver.h> 11 #include <ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 #include <rte_kvargs.h> 16 #include <rte_vect.h> 17 18 #include "bnxt.h" 19 #include "bnxt_filter.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_irq.h" 22 #include "bnxt_reps.h" 23 #include "bnxt_ring.h" 24 #include "bnxt_rxq.h" 25 #include "bnxt_rxr.h" 26 #include "bnxt_stats.h" 27 #include "bnxt_txq.h" 28 #include "bnxt_txr.h" 29 #include "bnxt_vnic.h" 30 #include "hsi_struct_def_dpdk.h" 31 #include "bnxt_nvm_defs.h" 32 #include "bnxt_tf_common.h" 33 #include "ulp_flow_db.h" 34 #include "rte_pmd_bnxt.h" 35 36 #define DRV_MODULE_NAME "bnxt" 37 static const char bnxt_version[] = 38 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 39 40 /* 41 * The set of PCI devices this driver supports 42 */ 43 static const struct rte_pci_id bnxt_pci_id_map[] = { 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) }, 87 { .vendor_id = 0, /* sentinel */ }, 88 }; 89 90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow" 91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" 92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" 93 #define BNXT_DEVARG_REPRESENTOR "representor" 94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf" 95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf" 96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f" 97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r" 98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f" 99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r" 100 101 static const char *const bnxt_dev_args[] = { 102 BNXT_DEVARG_REPRESENTOR, 103 BNXT_DEVARG_TRUFLOW, 104 BNXT_DEVARG_FLOW_XSTAT, 105 BNXT_DEVARG_MAX_NUM_KFLOWS, 106 BNXT_DEVARG_REP_BASED_PF, 107 BNXT_DEVARG_REP_IS_PF, 108 BNXT_DEVARG_REP_Q_R2F, 109 BNXT_DEVARG_REP_Q_F2R, 110 BNXT_DEVARG_REP_FC_R2F, 111 BNXT_DEVARG_REP_FC_F2R, 112 NULL 113 }; 114 115 /* 116 * truflow == false to disable the feature 117 * truflow == true to enable the feature 118 */ 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1) 120 121 /* 122 * flow_xstat == false to disable the feature 123 * flow_xstat == true to enable the feature 124 */ 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1) 126 127 /* 128 * rep_is_pf == false to indicate VF representor 129 * rep_is_pf == true to indicate PF representor 130 */ 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1) 132 133 /* 134 * rep_based_pf == Physical index of the PF 135 */ 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15) 137 /* 138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction 139 */ 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3) 141 142 /* 143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction 144 */ 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3) 146 147 /* 148 * rep_fc_r2f == Flow control for the representor to endpoint direction 149 */ 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1) 151 152 /* 153 * rep_fc_f2r == Flow control for the endpoint to representor direction 154 */ 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1) 156 157 int bnxt_cfa_code_dynfield_offset = -1; 158 159 /* 160 * max_num_kflows must be >= 32 161 * and must be a power-of-2 supported value 162 * return: 1 -> invalid 163 * 0 -> valid 164 */ 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows) 166 { 167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows)) 168 return 1; 169 return 0; 170 } 171 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 177 static int bnxt_restore_vlan_filters(struct bnxt *bp); 178 static void bnxt_dev_recover(void *arg); 179 static void bnxt_free_error_recovery_info(struct bnxt *bp); 180 static void bnxt_free_rep_info(struct bnxt *bp); 181 182 int is_bnxt_in_error(struct bnxt *bp) 183 { 184 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 185 return -EIO; 186 if (bp->flags & BNXT_FLAG_FW_RESET) 187 return -EBUSY; 188 189 return 0; 190 } 191 192 /***********************/ 193 194 /* 195 * High level utility functions 196 */ 197 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 199 { 200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings, 201 BNXT_RSS_TBL_SIZE_P5); 202 203 if (!BNXT_CHIP_P5(bp)) 204 return 1; 205 206 return RTE_ALIGN_MUL_CEIL(num_rss_rings, 207 BNXT_RSS_ENTRIES_PER_CTX_P5) / 208 BNXT_RSS_ENTRIES_PER_CTX_P5; 209 } 210 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 212 { 213 if (!BNXT_CHIP_P5(bp)) 214 return HW_HASH_INDEX_SIZE; 215 216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5; 217 } 218 219 static void bnxt_free_parent_info(struct bnxt *bp) 220 { 221 rte_free(bp->parent); 222 bp->parent = NULL; 223 } 224 225 static void bnxt_free_pf_info(struct bnxt *bp) 226 { 227 rte_free(bp->pf); 228 bp->pf = NULL; 229 } 230 231 static void bnxt_free_link_info(struct bnxt *bp) 232 { 233 rte_free(bp->link_info); 234 bp->link_info = NULL; 235 } 236 237 static void bnxt_free_leds_info(struct bnxt *bp) 238 { 239 if (BNXT_VF(bp)) 240 return; 241 242 rte_free(bp->leds); 243 bp->leds = NULL; 244 } 245 246 static void bnxt_free_flow_stats_info(struct bnxt *bp) 247 { 248 rte_free(bp->flow_stat); 249 bp->flow_stat = NULL; 250 } 251 252 static void bnxt_free_cos_queues(struct bnxt *bp) 253 { 254 rte_free(bp->rx_cos_queue); 255 bp->rx_cos_queue = NULL; 256 rte_free(bp->tx_cos_queue); 257 bp->tx_cos_queue = NULL; 258 } 259 260 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 261 { 262 bnxt_free_filter_mem(bp); 263 bnxt_free_vnic_attributes(bp); 264 bnxt_free_vnic_mem(bp); 265 266 /* tx/rx rings are configured as part of *_queue_setup callbacks. 267 * If the number of rings change across fw update, 268 * we don't have much choice except to warn the user. 269 */ 270 if (!reconfig) { 271 bnxt_free_stats(bp); 272 bnxt_free_tx_rings(bp); 273 bnxt_free_rx_rings(bp); 274 } 275 bnxt_free_async_cp_ring(bp); 276 bnxt_free_rxtx_nq_ring(bp); 277 278 rte_free(bp->grp_info); 279 bp->grp_info = NULL; 280 } 281 282 static int bnxt_alloc_parent_info(struct bnxt *bp) 283 { 284 bp->parent = rte_zmalloc("bnxt_parent_info", 285 sizeof(struct bnxt_parent_info), 0); 286 if (bp->parent == NULL) 287 return -ENOMEM; 288 289 return 0; 290 } 291 292 static int bnxt_alloc_pf_info(struct bnxt *bp) 293 { 294 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0); 295 if (bp->pf == NULL) 296 return -ENOMEM; 297 298 return 0; 299 } 300 301 static int bnxt_alloc_link_info(struct bnxt *bp) 302 { 303 bp->link_info = 304 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0); 305 if (bp->link_info == NULL) 306 return -ENOMEM; 307 308 return 0; 309 } 310 311 static int bnxt_alloc_leds_info(struct bnxt *bp) 312 { 313 if (BNXT_VF(bp)) 314 return 0; 315 316 bp->leds = rte_zmalloc("bnxt_leds", 317 BNXT_MAX_LED * sizeof(struct bnxt_led_info), 318 0); 319 if (bp->leds == NULL) 320 return -ENOMEM; 321 322 return 0; 323 } 324 325 static int bnxt_alloc_cos_queues(struct bnxt *bp) 326 { 327 bp->rx_cos_queue = 328 rte_zmalloc("bnxt_rx_cosq", 329 BNXT_COS_QUEUE_COUNT * 330 sizeof(struct bnxt_cos_queue_info), 331 0); 332 if (bp->rx_cos_queue == NULL) 333 return -ENOMEM; 334 335 bp->tx_cos_queue = 336 rte_zmalloc("bnxt_tx_cosq", 337 BNXT_COS_QUEUE_COUNT * 338 sizeof(struct bnxt_cos_queue_info), 339 0); 340 if (bp->tx_cos_queue == NULL) 341 return -ENOMEM; 342 343 return 0; 344 } 345 346 static int bnxt_alloc_flow_stats_info(struct bnxt *bp) 347 { 348 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat", 349 sizeof(struct bnxt_flow_stat_info), 0); 350 if (bp->flow_stat == NULL) 351 return -ENOMEM; 352 353 return 0; 354 } 355 356 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 357 { 358 int rc; 359 360 rc = bnxt_alloc_ring_grps(bp); 361 if (rc) 362 goto alloc_mem_err; 363 364 rc = bnxt_alloc_async_ring_struct(bp); 365 if (rc) 366 goto alloc_mem_err; 367 368 rc = bnxt_alloc_vnic_mem(bp); 369 if (rc) 370 goto alloc_mem_err; 371 372 rc = bnxt_alloc_vnic_attributes(bp); 373 if (rc) 374 goto alloc_mem_err; 375 376 rc = bnxt_alloc_filter_mem(bp); 377 if (rc) 378 goto alloc_mem_err; 379 380 rc = bnxt_alloc_async_cp_ring(bp); 381 if (rc) 382 goto alloc_mem_err; 383 384 rc = bnxt_alloc_rxtx_nq_ring(bp); 385 if (rc) 386 goto alloc_mem_err; 387 388 if (BNXT_FLOW_XSTATS_EN(bp)) { 389 rc = bnxt_alloc_flow_stats_info(bp); 390 if (rc) 391 goto alloc_mem_err; 392 } 393 394 return 0; 395 396 alloc_mem_err: 397 bnxt_free_mem(bp, reconfig); 398 return rc; 399 } 400 401 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 402 { 403 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 404 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 405 uint64_t rx_offloads = dev_conf->rxmode.offloads; 406 struct bnxt_rx_queue *rxq; 407 unsigned int j; 408 int rc; 409 410 rc = bnxt_vnic_grp_alloc(bp, vnic); 411 if (rc) 412 goto err_out; 413 414 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 415 vnic_id, vnic, vnic->fw_grp_ids); 416 417 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 418 if (rc) 419 goto err_out; 420 421 /* Alloc RSS context only if RSS mode is enabled */ 422 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 423 int j, nr_ctxs = bnxt_rss_ctxts(bp); 424 425 /* RSS table size in Thor is 512. 426 * Cap max Rx rings to same value 427 */ 428 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) { 429 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n", 430 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5); 431 goto err_out; 432 } 433 434 rc = 0; 435 for (j = 0; j < nr_ctxs; j++) { 436 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 437 if (rc) 438 break; 439 } 440 if (rc) { 441 PMD_DRV_LOG(ERR, 442 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 443 vnic_id, j, rc); 444 goto err_out; 445 } 446 vnic->num_lb_ctxts = nr_ctxs; 447 } 448 449 /* 450 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 451 * setting is not available at this time, it will not be 452 * configured correctly in the CFA. 453 */ 454 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 455 vnic->vlan_strip = true; 456 else 457 vnic->vlan_strip = false; 458 459 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 460 if (rc) 461 goto err_out; 462 463 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 464 if (rc) 465 goto err_out; 466 467 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 468 rxq = bp->eth_dev->data->rx_queues[j]; 469 470 PMD_DRV_LOG(DEBUG, 471 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 472 j, rxq->vnic, rxq->vnic->fw_grp_ids); 473 474 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 475 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 476 else 477 vnic->rx_queue_cnt++; 478 } 479 480 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 481 482 rc = bnxt_vnic_rss_configure(bp, vnic); 483 if (rc) 484 goto err_out; 485 486 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 487 488 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 489 (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ? 490 true : false); 491 if (rc) 492 goto err_out; 493 494 return 0; 495 err_out: 496 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 497 vnic_id, rc); 498 return rc; 499 } 500 501 static int bnxt_register_fc_ctx_mem(struct bnxt *bp) 502 { 503 int rc = 0; 504 505 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma, 506 &bp->flow_stat->rx_fc_in_tbl.ctx_id); 507 if (rc) 508 return rc; 509 510 PMD_DRV_LOG(DEBUG, 511 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p" 512 " rx_fc_in_tbl.ctx_id = %d\n", 513 bp->flow_stat->rx_fc_in_tbl.va, 514 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma), 515 bp->flow_stat->rx_fc_in_tbl.ctx_id); 516 517 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma, 518 &bp->flow_stat->rx_fc_out_tbl.ctx_id); 519 if (rc) 520 return rc; 521 522 PMD_DRV_LOG(DEBUG, 523 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p" 524 " rx_fc_out_tbl.ctx_id = %d\n", 525 bp->flow_stat->rx_fc_out_tbl.va, 526 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma), 527 bp->flow_stat->rx_fc_out_tbl.ctx_id); 528 529 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma, 530 &bp->flow_stat->tx_fc_in_tbl.ctx_id); 531 if (rc) 532 return rc; 533 534 PMD_DRV_LOG(DEBUG, 535 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p" 536 " tx_fc_in_tbl.ctx_id = %d\n", 537 bp->flow_stat->tx_fc_in_tbl.va, 538 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma), 539 bp->flow_stat->tx_fc_in_tbl.ctx_id); 540 541 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma, 542 &bp->flow_stat->tx_fc_out_tbl.ctx_id); 543 if (rc) 544 return rc; 545 546 PMD_DRV_LOG(DEBUG, 547 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p" 548 " tx_fc_out_tbl.ctx_id = %d\n", 549 bp->flow_stat->tx_fc_out_tbl.va, 550 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma), 551 bp->flow_stat->tx_fc_out_tbl.ctx_id); 552 553 memset(bp->flow_stat->rx_fc_out_tbl.va, 554 0, 555 bp->flow_stat->rx_fc_out_tbl.size); 556 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 557 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 558 bp->flow_stat->rx_fc_out_tbl.ctx_id, 559 bp->flow_stat->max_fc, 560 true); 561 if (rc) 562 return rc; 563 564 memset(bp->flow_stat->tx_fc_out_tbl.va, 565 0, 566 bp->flow_stat->tx_fc_out_tbl.size); 567 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 568 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 569 bp->flow_stat->tx_fc_out_tbl.ctx_id, 570 bp->flow_stat->max_fc, 571 true); 572 573 return rc; 574 } 575 576 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size, 577 struct bnxt_ctx_mem_buf_info *ctx) 578 { 579 if (!ctx) 580 return -EINVAL; 581 582 ctx->va = rte_zmalloc(type, size, 0); 583 if (ctx->va == NULL) 584 return -ENOMEM; 585 rte_mem_lock_page(ctx->va); 586 ctx->size = size; 587 ctx->dma = rte_mem_virt2iova(ctx->va); 588 if (ctx->dma == RTE_BAD_IOVA) 589 return -ENOMEM; 590 591 return 0; 592 } 593 594 static int bnxt_init_fc_ctx_mem(struct bnxt *bp) 595 { 596 struct rte_pci_device *pdev = bp->pdev; 597 char type[RTE_MEMZONE_NAMESIZE]; 598 uint16_t max_fc; 599 int rc = 0; 600 601 max_fc = bp->flow_stat->max_fc; 602 603 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 604 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 605 /* 4 bytes for each counter-id */ 606 rc = bnxt_alloc_ctx_mem_buf(type, 607 max_fc * 4, 608 &bp->flow_stat->rx_fc_in_tbl); 609 if (rc) 610 return rc; 611 612 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 613 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 614 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 615 rc = bnxt_alloc_ctx_mem_buf(type, 616 max_fc * 16, 617 &bp->flow_stat->rx_fc_out_tbl); 618 if (rc) 619 return rc; 620 621 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 622 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 623 /* 4 bytes for each counter-id */ 624 rc = bnxt_alloc_ctx_mem_buf(type, 625 max_fc * 4, 626 &bp->flow_stat->tx_fc_in_tbl); 627 if (rc) 628 return rc; 629 630 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 631 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 632 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 633 rc = bnxt_alloc_ctx_mem_buf(type, 634 max_fc * 16, 635 &bp->flow_stat->tx_fc_out_tbl); 636 if (rc) 637 return rc; 638 639 rc = bnxt_register_fc_ctx_mem(bp); 640 641 return rc; 642 } 643 644 static int bnxt_init_ctx_mem(struct bnxt *bp) 645 { 646 int rc = 0; 647 648 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) || 649 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) || 650 !BNXT_FLOW_XSTATS_EN(bp)) 651 return 0; 652 653 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc); 654 if (rc) 655 return rc; 656 657 rc = bnxt_init_fc_ctx_mem(bp); 658 659 return rc; 660 } 661 662 static int bnxt_update_phy_setting(struct bnxt *bp) 663 { 664 struct rte_eth_link new; 665 int rc; 666 667 rc = bnxt_get_hwrm_link_config(bp, &new); 668 if (rc) { 669 PMD_DRV_LOG(ERR, "Failed to get link settings\n"); 670 return rc; 671 } 672 673 /* 674 * On BCM957508-N2100 adapters, FW will not allow any user other 675 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call 676 * always returns link up. Force phy update always in that case. 677 */ 678 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) { 679 rc = bnxt_set_hwrm_link_config(bp, true); 680 if (rc) { 681 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n"); 682 return rc; 683 } 684 } 685 686 return rc; 687 } 688 689 static int bnxt_start_nic(struct bnxt *bp) 690 { 691 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 692 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 693 uint32_t intr_vector = 0; 694 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 695 uint32_t vec = BNXT_MISC_VEC_ID; 696 unsigned int i, j; 697 int rc; 698 699 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 700 bp->eth_dev->data->dev_conf.rxmode.offloads |= 701 DEV_RX_OFFLOAD_JUMBO_FRAME; 702 bp->flags |= BNXT_FLAG_JUMBO; 703 } else { 704 bp->eth_dev->data->dev_conf.rxmode.offloads &= 705 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 706 bp->flags &= ~BNXT_FLAG_JUMBO; 707 } 708 709 /* THOR does not support ring groups. 710 * But we will use the array to save RSS context IDs. 711 */ 712 if (BNXT_CHIP_P5(bp)) 713 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; 714 715 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 716 if (rc) { 717 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 718 goto err_out; 719 } 720 721 rc = bnxt_alloc_hwrm_rings(bp); 722 if (rc) { 723 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 724 goto err_out; 725 } 726 727 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 728 if (rc) { 729 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 730 goto err_out; 731 } 732 733 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 734 goto skip_cosq_cfg; 735 736 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 737 if (bp->rx_cos_queue[i].id != 0xff) { 738 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 739 740 if (!vnic) { 741 PMD_DRV_LOG(ERR, 742 "Num pools more than FW profile\n"); 743 rc = -EINVAL; 744 goto err_out; 745 } 746 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 747 bp->rx_cosq_cnt++; 748 } 749 } 750 751 skip_cosq_cfg: 752 rc = bnxt_mq_rx_configure(bp); 753 if (rc) { 754 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 755 goto err_out; 756 } 757 758 /* default vnic 0 */ 759 rc = bnxt_setup_one_vnic(bp, 0); 760 if (rc) 761 goto err_out; 762 /* VNIC configuration */ 763 if (BNXT_RFS_NEEDS_VNIC(bp)) { 764 for (i = 1; i < bp->nr_vnics; i++) { 765 rc = bnxt_setup_one_vnic(bp, i); 766 if (rc) 767 goto err_out; 768 } 769 } 770 771 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 772 if (rc) { 773 PMD_DRV_LOG(ERR, 774 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 775 goto err_out; 776 } 777 778 /* check and configure queue intr-vector mapping */ 779 if ((rte_intr_cap_multiple(intr_handle) || 780 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 781 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 782 intr_vector = bp->eth_dev->data->nb_rx_queues; 783 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 784 if (intr_vector > bp->rx_cp_nr_rings) { 785 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 786 bp->rx_cp_nr_rings); 787 return -ENOTSUP; 788 } 789 rc = rte_intr_efd_enable(intr_handle, intr_vector); 790 if (rc) 791 return rc; 792 } 793 794 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 795 intr_handle->intr_vec = 796 rte_zmalloc("intr_vec", 797 bp->eth_dev->data->nb_rx_queues * 798 sizeof(int), 0); 799 if (intr_handle->intr_vec == NULL) { 800 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 801 " intr_vec", bp->eth_dev->data->nb_rx_queues); 802 rc = -ENOMEM; 803 goto err_out; 804 } 805 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 806 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 807 intr_handle->intr_vec, intr_handle->nb_efd, 808 intr_handle->max_intr); 809 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 810 queue_id++) { 811 intr_handle->intr_vec[queue_id] = 812 vec + BNXT_RX_VEC_START; 813 if (vec < base + intr_handle->nb_efd - 1) 814 vec++; 815 } 816 } 817 818 /* enable uio/vfio intr/eventfd mapping */ 819 rc = rte_intr_enable(intr_handle); 820 #ifndef RTE_EXEC_ENV_FREEBSD 821 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 822 if (rc) 823 goto err_out; 824 #endif 825 826 rc = bnxt_update_phy_setting(bp); 827 if (rc) 828 goto err_out; 829 830 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 831 if (!bp->mark_table) 832 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 833 834 return 0; 835 836 err_out: 837 /* Some of the error status returned by FW may not be from errno.h */ 838 if (rc > 0) 839 rc = -EIO; 840 841 return rc; 842 } 843 844 static int bnxt_shutdown_nic(struct bnxt *bp) 845 { 846 bnxt_free_all_hwrm_resources(bp); 847 bnxt_free_all_filters(bp); 848 bnxt_free_all_vnics(bp); 849 return 0; 850 } 851 852 /* 853 * Device configuration and status function 854 */ 855 856 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) 857 { 858 uint32_t link_speed = 0; 859 uint32_t speed_capa = 0; 860 861 if (bp->link_info == NULL) 862 return 0; 863 864 link_speed = bp->link_info->support_speeds; 865 866 /* If PAM4 is configured, use PAM4 supported speed */ 867 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0) 868 link_speed = bp->link_info->support_pam4_speeds; 869 870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) 871 speed_capa |= ETH_LINK_SPEED_100M; 872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) 873 speed_capa |= ETH_LINK_SPEED_100M_HD; 874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) 875 speed_capa |= ETH_LINK_SPEED_1G; 876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 877 speed_capa |= ETH_LINK_SPEED_2_5G; 878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) 879 speed_capa |= ETH_LINK_SPEED_10G; 880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 881 speed_capa |= ETH_LINK_SPEED_20G; 882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) 883 speed_capa |= ETH_LINK_SPEED_25G; 884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) 885 speed_capa |= ETH_LINK_SPEED_40G; 886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) 887 speed_capa |= ETH_LINK_SPEED_50G; 888 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) 889 speed_capa |= ETH_LINK_SPEED_100G; 890 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) 891 speed_capa |= ETH_LINK_SPEED_50G; 892 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) 893 speed_capa |= ETH_LINK_SPEED_100G; 894 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G) 895 speed_capa |= ETH_LINK_SPEED_200G; 896 897 if (bp->link_info->auto_mode == 898 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 899 speed_capa |= ETH_LINK_SPEED_FIXED; 900 901 return speed_capa; 902 } 903 904 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 905 struct rte_eth_dev_info *dev_info) 906 { 907 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 908 struct bnxt *bp = eth_dev->data->dev_private; 909 uint16_t max_vnics, i, j, vpool, vrxq; 910 unsigned int max_rx_rings; 911 int rc; 912 913 rc = is_bnxt_in_error(bp); 914 if (rc) 915 return rc; 916 917 /* MAC Specifics */ 918 dev_info->max_mac_addrs = bp->max_l2_ctx; 919 dev_info->max_hash_mac_addrs = 0; 920 921 /* PF/VF specifics */ 922 if (BNXT_PF(bp)) 923 dev_info->max_vfs = pdev->max_vfs; 924 925 max_rx_rings = bnxt_max_rings(bp); 926 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 927 dev_info->max_rx_queues = max_rx_rings; 928 dev_info->max_tx_queues = max_rx_rings; 929 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 930 dev_info->hash_key_size = 40; 931 max_vnics = bp->max_vnics; 932 933 /* MTU specifics */ 934 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 935 dev_info->max_mtu = BNXT_MAX_MTU; 936 937 /* Fast path specifics */ 938 dev_info->min_rx_bufsize = 1; 939 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 940 941 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 942 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 943 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 944 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 945 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT | 946 dev_info->tx_queue_offload_capa; 947 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 948 949 dev_info->speed_capa = bnxt_get_speed_capabilities(bp); 950 951 /* *INDENT-OFF* */ 952 dev_info->default_rxconf = (struct rte_eth_rxconf) { 953 .rx_thresh = { 954 .pthresh = 8, 955 .hthresh = 8, 956 .wthresh = 0, 957 }, 958 .rx_free_thresh = 32, 959 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN, 960 }; 961 962 dev_info->default_txconf = (struct rte_eth_txconf) { 963 .tx_thresh = { 964 .pthresh = 32, 965 .hthresh = 0, 966 .wthresh = 0, 967 }, 968 .tx_free_thresh = 32, 969 .tx_rs_thresh = 32, 970 }; 971 eth_dev->data->dev_conf.intr_conf.lsc = 1; 972 973 eth_dev->data->dev_conf.intr_conf.rxq = 1; 974 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 975 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 976 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 977 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 978 979 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 980 dev_info->switch_info.name = eth_dev->device->name; 981 dev_info->switch_info.domain_id = bp->switch_domain_id; 982 dev_info->switch_info.port_id = 983 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF : 984 BNXT_SWITCH_PORT_ID_TRUSTED_VF; 985 } 986 987 /* *INDENT-ON* */ 988 989 /* 990 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 991 * need further investigation. 992 */ 993 994 /* VMDq resources */ 995 vpool = 64; /* ETH_64_POOLS */ 996 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 997 for (i = 0; i < 4; vpool >>= 1, i++) { 998 if (max_vnics > vpool) { 999 for (j = 0; j < 5; vrxq >>= 1, j++) { 1000 if (dev_info->max_rx_queues > vrxq) { 1001 if (vpool > vrxq) 1002 vpool = vrxq; 1003 goto found; 1004 } 1005 } 1006 /* Not enough resources to support VMDq */ 1007 break; 1008 } 1009 } 1010 /* Not enough resources to support VMDq */ 1011 vpool = 0; 1012 vrxq = 0; 1013 found: 1014 dev_info->max_vmdq_pools = vpool; 1015 dev_info->vmdq_queue_num = vrxq; 1016 1017 dev_info->vmdq_pool_base = 0; 1018 dev_info->vmdq_queue_base = 0; 1019 1020 return 0; 1021 } 1022 1023 /* Configure the device based on the configuration provided */ 1024 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 1025 { 1026 struct bnxt *bp = eth_dev->data->dev_private; 1027 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1028 int rc; 1029 1030 bp->rx_queues = (void *)eth_dev->data->rx_queues; 1031 bp->tx_queues = (void *)eth_dev->data->tx_queues; 1032 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 1033 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 1034 1035 rc = is_bnxt_in_error(bp); 1036 if (rc) 1037 return rc; 1038 1039 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 1040 rc = bnxt_hwrm_check_vf_rings(bp); 1041 if (rc) { 1042 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 1043 return -ENOSPC; 1044 } 1045 1046 /* If a resource has already been allocated - in this case 1047 * it is the async completion ring, free it. Reallocate it after 1048 * resource reservation. This will ensure the resource counts 1049 * are calculated correctly. 1050 */ 1051 1052 pthread_mutex_lock(&bp->def_cp_lock); 1053 1054 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1055 bnxt_disable_int(bp); 1056 bnxt_free_cp_ring(bp, bp->async_cp_ring); 1057 } 1058 1059 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 1060 if (rc) { 1061 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 1062 pthread_mutex_unlock(&bp->def_cp_lock); 1063 return -ENOSPC; 1064 } 1065 1066 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1067 rc = bnxt_alloc_async_cp_ring(bp); 1068 if (rc) { 1069 pthread_mutex_unlock(&bp->def_cp_lock); 1070 return rc; 1071 } 1072 bnxt_enable_int(bp); 1073 } 1074 1075 pthread_mutex_unlock(&bp->def_cp_lock); 1076 } 1077 1078 /* Inherit new configurations */ 1079 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 1080 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 1081 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 1082 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 1083 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 1084 bp->max_stat_ctx) 1085 goto resource_error; 1086 1087 if (BNXT_HAS_RING_GRPS(bp) && 1088 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 1089 goto resource_error; 1090 1091 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 1092 bp->max_vnics < eth_dev->data->nb_rx_queues) 1093 goto resource_error; 1094 1095 bp->rx_cp_nr_rings = bp->rx_nr_rings; 1096 bp->tx_cp_nr_rings = bp->tx_nr_rings; 1097 1098 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1099 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1100 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 1101 1102 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1103 eth_dev->data->mtu = 1104 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1105 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 1106 BNXT_NUM_VLANS; 1107 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 1108 } 1109 return 0; 1110 1111 resource_error: 1112 PMD_DRV_LOG(ERR, 1113 "Insufficient resources to support requested config\n"); 1114 PMD_DRV_LOG(ERR, 1115 "Num Queues Requested: Tx %d, Rx %d\n", 1116 eth_dev->data->nb_tx_queues, 1117 eth_dev->data->nb_rx_queues); 1118 PMD_DRV_LOG(ERR, 1119 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 1120 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 1121 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 1122 return -ENOSPC; 1123 } 1124 1125 void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 1126 { 1127 struct rte_eth_link *link = ð_dev->data->dev_link; 1128 1129 if (link->link_status) 1130 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 1131 eth_dev->data->port_id, 1132 (uint32_t)link->link_speed, 1133 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 1134 ("full-duplex") : ("half-duplex\n")); 1135 else 1136 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 1137 eth_dev->data->port_id); 1138 } 1139 1140 /* 1141 * Determine whether the current configuration requires support for scattered 1142 * receive; return 1 if scattered receive is required and 0 if not. 1143 */ 1144 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 1145 { 1146 uint16_t buf_size; 1147 int i; 1148 1149 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 1150 return 1; 1151 1152 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) 1153 return 1; 1154 1155 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 1156 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 1157 1158 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1159 RTE_PKTMBUF_HEADROOM); 1160 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 1161 return 1; 1162 } 1163 return 0; 1164 } 1165 1166 static eth_rx_burst_t 1167 bnxt_receive_function(struct rte_eth_dev *eth_dev) 1168 { 1169 struct bnxt *bp = eth_dev->data->dev_private; 1170 1171 /* Disable vector mode RX for Stingray2 for now */ 1172 if (BNXT_CHIP_SR2(bp)) { 1173 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1174 return bnxt_recv_pkts; 1175 } 1176 1177 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 1178 #ifndef RTE_LIBRTE_IEEE1588 1179 /* 1180 * Vector mode receive can be enabled only if scatter rx is not 1181 * in use and rx offloads are limited to VLAN stripping and 1182 * CRC stripping. 1183 */ 1184 if (!eth_dev->data->scattered_rx && 1185 !(eth_dev->data->dev_conf.rxmode.offloads & 1186 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 1187 DEV_RX_OFFLOAD_KEEP_CRC | 1188 DEV_RX_OFFLOAD_JUMBO_FRAME | 1189 DEV_RX_OFFLOAD_IPV4_CKSUM | 1190 DEV_RX_OFFLOAD_UDP_CKSUM | 1191 DEV_RX_OFFLOAD_TCP_CKSUM | 1192 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1193 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 1194 DEV_RX_OFFLOAD_RSS_HASH | 1195 DEV_RX_OFFLOAD_VLAN_FILTER)) && 1196 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) && 1197 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1198 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 1199 eth_dev->data->port_id); 1200 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1201 return bnxt_recv_pkts_vec; 1202 } 1203 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 1204 eth_dev->data->port_id); 1205 PMD_DRV_LOG(INFO, 1206 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 1207 eth_dev->data->port_id, 1208 eth_dev->data->scattered_rx, 1209 eth_dev->data->dev_conf.rxmode.offloads); 1210 #endif 1211 #endif 1212 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1213 return bnxt_recv_pkts; 1214 } 1215 1216 static eth_tx_burst_t 1217 bnxt_transmit_function(struct rte_eth_dev *eth_dev) 1218 { 1219 struct bnxt *bp = eth_dev->data->dev_private; 1220 1221 /* Disable vector mode TX for Stingray2 for now */ 1222 if (BNXT_CHIP_SR2(bp)) 1223 return bnxt_xmit_pkts; 1224 1225 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 1226 #ifndef RTE_LIBRTE_IEEE1588 1227 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; 1228 1229 /* 1230 * Vector mode transmit can be enabled only if not using scatter rx 1231 * or tx offloads. 1232 */ 1233 if (!eth_dev->data->scattered_rx && 1234 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) && 1235 !BNXT_TRUFLOW_EN(bp) && 1236 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1237 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 1238 eth_dev->data->port_id); 1239 return bnxt_xmit_pkts_vec; 1240 } 1241 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 1242 eth_dev->data->port_id); 1243 PMD_DRV_LOG(INFO, 1244 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 1245 eth_dev->data->port_id, 1246 eth_dev->data->scattered_rx, 1247 offloads); 1248 #endif 1249 #endif 1250 return bnxt_xmit_pkts; 1251 } 1252 1253 static int bnxt_handle_if_change_status(struct bnxt *bp) 1254 { 1255 int rc; 1256 1257 /* Since fw has undergone a reset and lost all contexts, 1258 * set fatal flag to not issue hwrm during cleanup 1259 */ 1260 bp->flags |= BNXT_FLAG_FATAL_ERROR; 1261 bnxt_uninit_resources(bp, true); 1262 1263 /* clear fatal flag so that re-init happens */ 1264 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 1265 rc = bnxt_init_resources(bp, true); 1266 1267 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 1268 1269 return rc; 1270 } 1271 1272 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 1273 { 1274 struct bnxt *bp = eth_dev->data->dev_private; 1275 int rc = 0; 1276 1277 if (!BNXT_SINGLE_PF(bp)) 1278 return -ENOTSUP; 1279 1280 if (!bp->link_info->link_up) 1281 rc = bnxt_set_hwrm_link_config(bp, true); 1282 if (!rc) 1283 eth_dev->data->dev_link.link_status = 1; 1284 1285 bnxt_print_link_info(eth_dev); 1286 return rc; 1287 } 1288 1289 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 1290 { 1291 struct bnxt *bp = eth_dev->data->dev_private; 1292 1293 if (!BNXT_SINGLE_PF(bp)) 1294 return -ENOTSUP; 1295 1296 eth_dev->data->dev_link.link_status = 0; 1297 bnxt_set_hwrm_link_config(bp, false); 1298 bp->link_info->link_up = 0; 1299 1300 return 0; 1301 } 1302 1303 static void bnxt_free_switch_domain(struct bnxt *bp) 1304 { 1305 int rc = 0; 1306 1307 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) 1308 return; 1309 1310 rc = rte_eth_switch_domain_free(bp->switch_domain_id); 1311 if (rc) 1312 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n", 1313 bp->switch_domain_id, rc); 1314 } 1315 1316 static void bnxt_ptp_get_current_time(void *arg) 1317 { 1318 struct bnxt *bp = arg; 1319 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1320 int rc; 1321 1322 rc = is_bnxt_in_error(bp); 1323 if (rc) 1324 return; 1325 1326 if (!ptp) 1327 return; 1328 1329 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1330 &ptp->current_time); 1331 1332 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1333 if (rc != 0) { 1334 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n"); 1335 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1336 } 1337 } 1338 1339 static int bnxt_schedule_ptp_alarm(struct bnxt *bp) 1340 { 1341 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1342 int rc; 1343 1344 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) 1345 return 0; 1346 1347 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1348 &ptp->current_time); 1349 1350 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1351 return rc; 1352 } 1353 1354 static void bnxt_cancel_ptp_alarm(struct bnxt *bp) 1355 { 1356 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) { 1357 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp); 1358 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1359 } 1360 } 1361 1362 static void bnxt_ptp_stop(struct bnxt *bp) 1363 { 1364 bnxt_cancel_ptp_alarm(bp); 1365 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1366 } 1367 1368 static int bnxt_ptp_start(struct bnxt *bp) 1369 { 1370 int rc; 1371 1372 rc = bnxt_schedule_ptp_alarm(bp); 1373 if (rc != 0) { 1374 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n"); 1375 } else { 1376 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1377 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1378 } 1379 1380 return rc; 1381 } 1382 1383 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev) 1384 { 1385 struct bnxt *bp = eth_dev->data->dev_private; 1386 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1387 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1388 struct rte_eth_link link; 1389 int ret; 1390 1391 eth_dev->data->dev_started = 0; 1392 eth_dev->data->scattered_rx = 0; 1393 1394 /* Prevent crashes when queues are still in use */ 1395 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 1396 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 1397 1398 bnxt_disable_int(bp); 1399 1400 /* disable uio/vfio intr/eventfd mapping */ 1401 rte_intr_disable(intr_handle); 1402 1403 /* Stop the child representors for this device */ 1404 ret = bnxt_rep_stop_all(bp); 1405 if (ret != 0) 1406 return ret; 1407 1408 /* delete the bnxt ULP port details */ 1409 bnxt_ulp_port_deinit(bp); 1410 1411 bnxt_cancel_fw_health_check(bp); 1412 1413 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1414 bnxt_cancel_ptp_alarm(bp); 1415 1416 /* Do not bring link down during reset recovery */ 1417 if (!is_bnxt_in_error(bp)) { 1418 bnxt_dev_set_link_down_op(eth_dev); 1419 /* Wait for link to be reset */ 1420 if (BNXT_SINGLE_PF(bp)) 1421 rte_delay_ms(500); 1422 /* clear the recorded link status */ 1423 memset(&link, 0, sizeof(link)); 1424 rte_eth_linkstatus_set(eth_dev, &link); 1425 } 1426 1427 /* Clean queue intr-vector mapping */ 1428 rte_intr_efd_disable(intr_handle); 1429 if (intr_handle->intr_vec != NULL) { 1430 rte_free(intr_handle->intr_vec); 1431 intr_handle->intr_vec = NULL; 1432 } 1433 1434 bnxt_hwrm_port_clr_stats(bp); 1435 bnxt_free_tx_mbufs(bp); 1436 bnxt_free_rx_mbufs(bp); 1437 /* Process any remaining notifications in default completion queue */ 1438 bnxt_int_handler(eth_dev); 1439 bnxt_shutdown_nic(bp); 1440 bnxt_hwrm_if_change(bp, false); 1441 1442 rte_free(bp->mark_table); 1443 bp->mark_table = NULL; 1444 1445 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1446 bp->rx_cosq_cnt = 0; 1447 /* All filters are deleted on a port stop. */ 1448 if (BNXT_FLOW_XSTATS_EN(bp)) 1449 bp->flow_stat->flow_count = 0; 1450 1451 return 0; 1452 } 1453 1454 /* Unload the driver, release resources */ 1455 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 1456 { 1457 struct bnxt *bp = eth_dev->data->dev_private; 1458 1459 pthread_mutex_lock(&bp->err_recovery_lock); 1460 if (bp->flags & BNXT_FLAG_FW_RESET) { 1461 PMD_DRV_LOG(ERR, 1462 "Adapter recovering from error..Please retry\n"); 1463 pthread_mutex_unlock(&bp->err_recovery_lock); 1464 return -EAGAIN; 1465 } 1466 pthread_mutex_unlock(&bp->err_recovery_lock); 1467 1468 return bnxt_dev_stop(eth_dev); 1469 } 1470 1471 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 1472 { 1473 struct bnxt *bp = eth_dev->data->dev_private; 1474 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1475 int vlan_mask = 0; 1476 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; 1477 1478 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 1479 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 1480 return -EINVAL; 1481 } 1482 1483 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) 1484 PMD_DRV_LOG(ERR, 1485 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 1486 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1487 1488 do { 1489 rc = bnxt_hwrm_if_change(bp, true); 1490 if (rc == 0 || rc != -EAGAIN) 1491 break; 1492 1493 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); 1494 } while (retry_cnt--); 1495 1496 if (rc) 1497 return rc; 1498 1499 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 1500 rc = bnxt_handle_if_change_status(bp); 1501 if (rc) 1502 return rc; 1503 } 1504 1505 bnxt_enable_int(bp); 1506 1507 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 1508 1509 rc = bnxt_start_nic(bp); 1510 if (rc) 1511 goto error; 1512 1513 eth_dev->data->dev_started = 1; 1514 1515 bnxt_link_update_op(eth_dev, 1); 1516 1517 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1518 vlan_mask |= ETH_VLAN_FILTER_MASK; 1519 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1520 vlan_mask |= ETH_VLAN_STRIP_MASK; 1521 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 1522 if (rc) 1523 goto error; 1524 1525 /* Initialize bnxt ULP port details */ 1526 rc = bnxt_ulp_port_init(bp); 1527 if (rc) 1528 goto error; 1529 1530 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 1531 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 1532 1533 bnxt_schedule_fw_health_check(bp); 1534 1535 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1536 bnxt_schedule_ptp_alarm(bp); 1537 1538 return 0; 1539 1540 error: 1541 bnxt_dev_stop(eth_dev); 1542 return rc; 1543 } 1544 1545 static void 1546 bnxt_uninit_locks(struct bnxt *bp) 1547 { 1548 pthread_mutex_destroy(&bp->flow_lock); 1549 pthread_mutex_destroy(&bp->def_cp_lock); 1550 pthread_mutex_destroy(&bp->health_check_lock); 1551 pthread_mutex_destroy(&bp->err_recovery_lock); 1552 if (bp->rep_info) { 1553 pthread_mutex_destroy(&bp->rep_info->vfr_lock); 1554 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); 1555 } 1556 } 1557 1558 static void bnxt_drv_uninit(struct bnxt *bp) 1559 { 1560 bnxt_free_leds_info(bp); 1561 bnxt_free_cos_queues(bp); 1562 bnxt_free_link_info(bp); 1563 bnxt_free_parent_info(bp); 1564 bnxt_uninit_locks(bp); 1565 1566 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 1567 bp->tx_mem_zone = NULL; 1568 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 1569 bp->rx_mem_zone = NULL; 1570 1571 bnxt_free_vf_info(bp); 1572 bnxt_free_pf_info(bp); 1573 1574 rte_free(bp->grp_info); 1575 bp->grp_info = NULL; 1576 } 1577 1578 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 1579 { 1580 struct bnxt *bp = eth_dev->data->dev_private; 1581 int ret = 0; 1582 1583 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1584 return 0; 1585 1586 pthread_mutex_lock(&bp->err_recovery_lock); 1587 if (bp->flags & BNXT_FLAG_FW_RESET) { 1588 PMD_DRV_LOG(ERR, 1589 "Adapter recovering from error...Please retry\n"); 1590 pthread_mutex_unlock(&bp->err_recovery_lock); 1591 return -EAGAIN; 1592 } 1593 pthread_mutex_unlock(&bp->err_recovery_lock); 1594 1595 /* cancel the recovery handler before remove dev */ 1596 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); 1597 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); 1598 bnxt_cancel_fc_thread(bp); 1599 1600 if (eth_dev->data->dev_started) 1601 ret = bnxt_dev_stop(eth_dev); 1602 1603 bnxt_uninit_resources(bp, false); 1604 1605 bnxt_drv_uninit(bp); 1606 1607 return ret; 1608 } 1609 1610 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1611 uint32_t index) 1612 { 1613 struct bnxt *bp = eth_dev->data->dev_private; 1614 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1615 struct bnxt_vnic_info *vnic; 1616 struct bnxt_filter_info *filter, *temp_filter; 1617 uint32_t i; 1618 1619 if (is_bnxt_in_error(bp)) 1620 return; 1621 1622 /* 1623 * Loop through all VNICs from the specified filter flow pools to 1624 * remove the corresponding MAC addr filter 1625 */ 1626 for (i = 0; i < bp->nr_vnics; i++) { 1627 if (!(pool_mask & (1ULL << i))) 1628 continue; 1629 1630 vnic = &bp->vnic_info[i]; 1631 filter = STAILQ_FIRST(&vnic->filter); 1632 while (filter) { 1633 temp_filter = STAILQ_NEXT(filter, next); 1634 if (filter->mac_index == index) { 1635 STAILQ_REMOVE(&vnic->filter, filter, 1636 bnxt_filter_info, next); 1637 bnxt_hwrm_clear_l2_filter(bp, filter); 1638 bnxt_free_filter(bp, filter); 1639 } 1640 filter = temp_filter; 1641 } 1642 } 1643 } 1644 1645 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1646 struct rte_ether_addr *mac_addr, uint32_t index, 1647 uint32_t pool) 1648 { 1649 struct bnxt_filter_info *filter; 1650 int rc = 0; 1651 1652 /* Attach requested MAC address to the new l2_filter */ 1653 STAILQ_FOREACH(filter, &vnic->filter, next) { 1654 if (filter->mac_index == index) { 1655 PMD_DRV_LOG(DEBUG, 1656 "MAC addr already existed for pool %d\n", 1657 pool); 1658 return 0; 1659 } 1660 } 1661 1662 filter = bnxt_alloc_filter(bp); 1663 if (!filter) { 1664 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1665 return -ENODEV; 1666 } 1667 1668 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1669 * if the MAC that's been programmed now is a different one, then, 1670 * copy that addr to filter->l2_addr 1671 */ 1672 if (mac_addr) 1673 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1674 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1675 1676 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1677 if (!rc) { 1678 filter->mac_index = index; 1679 if (filter->mac_index == 0) 1680 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1681 else 1682 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1683 } else { 1684 bnxt_free_filter(bp, filter); 1685 } 1686 1687 return rc; 1688 } 1689 1690 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1691 struct rte_ether_addr *mac_addr, 1692 uint32_t index, uint32_t pool) 1693 { 1694 struct bnxt *bp = eth_dev->data->dev_private; 1695 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1696 int rc = 0; 1697 1698 rc = is_bnxt_in_error(bp); 1699 if (rc) 1700 return rc; 1701 1702 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 1703 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1704 return -ENOTSUP; 1705 } 1706 1707 if (!vnic) { 1708 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1709 return -EINVAL; 1710 } 1711 1712 /* Filter settings will get applied when port is started */ 1713 if (!eth_dev->data->dev_started) 1714 return 0; 1715 1716 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1717 1718 return rc; 1719 } 1720 1721 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 1722 { 1723 int rc = 0; 1724 struct bnxt *bp = eth_dev->data->dev_private; 1725 struct rte_eth_link new; 1726 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT : 1727 BNXT_MIN_LINK_WAIT_CNT; 1728 1729 rc = is_bnxt_in_error(bp); 1730 if (rc) 1731 return rc; 1732 1733 memset(&new, 0, sizeof(new)); 1734 1735 if (bp->link_info == NULL) 1736 goto out; 1737 1738 do { 1739 /* Retrieve link info from hardware */ 1740 rc = bnxt_get_hwrm_link_config(bp, &new); 1741 if (rc) { 1742 new.link_speed = ETH_LINK_SPEED_100M; 1743 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1744 PMD_DRV_LOG(ERR, 1745 "Failed to retrieve link rc = 0x%x!\n", rc); 1746 goto out; 1747 } 1748 1749 if (!wait_to_complete || new.link_status) 1750 break; 1751 1752 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1753 } while (cnt--); 1754 1755 /* Only single function PF can bring phy down. 1756 * When port is stopped, report link down for VF/MH/NPAR functions. 1757 */ 1758 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started) 1759 memset(&new, 0, sizeof(new)); 1760 1761 out: 1762 /* Timed out or success */ 1763 if (new.link_status != eth_dev->data->dev_link.link_status || 1764 new.link_speed != eth_dev->data->dev_link.link_speed) { 1765 rte_eth_linkstatus_set(eth_dev, &new); 1766 1767 rte_eth_dev_callback_process(eth_dev, 1768 RTE_ETH_EVENT_INTR_LSC, 1769 NULL); 1770 1771 bnxt_print_link_info(eth_dev); 1772 } 1773 1774 return rc; 1775 } 1776 1777 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1778 { 1779 struct bnxt *bp = eth_dev->data->dev_private; 1780 struct bnxt_vnic_info *vnic; 1781 uint32_t old_flags; 1782 int rc; 1783 1784 rc = is_bnxt_in_error(bp); 1785 if (rc) 1786 return rc; 1787 1788 /* Filter settings will get applied when port is started */ 1789 if (!eth_dev->data->dev_started) 1790 return 0; 1791 1792 if (bp->vnic_info == NULL) 1793 return 0; 1794 1795 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1796 1797 old_flags = vnic->flags; 1798 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1799 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1800 if (rc != 0) 1801 vnic->flags = old_flags; 1802 1803 return rc; 1804 } 1805 1806 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1807 { 1808 struct bnxt *bp = eth_dev->data->dev_private; 1809 struct bnxt_vnic_info *vnic; 1810 uint32_t old_flags; 1811 int rc; 1812 1813 rc = is_bnxt_in_error(bp); 1814 if (rc) 1815 return rc; 1816 1817 /* Filter settings will get applied when port is started */ 1818 if (!eth_dev->data->dev_started) 1819 return 0; 1820 1821 if (bp->vnic_info == NULL) 1822 return 0; 1823 1824 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1825 1826 old_flags = vnic->flags; 1827 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1828 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1829 if (rc != 0) 1830 vnic->flags = old_flags; 1831 1832 return rc; 1833 } 1834 1835 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1836 { 1837 struct bnxt *bp = eth_dev->data->dev_private; 1838 struct bnxt_vnic_info *vnic; 1839 uint32_t old_flags; 1840 int rc; 1841 1842 rc = is_bnxt_in_error(bp); 1843 if (rc) 1844 return rc; 1845 1846 /* Filter settings will get applied when port is started */ 1847 if (!eth_dev->data->dev_started) 1848 return 0; 1849 1850 if (bp->vnic_info == NULL) 1851 return 0; 1852 1853 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1854 1855 old_flags = vnic->flags; 1856 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1857 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1858 if (rc != 0) 1859 vnic->flags = old_flags; 1860 1861 return rc; 1862 } 1863 1864 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1865 { 1866 struct bnxt *bp = eth_dev->data->dev_private; 1867 struct bnxt_vnic_info *vnic; 1868 uint32_t old_flags; 1869 int rc; 1870 1871 rc = is_bnxt_in_error(bp); 1872 if (rc) 1873 return rc; 1874 1875 /* Filter settings will get applied when port is started */ 1876 if (!eth_dev->data->dev_started) 1877 return 0; 1878 1879 if (bp->vnic_info == NULL) 1880 return 0; 1881 1882 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1883 1884 old_flags = vnic->flags; 1885 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1886 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1887 if (rc != 0) 1888 vnic->flags = old_flags; 1889 1890 return rc; 1891 } 1892 1893 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1894 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1895 { 1896 if (qid >= bp->rx_nr_rings) 1897 return NULL; 1898 1899 return bp->eth_dev->data->rx_queues[qid]; 1900 } 1901 1902 /* Return rxq corresponding to a given rss table ring/group ID. */ 1903 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1904 { 1905 struct bnxt_rx_queue *rxq; 1906 unsigned int i; 1907 1908 if (!BNXT_HAS_RING_GRPS(bp)) { 1909 for (i = 0; i < bp->rx_nr_rings; i++) { 1910 rxq = bp->eth_dev->data->rx_queues[i]; 1911 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1912 return rxq->index; 1913 } 1914 } else { 1915 for (i = 0; i < bp->rx_nr_rings; i++) { 1916 if (bp->grp_info[i].fw_grp_id == fwr) 1917 return i; 1918 } 1919 } 1920 1921 return INVALID_HW_RING_ID; 1922 } 1923 1924 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1925 struct rte_eth_rss_reta_entry64 *reta_conf, 1926 uint16_t reta_size) 1927 { 1928 struct bnxt *bp = eth_dev->data->dev_private; 1929 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1930 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1931 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1932 uint16_t idx, sft; 1933 int i, rc; 1934 1935 rc = is_bnxt_in_error(bp); 1936 if (rc) 1937 return rc; 1938 1939 if (!vnic->rss_table) 1940 return -EINVAL; 1941 1942 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1943 return -EINVAL; 1944 1945 if (reta_size != tbl_size) { 1946 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1947 "(%d) must equal the size supported by the hardware " 1948 "(%d)\n", reta_size, tbl_size); 1949 return -EINVAL; 1950 } 1951 1952 for (i = 0; i < reta_size; i++) { 1953 struct bnxt_rx_queue *rxq; 1954 1955 idx = i / RTE_RETA_GROUP_SIZE; 1956 sft = i % RTE_RETA_GROUP_SIZE; 1957 1958 if (!(reta_conf[idx].mask & (1ULL << sft))) 1959 continue; 1960 1961 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1962 if (!rxq) { 1963 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1964 return -EINVAL; 1965 } 1966 1967 if (BNXT_CHIP_P5(bp)) { 1968 vnic->rss_table[i * 2] = 1969 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1970 vnic->rss_table[i * 2 + 1] = 1971 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1972 } else { 1973 vnic->rss_table[i] = 1974 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1975 } 1976 } 1977 1978 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1979 return rc; 1980 } 1981 1982 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1983 struct rte_eth_rss_reta_entry64 *reta_conf, 1984 uint16_t reta_size) 1985 { 1986 struct bnxt *bp = eth_dev->data->dev_private; 1987 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1988 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1989 uint16_t idx, sft, i; 1990 int rc; 1991 1992 rc = is_bnxt_in_error(bp); 1993 if (rc) 1994 return rc; 1995 1996 /* Retrieve from the default VNIC */ 1997 if (!vnic) 1998 return -EINVAL; 1999 if (!vnic->rss_table) 2000 return -EINVAL; 2001 2002 if (reta_size != tbl_size) { 2003 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 2004 "(%d) must equal the size supported by the hardware " 2005 "(%d)\n", reta_size, tbl_size); 2006 return -EINVAL; 2007 } 2008 2009 for (idx = 0, i = 0; i < reta_size; i++) { 2010 idx = i / RTE_RETA_GROUP_SIZE; 2011 sft = i % RTE_RETA_GROUP_SIZE; 2012 2013 if (reta_conf[idx].mask & (1ULL << sft)) { 2014 uint16_t qid; 2015 2016 if (BNXT_CHIP_P5(bp)) 2017 qid = bnxt_rss_to_qid(bp, 2018 vnic->rss_table[i * 2]); 2019 else 2020 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 2021 2022 if (qid == INVALID_HW_RING_ID) { 2023 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 2024 return -EINVAL; 2025 } 2026 reta_conf[idx].reta[sft] = qid; 2027 } 2028 } 2029 2030 return 0; 2031 } 2032 2033 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 2034 struct rte_eth_rss_conf *rss_conf) 2035 { 2036 struct bnxt *bp = eth_dev->data->dev_private; 2037 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 2038 struct bnxt_vnic_info *vnic; 2039 int rc; 2040 2041 rc = is_bnxt_in_error(bp); 2042 if (rc) 2043 return rc; 2044 2045 /* 2046 * If RSS enablement were different than dev_configure, 2047 * then return -EINVAL 2048 */ 2049 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 2050 if (!rss_conf->rss_hf) 2051 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 2052 } else { 2053 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 2054 return -EINVAL; 2055 } 2056 2057 bp->flags |= BNXT_FLAG_UPDATE_HASH; 2058 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf, 2059 rss_conf, 2060 sizeof(*rss_conf)); 2061 2062 /* Update the default RSS VNIC(s) */ 2063 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2064 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 2065 vnic->hash_mode = 2066 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf, 2067 ETH_RSS_LEVEL(rss_conf->rss_hf)); 2068 2069 /* 2070 * If hashkey is not specified, use the previously configured 2071 * hashkey 2072 */ 2073 if (!rss_conf->rss_key) 2074 goto rss_config; 2075 2076 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 2077 PMD_DRV_LOG(ERR, 2078 "Invalid hashkey length, should be 16 bytes\n"); 2079 return -EINVAL; 2080 } 2081 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 2082 2083 rss_config: 2084 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 2085 return rc; 2086 } 2087 2088 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 2089 struct rte_eth_rss_conf *rss_conf) 2090 { 2091 struct bnxt *bp = eth_dev->data->dev_private; 2092 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2093 int len, rc; 2094 uint32_t hash_types; 2095 2096 rc = is_bnxt_in_error(bp); 2097 if (rc) 2098 return rc; 2099 2100 /* RSS configuration is the same for all VNICs */ 2101 if (vnic && vnic->rss_hash_key) { 2102 if (rss_conf->rss_key) { 2103 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 2104 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 2105 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 2106 } 2107 2108 hash_types = vnic->hash_type; 2109 rss_conf->rss_hf = 0; 2110 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 2111 rss_conf->rss_hf |= ETH_RSS_IPV4; 2112 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 2113 } 2114 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 2115 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 2116 hash_types &= 2117 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 2118 } 2119 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 2120 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 2121 hash_types &= 2122 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 2123 } 2124 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 2125 rss_conf->rss_hf |= ETH_RSS_IPV6; 2126 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 2127 } 2128 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 2129 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 2130 hash_types &= 2131 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 2132 } 2133 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 2134 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 2135 hash_types &= 2136 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 2137 } 2138 2139 rss_conf->rss_hf |= 2140 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode); 2141 2142 if (hash_types) { 2143 PMD_DRV_LOG(ERR, 2144 "Unknown RSS config from firmware (%08x), RSS disabled", 2145 vnic->hash_type); 2146 return -ENOTSUP; 2147 } 2148 } else { 2149 rss_conf->rss_hf = 0; 2150 } 2151 return 0; 2152 } 2153 2154 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 2155 struct rte_eth_fc_conf *fc_conf) 2156 { 2157 struct bnxt *bp = dev->data->dev_private; 2158 struct rte_eth_link link_info; 2159 int rc; 2160 2161 rc = is_bnxt_in_error(bp); 2162 if (rc) 2163 return rc; 2164 2165 rc = bnxt_get_hwrm_link_config(bp, &link_info); 2166 if (rc) 2167 return rc; 2168 2169 memset(fc_conf, 0, sizeof(*fc_conf)); 2170 if (bp->link_info->auto_pause) 2171 fc_conf->autoneg = 1; 2172 switch (bp->link_info->pause) { 2173 case 0: 2174 fc_conf->mode = RTE_FC_NONE; 2175 break; 2176 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 2177 fc_conf->mode = RTE_FC_TX_PAUSE; 2178 break; 2179 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 2180 fc_conf->mode = RTE_FC_RX_PAUSE; 2181 break; 2182 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 2183 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 2184 fc_conf->mode = RTE_FC_FULL; 2185 break; 2186 } 2187 return 0; 2188 } 2189 2190 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 2191 struct rte_eth_fc_conf *fc_conf) 2192 { 2193 struct bnxt *bp = dev->data->dev_private; 2194 int rc; 2195 2196 rc = is_bnxt_in_error(bp); 2197 if (rc) 2198 return rc; 2199 2200 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2201 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 2202 return -ENOTSUP; 2203 } 2204 2205 switch (fc_conf->mode) { 2206 case RTE_FC_NONE: 2207 bp->link_info->auto_pause = 0; 2208 bp->link_info->force_pause = 0; 2209 break; 2210 case RTE_FC_RX_PAUSE: 2211 if (fc_conf->autoneg) { 2212 bp->link_info->auto_pause = 2213 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2214 bp->link_info->force_pause = 0; 2215 } else { 2216 bp->link_info->auto_pause = 0; 2217 bp->link_info->force_pause = 2218 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2219 } 2220 break; 2221 case RTE_FC_TX_PAUSE: 2222 if (fc_conf->autoneg) { 2223 bp->link_info->auto_pause = 2224 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 2225 bp->link_info->force_pause = 0; 2226 } else { 2227 bp->link_info->auto_pause = 0; 2228 bp->link_info->force_pause = 2229 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 2230 } 2231 break; 2232 case RTE_FC_FULL: 2233 if (fc_conf->autoneg) { 2234 bp->link_info->auto_pause = 2235 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 2236 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2237 bp->link_info->force_pause = 0; 2238 } else { 2239 bp->link_info->auto_pause = 0; 2240 bp->link_info->force_pause = 2241 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 2242 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2243 } 2244 break; 2245 } 2246 return bnxt_set_hwrm_link_config(bp, true); 2247 } 2248 2249 /* Add UDP tunneling port */ 2250 static int 2251 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 2252 struct rte_eth_udp_tunnel *udp_tunnel) 2253 { 2254 struct bnxt *bp = eth_dev->data->dev_private; 2255 uint16_t tunnel_type = 0; 2256 int rc = 0; 2257 2258 rc = is_bnxt_in_error(bp); 2259 if (rc) 2260 return rc; 2261 2262 switch (udp_tunnel->prot_type) { 2263 case RTE_TUNNEL_TYPE_VXLAN: 2264 if (bp->vxlan_port_cnt) { 2265 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2266 udp_tunnel->udp_port); 2267 if (bp->vxlan_port != udp_tunnel->udp_port) { 2268 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2269 return -ENOSPC; 2270 } 2271 bp->vxlan_port_cnt++; 2272 return 0; 2273 } 2274 tunnel_type = 2275 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 2276 bp->vxlan_port_cnt++; 2277 break; 2278 case RTE_TUNNEL_TYPE_GENEVE: 2279 if (bp->geneve_port_cnt) { 2280 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2281 udp_tunnel->udp_port); 2282 if (bp->geneve_port != udp_tunnel->udp_port) { 2283 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2284 return -ENOSPC; 2285 } 2286 bp->geneve_port_cnt++; 2287 return 0; 2288 } 2289 tunnel_type = 2290 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 2291 bp->geneve_port_cnt++; 2292 break; 2293 default: 2294 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2295 return -ENOTSUP; 2296 } 2297 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 2298 tunnel_type); 2299 return rc; 2300 } 2301 2302 static int 2303 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 2304 struct rte_eth_udp_tunnel *udp_tunnel) 2305 { 2306 struct bnxt *bp = eth_dev->data->dev_private; 2307 uint16_t tunnel_type = 0; 2308 uint16_t port = 0; 2309 int rc = 0; 2310 2311 rc = is_bnxt_in_error(bp); 2312 if (rc) 2313 return rc; 2314 2315 switch (udp_tunnel->prot_type) { 2316 case RTE_TUNNEL_TYPE_VXLAN: 2317 if (!bp->vxlan_port_cnt) { 2318 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2319 return -EINVAL; 2320 } 2321 if (bp->vxlan_port != udp_tunnel->udp_port) { 2322 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2323 udp_tunnel->udp_port, bp->vxlan_port); 2324 return -EINVAL; 2325 } 2326 if (--bp->vxlan_port_cnt) 2327 return 0; 2328 2329 tunnel_type = 2330 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 2331 port = bp->vxlan_fw_dst_port_id; 2332 break; 2333 case RTE_TUNNEL_TYPE_GENEVE: 2334 if (!bp->geneve_port_cnt) { 2335 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2336 return -EINVAL; 2337 } 2338 if (bp->geneve_port != udp_tunnel->udp_port) { 2339 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2340 udp_tunnel->udp_port, bp->geneve_port); 2341 return -EINVAL; 2342 } 2343 if (--bp->geneve_port_cnt) 2344 return 0; 2345 2346 tunnel_type = 2347 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 2348 port = bp->geneve_fw_dst_port_id; 2349 break; 2350 default: 2351 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2352 return -ENOTSUP; 2353 } 2354 2355 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 2356 return rc; 2357 } 2358 2359 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2360 { 2361 struct bnxt_filter_info *filter; 2362 struct bnxt_vnic_info *vnic; 2363 int rc = 0; 2364 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2365 2366 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2367 filter = STAILQ_FIRST(&vnic->filter); 2368 while (filter) { 2369 /* Search for this matching MAC+VLAN filter */ 2370 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 2371 /* Delete the filter */ 2372 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2373 if (rc) 2374 return rc; 2375 STAILQ_REMOVE(&vnic->filter, filter, 2376 bnxt_filter_info, next); 2377 bnxt_free_filter(bp, filter); 2378 PMD_DRV_LOG(INFO, 2379 "Deleted vlan filter for %d\n", 2380 vlan_id); 2381 return 0; 2382 } 2383 filter = STAILQ_NEXT(filter, next); 2384 } 2385 return -ENOENT; 2386 } 2387 2388 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2389 { 2390 struct bnxt_filter_info *filter; 2391 struct bnxt_vnic_info *vnic; 2392 int rc = 0; 2393 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 2394 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 2395 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2396 2397 /* Implementation notes on the use of VNIC in this command: 2398 * 2399 * By default, these filters belong to default vnic for the function. 2400 * Once these filters are set up, only destination VNIC can be modified. 2401 * If the destination VNIC is not specified in this command, 2402 * then the HWRM shall only create an l2 context id. 2403 */ 2404 2405 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2406 filter = STAILQ_FIRST(&vnic->filter); 2407 /* Check if the VLAN has already been added */ 2408 while (filter) { 2409 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 2410 return -EEXIST; 2411 2412 filter = STAILQ_NEXT(filter, next); 2413 } 2414 2415 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 2416 * command to create MAC+VLAN filter with the right flags, enables set. 2417 */ 2418 filter = bnxt_alloc_filter(bp); 2419 if (!filter) { 2420 PMD_DRV_LOG(ERR, 2421 "MAC/VLAN filter alloc failed\n"); 2422 return -ENOMEM; 2423 } 2424 /* MAC + VLAN ID filter */ 2425 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 2426 * untagged packets are received 2427 * 2428 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 2429 * packets and only the programmed vlan's packets are received 2430 */ 2431 filter->l2_ivlan = vlan_id; 2432 filter->l2_ivlan_mask = 0x0FFF; 2433 filter->enables |= en; 2434 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2435 2436 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2437 if (rc) { 2438 /* Free the newly allocated filter as we were 2439 * not able to create the filter in hardware. 2440 */ 2441 bnxt_free_filter(bp, filter); 2442 return rc; 2443 } 2444 2445 filter->mac_index = 0; 2446 /* Add this new filter to the list */ 2447 if (vlan_id == 0) 2448 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 2449 else 2450 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2451 2452 PMD_DRV_LOG(INFO, 2453 "Added Vlan filter for %d\n", vlan_id); 2454 return rc; 2455 } 2456 2457 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 2458 uint16_t vlan_id, int on) 2459 { 2460 struct bnxt *bp = eth_dev->data->dev_private; 2461 int rc; 2462 2463 rc = is_bnxt_in_error(bp); 2464 if (rc) 2465 return rc; 2466 2467 if (!eth_dev->data->dev_started) { 2468 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n"); 2469 return -EINVAL; 2470 } 2471 2472 /* These operations apply to ALL existing MAC/VLAN filters */ 2473 if (on) 2474 return bnxt_add_vlan_filter(bp, vlan_id); 2475 else 2476 return bnxt_del_vlan_filter(bp, vlan_id); 2477 } 2478 2479 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 2480 struct bnxt_vnic_info *vnic) 2481 { 2482 struct bnxt_filter_info *filter; 2483 int rc; 2484 2485 filter = STAILQ_FIRST(&vnic->filter); 2486 while (filter) { 2487 if (filter->mac_index == 0 && 2488 !memcmp(filter->l2_addr, bp->mac_addr, 2489 RTE_ETHER_ADDR_LEN)) { 2490 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2491 if (!rc) { 2492 STAILQ_REMOVE(&vnic->filter, filter, 2493 bnxt_filter_info, next); 2494 bnxt_free_filter(bp, filter); 2495 } 2496 return rc; 2497 } 2498 filter = STAILQ_NEXT(filter, next); 2499 } 2500 return 0; 2501 } 2502 2503 static int 2504 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 2505 { 2506 struct bnxt_vnic_info *vnic; 2507 unsigned int i; 2508 int rc; 2509 2510 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2511 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 2512 /* Remove any VLAN filters programmed */ 2513 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2514 bnxt_del_vlan_filter(bp, i); 2515 2516 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2517 if (rc) 2518 return rc; 2519 } else { 2520 /* Default filter will allow packets that match the 2521 * dest mac. So, it has to be deleted, otherwise, we 2522 * will endup receiving vlan packets for which the 2523 * filter is not programmed, when hw-vlan-filter 2524 * configuration is ON 2525 */ 2526 bnxt_del_dflt_mac_filter(bp, vnic); 2527 /* This filter will allow only untagged packets */ 2528 bnxt_add_vlan_filter(bp, 0); 2529 } 2530 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 2531 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 2532 2533 return 0; 2534 } 2535 2536 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 2537 { 2538 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2539 unsigned int i; 2540 int rc; 2541 2542 /* Destroy vnic filters and vnic */ 2543 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2544 DEV_RX_OFFLOAD_VLAN_FILTER) { 2545 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2546 bnxt_del_vlan_filter(bp, i); 2547 } 2548 bnxt_del_dflt_mac_filter(bp, vnic); 2549 2550 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic); 2551 if (rc) 2552 return rc; 2553 2554 rc = bnxt_hwrm_vnic_free(bp, vnic); 2555 if (rc) 2556 return rc; 2557 2558 rte_free(vnic->fw_grp_ids); 2559 vnic->fw_grp_ids = NULL; 2560 2561 vnic->rx_queue_cnt = 0; 2562 2563 return 0; 2564 } 2565 2566 static int 2567 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 2568 { 2569 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2570 int rc; 2571 2572 /* Destroy, recreate and reconfigure the default vnic */ 2573 rc = bnxt_free_one_vnic(bp, 0); 2574 if (rc) 2575 return rc; 2576 2577 /* default vnic 0 */ 2578 rc = bnxt_setup_one_vnic(bp, 0); 2579 if (rc) 2580 return rc; 2581 2582 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2583 DEV_RX_OFFLOAD_VLAN_FILTER) { 2584 rc = bnxt_add_vlan_filter(bp, 0); 2585 if (rc) 2586 return rc; 2587 rc = bnxt_restore_vlan_filters(bp); 2588 if (rc) 2589 return rc; 2590 } else { 2591 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2592 if (rc) 2593 return rc; 2594 } 2595 2596 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2597 if (rc) 2598 return rc; 2599 2600 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 2601 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 2602 2603 return rc; 2604 } 2605 2606 static int 2607 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 2608 { 2609 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 2610 struct bnxt *bp = dev->data->dev_private; 2611 int rc; 2612 2613 rc = is_bnxt_in_error(bp); 2614 if (rc) 2615 return rc; 2616 2617 /* Filter settings will get applied when port is started */ 2618 if (!dev->data->dev_started) 2619 return 0; 2620 2621 if (mask & ETH_VLAN_FILTER_MASK) { 2622 /* Enable or disable VLAN filtering */ 2623 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 2624 if (rc) 2625 return rc; 2626 } 2627 2628 if (mask & ETH_VLAN_STRIP_MASK) { 2629 /* Enable or disable VLAN stripping */ 2630 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2631 if (rc) 2632 return rc; 2633 } 2634 2635 if (mask & ETH_VLAN_EXTEND_MASK) { 2636 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2637 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2638 else 2639 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2640 } 2641 2642 return 0; 2643 } 2644 2645 static int 2646 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2647 uint16_t tpid) 2648 { 2649 struct bnxt *bp = dev->data->dev_private; 2650 int qinq = dev->data->dev_conf.rxmode.offloads & 2651 DEV_RX_OFFLOAD_VLAN_EXTEND; 2652 2653 if (vlan_type != ETH_VLAN_TYPE_INNER && 2654 vlan_type != ETH_VLAN_TYPE_OUTER) { 2655 PMD_DRV_LOG(ERR, 2656 "Unsupported vlan type."); 2657 return -EINVAL; 2658 } 2659 if (!qinq) { 2660 PMD_DRV_LOG(ERR, 2661 "QinQ not enabled. Needs to be ON as we can " 2662 "accelerate only outer vlan\n"); 2663 return -EINVAL; 2664 } 2665 2666 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 2667 switch (tpid) { 2668 case RTE_ETHER_TYPE_QINQ: 2669 bp->outer_tpid_bd = 2670 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2671 break; 2672 case RTE_ETHER_TYPE_VLAN: 2673 bp->outer_tpid_bd = 2674 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2675 break; 2676 case RTE_ETHER_TYPE_QINQ1: 2677 bp->outer_tpid_bd = 2678 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2679 break; 2680 case RTE_ETHER_TYPE_QINQ2: 2681 bp->outer_tpid_bd = 2682 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2683 break; 2684 case RTE_ETHER_TYPE_QINQ3: 2685 bp->outer_tpid_bd = 2686 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2687 break; 2688 default: 2689 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2690 return -EINVAL; 2691 } 2692 bp->outer_tpid_bd |= tpid; 2693 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2694 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 2695 PMD_DRV_LOG(ERR, 2696 "Can accelerate only outer vlan in QinQ\n"); 2697 return -EINVAL; 2698 } 2699 2700 return 0; 2701 } 2702 2703 static int 2704 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2705 struct rte_ether_addr *addr) 2706 { 2707 struct bnxt *bp = dev->data->dev_private; 2708 /* Default Filter is tied to VNIC 0 */ 2709 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2710 int rc; 2711 2712 rc = is_bnxt_in_error(bp); 2713 if (rc) 2714 return rc; 2715 2716 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2717 return -EPERM; 2718 2719 if (rte_is_zero_ether_addr(addr)) 2720 return -EINVAL; 2721 2722 /* Filter settings will get applied when port is started */ 2723 if (!dev->data->dev_started) 2724 return 0; 2725 2726 /* Check if the requested MAC is already added */ 2727 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2728 return 0; 2729 2730 /* Destroy filter and re-create it */ 2731 bnxt_del_dflt_mac_filter(bp, vnic); 2732 2733 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2734 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 2735 /* This filter will allow only untagged packets */ 2736 rc = bnxt_add_vlan_filter(bp, 0); 2737 } else { 2738 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2739 } 2740 2741 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2742 return rc; 2743 } 2744 2745 static int 2746 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2747 struct rte_ether_addr *mc_addr_set, 2748 uint32_t nb_mc_addr) 2749 { 2750 struct bnxt *bp = eth_dev->data->dev_private; 2751 char *mc_addr_list = (char *)mc_addr_set; 2752 struct bnxt_vnic_info *vnic; 2753 uint32_t off = 0, i = 0; 2754 int rc; 2755 2756 rc = is_bnxt_in_error(bp); 2757 if (rc) 2758 return rc; 2759 2760 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2761 2762 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2763 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2764 goto allmulti; 2765 } 2766 2767 /* TODO Check for Duplicate mcast addresses */ 2768 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2769 for (i = 0; i < nb_mc_addr; i++) { 2770 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2771 RTE_ETHER_ADDR_LEN); 2772 off += RTE_ETHER_ADDR_LEN; 2773 } 2774 2775 vnic->mc_addr_cnt = i; 2776 if (vnic->mc_addr_cnt) 2777 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2778 else 2779 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2780 2781 allmulti: 2782 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2783 } 2784 2785 static int 2786 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2787 { 2788 struct bnxt *bp = dev->data->dev_private; 2789 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2790 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2791 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2792 uint8_t fw_rsvd = bp->fw_ver & 0xff; 2793 int ret; 2794 2795 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", 2796 fw_major, fw_minor, fw_updt, fw_rsvd); 2797 if (ret < 0) 2798 return -EINVAL; 2799 2800 ret += 1; /* add the size of '\0' */ 2801 if (fw_size < (size_t)ret) 2802 return ret; 2803 else 2804 return 0; 2805 } 2806 2807 static void 2808 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2809 struct rte_eth_rxq_info *qinfo) 2810 { 2811 struct bnxt *bp = dev->data->dev_private; 2812 struct bnxt_rx_queue *rxq; 2813 2814 if (is_bnxt_in_error(bp)) 2815 return; 2816 2817 rxq = dev->data->rx_queues[queue_id]; 2818 2819 qinfo->mp = rxq->mb_pool; 2820 qinfo->scattered_rx = dev->data->scattered_rx; 2821 qinfo->nb_desc = rxq->nb_rx_desc; 2822 2823 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2824 qinfo->conf.rx_drop_en = rxq->drop_en; 2825 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2826 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 2827 } 2828 2829 static void 2830 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2831 struct rte_eth_txq_info *qinfo) 2832 { 2833 struct bnxt *bp = dev->data->dev_private; 2834 struct bnxt_tx_queue *txq; 2835 2836 if (is_bnxt_in_error(bp)) 2837 return; 2838 2839 txq = dev->data->tx_queues[queue_id]; 2840 2841 qinfo->nb_desc = txq->nb_tx_desc; 2842 2843 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2844 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2845 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2846 2847 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2848 qinfo->conf.tx_rs_thresh = 0; 2849 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2850 qinfo->conf.offloads = txq->offloads; 2851 } 2852 2853 static const struct { 2854 eth_rx_burst_t pkt_burst; 2855 const char *info; 2856 } bnxt_rx_burst_info[] = { 2857 {bnxt_recv_pkts, "Scalar"}, 2858 #if defined(RTE_ARCH_X86) 2859 {bnxt_recv_pkts_vec, "Vector SSE"}, 2860 #elif defined(RTE_ARCH_ARM64) 2861 {bnxt_recv_pkts_vec, "Vector Neon"}, 2862 #endif 2863 }; 2864 2865 static int 2866 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2867 struct rte_eth_burst_mode *mode) 2868 { 2869 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 2870 size_t i; 2871 2872 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) { 2873 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) { 2874 snprintf(mode->info, sizeof(mode->info), "%s", 2875 bnxt_rx_burst_info[i].info); 2876 return 0; 2877 } 2878 } 2879 2880 return -EINVAL; 2881 } 2882 2883 static const struct { 2884 eth_tx_burst_t pkt_burst; 2885 const char *info; 2886 } bnxt_tx_burst_info[] = { 2887 {bnxt_xmit_pkts, "Scalar"}, 2888 #if defined(RTE_ARCH_X86) 2889 {bnxt_xmit_pkts_vec, "Vector SSE"}, 2890 #elif defined(RTE_ARCH_ARM64) 2891 {bnxt_xmit_pkts_vec, "Vector Neon"}, 2892 #endif 2893 }; 2894 2895 static int 2896 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2897 struct rte_eth_burst_mode *mode) 2898 { 2899 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 2900 size_t i; 2901 2902 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) { 2903 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) { 2904 snprintf(mode->info, sizeof(mode->info), "%s", 2905 bnxt_tx_burst_info[i].info); 2906 return 0; 2907 } 2908 } 2909 2910 return -EINVAL; 2911 } 2912 2913 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 2914 { 2915 struct bnxt *bp = eth_dev->data->dev_private; 2916 uint32_t new_pkt_size; 2917 uint32_t rc = 0; 2918 uint32_t i; 2919 2920 rc = is_bnxt_in_error(bp); 2921 if (rc) 2922 return rc; 2923 2924 /* Exit if receive queues are not configured yet */ 2925 if (!eth_dev->data->nb_rx_queues) 2926 return rc; 2927 2928 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 2929 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 2930 2931 /* 2932 * Disallow any MTU change that would require scattered receive support 2933 * if it is not already enabled. 2934 */ 2935 if (eth_dev->data->dev_started && 2936 !eth_dev->data->scattered_rx && 2937 (new_pkt_size > 2938 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 2939 PMD_DRV_LOG(ERR, 2940 "MTU change would require scattered rx support. "); 2941 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 2942 return -EINVAL; 2943 } 2944 2945 if (new_mtu > RTE_ETHER_MTU) { 2946 bp->flags |= BNXT_FLAG_JUMBO; 2947 bp->eth_dev->data->dev_conf.rxmode.offloads |= 2948 DEV_RX_OFFLOAD_JUMBO_FRAME; 2949 } else { 2950 bp->eth_dev->data->dev_conf.rxmode.offloads &= 2951 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2952 bp->flags &= ~BNXT_FLAG_JUMBO; 2953 } 2954 2955 /* Is there a change in mtu setting? */ 2956 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) 2957 return rc; 2958 2959 for (i = 0; i < bp->nr_vnics; i++) { 2960 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2961 uint16_t size = 0; 2962 2963 vnic->mru = BNXT_VNIC_MRU(new_mtu); 2964 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 2965 if (rc) 2966 break; 2967 2968 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 2969 size -= RTE_PKTMBUF_HEADROOM; 2970 2971 if (size < new_mtu) { 2972 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 2973 if (rc) 2974 return rc; 2975 } 2976 } 2977 2978 if (!rc) 2979 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 2980 2981 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 2982 2983 return rc; 2984 } 2985 2986 static int 2987 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 2988 { 2989 struct bnxt *bp = dev->data->dev_private; 2990 uint16_t vlan = bp->vlan; 2991 int rc; 2992 2993 rc = is_bnxt_in_error(bp); 2994 if (rc) 2995 return rc; 2996 2997 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2998 PMD_DRV_LOG(ERR, 2999 "PVID cannot be modified for this function\n"); 3000 return -ENOTSUP; 3001 } 3002 bp->vlan = on ? pvid : 0; 3003 3004 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 3005 if (rc) 3006 bp->vlan = vlan; 3007 return rc; 3008 } 3009 3010 static int 3011 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 3012 { 3013 struct bnxt *bp = dev->data->dev_private; 3014 int rc; 3015 3016 rc = is_bnxt_in_error(bp); 3017 if (rc) 3018 return rc; 3019 3020 return bnxt_hwrm_port_led_cfg(bp, true); 3021 } 3022 3023 static int 3024 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 3025 { 3026 struct bnxt *bp = dev->data->dev_private; 3027 int rc; 3028 3029 rc = is_bnxt_in_error(bp); 3030 if (rc) 3031 return rc; 3032 3033 return bnxt_hwrm_port_led_cfg(bp, false); 3034 } 3035 3036 static uint32_t 3037 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 3038 { 3039 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 3040 struct bnxt_cp_ring_info *cpr; 3041 uint32_t desc = 0, raw_cons; 3042 struct bnxt_rx_queue *rxq; 3043 struct rx_pkt_cmpl *rxcmp; 3044 int rc; 3045 3046 rc = is_bnxt_in_error(bp); 3047 if (rc) 3048 return rc; 3049 3050 rxq = dev->data->rx_queues[rx_queue_id]; 3051 cpr = rxq->cp_ring; 3052 raw_cons = cpr->cp_raw_cons; 3053 3054 while (1) { 3055 uint32_t agg_cnt, cons, cmpl_type; 3056 3057 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3058 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3059 3060 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 3061 break; 3062 3063 cmpl_type = CMP_TYPE(rxcmp); 3064 3065 switch (cmpl_type) { 3066 case CMPL_BASE_TYPE_RX_L2: 3067 case CMPL_BASE_TYPE_RX_L2_V2: 3068 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3069 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3070 desc++; 3071 break; 3072 3073 case CMPL_BASE_TYPE_RX_TPA_END: 3074 if (BNXT_CHIP_P5(rxq->bp)) { 3075 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3076 3077 p5_tpa_end = (void *)rxcmp; 3078 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3079 } else { 3080 struct rx_tpa_end_cmpl *tpa_end; 3081 3082 tpa_end = (void *)rxcmp; 3083 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3084 } 3085 3086 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3087 desc++; 3088 break; 3089 3090 default: 3091 raw_cons += CMP_LEN(cmpl_type); 3092 } 3093 } 3094 3095 return desc; 3096 } 3097 3098 static int 3099 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 3100 { 3101 struct bnxt_rx_queue *rxq = rx_queue; 3102 struct bnxt_cp_ring_info *cpr; 3103 struct bnxt_rx_ring_info *rxr; 3104 uint32_t desc, raw_cons; 3105 struct bnxt *bp = rxq->bp; 3106 struct rx_pkt_cmpl *rxcmp; 3107 int rc; 3108 3109 rc = is_bnxt_in_error(bp); 3110 if (rc) 3111 return rc; 3112 3113 if (offset >= rxq->nb_rx_desc) 3114 return -EINVAL; 3115 3116 rxr = rxq->rx_ring; 3117 cpr = rxq->cp_ring; 3118 3119 /* 3120 * For the vector receive case, the completion at the requested 3121 * offset can be indexed directly. 3122 */ 3123 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 3124 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) { 3125 struct rx_pkt_cmpl *rxcmp; 3126 uint32_t cons; 3127 3128 /* Check status of completion descriptor. */ 3129 raw_cons = cpr->cp_raw_cons + 3130 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2); 3131 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3132 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3133 3134 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 3135 return RTE_ETH_RX_DESC_DONE; 3136 3137 /* Check whether rx desc has an mbuf attached. */ 3138 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2); 3139 if (cons >= rxq->rxrearm_start && 3140 cons < rxq->rxrearm_start + rxq->rxrearm_nb) { 3141 return RTE_ETH_RX_DESC_UNAVAIL; 3142 } 3143 3144 return RTE_ETH_RX_DESC_AVAIL; 3145 } 3146 #endif 3147 3148 /* 3149 * For the non-vector receive case, scan the completion ring to 3150 * locate the completion descriptor for the requested offset. 3151 */ 3152 raw_cons = cpr->cp_raw_cons; 3153 desc = 0; 3154 while (1) { 3155 uint32_t agg_cnt, cons, cmpl_type; 3156 3157 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3158 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3159 3160 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 3161 break; 3162 3163 cmpl_type = CMP_TYPE(rxcmp); 3164 3165 switch (cmpl_type) { 3166 case CMPL_BASE_TYPE_RX_L2: 3167 case CMPL_BASE_TYPE_RX_L2_V2: 3168 if (desc == offset) { 3169 cons = rxcmp->opaque; 3170 if (rxr->rx_buf_ring[cons]) 3171 return RTE_ETH_RX_DESC_DONE; 3172 else 3173 return RTE_ETH_RX_DESC_UNAVAIL; 3174 } 3175 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3176 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3177 desc++; 3178 break; 3179 3180 case CMPL_BASE_TYPE_RX_TPA_END: 3181 if (desc == offset) 3182 return RTE_ETH_RX_DESC_DONE; 3183 3184 if (BNXT_CHIP_P5(rxq->bp)) { 3185 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3186 3187 p5_tpa_end = (void *)rxcmp; 3188 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3189 } else { 3190 struct rx_tpa_end_cmpl *tpa_end; 3191 3192 tpa_end = (void *)rxcmp; 3193 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3194 } 3195 3196 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3197 desc++; 3198 break; 3199 3200 default: 3201 raw_cons += CMP_LEN(cmpl_type); 3202 } 3203 } 3204 3205 return RTE_ETH_RX_DESC_AVAIL; 3206 } 3207 3208 static int 3209 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 3210 { 3211 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 3212 struct bnxt_tx_ring_info *txr; 3213 struct bnxt_cp_ring_info *cpr; 3214 struct rte_mbuf **tx_buf; 3215 struct tx_pkt_cmpl *txcmp; 3216 uint32_t cons, cp_cons; 3217 int rc; 3218 3219 if (!txq) 3220 return -EINVAL; 3221 3222 rc = is_bnxt_in_error(txq->bp); 3223 if (rc) 3224 return rc; 3225 3226 cpr = txq->cp_ring; 3227 txr = txq->tx_ring; 3228 3229 if (offset >= txq->nb_tx_desc) 3230 return -EINVAL; 3231 3232 cons = RING_CMP(cpr->cp_ring_struct, offset); 3233 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3234 cp_cons = cpr->cp_raw_cons; 3235 3236 if (cons > cp_cons) { 3237 if (CMPL_VALID(txcmp, cpr->valid)) 3238 return RTE_ETH_TX_DESC_UNAVAIL; 3239 } else { 3240 if (CMPL_VALID(txcmp, !cpr->valid)) 3241 return RTE_ETH_TX_DESC_UNAVAIL; 3242 } 3243 tx_buf = &txr->tx_buf_ring[cons]; 3244 if (*tx_buf == NULL) 3245 return RTE_ETH_TX_DESC_DONE; 3246 3247 return RTE_ETH_TX_DESC_FULL; 3248 } 3249 3250 int 3251 bnxt_flow_ops_get_op(struct rte_eth_dev *dev, 3252 const struct rte_flow_ops **ops) 3253 { 3254 struct bnxt *bp = dev->data->dev_private; 3255 int ret = 0; 3256 3257 if (!bp) 3258 return -EIO; 3259 3260 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) { 3261 struct bnxt_representor *vfr = dev->data->dev_private; 3262 bp = vfr->parent_dev->data->dev_private; 3263 /* parent is deleted while children are still valid */ 3264 if (!bp) { 3265 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n", 3266 dev->data->port_id); 3267 return -EIO; 3268 } 3269 } 3270 3271 ret = is_bnxt_in_error(bp); 3272 if (ret) 3273 return ret; 3274 3275 /* PMD supports thread-safe flow operations. rte_flow API 3276 * functions can avoid mutex for multi-thread safety. 3277 */ 3278 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 3279 3280 if (BNXT_TRUFLOW_EN(bp)) 3281 *ops = &bnxt_ulp_rte_flow_ops; 3282 else 3283 *ops = &bnxt_flow_ops; 3284 3285 return ret; 3286 } 3287 3288 static const uint32_t * 3289 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3290 { 3291 static const uint32_t ptypes[] = { 3292 RTE_PTYPE_L2_ETHER_VLAN, 3293 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3294 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3295 RTE_PTYPE_L4_ICMP, 3296 RTE_PTYPE_L4_TCP, 3297 RTE_PTYPE_L4_UDP, 3298 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3299 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3300 RTE_PTYPE_INNER_L4_ICMP, 3301 RTE_PTYPE_INNER_L4_TCP, 3302 RTE_PTYPE_INNER_L4_UDP, 3303 RTE_PTYPE_UNKNOWN 3304 }; 3305 3306 if (!dev->rx_pkt_burst) 3307 return NULL; 3308 3309 return ptypes; 3310 } 3311 3312 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3313 int reg_win) 3314 { 3315 uint32_t reg_base = *reg_arr & 0xfffff000; 3316 uint32_t win_off; 3317 int i; 3318 3319 for (i = 0; i < count; i++) { 3320 if ((reg_arr[i] & 0xfffff000) != reg_base) 3321 return -ERANGE; 3322 } 3323 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3324 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3325 return 0; 3326 } 3327 3328 static int bnxt_map_ptp_regs(struct bnxt *bp) 3329 { 3330 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3331 uint32_t *reg_arr; 3332 int rc, i; 3333 3334 reg_arr = ptp->rx_regs; 3335 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3336 if (rc) 3337 return rc; 3338 3339 reg_arr = ptp->tx_regs; 3340 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3341 if (rc) 3342 return rc; 3343 3344 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3345 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3346 3347 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3348 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3349 3350 return 0; 3351 } 3352 3353 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3354 { 3355 rte_write32(0, (uint8_t *)bp->bar0 + 3356 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3357 rte_write32(0, (uint8_t *)bp->bar0 + 3358 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3359 } 3360 3361 static uint64_t bnxt_cc_read(struct bnxt *bp) 3362 { 3363 uint64_t ns; 3364 3365 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3366 BNXT_GRCPF_REG_SYNC_TIME)); 3367 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3368 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3369 return ns; 3370 } 3371 3372 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3373 { 3374 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3375 uint32_t fifo; 3376 3377 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3378 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3379 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3380 return -EAGAIN; 3381 3382 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3383 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3384 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3385 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3386 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3387 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3388 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]); 3389 3390 return 0; 3391 } 3392 3393 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3394 { 3395 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3396 struct bnxt_pf_info *pf = bp->pf; 3397 uint16_t port_id; 3398 uint32_t fifo; 3399 3400 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3401 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3402 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3403 return -EAGAIN; 3404 3405 port_id = pf->port_id; 3406 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3407 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3408 3409 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3410 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3411 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 3412 /* bnxt_clr_rx_ts(bp); TBD */ 3413 return -EBUSY; 3414 } 3415 3416 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3417 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3418 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3419 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3420 3421 return 0; 3422 } 3423 3424 static int 3425 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3426 { 3427 uint64_t ns; 3428 struct bnxt *bp = dev->data->dev_private; 3429 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3430 3431 if (!ptp) 3432 return -ENOTSUP; 3433 3434 ns = rte_timespec_to_ns(ts); 3435 /* Set the timecounters to a new value. */ 3436 ptp->tc.nsec = ns; 3437 ptp->tx_tstamp_tc.nsec = ns; 3438 ptp->rx_tstamp_tc.nsec = ns; 3439 3440 return 0; 3441 } 3442 3443 static int 3444 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3445 { 3446 struct bnxt *bp = dev->data->dev_private; 3447 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3448 uint64_t ns, systime_cycles = 0; 3449 int rc = 0; 3450 3451 if (!ptp) 3452 return -ENOTSUP; 3453 3454 if (BNXT_CHIP_P5(bp)) 3455 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3456 &systime_cycles); 3457 else 3458 systime_cycles = bnxt_cc_read(bp); 3459 3460 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3461 *ts = rte_ns_to_timespec(ns); 3462 3463 return rc; 3464 } 3465 static int 3466 bnxt_timesync_enable(struct rte_eth_dev *dev) 3467 { 3468 struct bnxt *bp = dev->data->dev_private; 3469 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3470 uint32_t shift = 0; 3471 int rc; 3472 3473 if (!ptp) 3474 return -ENOTSUP; 3475 3476 ptp->rx_filter = 1; 3477 ptp->tx_tstamp_en = 1; 3478 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3479 3480 rc = bnxt_hwrm_ptp_cfg(bp); 3481 if (rc) 3482 return rc; 3483 3484 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3485 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3486 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3487 3488 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3489 ptp->tc.cc_shift = shift; 3490 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3491 3492 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3493 ptp->rx_tstamp_tc.cc_shift = shift; 3494 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3495 3496 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3497 ptp->tx_tstamp_tc.cc_shift = shift; 3498 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3499 3500 if (!BNXT_CHIP_P5(bp)) 3501 bnxt_map_ptp_regs(bp); 3502 else 3503 rc = bnxt_ptp_start(bp); 3504 3505 return rc; 3506 } 3507 3508 static int 3509 bnxt_timesync_disable(struct rte_eth_dev *dev) 3510 { 3511 struct bnxt *bp = dev->data->dev_private; 3512 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3513 3514 if (!ptp) 3515 return -ENOTSUP; 3516 3517 ptp->rx_filter = 0; 3518 ptp->tx_tstamp_en = 0; 3519 ptp->rxctl = 0; 3520 3521 bnxt_hwrm_ptp_cfg(bp); 3522 3523 if (!BNXT_CHIP_P5(bp)) 3524 bnxt_unmap_ptp_regs(bp); 3525 else 3526 bnxt_ptp_stop(bp); 3527 3528 return 0; 3529 } 3530 3531 static int 3532 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3533 struct timespec *timestamp, 3534 uint32_t flags __rte_unused) 3535 { 3536 struct bnxt *bp = dev->data->dev_private; 3537 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3538 uint64_t rx_tstamp_cycles = 0; 3539 uint64_t ns; 3540 3541 if (!ptp) 3542 return -ENOTSUP; 3543 3544 if (BNXT_CHIP_P5(bp)) 3545 rx_tstamp_cycles = ptp->rx_timestamp; 3546 else 3547 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3548 3549 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3550 *timestamp = rte_ns_to_timespec(ns); 3551 return 0; 3552 } 3553 3554 static int 3555 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3556 struct timespec *timestamp) 3557 { 3558 struct bnxt *bp = dev->data->dev_private; 3559 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3560 uint64_t tx_tstamp_cycles = 0; 3561 uint64_t ns; 3562 int rc = 0; 3563 3564 if (!ptp) 3565 return -ENOTSUP; 3566 3567 if (BNXT_CHIP_P5(bp)) 3568 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3569 &tx_tstamp_cycles); 3570 else 3571 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3572 3573 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3574 *timestamp = rte_ns_to_timespec(ns); 3575 3576 return rc; 3577 } 3578 3579 static int 3580 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3581 { 3582 struct bnxt *bp = dev->data->dev_private; 3583 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3584 3585 if (!ptp) 3586 return -ENOTSUP; 3587 3588 ptp->tc.nsec += delta; 3589 ptp->tx_tstamp_tc.nsec += delta; 3590 ptp->rx_tstamp_tc.nsec += delta; 3591 3592 return 0; 3593 } 3594 3595 static int 3596 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3597 { 3598 struct bnxt *bp = dev->data->dev_private; 3599 int rc; 3600 uint32_t dir_entries; 3601 uint32_t entry_length; 3602 3603 rc = is_bnxt_in_error(bp); 3604 if (rc) 3605 return rc; 3606 3607 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 3608 bp->pdev->addr.domain, bp->pdev->addr.bus, 3609 bp->pdev->addr.devid, bp->pdev->addr.function); 3610 3611 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3612 if (rc != 0) 3613 return rc; 3614 3615 return dir_entries * entry_length; 3616 } 3617 3618 static int 3619 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3620 struct rte_dev_eeprom_info *in_eeprom) 3621 { 3622 struct bnxt *bp = dev->data->dev_private; 3623 uint32_t index; 3624 uint32_t offset; 3625 int rc; 3626 3627 rc = is_bnxt_in_error(bp); 3628 if (rc) 3629 return rc; 3630 3631 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3632 bp->pdev->addr.domain, bp->pdev->addr.bus, 3633 bp->pdev->addr.devid, bp->pdev->addr.function, 3634 in_eeprom->offset, in_eeprom->length); 3635 3636 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3637 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3638 in_eeprom->data); 3639 3640 index = in_eeprom->offset >> 24; 3641 offset = in_eeprom->offset & 0xffffff; 3642 3643 if (index != 0) 3644 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3645 in_eeprom->length, in_eeprom->data); 3646 3647 return 0; 3648 } 3649 3650 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3651 { 3652 switch (dir_type) { 3653 case BNX_DIR_TYPE_CHIMP_PATCH: 3654 case BNX_DIR_TYPE_BOOTCODE: 3655 case BNX_DIR_TYPE_BOOTCODE_2: 3656 case BNX_DIR_TYPE_APE_FW: 3657 case BNX_DIR_TYPE_APE_PATCH: 3658 case BNX_DIR_TYPE_KONG_FW: 3659 case BNX_DIR_TYPE_KONG_PATCH: 3660 case BNX_DIR_TYPE_BONO_FW: 3661 case BNX_DIR_TYPE_BONO_PATCH: 3662 /* FALLTHROUGH */ 3663 return true; 3664 } 3665 3666 return false; 3667 } 3668 3669 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3670 { 3671 switch (dir_type) { 3672 case BNX_DIR_TYPE_AVS: 3673 case BNX_DIR_TYPE_EXP_ROM_MBA: 3674 case BNX_DIR_TYPE_PCIE: 3675 case BNX_DIR_TYPE_TSCF_UCODE: 3676 case BNX_DIR_TYPE_EXT_PHY: 3677 case BNX_DIR_TYPE_CCM: 3678 case BNX_DIR_TYPE_ISCSI_BOOT: 3679 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3680 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3681 /* FALLTHROUGH */ 3682 return true; 3683 } 3684 3685 return false; 3686 } 3687 3688 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3689 { 3690 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3691 bnxt_dir_type_is_other_exec_format(dir_type); 3692 } 3693 3694 static int 3695 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3696 struct rte_dev_eeprom_info *in_eeprom) 3697 { 3698 struct bnxt *bp = dev->data->dev_private; 3699 uint8_t index, dir_op; 3700 uint16_t type, ext, ordinal, attr; 3701 int rc; 3702 3703 rc = is_bnxt_in_error(bp); 3704 if (rc) 3705 return rc; 3706 3707 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3708 bp->pdev->addr.domain, bp->pdev->addr.bus, 3709 bp->pdev->addr.devid, bp->pdev->addr.function, 3710 in_eeprom->offset, in_eeprom->length); 3711 3712 if (!BNXT_PF(bp)) { 3713 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3714 return -EINVAL; 3715 } 3716 3717 type = in_eeprom->magic >> 16; 3718 3719 if (type == 0xffff) { /* special value for directory operations */ 3720 index = in_eeprom->magic & 0xff; 3721 dir_op = in_eeprom->magic >> 8; 3722 if (index == 0) 3723 return -EINVAL; 3724 switch (dir_op) { 3725 case 0x0e: /* erase */ 3726 if (in_eeprom->offset != ~in_eeprom->magic) 3727 return -EINVAL; 3728 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3729 default: 3730 return -EINVAL; 3731 } 3732 } 3733 3734 /* Create or re-write an NVM item: */ 3735 if (bnxt_dir_type_is_executable(type) == true) 3736 return -EOPNOTSUPP; 3737 ext = in_eeprom->magic & 0xffff; 3738 ordinal = in_eeprom->offset >> 16; 3739 attr = in_eeprom->offset & 0xffff; 3740 3741 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3742 in_eeprom->data, in_eeprom->length); 3743 } 3744 3745 /* 3746 * Initialization 3747 */ 3748 3749 static const struct eth_dev_ops bnxt_dev_ops = { 3750 .dev_infos_get = bnxt_dev_info_get_op, 3751 .dev_close = bnxt_dev_close_op, 3752 .dev_configure = bnxt_dev_configure_op, 3753 .dev_start = bnxt_dev_start_op, 3754 .dev_stop = bnxt_dev_stop_op, 3755 .dev_set_link_up = bnxt_dev_set_link_up_op, 3756 .dev_set_link_down = bnxt_dev_set_link_down_op, 3757 .stats_get = bnxt_stats_get_op, 3758 .stats_reset = bnxt_stats_reset_op, 3759 .rx_queue_setup = bnxt_rx_queue_setup_op, 3760 .rx_queue_release = bnxt_rx_queue_release_op, 3761 .tx_queue_setup = bnxt_tx_queue_setup_op, 3762 .tx_queue_release = bnxt_tx_queue_release_op, 3763 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3764 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3765 .reta_update = bnxt_reta_update_op, 3766 .reta_query = bnxt_reta_query_op, 3767 .rss_hash_update = bnxt_rss_hash_update_op, 3768 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3769 .link_update = bnxt_link_update_op, 3770 .promiscuous_enable = bnxt_promiscuous_enable_op, 3771 .promiscuous_disable = bnxt_promiscuous_disable_op, 3772 .allmulticast_enable = bnxt_allmulticast_enable_op, 3773 .allmulticast_disable = bnxt_allmulticast_disable_op, 3774 .mac_addr_add = bnxt_mac_addr_add_op, 3775 .mac_addr_remove = bnxt_mac_addr_remove_op, 3776 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3777 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3778 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3779 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3780 .vlan_filter_set = bnxt_vlan_filter_set_op, 3781 .vlan_offload_set = bnxt_vlan_offload_set_op, 3782 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 3783 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3784 .mtu_set = bnxt_mtu_set_op, 3785 .mac_addr_set = bnxt_set_default_mac_addr_op, 3786 .xstats_get = bnxt_dev_xstats_get_op, 3787 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3788 .xstats_reset = bnxt_dev_xstats_reset_op, 3789 .fw_version_get = bnxt_fw_version_get, 3790 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3791 .rxq_info_get = bnxt_rxq_info_get_op, 3792 .txq_info_get = bnxt_txq_info_get_op, 3793 .rx_burst_mode_get = bnxt_rx_burst_mode_get, 3794 .tx_burst_mode_get = bnxt_tx_burst_mode_get, 3795 .dev_led_on = bnxt_dev_led_on_op, 3796 .dev_led_off = bnxt_dev_led_off_op, 3797 .rx_queue_start = bnxt_rx_queue_start, 3798 .rx_queue_stop = bnxt_rx_queue_stop, 3799 .tx_queue_start = bnxt_tx_queue_start, 3800 .tx_queue_stop = bnxt_tx_queue_stop, 3801 .flow_ops_get = bnxt_flow_ops_get_op, 3802 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3803 .get_eeprom_length = bnxt_get_eeprom_length_op, 3804 .get_eeprom = bnxt_get_eeprom_op, 3805 .set_eeprom = bnxt_set_eeprom_op, 3806 .timesync_enable = bnxt_timesync_enable, 3807 .timesync_disable = bnxt_timesync_disable, 3808 .timesync_read_time = bnxt_timesync_read_time, 3809 .timesync_write_time = bnxt_timesync_write_time, 3810 .timesync_adjust_time = bnxt_timesync_adjust_time, 3811 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3812 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3813 }; 3814 3815 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 3816 { 3817 uint32_t offset; 3818 3819 /* Only pre-map the reset GRC registers using window 3 */ 3820 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 3821 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 3822 3823 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 3824 3825 return offset; 3826 } 3827 3828 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 3829 { 3830 struct bnxt_error_recovery_info *info = bp->recovery_info; 3831 uint32_t reg_base = 0xffffffff; 3832 int i; 3833 3834 /* Only pre-map the monitoring GRC registers using window 2 */ 3835 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 3836 uint32_t reg = info->status_regs[i]; 3837 3838 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 3839 continue; 3840 3841 if (reg_base == 0xffffffff) 3842 reg_base = reg & 0xfffff000; 3843 if ((reg & 0xfffff000) != reg_base) 3844 return -ERANGE; 3845 3846 /* Use mask 0xffc as the Lower 2 bits indicates 3847 * address space location 3848 */ 3849 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 3850 (reg & 0xffc); 3851 } 3852 3853 if (reg_base == 0xffffffff) 3854 return 0; 3855 3856 rte_write32(reg_base, (uint8_t *)bp->bar0 + 3857 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 3858 3859 return 0; 3860 } 3861 3862 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 3863 { 3864 struct bnxt_error_recovery_info *info = bp->recovery_info; 3865 uint32_t delay = info->delay_after_reset[index]; 3866 uint32_t val = info->reset_reg_val[index]; 3867 uint32_t reg = info->reset_reg[index]; 3868 uint32_t type, offset; 3869 int ret; 3870 3871 type = BNXT_FW_STATUS_REG_TYPE(reg); 3872 offset = BNXT_FW_STATUS_REG_OFF(reg); 3873 3874 switch (type) { 3875 case BNXT_FW_STATUS_REG_TYPE_CFG: 3876 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 3877 if (ret < 0) { 3878 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x", 3879 val, offset); 3880 return; 3881 } 3882 break; 3883 case BNXT_FW_STATUS_REG_TYPE_GRC: 3884 offset = bnxt_map_reset_regs(bp, offset); 3885 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3886 break; 3887 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3888 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3889 break; 3890 } 3891 /* wait on a specific interval of time until core reset is complete */ 3892 if (delay) 3893 rte_delay_ms(delay); 3894 } 3895 3896 static void bnxt_dev_cleanup(struct bnxt *bp) 3897 { 3898 bp->eth_dev->data->dev_link.link_status = 0; 3899 bp->link_info->link_up = 0; 3900 if (bp->eth_dev->data->dev_started) 3901 bnxt_dev_stop(bp->eth_dev); 3902 3903 bnxt_uninit_resources(bp, true); 3904 } 3905 3906 static int 3907 bnxt_check_fw_reset_done(struct bnxt *bp) 3908 { 3909 int timeout = bp->fw_reset_max_msecs; 3910 uint16_t val = 0; 3911 int rc; 3912 3913 do { 3914 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 3915 if (rc < 0) { 3916 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 3917 return rc; 3918 } 3919 if (val != 0xffff) 3920 break; 3921 rte_delay_ms(1); 3922 } while (timeout--); 3923 3924 if (val == 0xffff) { 3925 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); 3926 return -1; 3927 } 3928 3929 return 0; 3930 } 3931 3932 static int bnxt_restore_vlan_filters(struct bnxt *bp) 3933 { 3934 struct rte_eth_dev *dev = bp->eth_dev; 3935 struct rte_vlan_filter_conf *vfc; 3936 int vidx, vbit, rc; 3937 uint16_t vlan_id; 3938 3939 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 3940 vfc = &dev->data->vlan_filter_conf; 3941 vidx = vlan_id / 64; 3942 vbit = vlan_id % 64; 3943 3944 /* Each bit corresponds to a VLAN id */ 3945 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 3946 rc = bnxt_add_vlan_filter(bp, vlan_id); 3947 if (rc) 3948 return rc; 3949 } 3950 } 3951 3952 return 0; 3953 } 3954 3955 static int bnxt_restore_mac_filters(struct bnxt *bp) 3956 { 3957 struct rte_eth_dev *dev = bp->eth_dev; 3958 struct rte_eth_dev_info dev_info; 3959 struct rte_ether_addr *addr; 3960 uint64_t pool_mask; 3961 uint32_t pool = 0; 3962 uint16_t i; 3963 int rc; 3964 3965 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 3966 return 0; 3967 3968 rc = bnxt_dev_info_get_op(dev, &dev_info); 3969 if (rc) 3970 return rc; 3971 3972 /* replay MAC address configuration */ 3973 for (i = 1; i < dev_info.max_mac_addrs; i++) { 3974 addr = &dev->data->mac_addrs[i]; 3975 3976 /* skip zero address */ 3977 if (rte_is_zero_ether_addr(addr)) 3978 continue; 3979 3980 pool = 0; 3981 pool_mask = dev->data->mac_pool_sel[i]; 3982 3983 do { 3984 if (pool_mask & 1ULL) { 3985 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 3986 if (rc) 3987 return rc; 3988 } 3989 pool_mask >>= 1; 3990 pool++; 3991 } while (pool_mask); 3992 } 3993 3994 return 0; 3995 } 3996 3997 static int bnxt_restore_filters(struct bnxt *bp) 3998 { 3999 struct rte_eth_dev *dev = bp->eth_dev; 4000 int ret = 0; 4001 4002 if (dev->data->all_multicast) { 4003 ret = bnxt_allmulticast_enable_op(dev); 4004 if (ret) 4005 return ret; 4006 } 4007 if (dev->data->promiscuous) { 4008 ret = bnxt_promiscuous_enable_op(dev); 4009 if (ret) 4010 return ret; 4011 } 4012 4013 ret = bnxt_restore_mac_filters(bp); 4014 if (ret) 4015 return ret; 4016 4017 ret = bnxt_restore_vlan_filters(bp); 4018 /* TODO restore other filters as well */ 4019 return ret; 4020 } 4021 4022 static int bnxt_check_fw_ready(struct bnxt *bp) 4023 { 4024 int timeout = bp->fw_reset_max_msecs; 4025 int rc = 0; 4026 4027 do { 4028 rc = bnxt_hwrm_poll_ver_get(bp); 4029 if (rc == 0) 4030 break; 4031 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 4032 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 4033 } while (rc && timeout > 0); 4034 4035 if (rc) 4036 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 4037 4038 return rc; 4039 } 4040 4041 static void bnxt_dev_recover(void *arg) 4042 { 4043 struct bnxt *bp = arg; 4044 int rc = 0; 4045 4046 pthread_mutex_lock(&bp->err_recovery_lock); 4047 4048 if (!bp->fw_reset_min_msecs) { 4049 rc = bnxt_check_fw_reset_done(bp); 4050 if (rc) 4051 goto err; 4052 } 4053 4054 /* Clear Error flag so that device re-init should happen */ 4055 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 4056 4057 rc = bnxt_check_fw_ready(bp); 4058 if (rc) 4059 goto err; 4060 4061 rc = bnxt_init_resources(bp, true); 4062 if (rc) { 4063 PMD_DRV_LOG(ERR, 4064 "Failed to initialize resources after reset\n"); 4065 goto err; 4066 } 4067 /* clear reset flag as the device is initialized now */ 4068 bp->flags &= ~BNXT_FLAG_FW_RESET; 4069 4070 rc = bnxt_dev_start_op(bp->eth_dev); 4071 if (rc) { 4072 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 4073 goto err_start; 4074 } 4075 4076 rc = bnxt_restore_filters(bp); 4077 if (rc) 4078 goto err_start; 4079 4080 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 4081 pthread_mutex_unlock(&bp->err_recovery_lock); 4082 4083 return; 4084 err_start: 4085 bnxt_dev_stop(bp->eth_dev); 4086 err: 4087 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4088 bnxt_uninit_resources(bp, false); 4089 pthread_mutex_unlock(&bp->err_recovery_lock); 4090 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 4091 } 4092 4093 void bnxt_dev_reset_and_resume(void *arg) 4094 { 4095 struct bnxt *bp = arg; 4096 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; 4097 uint16_t val = 0; 4098 int rc; 4099 4100 bnxt_dev_cleanup(bp); 4101 4102 bnxt_wait_for_device_shutdown(bp); 4103 4104 /* During some fatal firmware error conditions, the PCI config space 4105 * register 0x2e which normally contains the subsystem ID will become 4106 * 0xffff. This register will revert back to the normal value after 4107 * the chip has completed core reset. If we detect this condition, 4108 * we can poll this config register immediately for the value to revert. 4109 */ 4110 if (bp->flags & BNXT_FLAG_FATAL_ERROR) { 4111 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 4112 if (rc < 0) { 4113 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 4114 return; 4115 } 4116 if (val == 0xffff) { 4117 bp->fw_reset_min_msecs = 0; 4118 us = 1; 4119 } 4120 } 4121 4122 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); 4123 if (rc) 4124 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 4125 } 4126 4127 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 4128 { 4129 struct bnxt_error_recovery_info *info = bp->recovery_info; 4130 uint32_t reg = info->status_regs[index]; 4131 uint32_t type, offset, val = 0; 4132 4133 type = BNXT_FW_STATUS_REG_TYPE(reg); 4134 offset = BNXT_FW_STATUS_REG_OFF(reg); 4135 4136 switch (type) { 4137 case BNXT_FW_STATUS_REG_TYPE_CFG: 4138 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 4139 break; 4140 case BNXT_FW_STATUS_REG_TYPE_GRC: 4141 offset = info->mapped_status_regs[index]; 4142 /* FALLTHROUGH */ 4143 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4144 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4145 offset)); 4146 break; 4147 } 4148 4149 return val; 4150 } 4151 4152 static int bnxt_fw_reset_all(struct bnxt *bp) 4153 { 4154 struct bnxt_error_recovery_info *info = bp->recovery_info; 4155 uint32_t i; 4156 int rc = 0; 4157 4158 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4159 /* Reset through master function driver */ 4160 for (i = 0; i < info->reg_array_cnt; i++) 4161 bnxt_write_fw_reset_reg(bp, i); 4162 /* Wait for time specified by FW after triggering reset */ 4163 rte_delay_ms(info->master_func_wait_period_after_reset); 4164 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 4165 /* Reset with the help of Kong processor */ 4166 rc = bnxt_hwrm_fw_reset(bp); 4167 if (rc) 4168 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 4169 } 4170 4171 return rc; 4172 } 4173 4174 static void bnxt_fw_reset_cb(void *arg) 4175 { 4176 struct bnxt *bp = arg; 4177 struct bnxt_error_recovery_info *info = bp->recovery_info; 4178 int rc = 0; 4179 4180 /* Only Master function can do FW reset */ 4181 if (bnxt_is_master_func(bp) && 4182 bnxt_is_recovery_enabled(bp)) { 4183 rc = bnxt_fw_reset_all(bp); 4184 if (rc) { 4185 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 4186 return; 4187 } 4188 } 4189 4190 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 4191 * EXCEPTION_FATAL_ASYNC event to all the functions 4192 * (including MASTER FUNC). After receiving this Async, all the active 4193 * drivers should treat this case as FW initiated recovery 4194 */ 4195 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4196 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 4197 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 4198 4199 /* To recover from error */ 4200 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 4201 (void *)bp); 4202 } 4203 } 4204 4205 /* Driver should poll FW heartbeat, reset_counter with the frequency 4206 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 4207 * When the driver detects heartbeat stop or change in reset_counter, 4208 * it has to trigger a reset to recover from the error condition. 4209 * A “master PF” is the function who will have the privilege to 4210 * initiate the chimp reset. The master PF will be elected by the 4211 * firmware and will be notified through async message. 4212 */ 4213 static void bnxt_check_fw_health(void *arg) 4214 { 4215 struct bnxt *bp = arg; 4216 struct bnxt_error_recovery_info *info = bp->recovery_info; 4217 uint32_t val = 0, wait_msec; 4218 4219 if (!info || !bnxt_is_recovery_enabled(bp) || 4220 is_bnxt_in_error(bp)) 4221 return; 4222 4223 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4224 if (val == info->last_heart_beat) 4225 goto reset; 4226 4227 info->last_heart_beat = val; 4228 4229 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4230 if (val != info->last_reset_counter) 4231 goto reset; 4232 4233 info->last_reset_counter = val; 4234 4235 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4236 bnxt_check_fw_health, (void *)bp); 4237 4238 return; 4239 reset: 4240 /* Stop DMA to/from device */ 4241 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4242 bp->flags |= BNXT_FLAG_FW_RESET; 4243 4244 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4245 4246 if (bnxt_is_master_func(bp)) 4247 wait_msec = info->master_func_wait_period; 4248 else 4249 wait_msec = info->normal_func_wait_period; 4250 4251 rte_eal_alarm_set(US_PER_MS * wait_msec, 4252 bnxt_fw_reset_cb, (void *)bp); 4253 } 4254 4255 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4256 { 4257 uint32_t polling_freq; 4258 4259 pthread_mutex_lock(&bp->health_check_lock); 4260 4261 if (!bnxt_is_recovery_enabled(bp)) 4262 goto done; 4263 4264 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4265 goto done; 4266 4267 polling_freq = bp->recovery_info->driver_polling_freq; 4268 4269 rte_eal_alarm_set(US_PER_MS * polling_freq, 4270 bnxt_check_fw_health, (void *)bp); 4271 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4272 4273 done: 4274 pthread_mutex_unlock(&bp->health_check_lock); 4275 } 4276 4277 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4278 { 4279 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4280 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4281 } 4282 4283 static bool bnxt_vf_pciid(uint16_t device_id) 4284 { 4285 switch (device_id) { 4286 case BROADCOM_DEV_ID_57304_VF: 4287 case BROADCOM_DEV_ID_57406_VF: 4288 case BROADCOM_DEV_ID_5731X_VF: 4289 case BROADCOM_DEV_ID_5741X_VF: 4290 case BROADCOM_DEV_ID_57414_VF: 4291 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4292 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4293 case BROADCOM_DEV_ID_58802_VF: 4294 case BROADCOM_DEV_ID_57500_VF1: 4295 case BROADCOM_DEV_ID_57500_VF2: 4296 case BROADCOM_DEV_ID_58818_VF: 4297 /* FALLTHROUGH */ 4298 return true; 4299 default: 4300 return false; 4301 } 4302 } 4303 4304 /* Phase 5 device */ 4305 static bool bnxt_p5_device(uint16_t device_id) 4306 { 4307 switch (device_id) { 4308 case BROADCOM_DEV_ID_57508: 4309 case BROADCOM_DEV_ID_57504: 4310 case BROADCOM_DEV_ID_57502: 4311 case BROADCOM_DEV_ID_57508_MF1: 4312 case BROADCOM_DEV_ID_57504_MF1: 4313 case BROADCOM_DEV_ID_57502_MF1: 4314 case BROADCOM_DEV_ID_57508_MF2: 4315 case BROADCOM_DEV_ID_57504_MF2: 4316 case BROADCOM_DEV_ID_57502_MF2: 4317 case BROADCOM_DEV_ID_57500_VF1: 4318 case BROADCOM_DEV_ID_57500_VF2: 4319 case BROADCOM_DEV_ID_58812: 4320 case BROADCOM_DEV_ID_58814: 4321 case BROADCOM_DEV_ID_58818: 4322 case BROADCOM_DEV_ID_58818_VF: 4323 /* FALLTHROUGH */ 4324 return true; 4325 default: 4326 return false; 4327 } 4328 } 4329 4330 bool bnxt_stratus_device(struct bnxt *bp) 4331 { 4332 uint16_t device_id = bp->pdev->id.device_id; 4333 4334 switch (device_id) { 4335 case BROADCOM_DEV_ID_STRATUS_NIC: 4336 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4337 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4338 /* FALLTHROUGH */ 4339 return true; 4340 default: 4341 return false; 4342 } 4343 } 4344 4345 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev) 4346 { 4347 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4348 struct bnxt *bp = eth_dev->data->dev_private; 4349 4350 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4351 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4352 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4353 if (!bp->bar0 || !bp->doorbell_base) { 4354 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4355 return -ENODEV; 4356 } 4357 4358 bp->eth_dev = eth_dev; 4359 bp->pdev = pci_dev; 4360 4361 return 0; 4362 } 4363 4364 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4365 struct bnxt_ctx_pg_info *ctx_pg, 4366 uint32_t mem_size, 4367 const char *suffix, 4368 uint16_t idx) 4369 { 4370 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4371 const struct rte_memzone *mz = NULL; 4372 char mz_name[RTE_MEMZONE_NAMESIZE]; 4373 rte_iova_t mz_phys_addr; 4374 uint64_t valid_bits = 0; 4375 uint32_t sz; 4376 int i; 4377 4378 if (!mem_size) 4379 return 0; 4380 4381 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4382 BNXT_PAGE_SIZE; 4383 rmem->page_size = BNXT_PAGE_SIZE; 4384 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4385 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4386 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4387 4388 valid_bits = PTU_PTE_VALID; 4389 4390 if (rmem->nr_pages > 1) { 4391 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4392 "bnxt_ctx_pg_tbl%s_%x_%d", 4393 suffix, idx, bp->eth_dev->data->port_id); 4394 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4395 mz = rte_memzone_lookup(mz_name); 4396 if (!mz) { 4397 mz = rte_memzone_reserve_aligned(mz_name, 4398 rmem->nr_pages * 8, 4399 SOCKET_ID_ANY, 4400 RTE_MEMZONE_2MB | 4401 RTE_MEMZONE_SIZE_HINT_ONLY | 4402 RTE_MEMZONE_IOVA_CONTIG, 4403 BNXT_PAGE_SIZE); 4404 if (mz == NULL) 4405 return -ENOMEM; 4406 } 4407 4408 memset(mz->addr, 0, mz->len); 4409 mz_phys_addr = mz->iova; 4410 4411 rmem->pg_tbl = mz->addr; 4412 rmem->pg_tbl_map = mz_phys_addr; 4413 rmem->pg_tbl_mz = mz; 4414 } 4415 4416 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4417 suffix, idx, bp->eth_dev->data->port_id); 4418 mz = rte_memzone_lookup(mz_name); 4419 if (!mz) { 4420 mz = rte_memzone_reserve_aligned(mz_name, 4421 mem_size, 4422 SOCKET_ID_ANY, 4423 RTE_MEMZONE_1GB | 4424 RTE_MEMZONE_SIZE_HINT_ONLY | 4425 RTE_MEMZONE_IOVA_CONTIG, 4426 BNXT_PAGE_SIZE); 4427 if (mz == NULL) 4428 return -ENOMEM; 4429 } 4430 4431 memset(mz->addr, 0, mz->len); 4432 mz_phys_addr = mz->iova; 4433 4434 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4435 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4436 rmem->dma_arr[i] = mz_phys_addr + sz; 4437 4438 if (rmem->nr_pages > 1) { 4439 if (i == rmem->nr_pages - 2 && 4440 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4441 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4442 else if (i == rmem->nr_pages - 1 && 4443 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4444 valid_bits |= PTU_PTE_LAST; 4445 4446 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4447 valid_bits); 4448 } 4449 } 4450 4451 rmem->mz = mz; 4452 if (rmem->vmem_size) 4453 rmem->vmem = (void **)mz->addr; 4454 rmem->dma_arr[0] = mz_phys_addr; 4455 return 0; 4456 } 4457 4458 static void bnxt_free_ctx_mem(struct bnxt *bp) 4459 { 4460 int i; 4461 4462 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4463 return; 4464 4465 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4466 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4467 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4468 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4469 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4470 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4471 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4472 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4473 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4474 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4475 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4476 4477 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) { 4478 if (bp->ctx->tqm_mem[i]) 4479 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4480 } 4481 4482 rte_free(bp->ctx); 4483 bp->ctx = NULL; 4484 } 4485 4486 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4487 4488 #define min_t(type, x, y) ({ \ 4489 type __min1 = (x); \ 4490 type __min2 = (y); \ 4491 __min1 < __min2 ? __min1 : __min2; }) 4492 4493 #define max_t(type, x, y) ({ \ 4494 type __max1 = (x); \ 4495 type __max2 = (y); \ 4496 __max1 > __max2 ? __max1 : __max2; }) 4497 4498 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4499 4500 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4501 { 4502 struct bnxt_ctx_pg_info *ctx_pg; 4503 struct bnxt_ctx_mem_info *ctx; 4504 uint32_t mem_size, ena, entries; 4505 uint32_t entries_sp, min; 4506 int i, rc; 4507 4508 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4509 if (rc) { 4510 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4511 return rc; 4512 } 4513 ctx = bp->ctx; 4514 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4515 return 0; 4516 4517 ctx_pg = &ctx->qp_mem; 4518 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4519 if (ctx->qp_entry_size) { 4520 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4521 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4522 if (rc) 4523 return rc; 4524 } 4525 4526 ctx_pg = &ctx->srq_mem; 4527 ctx_pg->entries = ctx->srq_max_l2_entries; 4528 if (ctx->srq_entry_size) { 4529 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4530 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4531 if (rc) 4532 return rc; 4533 } 4534 4535 ctx_pg = &ctx->cq_mem; 4536 ctx_pg->entries = ctx->cq_max_l2_entries; 4537 if (ctx->cq_entry_size) { 4538 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4539 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4540 if (rc) 4541 return rc; 4542 } 4543 4544 ctx_pg = &ctx->vnic_mem; 4545 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4546 ctx->vnic_max_ring_table_entries; 4547 if (ctx->vnic_entry_size) { 4548 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4549 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4550 if (rc) 4551 return rc; 4552 } 4553 4554 ctx_pg = &ctx->stat_mem; 4555 ctx_pg->entries = ctx->stat_max_entries; 4556 if (ctx->stat_entry_size) { 4557 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4558 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4559 if (rc) 4560 return rc; 4561 } 4562 4563 min = ctx->tqm_min_entries_per_ring; 4564 4565 entries_sp = ctx->qp_max_l2_entries + 4566 ctx->vnic_max_vnic_entries + 4567 2 * ctx->qp_min_qp1_entries + min; 4568 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple); 4569 4570 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries; 4571 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4572 entries = clamp_t(uint32_t, entries, min, 4573 ctx->tqm_max_entries_per_ring); 4574 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 4575 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7. 4576 * i > 8 is other ext rings. 4577 */ 4578 ctx_pg = ctx->tqm_mem[i]; 4579 ctx_pg->entries = i ? entries : entries_sp; 4580 if (ctx->tqm_entry_size) { 4581 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4582 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, 4583 "tqm_mem", i); 4584 if (rc) 4585 return rc; 4586 } 4587 if (i < BNXT_MAX_TQM_LEGACY_RINGS) 4588 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4589 else 4590 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8; 4591 } 4592 4593 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4594 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4595 if (rc) 4596 PMD_DRV_LOG(ERR, 4597 "Failed to configure context mem: rc = %d\n", rc); 4598 else 4599 ctx->flags |= BNXT_CTX_FLAG_INITED; 4600 4601 return rc; 4602 } 4603 4604 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4605 { 4606 struct rte_pci_device *pci_dev = bp->pdev; 4607 char mz_name[RTE_MEMZONE_NAMESIZE]; 4608 const struct rte_memzone *mz = NULL; 4609 uint32_t total_alloc_len; 4610 rte_iova_t mz_phys_addr; 4611 4612 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4613 return 0; 4614 4615 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4616 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4617 pci_dev->addr.bus, pci_dev->addr.devid, 4618 pci_dev->addr.function, "rx_port_stats"); 4619 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4620 mz = rte_memzone_lookup(mz_name); 4621 total_alloc_len = 4622 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4623 sizeof(struct rx_port_stats_ext) + 512); 4624 if (!mz) { 4625 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4626 SOCKET_ID_ANY, 4627 RTE_MEMZONE_2MB | 4628 RTE_MEMZONE_SIZE_HINT_ONLY | 4629 RTE_MEMZONE_IOVA_CONTIG); 4630 if (mz == NULL) 4631 return -ENOMEM; 4632 } 4633 memset(mz->addr, 0, mz->len); 4634 mz_phys_addr = mz->iova; 4635 4636 bp->rx_mem_zone = (const void *)mz; 4637 bp->hw_rx_port_stats = mz->addr; 4638 bp->hw_rx_port_stats_map = mz_phys_addr; 4639 4640 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4641 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4642 pci_dev->addr.bus, pci_dev->addr.devid, 4643 pci_dev->addr.function, "tx_port_stats"); 4644 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4645 mz = rte_memzone_lookup(mz_name); 4646 total_alloc_len = 4647 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4648 sizeof(struct tx_port_stats_ext) + 512); 4649 if (!mz) { 4650 mz = rte_memzone_reserve(mz_name, 4651 total_alloc_len, 4652 SOCKET_ID_ANY, 4653 RTE_MEMZONE_2MB | 4654 RTE_MEMZONE_SIZE_HINT_ONLY | 4655 RTE_MEMZONE_IOVA_CONTIG); 4656 if (mz == NULL) 4657 return -ENOMEM; 4658 } 4659 memset(mz->addr, 0, mz->len); 4660 mz_phys_addr = mz->iova; 4661 4662 bp->tx_mem_zone = (const void *)mz; 4663 bp->hw_tx_port_stats = mz->addr; 4664 bp->hw_tx_port_stats_map = mz_phys_addr; 4665 bp->flags |= BNXT_FLAG_PORT_STATS; 4666 4667 /* Display extended statistics if FW supports it */ 4668 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4669 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4670 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4671 return 0; 4672 4673 bp->hw_rx_port_stats_ext = (void *) 4674 ((uint8_t *)bp->hw_rx_port_stats + 4675 sizeof(struct rx_port_stats)); 4676 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4677 sizeof(struct rx_port_stats); 4678 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4679 4680 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4681 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4682 bp->hw_tx_port_stats_ext = (void *) 4683 ((uint8_t *)bp->hw_tx_port_stats + 4684 sizeof(struct tx_port_stats)); 4685 bp->hw_tx_port_stats_ext_map = 4686 bp->hw_tx_port_stats_map + 4687 sizeof(struct tx_port_stats); 4688 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4689 } 4690 4691 return 0; 4692 } 4693 4694 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4695 { 4696 struct bnxt *bp = eth_dev->data->dev_private; 4697 int rc = 0; 4698 4699 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4700 RTE_ETHER_ADDR_LEN * 4701 bp->max_l2_ctx, 4702 0); 4703 if (eth_dev->data->mac_addrs == NULL) { 4704 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4705 return -ENOMEM; 4706 } 4707 4708 if (!BNXT_HAS_DFLT_MAC_SET(bp)) { 4709 if (BNXT_PF(bp)) 4710 return -EINVAL; 4711 4712 /* Generate a random MAC address, if none was assigned by PF */ 4713 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 4714 bnxt_eth_hw_addr_random(bp->mac_addr); 4715 PMD_DRV_LOG(INFO, 4716 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 4717 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 4718 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 4719 4720 rc = bnxt_hwrm_set_mac(bp); 4721 if (rc) 4722 return rc; 4723 } 4724 4725 /* Copy the permanent MAC from the FUNC_QCAPS response */ 4726 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 4727 4728 return rc; 4729 } 4730 4731 static int bnxt_restore_dflt_mac(struct bnxt *bp) 4732 { 4733 int rc = 0; 4734 4735 /* MAC is already configured in FW */ 4736 if (BNXT_HAS_DFLT_MAC_SET(bp)) 4737 return 0; 4738 4739 /* Restore the old MAC configured */ 4740 rc = bnxt_hwrm_set_mac(bp); 4741 if (rc) 4742 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 4743 4744 return rc; 4745 } 4746 4747 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 4748 { 4749 if (!BNXT_PF(bp)) 4750 return; 4751 4752 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd)); 4753 4754 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN)) 4755 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG); 4756 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG); 4757 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG); 4758 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC); 4759 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); 4760 } 4761 4762 uint16_t 4763 bnxt_get_svif(uint16_t port_id, bool func_svif, 4764 enum bnxt_ulp_intf_type type) 4765 { 4766 struct rte_eth_dev *eth_dev; 4767 struct bnxt *bp; 4768 4769 eth_dev = &rte_eth_devices[port_id]; 4770 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4771 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4772 if (!vfr) 4773 return 0; 4774 4775 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4776 return vfr->svif; 4777 4778 eth_dev = vfr->parent_dev; 4779 } 4780 4781 bp = eth_dev->data->dev_private; 4782 4783 return func_svif ? bp->func_svif : bp->port_svif; 4784 } 4785 4786 uint16_t 4787 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 4788 { 4789 struct rte_eth_dev *eth_dev; 4790 struct bnxt_vnic_info *vnic; 4791 struct bnxt *bp; 4792 4793 eth_dev = &rte_eth_devices[port]; 4794 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4795 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4796 if (!vfr) 4797 return 0; 4798 4799 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4800 return vfr->dflt_vnic_id; 4801 4802 eth_dev = vfr->parent_dev; 4803 } 4804 4805 bp = eth_dev->data->dev_private; 4806 4807 vnic = BNXT_GET_DEFAULT_VNIC(bp); 4808 4809 return vnic->fw_vnic_id; 4810 } 4811 4812 uint16_t 4813 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) 4814 { 4815 struct rte_eth_dev *eth_dev; 4816 struct bnxt *bp; 4817 4818 eth_dev = &rte_eth_devices[port]; 4819 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4820 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4821 if (!vfr) 4822 return 0; 4823 4824 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4825 return vfr->fw_fid; 4826 4827 eth_dev = vfr->parent_dev; 4828 } 4829 4830 bp = eth_dev->data->dev_private; 4831 4832 return bp->fw_fid; 4833 } 4834 4835 enum bnxt_ulp_intf_type 4836 bnxt_get_interface_type(uint16_t port) 4837 { 4838 struct rte_eth_dev *eth_dev; 4839 struct bnxt *bp; 4840 4841 eth_dev = &rte_eth_devices[port]; 4842 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) 4843 return BNXT_ULP_INTF_TYPE_VF_REP; 4844 4845 bp = eth_dev->data->dev_private; 4846 if (BNXT_PF(bp)) 4847 return BNXT_ULP_INTF_TYPE_PF; 4848 else if (BNXT_VF_IS_TRUSTED(bp)) 4849 return BNXT_ULP_INTF_TYPE_TRUSTED_VF; 4850 else if (BNXT_VF(bp)) 4851 return BNXT_ULP_INTF_TYPE_VF; 4852 4853 return BNXT_ULP_INTF_TYPE_INVALID; 4854 } 4855 4856 uint16_t 4857 bnxt_get_phy_port_id(uint16_t port_id) 4858 { 4859 struct bnxt_representor *vfr; 4860 struct rte_eth_dev *eth_dev; 4861 struct bnxt *bp; 4862 4863 eth_dev = &rte_eth_devices[port_id]; 4864 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4865 vfr = eth_dev->data->dev_private; 4866 if (!vfr) 4867 return 0; 4868 4869 eth_dev = vfr->parent_dev; 4870 } 4871 4872 bp = eth_dev->data->dev_private; 4873 4874 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; 4875 } 4876 4877 uint16_t 4878 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) 4879 { 4880 struct rte_eth_dev *eth_dev; 4881 struct bnxt *bp; 4882 4883 eth_dev = &rte_eth_devices[port_id]; 4884 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4885 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4886 if (!vfr) 4887 return 0; 4888 4889 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4890 return vfr->fw_fid - 1; 4891 4892 eth_dev = vfr->parent_dev; 4893 } 4894 4895 bp = eth_dev->data->dev_private; 4896 4897 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; 4898 } 4899 4900 uint16_t 4901 bnxt_get_vport(uint16_t port_id) 4902 { 4903 return (1 << bnxt_get_phy_port_id(port_id)); 4904 } 4905 4906 static void bnxt_alloc_error_recovery_info(struct bnxt *bp) 4907 { 4908 struct bnxt_error_recovery_info *info = bp->recovery_info; 4909 4910 if (info) { 4911 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)) 4912 memset(info, 0, sizeof(*info)); 4913 return; 4914 } 4915 4916 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 4917 return; 4918 4919 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 4920 sizeof(*info), 0); 4921 if (!info) 4922 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 4923 4924 bp->recovery_info = info; 4925 } 4926 4927 static void bnxt_check_fw_status(struct bnxt *bp) 4928 { 4929 uint32_t fw_status; 4930 4931 if (!(bp->recovery_info && 4932 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))) 4933 return; 4934 4935 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG); 4936 if (fw_status != BNXT_FW_STATUS_HEALTHY) 4937 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n", 4938 fw_status); 4939 } 4940 4941 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) 4942 { 4943 struct bnxt_error_recovery_info *info = bp->recovery_info; 4944 uint32_t status_loc; 4945 uint32_t sig_ver; 4946 4947 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 + 4948 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4949 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4950 BNXT_GRCP_WINDOW_2_BASE + 4951 offsetof(struct hcomm_status, 4952 sig_ver))); 4953 /* If the signature is absent, then FW does not support this feature */ 4954 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) != 4955 HCOMM_STATUS_SIGNATURE_VAL) 4956 return 0; 4957 4958 if (!info) { 4959 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 4960 sizeof(*info), 0); 4961 if (!info) 4962 return -ENOMEM; 4963 bp->recovery_info = info; 4964 } else { 4965 memset(info, 0, sizeof(*info)); 4966 } 4967 4968 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4969 BNXT_GRCP_WINDOW_2_BASE + 4970 offsetof(struct hcomm_status, 4971 fw_status_loc))); 4972 4973 /* Only pre-map the FW health status GRC register */ 4974 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC) 4975 return 0; 4976 4977 info->status_regs[BNXT_FW_STATUS_REG] = status_loc; 4978 info->mapped_status_regs[BNXT_FW_STATUS_REG] = 4979 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK); 4980 4981 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 + 4982 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4983 4984 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS; 4985 4986 return 0; 4987 } 4988 4989 /* This function gets the FW version along with the 4990 * capabilities(MAX and current) of the function, vnic, 4991 * error recovery, phy and other chip related info 4992 */ 4993 static int bnxt_get_config(struct bnxt *bp) 4994 { 4995 uint16_t mtu; 4996 int rc = 0; 4997 4998 bp->fw_cap = 0; 4999 5000 rc = bnxt_map_hcomm_fw_status_reg(bp); 5001 if (rc) 5002 return rc; 5003 5004 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT); 5005 if (rc) { 5006 bnxt_check_fw_status(bp); 5007 return rc; 5008 } 5009 5010 rc = bnxt_hwrm_func_reset(bp); 5011 if (rc) 5012 return -EIO; 5013 5014 rc = bnxt_hwrm_vnic_qcaps(bp); 5015 if (rc) 5016 return rc; 5017 5018 rc = bnxt_hwrm_queue_qportcfg(bp); 5019 if (rc) 5020 return rc; 5021 5022 /* Get the MAX capabilities for this function. 5023 * This function also allocates context memory for TQM rings and 5024 * informs the firmware about this allocated backing store memory. 5025 */ 5026 rc = bnxt_hwrm_func_qcaps(bp); 5027 if (rc) 5028 return rc; 5029 5030 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 5031 if (rc) 5032 return rc; 5033 5034 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 5035 if (rc) 5036 return rc; 5037 5038 bnxt_hwrm_port_mac_qcfg(bp); 5039 5040 bnxt_hwrm_parent_pf_qcfg(bp); 5041 5042 bnxt_hwrm_port_phy_qcaps(bp); 5043 5044 bnxt_alloc_error_recovery_info(bp); 5045 /* Get the adapter error recovery support info */ 5046 rc = bnxt_hwrm_error_recovery_qcfg(bp); 5047 if (rc) 5048 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5049 5050 bnxt_hwrm_port_led_qcaps(bp); 5051 5052 return 0; 5053 } 5054 5055 static int 5056 bnxt_init_locks(struct bnxt *bp) 5057 { 5058 int err; 5059 5060 err = pthread_mutex_init(&bp->flow_lock, NULL); 5061 if (err) { 5062 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 5063 return err; 5064 } 5065 5066 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 5067 if (err) { 5068 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 5069 return err; 5070 } 5071 5072 err = pthread_mutex_init(&bp->health_check_lock, NULL); 5073 if (err) { 5074 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n"); 5075 return err; 5076 } 5077 5078 err = pthread_mutex_init(&bp->err_recovery_lock, NULL); 5079 if (err) 5080 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n"); 5081 5082 return err; 5083 } 5084 5085 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 5086 { 5087 int rc = 0; 5088 5089 rc = bnxt_get_config(bp); 5090 if (rc) 5091 return rc; 5092 5093 if (!reconfig_dev) { 5094 rc = bnxt_setup_mac_addr(bp->eth_dev); 5095 if (rc) 5096 return rc; 5097 } else { 5098 rc = bnxt_restore_dflt_mac(bp); 5099 if (rc) 5100 return rc; 5101 } 5102 5103 bnxt_config_vf_req_fwd(bp); 5104 5105 rc = bnxt_hwrm_func_driver_register(bp); 5106 if (rc) { 5107 PMD_DRV_LOG(ERR, "Failed to register driver"); 5108 return -EBUSY; 5109 } 5110 5111 if (BNXT_PF(bp)) { 5112 if (bp->pdev->max_vfs) { 5113 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 5114 if (rc) { 5115 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 5116 return rc; 5117 } 5118 } else { 5119 rc = bnxt_hwrm_allocate_pf_only(bp); 5120 if (rc) { 5121 PMD_DRV_LOG(ERR, 5122 "Failed to allocate PF resources"); 5123 return rc; 5124 } 5125 } 5126 } 5127 5128 rc = bnxt_alloc_mem(bp, reconfig_dev); 5129 if (rc) 5130 return rc; 5131 5132 rc = bnxt_setup_int(bp); 5133 if (rc) 5134 return rc; 5135 5136 rc = bnxt_request_int(bp); 5137 if (rc) 5138 return rc; 5139 5140 rc = bnxt_init_ctx_mem(bp); 5141 if (rc) { 5142 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n"); 5143 return rc; 5144 } 5145 5146 return 0; 5147 } 5148 5149 static int 5150 bnxt_parse_devarg_truflow(__rte_unused const char *key, 5151 const char *value, void *opaque_arg) 5152 { 5153 struct bnxt *bp = opaque_arg; 5154 unsigned long truflow; 5155 char *end = NULL; 5156 5157 if (!value || !opaque_arg) { 5158 PMD_DRV_LOG(ERR, 5159 "Invalid parameter passed to truflow devargs.\n"); 5160 return -EINVAL; 5161 } 5162 5163 truflow = strtoul(value, &end, 10); 5164 if (end == NULL || *end != '\0' || 5165 (truflow == ULONG_MAX && errno == ERANGE)) { 5166 PMD_DRV_LOG(ERR, 5167 "Invalid parameter passed to truflow devargs.\n"); 5168 return -EINVAL; 5169 } 5170 5171 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) { 5172 PMD_DRV_LOG(ERR, 5173 "Invalid value passed to truflow devargs.\n"); 5174 return -EINVAL; 5175 } 5176 5177 if (truflow) { 5178 bp->flags |= BNXT_FLAG_TRUFLOW_EN; 5179 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n"); 5180 } else { 5181 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN; 5182 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n"); 5183 } 5184 5185 return 0; 5186 } 5187 5188 static int 5189 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, 5190 const char *value, void *opaque_arg) 5191 { 5192 struct bnxt *bp = opaque_arg; 5193 unsigned long flow_xstat; 5194 char *end = NULL; 5195 5196 if (!value || !opaque_arg) { 5197 PMD_DRV_LOG(ERR, 5198 "Invalid parameter passed to flow_xstat devarg.\n"); 5199 return -EINVAL; 5200 } 5201 5202 flow_xstat = strtoul(value, &end, 10); 5203 if (end == NULL || *end != '\0' || 5204 (flow_xstat == ULONG_MAX && errno == ERANGE)) { 5205 PMD_DRV_LOG(ERR, 5206 "Invalid parameter passed to flow_xstat devarg.\n"); 5207 return -EINVAL; 5208 } 5209 5210 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) { 5211 PMD_DRV_LOG(ERR, 5212 "Invalid value passed to flow_xstat devarg.\n"); 5213 return -EINVAL; 5214 } 5215 5216 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN; 5217 if (BNXT_FLOW_XSTATS_EN(bp)) 5218 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n"); 5219 5220 return 0; 5221 } 5222 5223 static int 5224 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, 5225 const char *value, void *opaque_arg) 5226 { 5227 struct bnxt *bp = opaque_arg; 5228 unsigned long max_num_kflows; 5229 char *end = NULL; 5230 5231 if (!value || !opaque_arg) { 5232 PMD_DRV_LOG(ERR, 5233 "Invalid parameter passed to max_num_kflows devarg.\n"); 5234 return -EINVAL; 5235 } 5236 5237 max_num_kflows = strtoul(value, &end, 10); 5238 if (end == NULL || *end != '\0' || 5239 (max_num_kflows == ULONG_MAX && errno == ERANGE)) { 5240 PMD_DRV_LOG(ERR, 5241 "Invalid parameter passed to max_num_kflows devarg.\n"); 5242 return -EINVAL; 5243 } 5244 5245 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) { 5246 PMD_DRV_LOG(ERR, 5247 "Invalid value passed to max_num_kflows devarg.\n"); 5248 return -EINVAL; 5249 } 5250 5251 bp->max_num_kflows = max_num_kflows; 5252 if (bp->max_num_kflows) 5253 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n", 5254 max_num_kflows); 5255 5256 return 0; 5257 } 5258 5259 static int 5260 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key, 5261 const char *value, void *opaque_arg) 5262 { 5263 struct bnxt_representor *vfr_bp = opaque_arg; 5264 unsigned long rep_is_pf; 5265 char *end = NULL; 5266 5267 if (!value || !opaque_arg) { 5268 PMD_DRV_LOG(ERR, 5269 "Invalid parameter passed to rep_is_pf devargs.\n"); 5270 return -EINVAL; 5271 } 5272 5273 rep_is_pf = strtoul(value, &end, 10); 5274 if (end == NULL || *end != '\0' || 5275 (rep_is_pf == ULONG_MAX && errno == ERANGE)) { 5276 PMD_DRV_LOG(ERR, 5277 "Invalid parameter passed to rep_is_pf devargs.\n"); 5278 return -EINVAL; 5279 } 5280 5281 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) { 5282 PMD_DRV_LOG(ERR, 5283 "Invalid value passed to rep_is_pf devargs.\n"); 5284 return -EINVAL; 5285 } 5286 5287 vfr_bp->flags |= rep_is_pf; 5288 if (BNXT_REP_PF(vfr_bp)) 5289 PMD_DRV_LOG(INFO, "PF representor\n"); 5290 else 5291 PMD_DRV_LOG(INFO, "VF representor\n"); 5292 5293 return 0; 5294 } 5295 5296 static int 5297 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key, 5298 const char *value, void *opaque_arg) 5299 { 5300 struct bnxt_representor *vfr_bp = opaque_arg; 5301 unsigned long rep_based_pf; 5302 char *end = NULL; 5303 5304 if (!value || !opaque_arg) { 5305 PMD_DRV_LOG(ERR, 5306 "Invalid parameter passed to rep_based_pf " 5307 "devargs.\n"); 5308 return -EINVAL; 5309 } 5310 5311 rep_based_pf = strtoul(value, &end, 10); 5312 if (end == NULL || *end != '\0' || 5313 (rep_based_pf == ULONG_MAX && errno == ERANGE)) { 5314 PMD_DRV_LOG(ERR, 5315 "Invalid parameter passed to rep_based_pf " 5316 "devargs.\n"); 5317 return -EINVAL; 5318 } 5319 5320 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) { 5321 PMD_DRV_LOG(ERR, 5322 "Invalid value passed to rep_based_pf devargs.\n"); 5323 return -EINVAL; 5324 } 5325 5326 vfr_bp->rep_based_pf = rep_based_pf; 5327 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID; 5328 5329 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf); 5330 5331 return 0; 5332 } 5333 5334 static int 5335 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key, 5336 const char *value, void *opaque_arg) 5337 { 5338 struct bnxt_representor *vfr_bp = opaque_arg; 5339 unsigned long rep_q_r2f; 5340 char *end = NULL; 5341 5342 if (!value || !opaque_arg) { 5343 PMD_DRV_LOG(ERR, 5344 "Invalid parameter passed to rep_q_r2f " 5345 "devargs.\n"); 5346 return -EINVAL; 5347 } 5348 5349 rep_q_r2f = strtoul(value, &end, 10); 5350 if (end == NULL || *end != '\0' || 5351 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) { 5352 PMD_DRV_LOG(ERR, 5353 "Invalid parameter passed to rep_q_r2f " 5354 "devargs.\n"); 5355 return -EINVAL; 5356 } 5357 5358 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) { 5359 PMD_DRV_LOG(ERR, 5360 "Invalid value passed to rep_q_r2f devargs.\n"); 5361 return -EINVAL; 5362 } 5363 5364 vfr_bp->rep_q_r2f = rep_q_r2f; 5365 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID; 5366 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f); 5367 5368 return 0; 5369 } 5370 5371 static int 5372 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key, 5373 const char *value, void *opaque_arg) 5374 { 5375 struct bnxt_representor *vfr_bp = opaque_arg; 5376 unsigned long rep_q_f2r; 5377 char *end = NULL; 5378 5379 if (!value || !opaque_arg) { 5380 PMD_DRV_LOG(ERR, 5381 "Invalid parameter passed to rep_q_f2r " 5382 "devargs.\n"); 5383 return -EINVAL; 5384 } 5385 5386 rep_q_f2r = strtoul(value, &end, 10); 5387 if (end == NULL || *end != '\0' || 5388 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) { 5389 PMD_DRV_LOG(ERR, 5390 "Invalid parameter passed to rep_q_f2r " 5391 "devargs.\n"); 5392 return -EINVAL; 5393 } 5394 5395 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) { 5396 PMD_DRV_LOG(ERR, 5397 "Invalid value passed to rep_q_f2r devargs.\n"); 5398 return -EINVAL; 5399 } 5400 5401 vfr_bp->rep_q_f2r = rep_q_f2r; 5402 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID; 5403 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r); 5404 5405 return 0; 5406 } 5407 5408 static int 5409 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key, 5410 const char *value, void *opaque_arg) 5411 { 5412 struct bnxt_representor *vfr_bp = opaque_arg; 5413 unsigned long rep_fc_r2f; 5414 char *end = NULL; 5415 5416 if (!value || !opaque_arg) { 5417 PMD_DRV_LOG(ERR, 5418 "Invalid parameter passed to rep_fc_r2f " 5419 "devargs.\n"); 5420 return -EINVAL; 5421 } 5422 5423 rep_fc_r2f = strtoul(value, &end, 10); 5424 if (end == NULL || *end != '\0' || 5425 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) { 5426 PMD_DRV_LOG(ERR, 5427 "Invalid parameter passed to rep_fc_r2f " 5428 "devargs.\n"); 5429 return -EINVAL; 5430 } 5431 5432 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) { 5433 PMD_DRV_LOG(ERR, 5434 "Invalid value passed to rep_fc_r2f devargs.\n"); 5435 return -EINVAL; 5436 } 5437 5438 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID; 5439 vfr_bp->rep_fc_r2f = rep_fc_r2f; 5440 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f); 5441 5442 return 0; 5443 } 5444 5445 static int 5446 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key, 5447 const char *value, void *opaque_arg) 5448 { 5449 struct bnxt_representor *vfr_bp = opaque_arg; 5450 unsigned long rep_fc_f2r; 5451 char *end = NULL; 5452 5453 if (!value || !opaque_arg) { 5454 PMD_DRV_LOG(ERR, 5455 "Invalid parameter passed to rep_fc_f2r " 5456 "devargs.\n"); 5457 return -EINVAL; 5458 } 5459 5460 rep_fc_f2r = strtoul(value, &end, 10); 5461 if (end == NULL || *end != '\0' || 5462 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) { 5463 PMD_DRV_LOG(ERR, 5464 "Invalid parameter passed to rep_fc_f2r " 5465 "devargs.\n"); 5466 return -EINVAL; 5467 } 5468 5469 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) { 5470 PMD_DRV_LOG(ERR, 5471 "Invalid value passed to rep_fc_f2r devargs.\n"); 5472 return -EINVAL; 5473 } 5474 5475 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID; 5476 vfr_bp->rep_fc_f2r = rep_fc_f2r; 5477 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r); 5478 5479 return 0; 5480 } 5481 5482 static int 5483 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) 5484 { 5485 struct rte_kvargs *kvlist; 5486 int ret; 5487 5488 if (devargs == NULL) 5489 return 0; 5490 5491 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); 5492 if (kvlist == NULL) 5493 return -EINVAL; 5494 5495 /* 5496 * Handler for "truflow" devarg. 5497 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1" 5498 */ 5499 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW, 5500 bnxt_parse_devarg_truflow, bp); 5501 if (ret) 5502 goto err; 5503 5504 /* 5505 * Handler for "flow_xstat" devarg. 5506 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1" 5507 */ 5508 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, 5509 bnxt_parse_devarg_flow_xstat, bp); 5510 if (ret) 5511 goto err; 5512 5513 /* 5514 * Handler for "max_num_kflows" devarg. 5515 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" 5516 */ 5517 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, 5518 bnxt_parse_devarg_max_num_kflows, bp); 5519 if (ret) 5520 goto err; 5521 5522 err: 5523 rte_kvargs_free(kvlist); 5524 return ret; 5525 } 5526 5527 static int bnxt_alloc_switch_domain(struct bnxt *bp) 5528 { 5529 int rc = 0; 5530 5531 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 5532 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id); 5533 if (rc) 5534 PMD_DRV_LOG(ERR, 5535 "Failed to alloc switch domain: %d\n", rc); 5536 else 5537 PMD_DRV_LOG(INFO, 5538 "Switch domain allocated %d\n", 5539 bp->switch_domain_id); 5540 } 5541 5542 return rc; 5543 } 5544 5545 /* Allocate and initialize various fields in bnxt struct that 5546 * need to be allocated/destroyed only once in the lifetime of the driver 5547 */ 5548 static int bnxt_drv_init(struct rte_eth_dev *eth_dev) 5549 { 5550 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5551 struct bnxt *bp = eth_dev->data->dev_private; 5552 int rc = 0; 5553 5554 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 5555 5556 if (bnxt_vf_pciid(pci_dev->id.device_id)) 5557 bp->flags |= BNXT_FLAG_VF; 5558 5559 if (bnxt_p5_device(pci_dev->id.device_id)) 5560 bp->flags |= BNXT_FLAG_CHIP_P5; 5561 5562 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 5563 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 5564 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 5565 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 5566 bp->flags |= BNXT_FLAG_STINGRAY; 5567 5568 if (BNXT_TRUFLOW_EN(bp)) { 5569 /* extra mbuf field is required to store CFA code from mark */ 5570 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = { 5571 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME, 5572 .size = sizeof(bnxt_cfa_code_dynfield_t), 5573 .align = __alignof__(bnxt_cfa_code_dynfield_t), 5574 }; 5575 bnxt_cfa_code_dynfield_offset = 5576 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc); 5577 if (bnxt_cfa_code_dynfield_offset < 0) { 5578 PMD_DRV_LOG(ERR, 5579 "Failed to register mbuf field for TruFlow mark\n"); 5580 return -rte_errno; 5581 } 5582 } 5583 5584 rc = bnxt_map_pci_bars(eth_dev); 5585 if (rc) { 5586 PMD_DRV_LOG(ERR, 5587 "Failed to initialize board rc: %x\n", rc); 5588 return rc; 5589 } 5590 5591 rc = bnxt_alloc_pf_info(bp); 5592 if (rc) 5593 return rc; 5594 5595 rc = bnxt_alloc_link_info(bp); 5596 if (rc) 5597 return rc; 5598 5599 rc = bnxt_alloc_parent_info(bp); 5600 if (rc) 5601 return rc; 5602 5603 rc = bnxt_alloc_hwrm_resources(bp); 5604 if (rc) { 5605 PMD_DRV_LOG(ERR, 5606 "Failed to allocate response buffer rc: %x\n", rc); 5607 return rc; 5608 } 5609 rc = bnxt_alloc_leds_info(bp); 5610 if (rc) 5611 return rc; 5612 5613 rc = bnxt_alloc_cos_queues(bp); 5614 if (rc) 5615 return rc; 5616 5617 rc = bnxt_init_locks(bp); 5618 if (rc) 5619 return rc; 5620 5621 rc = bnxt_alloc_switch_domain(bp); 5622 if (rc) 5623 return rc; 5624 5625 return rc; 5626 } 5627 5628 static int 5629 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) 5630 { 5631 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5632 static int version_printed; 5633 struct bnxt *bp; 5634 int rc; 5635 5636 if (version_printed++ == 0) 5637 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 5638 5639 eth_dev->dev_ops = &bnxt_dev_ops; 5640 eth_dev->rx_queue_count = bnxt_rx_queue_count_op; 5641 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; 5642 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; 5643 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 5644 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 5645 5646 /* 5647 * For secondary processes, we don't initialise any further 5648 * as primary has already done this work. 5649 */ 5650 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5651 return 0; 5652 5653 rte_eth_copy_pci_info(eth_dev, pci_dev); 5654 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 5655 5656 bp = eth_dev->data->dev_private; 5657 5658 /* Parse dev arguments passed on when starting the DPDK application. */ 5659 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs); 5660 if (rc) 5661 goto error_free; 5662 5663 rc = bnxt_drv_init(eth_dev); 5664 if (rc) 5665 goto error_free; 5666 5667 rc = bnxt_init_resources(bp, false); 5668 if (rc) 5669 goto error_free; 5670 5671 rc = bnxt_alloc_stats_mem(bp); 5672 if (rc) 5673 goto error_free; 5674 5675 PMD_DRV_LOG(INFO, 5676 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", 5677 pci_dev->mem_resource[0].phys_addr, 5678 pci_dev->mem_resource[0].addr); 5679 5680 return 0; 5681 5682 error_free: 5683 bnxt_dev_uninit(eth_dev); 5684 return rc; 5685 } 5686 5687 5688 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx) 5689 { 5690 if (!ctx) 5691 return; 5692 5693 if (ctx->va) 5694 rte_free(ctx->va); 5695 5696 ctx->va = NULL; 5697 ctx->dma = RTE_BAD_IOVA; 5698 ctx->ctx_id = BNXT_CTX_VAL_INVAL; 5699 } 5700 5701 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp) 5702 { 5703 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 5704 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5705 bp->flow_stat->rx_fc_out_tbl.ctx_id, 5706 bp->flow_stat->max_fc, 5707 false); 5708 5709 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 5710 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5711 bp->flow_stat->tx_fc_out_tbl.ctx_id, 5712 bp->flow_stat->max_fc, 5713 false); 5714 5715 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5716 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id); 5717 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5718 5719 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5720 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id); 5721 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5722 5723 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5724 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id); 5725 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5726 5727 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5728 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id); 5729 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5730 } 5731 5732 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp) 5733 { 5734 bnxt_unregister_fc_ctx_mem(bp); 5735 5736 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl); 5737 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl); 5738 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl); 5739 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl); 5740 } 5741 5742 static void bnxt_uninit_ctx_mem(struct bnxt *bp) 5743 { 5744 if (BNXT_FLOW_XSTATS_EN(bp)) 5745 bnxt_uninit_fc_ctx_mem(bp); 5746 } 5747 5748 static void 5749 bnxt_free_error_recovery_info(struct bnxt *bp) 5750 { 5751 rte_free(bp->recovery_info); 5752 bp->recovery_info = NULL; 5753 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5754 } 5755 5756 static int 5757 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 5758 { 5759 int rc; 5760 5761 bnxt_free_int(bp); 5762 bnxt_free_mem(bp, reconfig_dev); 5763 5764 bnxt_hwrm_func_buf_unrgtr(bp); 5765 if (bp->pf != NULL) { 5766 rte_free(bp->pf->vf_req_buf); 5767 bp->pf->vf_req_buf = NULL; 5768 } 5769 5770 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 5771 bp->flags &= ~BNXT_FLAG_REGISTERED; 5772 bnxt_free_ctx_mem(bp); 5773 if (!reconfig_dev) { 5774 bnxt_free_hwrm_resources(bp); 5775 bnxt_free_error_recovery_info(bp); 5776 } 5777 5778 bnxt_uninit_ctx_mem(bp); 5779 5780 bnxt_free_flow_stats_info(bp); 5781 if (bp->rep_info != NULL) 5782 bnxt_free_switch_domain(bp); 5783 bnxt_free_rep_info(bp); 5784 rte_free(bp->ptp_cfg); 5785 bp->ptp_cfg = NULL; 5786 return rc; 5787 } 5788 5789 static int 5790 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 5791 { 5792 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5793 return -EPERM; 5794 5795 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 5796 5797 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 5798 bnxt_dev_close_op(eth_dev); 5799 5800 return 0; 5801 } 5802 5803 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev) 5804 { 5805 struct bnxt *bp = eth_dev->data->dev_private; 5806 struct rte_eth_dev *vf_rep_eth_dev; 5807 int ret = 0, i; 5808 5809 if (!bp) 5810 return -EINVAL; 5811 5812 for (i = 0; i < bp->num_reps; i++) { 5813 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev; 5814 if (!vf_rep_eth_dev) 5815 continue; 5816 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n", 5817 vf_rep_eth_dev->data->port_id); 5818 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit); 5819 } 5820 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", 5821 eth_dev->data->port_id); 5822 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit); 5823 5824 return ret; 5825 } 5826 5827 static void bnxt_free_rep_info(struct bnxt *bp) 5828 { 5829 rte_free(bp->rep_info); 5830 bp->rep_info = NULL; 5831 rte_free(bp->cfa_code_map); 5832 bp->cfa_code_map = NULL; 5833 } 5834 5835 static int bnxt_init_rep_info(struct bnxt *bp) 5836 { 5837 int i = 0, rc; 5838 5839 if (bp->rep_info) 5840 return 0; 5841 5842 bp->rep_info = rte_zmalloc("bnxt_rep_info", 5843 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, 5844 0); 5845 if (!bp->rep_info) { 5846 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); 5847 return -ENOMEM; 5848 } 5849 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map", 5850 sizeof(*bp->cfa_code_map) * 5851 BNXT_MAX_CFA_CODE, 0); 5852 if (!bp->cfa_code_map) { 5853 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n"); 5854 bnxt_free_rep_info(bp); 5855 return -ENOMEM; 5856 } 5857 5858 for (i = 0; i < BNXT_MAX_CFA_CODE; i++) 5859 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID; 5860 5861 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL); 5862 if (rc) { 5863 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n"); 5864 bnxt_free_rep_info(bp); 5865 return rc; 5866 } 5867 5868 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL); 5869 if (rc) { 5870 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n"); 5871 bnxt_free_rep_info(bp); 5872 return rc; 5873 } 5874 5875 return rc; 5876 } 5877 5878 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, 5879 struct rte_eth_devargs *eth_da, 5880 struct rte_eth_dev *backing_eth_dev, 5881 const char *dev_args) 5882 { 5883 struct rte_eth_dev *vf_rep_eth_dev; 5884 char name[RTE_ETH_NAME_MAX_LEN]; 5885 struct bnxt *backing_bp; 5886 uint16_t num_rep; 5887 int i, ret = 0; 5888 struct rte_kvargs *kvlist = NULL; 5889 5890 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) 5891 return 0; 5892 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) { 5893 PMD_DRV_LOG(ERR, "unsupported representor type %d\n", 5894 eth_da->type); 5895 return -ENOTSUP; 5896 } 5897 num_rep = eth_da->nb_representor_ports; 5898 if (num_rep > BNXT_MAX_VF_REPS) { 5899 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", 5900 num_rep, BNXT_MAX_VF_REPS); 5901 return -EINVAL; 5902 } 5903 5904 if (num_rep >= RTE_MAX_ETHPORTS) { 5905 PMD_DRV_LOG(ERR, 5906 "nb_representor_ports = %d > %d MAX ETHPORTS\n", 5907 num_rep, RTE_MAX_ETHPORTS); 5908 return -EINVAL; 5909 } 5910 5911 backing_bp = backing_eth_dev->data->dev_private; 5912 5913 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { 5914 PMD_DRV_LOG(ERR, 5915 "Not a PF or trusted VF. No Representor support\n"); 5916 /* Returning an error is not an option. 5917 * Applications are not handling this correctly 5918 */ 5919 return 0; 5920 } 5921 5922 if (bnxt_init_rep_info(backing_bp)) 5923 return 0; 5924 5925 for (i = 0; i < num_rep; i++) { 5926 struct bnxt_representor representor = { 5927 .vf_id = eth_da->representor_ports[i], 5928 .switch_domain_id = backing_bp->switch_domain_id, 5929 .parent_dev = backing_eth_dev 5930 }; 5931 5932 if (representor.vf_id >= BNXT_MAX_VF_REPS) { 5933 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", 5934 representor.vf_id, BNXT_MAX_VF_REPS); 5935 continue; 5936 } 5937 5938 /* representor port net_bdf_port */ 5939 snprintf(name, sizeof(name), "net_%s_representor_%d", 5940 pci_dev->device.name, eth_da->representor_ports[i]); 5941 5942 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args); 5943 if (kvlist) { 5944 /* 5945 * Handler for "rep_is_pf" devarg. 5946 * Invoked as for ex: "-a 000:00:0d.0, 5947 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5948 */ 5949 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF, 5950 bnxt_parse_devarg_rep_is_pf, 5951 (void *)&representor); 5952 if (ret) { 5953 ret = -EINVAL; 5954 goto err; 5955 } 5956 /* 5957 * Handler for "rep_based_pf" devarg. 5958 * Invoked as for ex: "-a 000:00:0d.0, 5959 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5960 */ 5961 ret = rte_kvargs_process(kvlist, 5962 BNXT_DEVARG_REP_BASED_PF, 5963 bnxt_parse_devarg_rep_based_pf, 5964 (void *)&representor); 5965 if (ret) { 5966 ret = -EINVAL; 5967 goto err; 5968 } 5969 /* 5970 * Handler for "rep_based_pf" devarg. 5971 * Invoked as for ex: "-a 000:00:0d.0, 5972 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5973 */ 5974 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F, 5975 bnxt_parse_devarg_rep_q_r2f, 5976 (void *)&representor); 5977 if (ret) { 5978 ret = -EINVAL; 5979 goto err; 5980 } 5981 /* 5982 * Handler for "rep_based_pf" devarg. 5983 * Invoked as for ex: "-a 000:00:0d.0, 5984 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5985 */ 5986 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R, 5987 bnxt_parse_devarg_rep_q_f2r, 5988 (void *)&representor); 5989 if (ret) { 5990 ret = -EINVAL; 5991 goto err; 5992 } 5993 /* 5994 * Handler for "rep_based_pf" devarg. 5995 * Invoked as for ex: "-a 000:00:0d.0, 5996 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5997 */ 5998 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F, 5999 bnxt_parse_devarg_rep_fc_r2f, 6000 (void *)&representor); 6001 if (ret) { 6002 ret = -EINVAL; 6003 goto err; 6004 } 6005 /* 6006 * Handler for "rep_based_pf" devarg. 6007 * Invoked as for ex: "-a 000:00:0d.0, 6008 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6009 */ 6010 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R, 6011 bnxt_parse_devarg_rep_fc_f2r, 6012 (void *)&representor); 6013 if (ret) { 6014 ret = -EINVAL; 6015 goto err; 6016 } 6017 } 6018 6019 ret = rte_eth_dev_create(&pci_dev->device, name, 6020 sizeof(struct bnxt_representor), 6021 NULL, NULL, 6022 bnxt_representor_init, 6023 &representor); 6024 if (ret) { 6025 PMD_DRV_LOG(ERR, "failed to create bnxt vf " 6026 "representor %s.", name); 6027 goto err; 6028 } 6029 6030 vf_rep_eth_dev = rte_eth_dev_allocated(name); 6031 if (!vf_rep_eth_dev) { 6032 PMD_DRV_LOG(ERR, "Failed to find the eth_dev" 6033 " for VF-Rep: %s.", name); 6034 ret = -ENODEV; 6035 goto err; 6036 } 6037 6038 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n", 6039 backing_eth_dev->data->port_id); 6040 backing_bp->rep_info[representor.vf_id].vfr_eth_dev = 6041 vf_rep_eth_dev; 6042 backing_bp->num_reps++; 6043 6044 } 6045 6046 rte_kvargs_free(kvlist); 6047 return 0; 6048 6049 err: 6050 /* If num_rep > 1, then rollback already created 6051 * ports, since we'll be failing the probe anyway 6052 */ 6053 if (num_rep > 1) 6054 bnxt_pci_remove_dev_with_reps(backing_eth_dev); 6055 rte_errno = -ret; 6056 rte_kvargs_free(kvlist); 6057 6058 return ret; 6059 } 6060 6061 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 6062 struct rte_pci_device *pci_dev) 6063 { 6064 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 6065 struct rte_eth_dev *backing_eth_dev; 6066 uint16_t num_rep; 6067 int ret = 0; 6068 6069 if (pci_dev->device.devargs) { 6070 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, 6071 ð_da); 6072 if (ret) 6073 return ret; 6074 } 6075 6076 num_rep = eth_da.nb_representor_ports; 6077 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n", 6078 num_rep); 6079 6080 /* We could come here after first level of probe is already invoked 6081 * as part of an application bringup(OVS-DPDK vswitchd), so first check 6082 * for already allocated eth_dev for the backing device (PF/Trusted VF) 6083 */ 6084 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6085 if (backing_eth_dev == NULL) { 6086 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 6087 sizeof(struct bnxt), 6088 eth_dev_pci_specific_init, pci_dev, 6089 bnxt_dev_init, NULL); 6090 6091 if (ret || !num_rep) 6092 return ret; 6093 6094 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6095 } 6096 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n", 6097 backing_eth_dev->data->port_id); 6098 6099 if (!num_rep) 6100 return ret; 6101 6102 /* probe representor ports now */ 6103 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev, 6104 pci_dev->device.devargs->args); 6105 6106 return ret; 6107 } 6108 6109 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 6110 { 6111 struct rte_eth_dev *eth_dev; 6112 6113 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6114 if (!eth_dev) 6115 return 0; /* Invoked typically only by OVS-DPDK, by the 6116 * time it comes here the eth_dev is already 6117 * deleted by rte_eth_dev_close(), so returning 6118 * +ve value will at least help in proper cleanup 6119 */ 6120 6121 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id); 6122 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 6123 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 6124 return rte_eth_dev_destroy(eth_dev, 6125 bnxt_representor_uninit); 6126 else 6127 return rte_eth_dev_destroy(eth_dev, 6128 bnxt_dev_uninit); 6129 } else { 6130 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 6131 } 6132 } 6133 6134 static struct rte_pci_driver bnxt_rte_pmd = { 6135 .id_table = bnxt_pci_id_map, 6136 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 6137 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs 6138 * and OVS-DPDK 6139 */ 6140 .probe = bnxt_pci_probe, 6141 .remove = bnxt_pci_remove, 6142 }; 6143 6144 static bool 6145 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 6146 { 6147 if (strcmp(dev->device->driver->name, drv->driver.name)) 6148 return false; 6149 6150 return true; 6151 } 6152 6153 bool is_bnxt_supported(struct rte_eth_dev *dev) 6154 { 6155 return is_device_supported(dev, &bnxt_rte_pmd); 6156 } 6157 6158 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE); 6159 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 6160 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 6161 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 6162