1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <ethdev_driver.h> 11 #include <ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 #include <rte_kvargs.h> 16 #include <rte_vect.h> 17 18 #include "bnxt.h" 19 #include "bnxt_filter.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_irq.h" 22 #include "bnxt_reps.h" 23 #include "bnxt_ring.h" 24 #include "bnxt_rxq.h" 25 #include "bnxt_rxr.h" 26 #include "bnxt_stats.h" 27 #include "bnxt_txq.h" 28 #include "bnxt_txr.h" 29 #include "bnxt_vnic.h" 30 #include "hsi_struct_def_dpdk.h" 31 #include "bnxt_nvm_defs.h" 32 #include "bnxt_tf_common.h" 33 #include "ulp_flow_db.h" 34 #include "rte_pmd_bnxt.h" 35 36 #define DRV_MODULE_NAME "bnxt" 37 static const char bnxt_version[] = 38 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 39 40 /* 41 * The set of PCI devices this driver supports 42 */ 43 static const struct rte_pci_id bnxt_pci_id_map[] = { 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) }, 87 { .vendor_id = 0, /* sentinel */ }, 88 }; 89 90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats" 91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" 92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" 93 #define BNXT_DEVARG_REPRESENTOR "representor" 94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf" 95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf" 96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f" 97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r" 98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f" 99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r" 100 #define BNXT_DEVARG_APP_ID "app-id" 101 102 static const char *const bnxt_dev_args[] = { 103 BNXT_DEVARG_REPRESENTOR, 104 BNXT_DEVARG_ACCUM_STATS, 105 BNXT_DEVARG_FLOW_XSTAT, 106 BNXT_DEVARG_MAX_NUM_KFLOWS, 107 BNXT_DEVARG_REP_BASED_PF, 108 BNXT_DEVARG_REP_IS_PF, 109 BNXT_DEVARG_REP_Q_R2F, 110 BNXT_DEVARG_REP_Q_F2R, 111 BNXT_DEVARG_REP_FC_R2F, 112 BNXT_DEVARG_REP_FC_F2R, 113 BNXT_DEVARG_APP_ID, 114 NULL 115 }; 116 117 /* 118 * accum-stats == false to disable flow counter accumulation 119 * accum-stats == true to enable flow counter accumulation 120 */ 121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1) 122 123 /* 124 * app-id = an non-negative 8-bit number 125 */ 126 #define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255) 127 128 /* 129 * flow_xstat == false to disable the feature 130 * flow_xstat == true to enable the feature 131 */ 132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1) 133 134 /* 135 * rep_is_pf == false to indicate VF representor 136 * rep_is_pf == true to indicate PF representor 137 */ 138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1) 139 140 /* 141 * rep_based_pf == Physical index of the PF 142 */ 143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15) 144 /* 145 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction 146 */ 147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3) 148 149 /* 150 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction 151 */ 152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3) 153 154 /* 155 * rep_fc_r2f == Flow control for the representor to endpoint direction 156 */ 157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1) 158 159 /* 160 * rep_fc_f2r == Flow control for the endpoint to representor direction 161 */ 162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1) 163 164 int bnxt_cfa_code_dynfield_offset = -1; 165 166 /* 167 * max_num_kflows must be >= 32 168 * and must be a power-of-2 supported value 169 * return: 1 -> invalid 170 * 0 -> valid 171 */ 172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows) 173 { 174 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows)) 175 return 1; 176 return 0; 177 } 178 179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 183 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 184 static int bnxt_restore_vlan_filters(struct bnxt *bp); 185 static void bnxt_dev_recover(void *arg); 186 static void bnxt_free_error_recovery_info(struct bnxt *bp); 187 static void bnxt_free_rep_info(struct bnxt *bp); 188 189 int is_bnxt_in_error(struct bnxt *bp) 190 { 191 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 192 return -EIO; 193 if (bp->flags & BNXT_FLAG_FW_RESET) 194 return -EBUSY; 195 196 return 0; 197 } 198 199 /***********************/ 200 201 /* 202 * High level utility functions 203 */ 204 205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 206 { 207 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings, 208 BNXT_RSS_TBL_SIZE_P5); 209 210 if (!BNXT_CHIP_P5(bp)) 211 return 1; 212 213 return RTE_ALIGN_MUL_CEIL(num_rss_rings, 214 BNXT_RSS_ENTRIES_PER_CTX_P5) / 215 BNXT_RSS_ENTRIES_PER_CTX_P5; 216 } 217 218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 219 { 220 if (!BNXT_CHIP_P5(bp)) 221 return HW_HASH_INDEX_SIZE; 222 223 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5; 224 } 225 226 static void bnxt_free_parent_info(struct bnxt *bp) 227 { 228 rte_free(bp->parent); 229 bp->parent = NULL; 230 } 231 232 static void bnxt_free_pf_info(struct bnxt *bp) 233 { 234 rte_free(bp->pf); 235 bp->pf = NULL; 236 } 237 238 static void bnxt_free_link_info(struct bnxt *bp) 239 { 240 rte_free(bp->link_info); 241 bp->link_info = NULL; 242 } 243 244 static void bnxt_free_leds_info(struct bnxt *bp) 245 { 246 if (BNXT_VF(bp)) 247 return; 248 249 rte_free(bp->leds); 250 bp->leds = NULL; 251 } 252 253 static void bnxt_free_flow_stats_info(struct bnxt *bp) 254 { 255 rte_free(bp->flow_stat); 256 bp->flow_stat = NULL; 257 } 258 259 static void bnxt_free_cos_queues(struct bnxt *bp) 260 { 261 rte_free(bp->rx_cos_queue); 262 bp->rx_cos_queue = NULL; 263 rte_free(bp->tx_cos_queue); 264 bp->tx_cos_queue = NULL; 265 } 266 267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 268 { 269 bnxt_free_filter_mem(bp); 270 bnxt_free_vnic_attributes(bp); 271 bnxt_free_vnic_mem(bp); 272 273 /* tx/rx rings are configured as part of *_queue_setup callbacks. 274 * If the number of rings change across fw update, 275 * we don't have much choice except to warn the user. 276 */ 277 if (!reconfig) { 278 bnxt_free_stats(bp); 279 bnxt_free_tx_rings(bp); 280 bnxt_free_rx_rings(bp); 281 } 282 bnxt_free_async_cp_ring(bp); 283 bnxt_free_rxtx_nq_ring(bp); 284 285 rte_free(bp->grp_info); 286 bp->grp_info = NULL; 287 } 288 289 static int bnxt_alloc_parent_info(struct bnxt *bp) 290 { 291 bp->parent = rte_zmalloc("bnxt_parent_info", 292 sizeof(struct bnxt_parent_info), 0); 293 if (bp->parent == NULL) 294 return -ENOMEM; 295 296 return 0; 297 } 298 299 static int bnxt_alloc_pf_info(struct bnxt *bp) 300 { 301 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0); 302 if (bp->pf == NULL) 303 return -ENOMEM; 304 305 return 0; 306 } 307 308 static int bnxt_alloc_link_info(struct bnxt *bp) 309 { 310 bp->link_info = 311 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0); 312 if (bp->link_info == NULL) 313 return -ENOMEM; 314 315 return 0; 316 } 317 318 static int bnxt_alloc_leds_info(struct bnxt *bp) 319 { 320 if (BNXT_VF(bp)) 321 return 0; 322 323 bp->leds = rte_zmalloc("bnxt_leds", 324 BNXT_MAX_LED * sizeof(struct bnxt_led_info), 325 0); 326 if (bp->leds == NULL) 327 return -ENOMEM; 328 329 return 0; 330 } 331 332 static int bnxt_alloc_cos_queues(struct bnxt *bp) 333 { 334 bp->rx_cos_queue = 335 rte_zmalloc("bnxt_rx_cosq", 336 BNXT_COS_QUEUE_COUNT * 337 sizeof(struct bnxt_cos_queue_info), 338 0); 339 if (bp->rx_cos_queue == NULL) 340 return -ENOMEM; 341 342 bp->tx_cos_queue = 343 rte_zmalloc("bnxt_tx_cosq", 344 BNXT_COS_QUEUE_COUNT * 345 sizeof(struct bnxt_cos_queue_info), 346 0); 347 if (bp->tx_cos_queue == NULL) 348 return -ENOMEM; 349 350 return 0; 351 } 352 353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp) 354 { 355 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat", 356 sizeof(struct bnxt_flow_stat_info), 0); 357 if (bp->flow_stat == NULL) 358 return -ENOMEM; 359 360 return 0; 361 } 362 363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 364 { 365 int rc; 366 367 rc = bnxt_alloc_ring_grps(bp); 368 if (rc) 369 goto alloc_mem_err; 370 371 rc = bnxt_alloc_async_ring_struct(bp); 372 if (rc) 373 goto alloc_mem_err; 374 375 rc = bnxt_alloc_vnic_mem(bp); 376 if (rc) 377 goto alloc_mem_err; 378 379 rc = bnxt_alloc_vnic_attributes(bp); 380 if (rc) 381 goto alloc_mem_err; 382 383 rc = bnxt_alloc_filter_mem(bp); 384 if (rc) 385 goto alloc_mem_err; 386 387 rc = bnxt_alloc_async_cp_ring(bp); 388 if (rc) 389 goto alloc_mem_err; 390 391 rc = bnxt_alloc_rxtx_nq_ring(bp); 392 if (rc) 393 goto alloc_mem_err; 394 395 if (BNXT_FLOW_XSTATS_EN(bp)) { 396 rc = bnxt_alloc_flow_stats_info(bp); 397 if (rc) 398 goto alloc_mem_err; 399 } 400 401 return 0; 402 403 alloc_mem_err: 404 bnxt_free_mem(bp, reconfig); 405 return rc; 406 } 407 408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 409 { 410 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 411 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 412 uint64_t rx_offloads = dev_conf->rxmode.offloads; 413 struct bnxt_rx_queue *rxq; 414 unsigned int j; 415 int rc; 416 417 rc = bnxt_vnic_grp_alloc(bp, vnic); 418 if (rc) 419 goto err_out; 420 421 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 422 vnic_id, vnic, vnic->fw_grp_ids); 423 424 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 425 if (rc) 426 goto err_out; 427 428 /* Alloc RSS context only if RSS mode is enabled */ 429 if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) { 430 int j, nr_ctxs = bnxt_rss_ctxts(bp); 431 432 /* RSS table size in Thor is 512. 433 * Cap max Rx rings to same value 434 */ 435 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) { 436 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n", 437 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5); 438 goto err_out; 439 } 440 441 rc = 0; 442 for (j = 0; j < nr_ctxs; j++) { 443 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 444 if (rc) 445 break; 446 } 447 if (rc) { 448 PMD_DRV_LOG(ERR, 449 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 450 vnic_id, j, rc); 451 goto err_out; 452 } 453 vnic->num_lb_ctxts = nr_ctxs; 454 } 455 456 /* 457 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 458 * setting is not available at this time, it will not be 459 * configured correctly in the CFA. 460 */ 461 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 462 vnic->vlan_strip = true; 463 else 464 vnic->vlan_strip = false; 465 466 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 467 if (rc) 468 goto err_out; 469 470 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 471 if (rc) 472 goto err_out; 473 474 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 475 rxq = bp->eth_dev->data->rx_queues[j]; 476 477 PMD_DRV_LOG(DEBUG, 478 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 479 j, rxq->vnic, rxq->vnic->fw_grp_ids); 480 481 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 482 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 483 else 484 vnic->rx_queue_cnt++; 485 } 486 487 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 488 489 rc = bnxt_vnic_rss_configure(bp, vnic); 490 if (rc) 491 goto err_out; 492 493 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 494 495 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 496 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ? 497 true : false); 498 if (rc) 499 goto err_out; 500 501 return 0; 502 err_out: 503 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 504 vnic_id, rc); 505 return rc; 506 } 507 508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp) 509 { 510 int rc = 0; 511 512 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma, 513 &bp->flow_stat->rx_fc_in_tbl.ctx_id); 514 if (rc) 515 return rc; 516 517 PMD_DRV_LOG(DEBUG, 518 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p" 519 " rx_fc_in_tbl.ctx_id = %d\n", 520 bp->flow_stat->rx_fc_in_tbl.va, 521 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma), 522 bp->flow_stat->rx_fc_in_tbl.ctx_id); 523 524 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma, 525 &bp->flow_stat->rx_fc_out_tbl.ctx_id); 526 if (rc) 527 return rc; 528 529 PMD_DRV_LOG(DEBUG, 530 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p" 531 " rx_fc_out_tbl.ctx_id = %d\n", 532 bp->flow_stat->rx_fc_out_tbl.va, 533 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma), 534 bp->flow_stat->rx_fc_out_tbl.ctx_id); 535 536 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma, 537 &bp->flow_stat->tx_fc_in_tbl.ctx_id); 538 if (rc) 539 return rc; 540 541 PMD_DRV_LOG(DEBUG, 542 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p" 543 " tx_fc_in_tbl.ctx_id = %d\n", 544 bp->flow_stat->tx_fc_in_tbl.va, 545 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma), 546 bp->flow_stat->tx_fc_in_tbl.ctx_id); 547 548 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma, 549 &bp->flow_stat->tx_fc_out_tbl.ctx_id); 550 if (rc) 551 return rc; 552 553 PMD_DRV_LOG(DEBUG, 554 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p" 555 " tx_fc_out_tbl.ctx_id = %d\n", 556 bp->flow_stat->tx_fc_out_tbl.va, 557 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma), 558 bp->flow_stat->tx_fc_out_tbl.ctx_id); 559 560 memset(bp->flow_stat->rx_fc_out_tbl.va, 561 0, 562 bp->flow_stat->rx_fc_out_tbl.size); 563 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 564 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 565 bp->flow_stat->rx_fc_out_tbl.ctx_id, 566 bp->flow_stat->max_fc, 567 true); 568 if (rc) 569 return rc; 570 571 memset(bp->flow_stat->tx_fc_out_tbl.va, 572 0, 573 bp->flow_stat->tx_fc_out_tbl.size); 574 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 575 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 576 bp->flow_stat->tx_fc_out_tbl.ctx_id, 577 bp->flow_stat->max_fc, 578 true); 579 580 return rc; 581 } 582 583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size, 584 struct bnxt_ctx_mem_buf_info *ctx) 585 { 586 if (!ctx) 587 return -EINVAL; 588 589 ctx->va = rte_zmalloc_socket(type, size, 0, 590 bp->eth_dev->device->numa_node); 591 if (ctx->va == NULL) 592 return -ENOMEM; 593 rte_mem_lock_page(ctx->va); 594 ctx->size = size; 595 ctx->dma = rte_mem_virt2iova(ctx->va); 596 if (ctx->dma == RTE_BAD_IOVA) 597 return -ENOMEM; 598 599 return 0; 600 } 601 602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp) 603 { 604 struct rte_pci_device *pdev = bp->pdev; 605 char type[RTE_MEMZONE_NAMESIZE]; 606 uint16_t max_fc; 607 int rc = 0; 608 609 max_fc = bp->flow_stat->max_fc; 610 611 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 612 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 613 /* 4 bytes for each counter-id */ 614 rc = bnxt_alloc_ctx_mem_buf(bp, type, 615 max_fc * 4, 616 &bp->flow_stat->rx_fc_in_tbl); 617 if (rc) 618 return rc; 619 620 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 621 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 622 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 623 rc = bnxt_alloc_ctx_mem_buf(bp, type, 624 max_fc * 16, 625 &bp->flow_stat->rx_fc_out_tbl); 626 if (rc) 627 return rc; 628 629 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 630 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 631 /* 4 bytes for each counter-id */ 632 rc = bnxt_alloc_ctx_mem_buf(bp, type, 633 max_fc * 4, 634 &bp->flow_stat->tx_fc_in_tbl); 635 if (rc) 636 return rc; 637 638 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 639 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 640 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 641 rc = bnxt_alloc_ctx_mem_buf(bp, type, 642 max_fc * 16, 643 &bp->flow_stat->tx_fc_out_tbl); 644 if (rc) 645 return rc; 646 647 rc = bnxt_register_fc_ctx_mem(bp); 648 649 return rc; 650 } 651 652 static int bnxt_init_ctx_mem(struct bnxt *bp) 653 { 654 int rc = 0; 655 656 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) || 657 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) || 658 !BNXT_FLOW_XSTATS_EN(bp)) 659 return 0; 660 661 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc); 662 if (rc) 663 return rc; 664 665 rc = bnxt_init_fc_ctx_mem(bp); 666 667 return rc; 668 } 669 670 static int bnxt_update_phy_setting(struct bnxt *bp) 671 { 672 struct rte_eth_link new; 673 int rc; 674 675 rc = bnxt_get_hwrm_link_config(bp, &new); 676 if (rc) { 677 PMD_DRV_LOG(ERR, "Failed to get link settings\n"); 678 return rc; 679 } 680 681 /* 682 * On BCM957508-N2100 adapters, FW will not allow any user other 683 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call 684 * always returns link up. Force phy update always in that case. 685 */ 686 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) { 687 rc = bnxt_set_hwrm_link_config(bp, true); 688 if (rc) { 689 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n"); 690 return rc; 691 } 692 } 693 694 return rc; 695 } 696 697 static void bnxt_free_prev_ring_stats(struct bnxt *bp) 698 { 699 rte_free(bp->prev_rx_ring_stats); 700 rte_free(bp->prev_tx_ring_stats); 701 702 bp->prev_rx_ring_stats = NULL; 703 bp->prev_tx_ring_stats = NULL; 704 } 705 706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp) 707 { 708 bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats", 709 sizeof(struct bnxt_ring_stats) * 710 bp->rx_cp_nr_rings, 711 0); 712 if (bp->prev_rx_ring_stats == NULL) 713 return -ENOMEM; 714 715 bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats", 716 sizeof(struct bnxt_ring_stats) * 717 bp->tx_cp_nr_rings, 718 0); 719 if (bp->prev_tx_ring_stats == NULL) 720 goto error; 721 722 return 0; 723 724 error: 725 bnxt_free_prev_ring_stats(bp); 726 return -ENOMEM; 727 } 728 729 static int bnxt_start_nic(struct bnxt *bp) 730 { 731 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 732 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 733 uint32_t intr_vector = 0; 734 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 735 uint32_t vec = BNXT_MISC_VEC_ID; 736 unsigned int i, j; 737 int rc; 738 739 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) 740 bp->flags |= BNXT_FLAG_JUMBO; 741 else 742 bp->flags &= ~BNXT_FLAG_JUMBO; 743 744 /* THOR does not support ring groups. 745 * But we will use the array to save RSS context IDs. 746 */ 747 if (BNXT_CHIP_P5(bp)) 748 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; 749 750 rc = bnxt_alloc_hwrm_rings(bp); 751 if (rc) { 752 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 753 goto err_out; 754 } 755 756 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 757 if (rc) { 758 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 759 goto err_out; 760 } 761 762 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 763 goto skip_cosq_cfg; 764 765 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 766 if (bp->rx_cos_queue[i].id != 0xff) { 767 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 768 769 if (!vnic) { 770 PMD_DRV_LOG(ERR, 771 "Num pools more than FW profile\n"); 772 rc = -EINVAL; 773 goto err_out; 774 } 775 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 776 bp->rx_cosq_cnt++; 777 } 778 } 779 780 skip_cosq_cfg: 781 rc = bnxt_mq_rx_configure(bp); 782 if (rc) { 783 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 784 goto err_out; 785 } 786 787 for (j = 0; j < bp->rx_nr_rings; j++) { 788 struct bnxt_rx_queue *rxq = bp->rx_queues[j]; 789 790 if (!rxq->rx_deferred_start) { 791 bp->eth_dev->data->rx_queue_state[j] = 792 RTE_ETH_QUEUE_STATE_STARTED; 793 rxq->rx_started = true; 794 } 795 } 796 797 /* default vnic 0 */ 798 rc = bnxt_setup_one_vnic(bp, 0); 799 if (rc) 800 goto err_out; 801 /* VNIC configuration */ 802 if (BNXT_RFS_NEEDS_VNIC(bp)) { 803 for (i = 1; i < bp->nr_vnics; i++) { 804 rc = bnxt_setup_one_vnic(bp, i); 805 if (rc) 806 goto err_out; 807 } 808 } 809 810 for (j = 0; j < bp->tx_nr_rings; j++) { 811 struct bnxt_tx_queue *txq = bp->tx_queues[j]; 812 813 if (!txq->tx_deferred_start) { 814 bp->eth_dev->data->tx_queue_state[j] = 815 RTE_ETH_QUEUE_STATE_STARTED; 816 txq->tx_started = true; 817 } 818 } 819 820 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 821 if (rc) { 822 PMD_DRV_LOG(ERR, 823 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 824 goto err_out; 825 } 826 827 /* check and configure queue intr-vector mapping */ 828 if ((rte_intr_cap_multiple(intr_handle) || 829 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 830 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 831 intr_vector = bp->eth_dev->data->nb_rx_queues; 832 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 833 if (intr_vector > bp->rx_cp_nr_rings) { 834 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 835 bp->rx_cp_nr_rings); 836 return -ENOTSUP; 837 } 838 rc = rte_intr_efd_enable(intr_handle, intr_vector); 839 if (rc) 840 return rc; 841 } 842 843 if (rte_intr_dp_is_en(intr_handle)) { 844 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec", 845 bp->eth_dev->data->nb_rx_queues)) { 846 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 847 " intr_vec", bp->eth_dev->data->nb_rx_queues); 848 rc = -ENOMEM; 849 goto err_out; 850 } 851 PMD_DRV_LOG(DEBUG, "intr_handle->nb_efd = %d " 852 "intr_handle->max_intr = %d\n", 853 rte_intr_nb_efd_get(intr_handle), 854 rte_intr_max_intr_get(intr_handle)); 855 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 856 queue_id++) { 857 rte_intr_vec_list_index_set(intr_handle, 858 queue_id, vec + BNXT_RX_VEC_START); 859 if (vec < base + rte_intr_nb_efd_get(intr_handle) 860 - 1) 861 vec++; 862 } 863 } 864 865 /* enable uio/vfio intr/eventfd mapping */ 866 rc = rte_intr_enable(intr_handle); 867 #ifndef RTE_EXEC_ENV_FREEBSD 868 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 869 if (rc) 870 goto err_out; 871 #endif 872 873 rc = bnxt_update_phy_setting(bp); 874 if (rc) 875 goto err_out; 876 877 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 878 if (!bp->mark_table) 879 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 880 881 return 0; 882 883 err_out: 884 /* Some of the error status returned by FW may not be from errno.h */ 885 if (rc > 0) 886 rc = -EIO; 887 888 return rc; 889 } 890 891 static int bnxt_shutdown_nic(struct bnxt *bp) 892 { 893 bnxt_free_all_hwrm_resources(bp); 894 bnxt_free_all_filters(bp); 895 bnxt_free_all_vnics(bp); 896 return 0; 897 } 898 899 /* 900 * Device configuration and status function 901 */ 902 903 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) 904 { 905 uint32_t link_speed = 0; 906 uint32_t speed_capa = 0; 907 908 if (bp->link_info == NULL) 909 return 0; 910 911 link_speed = bp->link_info->support_speeds; 912 913 /* If PAM4 is configured, use PAM4 supported speed */ 914 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0) 915 link_speed = bp->link_info->support_pam4_speeds; 916 917 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) 918 speed_capa |= RTE_ETH_LINK_SPEED_100M; 919 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) 920 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD; 921 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) 922 speed_capa |= RTE_ETH_LINK_SPEED_1G; 923 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 924 speed_capa |= RTE_ETH_LINK_SPEED_2_5G; 925 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) 926 speed_capa |= RTE_ETH_LINK_SPEED_10G; 927 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 928 speed_capa |= RTE_ETH_LINK_SPEED_20G; 929 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) 930 speed_capa |= RTE_ETH_LINK_SPEED_25G; 931 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) 932 speed_capa |= RTE_ETH_LINK_SPEED_40G; 933 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) 934 speed_capa |= RTE_ETH_LINK_SPEED_50G; 935 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) 936 speed_capa |= RTE_ETH_LINK_SPEED_100G; 937 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) 938 speed_capa |= RTE_ETH_LINK_SPEED_50G; 939 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) 940 speed_capa |= RTE_ETH_LINK_SPEED_100G; 941 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G) 942 speed_capa |= RTE_ETH_LINK_SPEED_200G; 943 944 if (bp->link_info->auto_mode == 945 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 946 speed_capa |= RTE_ETH_LINK_SPEED_FIXED; 947 948 return speed_capa; 949 } 950 951 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 952 struct rte_eth_dev_info *dev_info) 953 { 954 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 955 struct bnxt *bp = eth_dev->data->dev_private; 956 uint16_t max_vnics, i, j, vpool, vrxq; 957 unsigned int max_rx_rings; 958 int rc; 959 960 rc = is_bnxt_in_error(bp); 961 if (rc) 962 return rc; 963 964 /* MAC Specifics */ 965 dev_info->max_mac_addrs = bp->max_l2_ctx; 966 dev_info->max_hash_mac_addrs = 0; 967 968 /* PF/VF specifics */ 969 if (BNXT_PF(bp)) 970 dev_info->max_vfs = pdev->max_vfs; 971 972 max_rx_rings = bnxt_max_rings(bp); 973 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 974 dev_info->max_rx_queues = max_rx_rings; 975 dev_info->max_tx_queues = max_rx_rings; 976 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 977 dev_info->hash_key_size = HW_HASH_KEY_SIZE; 978 max_vnics = bp->max_vnics; 979 980 /* MTU specifics */ 981 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 982 dev_info->max_mtu = BNXT_MAX_MTU; 983 984 /* Fast path specifics */ 985 dev_info->min_rx_bufsize = 1; 986 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 987 988 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 989 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 990 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP; 991 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP) 992 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 993 dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 994 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT | 995 dev_info->tx_queue_offload_capa; 996 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT) 997 dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_VLAN_INSERT; 998 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 999 1000 dev_info->speed_capa = bnxt_get_speed_capabilities(bp); 1001 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 1002 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 1003 1004 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1005 .rx_thresh = { 1006 .pthresh = 8, 1007 .hthresh = 8, 1008 .wthresh = 0, 1009 }, 1010 .rx_free_thresh = 32, 1011 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN, 1012 }; 1013 1014 dev_info->default_txconf = (struct rte_eth_txconf) { 1015 .tx_thresh = { 1016 .pthresh = 32, 1017 .hthresh = 0, 1018 .wthresh = 0, 1019 }, 1020 .tx_free_thresh = 32, 1021 .tx_rs_thresh = 32, 1022 }; 1023 eth_dev->data->dev_conf.intr_conf.lsc = 1; 1024 1025 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 1026 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 1027 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 1028 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 1029 1030 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 1031 dev_info->switch_info.name = eth_dev->device->name; 1032 dev_info->switch_info.domain_id = bp->switch_domain_id; 1033 dev_info->switch_info.port_id = 1034 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF : 1035 BNXT_SWITCH_PORT_ID_TRUSTED_VF; 1036 } 1037 1038 /* 1039 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 1040 * need further investigation. 1041 */ 1042 1043 /* VMDq resources */ 1044 vpool = 64; /* RTE_ETH_64_POOLS */ 1045 vrxq = 128; /* RTE_ETH_VMDQ_DCB_NUM_QUEUES */ 1046 for (i = 0; i < 4; vpool >>= 1, i++) { 1047 if (max_vnics > vpool) { 1048 for (j = 0; j < 5; vrxq >>= 1, j++) { 1049 if (dev_info->max_rx_queues > vrxq) { 1050 if (vpool > vrxq) 1051 vpool = vrxq; 1052 goto found; 1053 } 1054 } 1055 /* Not enough resources to support VMDq */ 1056 break; 1057 } 1058 } 1059 /* Not enough resources to support VMDq */ 1060 vpool = 0; 1061 vrxq = 0; 1062 found: 1063 dev_info->max_vmdq_pools = vpool; 1064 dev_info->vmdq_queue_num = vrxq; 1065 1066 dev_info->vmdq_pool_base = 0; 1067 dev_info->vmdq_queue_base = 0; 1068 1069 return 0; 1070 } 1071 1072 /* Configure the device based on the configuration provided */ 1073 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 1074 { 1075 struct bnxt *bp = eth_dev->data->dev_private; 1076 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1077 int rc; 1078 1079 bp->rx_queues = (void *)eth_dev->data->rx_queues; 1080 bp->tx_queues = (void *)eth_dev->data->tx_queues; 1081 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 1082 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 1083 1084 rc = is_bnxt_in_error(bp); 1085 if (rc) 1086 return rc; 1087 1088 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 1089 rc = bnxt_hwrm_check_vf_rings(bp); 1090 if (rc) { 1091 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 1092 return -ENOSPC; 1093 } 1094 1095 /* If a resource has already been allocated - in this case 1096 * it is the async completion ring, free it. Reallocate it after 1097 * resource reservation. This will ensure the resource counts 1098 * are calculated correctly. 1099 */ 1100 1101 pthread_mutex_lock(&bp->def_cp_lock); 1102 1103 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1104 bnxt_disable_int(bp); 1105 bnxt_free_cp_ring(bp, bp->async_cp_ring); 1106 } 1107 1108 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 1109 if (rc) { 1110 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 1111 pthread_mutex_unlock(&bp->def_cp_lock); 1112 return -ENOSPC; 1113 } 1114 1115 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1116 rc = bnxt_alloc_async_cp_ring(bp); 1117 if (rc) { 1118 pthread_mutex_unlock(&bp->def_cp_lock); 1119 return rc; 1120 } 1121 bnxt_enable_int(bp); 1122 } 1123 1124 pthread_mutex_unlock(&bp->def_cp_lock); 1125 } 1126 1127 /* Inherit new configurations */ 1128 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 1129 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 1130 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 1131 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 1132 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 1133 bp->max_stat_ctx) 1134 goto resource_error; 1135 1136 if (BNXT_HAS_RING_GRPS(bp) && 1137 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 1138 goto resource_error; 1139 1140 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) && 1141 bp->max_vnics < eth_dev->data->nb_rx_queues) 1142 goto resource_error; 1143 1144 bp->rx_cp_nr_rings = bp->rx_nr_rings; 1145 bp->tx_cp_nr_rings = bp->tx_nr_rings; 1146 1147 if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 1148 rx_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 1149 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 1150 1151 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 1152 1153 return 0; 1154 1155 resource_error: 1156 PMD_DRV_LOG(ERR, 1157 "Insufficient resources to support requested config\n"); 1158 PMD_DRV_LOG(ERR, 1159 "Num Queues Requested: Tx %d, Rx %d\n", 1160 eth_dev->data->nb_tx_queues, 1161 eth_dev->data->nb_rx_queues); 1162 PMD_DRV_LOG(ERR, 1163 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 1164 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 1165 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 1166 return -ENOSPC; 1167 } 1168 1169 void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 1170 { 1171 struct rte_eth_link *link = ð_dev->data->dev_link; 1172 1173 if (link->link_status) 1174 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 1175 eth_dev->data->port_id, 1176 (uint32_t)link->link_speed, 1177 (link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? 1178 ("full-duplex") : ("half-duplex\n")); 1179 else 1180 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 1181 eth_dev->data->port_id); 1182 } 1183 1184 /* 1185 * Determine whether the current configuration requires support for scattered 1186 * receive; return 1 if scattered receive is required and 0 if not. 1187 */ 1188 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 1189 { 1190 uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU; 1191 uint16_t buf_size; 1192 int i; 1193 1194 if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) 1195 return 1; 1196 1197 if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) 1198 return 1; 1199 1200 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 1201 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 1202 1203 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1204 RTE_PKTMBUF_HEADROOM); 1205 if (eth_dev->data->mtu + overhead > buf_size) 1206 return 1; 1207 } 1208 return 0; 1209 } 1210 1211 static eth_rx_burst_t 1212 bnxt_receive_function(struct rte_eth_dev *eth_dev) 1213 { 1214 struct bnxt *bp = eth_dev->data->dev_private; 1215 1216 /* Disable vector mode RX for Stingray2 for now */ 1217 if (BNXT_CHIP_SR2(bp)) { 1218 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1219 return bnxt_recv_pkts; 1220 } 1221 1222 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \ 1223 !defined(RTE_LIBRTE_IEEE1588) 1224 1225 /* Vector mode receive cannot be enabled if scattered rx is in use. */ 1226 if (eth_dev->data->scattered_rx) 1227 goto use_scalar_rx; 1228 1229 /* 1230 * Vector mode receive cannot be enabled if Truflow is enabled or if 1231 * asynchronous completions and receive completions can be placed in 1232 * the same completion ring. 1233 */ 1234 if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp)) 1235 goto use_scalar_rx; 1236 1237 /* 1238 * Vector mode receive cannot be enabled if any receive offloads outside 1239 * a limited subset have been enabled. 1240 */ 1241 if (eth_dev->data->dev_conf.rxmode.offloads & 1242 ~(RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 1243 RTE_ETH_RX_OFFLOAD_KEEP_CRC | 1244 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 1245 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 1246 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 1247 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1248 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | 1249 RTE_ETH_RX_OFFLOAD_RSS_HASH | 1250 RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) 1251 goto use_scalar_rx; 1252 1253 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 1254 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && 1255 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) { 1256 PMD_DRV_LOG(INFO, 1257 "Using AVX2 vector mode receive for port %d\n", 1258 eth_dev->data->port_id); 1259 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1260 return bnxt_recv_pkts_vec_avx2; 1261 } 1262 #endif 1263 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1264 PMD_DRV_LOG(INFO, 1265 "Using SSE vector mode receive for port %d\n", 1266 eth_dev->data->port_id); 1267 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1268 return bnxt_recv_pkts_vec; 1269 } 1270 1271 use_scalar_rx: 1272 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 1273 eth_dev->data->port_id); 1274 PMD_DRV_LOG(INFO, 1275 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 1276 eth_dev->data->port_id, 1277 eth_dev->data->scattered_rx, 1278 eth_dev->data->dev_conf.rxmode.offloads); 1279 #endif 1280 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1281 return bnxt_recv_pkts; 1282 } 1283 1284 static eth_tx_burst_t 1285 bnxt_transmit_function(struct rte_eth_dev *eth_dev) 1286 { 1287 struct bnxt *bp = eth_dev->data->dev_private; 1288 1289 /* Disable vector mode TX for Stingray2 for now */ 1290 if (BNXT_CHIP_SR2(bp)) 1291 return bnxt_xmit_pkts; 1292 1293 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \ 1294 !defined(RTE_LIBRTE_IEEE1588) 1295 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; 1296 1297 /* 1298 * Vector mode transmit can be enabled only if not using scatter rx 1299 * or tx offloads. 1300 */ 1301 if (eth_dev->data->scattered_rx || 1302 (offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) || 1303 BNXT_TRUFLOW_EN(bp)) 1304 goto use_scalar_tx; 1305 1306 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 1307 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && 1308 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) { 1309 PMD_DRV_LOG(INFO, 1310 "Using AVX2 vector mode transmit for port %d\n", 1311 eth_dev->data->port_id); 1312 return bnxt_xmit_pkts_vec_avx2; 1313 } 1314 #endif 1315 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1316 PMD_DRV_LOG(INFO, 1317 "Using SSE vector mode transmit for port %d\n", 1318 eth_dev->data->port_id); 1319 return bnxt_xmit_pkts_vec; 1320 } 1321 1322 use_scalar_tx: 1323 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 1324 eth_dev->data->port_id); 1325 PMD_DRV_LOG(INFO, 1326 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 1327 eth_dev->data->port_id, 1328 eth_dev->data->scattered_rx, 1329 offloads); 1330 #endif 1331 return bnxt_xmit_pkts; 1332 } 1333 1334 static int bnxt_handle_if_change_status(struct bnxt *bp) 1335 { 1336 int rc; 1337 1338 /* Since fw has undergone a reset and lost all contexts, 1339 * set fatal flag to not issue hwrm during cleanup 1340 */ 1341 bp->flags |= BNXT_FLAG_FATAL_ERROR; 1342 bnxt_uninit_resources(bp, true); 1343 1344 /* clear fatal flag so that re-init happens */ 1345 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 1346 rc = bnxt_init_resources(bp, true); 1347 1348 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 1349 1350 return rc; 1351 } 1352 1353 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 1354 { 1355 struct bnxt *bp = eth_dev->data->dev_private; 1356 int rc = 0; 1357 1358 if (!BNXT_SINGLE_PF(bp)) 1359 return -ENOTSUP; 1360 1361 if (!bp->link_info->link_up) 1362 rc = bnxt_set_hwrm_link_config(bp, true); 1363 if (!rc) 1364 eth_dev->data->dev_link.link_status = 1; 1365 1366 bnxt_print_link_info(eth_dev); 1367 return rc; 1368 } 1369 1370 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 1371 { 1372 struct bnxt *bp = eth_dev->data->dev_private; 1373 1374 if (!BNXT_SINGLE_PF(bp)) 1375 return -ENOTSUP; 1376 1377 eth_dev->data->dev_link.link_status = 0; 1378 bnxt_set_hwrm_link_config(bp, false); 1379 bp->link_info->link_up = 0; 1380 1381 return 0; 1382 } 1383 1384 static void bnxt_free_switch_domain(struct bnxt *bp) 1385 { 1386 int rc = 0; 1387 1388 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) 1389 return; 1390 1391 rc = rte_eth_switch_domain_free(bp->switch_domain_id); 1392 if (rc) 1393 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n", 1394 bp->switch_domain_id, rc); 1395 } 1396 1397 static void bnxt_ptp_get_current_time(void *arg) 1398 { 1399 struct bnxt *bp = arg; 1400 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1401 int rc; 1402 1403 rc = is_bnxt_in_error(bp); 1404 if (rc) 1405 return; 1406 1407 if (!ptp) 1408 return; 1409 1410 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1411 &ptp->current_time); 1412 1413 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1414 if (rc != 0) { 1415 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n"); 1416 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1417 } 1418 } 1419 1420 static int bnxt_schedule_ptp_alarm(struct bnxt *bp) 1421 { 1422 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1423 int rc; 1424 1425 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) 1426 return 0; 1427 1428 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1429 &ptp->current_time); 1430 1431 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1432 return rc; 1433 } 1434 1435 static void bnxt_cancel_ptp_alarm(struct bnxt *bp) 1436 { 1437 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) { 1438 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp); 1439 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1440 } 1441 } 1442 1443 static void bnxt_ptp_stop(struct bnxt *bp) 1444 { 1445 bnxt_cancel_ptp_alarm(bp); 1446 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1447 } 1448 1449 static int bnxt_ptp_start(struct bnxt *bp) 1450 { 1451 int rc; 1452 1453 rc = bnxt_schedule_ptp_alarm(bp); 1454 if (rc != 0) { 1455 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n"); 1456 } else { 1457 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1458 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1459 } 1460 1461 return rc; 1462 } 1463 1464 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev) 1465 { 1466 struct bnxt *bp = eth_dev->data->dev_private; 1467 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1468 struct rte_intr_handle *intr_handle = pci_dev->intr_handle; 1469 struct rte_eth_link link; 1470 int ret; 1471 1472 eth_dev->data->dev_started = 0; 1473 1474 /* Prevent crashes when queues are still in use */ 1475 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 1476 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 1477 1478 bnxt_disable_int(bp); 1479 1480 /* disable uio/vfio intr/eventfd mapping */ 1481 rte_intr_disable(intr_handle); 1482 1483 /* Stop the child representors for this device */ 1484 ret = bnxt_rep_stop_all(bp); 1485 if (ret != 0) 1486 return ret; 1487 1488 /* delete the bnxt ULP port details */ 1489 bnxt_ulp_port_deinit(bp); 1490 1491 bnxt_cancel_fw_health_check(bp); 1492 1493 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1494 bnxt_cancel_ptp_alarm(bp); 1495 1496 /* Do not bring link down during reset recovery */ 1497 if (!is_bnxt_in_error(bp)) { 1498 bnxt_dev_set_link_down_op(eth_dev); 1499 /* Wait for link to be reset */ 1500 if (BNXT_SINGLE_PF(bp)) 1501 rte_delay_ms(500); 1502 /* clear the recorded link status */ 1503 memset(&link, 0, sizeof(link)); 1504 rte_eth_linkstatus_set(eth_dev, &link); 1505 } 1506 1507 /* Clean queue intr-vector mapping */ 1508 rte_intr_efd_disable(intr_handle); 1509 rte_intr_vec_list_free(intr_handle); 1510 1511 bnxt_hwrm_port_clr_stats(bp); 1512 bnxt_free_tx_mbufs(bp); 1513 bnxt_free_rx_mbufs(bp); 1514 /* Process any remaining notifications in default completion queue */ 1515 bnxt_int_handler(eth_dev); 1516 bnxt_shutdown_nic(bp); 1517 bnxt_hwrm_if_change(bp, false); 1518 1519 bnxt_free_prev_ring_stats(bp); 1520 rte_free(bp->mark_table); 1521 bp->mark_table = NULL; 1522 1523 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1524 bp->rx_cosq_cnt = 0; 1525 /* All filters are deleted on a port stop. */ 1526 if (BNXT_FLOW_XSTATS_EN(bp)) 1527 bp->flow_stat->flow_count = 0; 1528 1529 eth_dev->data->scattered_rx = 0; 1530 1531 return 0; 1532 } 1533 1534 /* Unload the driver, release resources */ 1535 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 1536 { 1537 struct bnxt *bp = eth_dev->data->dev_private; 1538 1539 pthread_mutex_lock(&bp->err_recovery_lock); 1540 if (bp->flags & BNXT_FLAG_FW_RESET) { 1541 PMD_DRV_LOG(ERR, 1542 "Adapter recovering from error..Please retry\n"); 1543 pthread_mutex_unlock(&bp->err_recovery_lock); 1544 return -EAGAIN; 1545 } 1546 pthread_mutex_unlock(&bp->err_recovery_lock); 1547 1548 return bnxt_dev_stop(eth_dev); 1549 } 1550 1551 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 1552 { 1553 struct bnxt *bp = eth_dev->data->dev_private; 1554 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1555 int vlan_mask = 0; 1556 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; 1557 1558 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 1559 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 1560 return -EINVAL; 1561 } 1562 1563 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) 1564 PMD_DRV_LOG(ERR, 1565 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 1566 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1567 1568 do { 1569 rc = bnxt_hwrm_if_change(bp, true); 1570 if (rc == 0 || rc != -EAGAIN) 1571 break; 1572 1573 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); 1574 } while (retry_cnt--); 1575 1576 if (rc) 1577 return rc; 1578 1579 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 1580 rc = bnxt_handle_if_change_status(bp); 1581 if (rc) 1582 return rc; 1583 } 1584 1585 bnxt_enable_int(bp); 1586 1587 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 1588 1589 rc = bnxt_start_nic(bp); 1590 if (rc) 1591 goto error; 1592 1593 rc = bnxt_alloc_prev_ring_stats(bp); 1594 if (rc) 1595 goto error; 1596 1597 eth_dev->data->dev_started = 1; 1598 1599 bnxt_link_update_op(eth_dev, 1); 1600 1601 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 1602 vlan_mask |= RTE_ETH_VLAN_FILTER_MASK; 1603 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 1604 vlan_mask |= RTE_ETH_VLAN_STRIP_MASK; 1605 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 1606 if (rc) 1607 goto error; 1608 1609 /* Initialize bnxt ULP port details */ 1610 rc = bnxt_ulp_port_init(bp); 1611 if (rc) 1612 goto error; 1613 1614 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 1615 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 1616 1617 bnxt_schedule_fw_health_check(bp); 1618 1619 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1620 bnxt_schedule_ptp_alarm(bp); 1621 1622 return 0; 1623 1624 error: 1625 bnxt_dev_stop(eth_dev); 1626 return rc; 1627 } 1628 1629 static void 1630 bnxt_uninit_locks(struct bnxt *bp) 1631 { 1632 pthread_mutex_destroy(&bp->flow_lock); 1633 pthread_mutex_destroy(&bp->def_cp_lock); 1634 pthread_mutex_destroy(&bp->health_check_lock); 1635 pthread_mutex_destroy(&bp->err_recovery_lock); 1636 if (bp->rep_info) { 1637 pthread_mutex_destroy(&bp->rep_info->vfr_lock); 1638 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); 1639 } 1640 } 1641 1642 static void bnxt_drv_uninit(struct bnxt *bp) 1643 { 1644 bnxt_free_leds_info(bp); 1645 bnxt_free_cos_queues(bp); 1646 bnxt_free_link_info(bp); 1647 bnxt_free_parent_info(bp); 1648 bnxt_uninit_locks(bp); 1649 1650 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 1651 bp->tx_mem_zone = NULL; 1652 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 1653 bp->rx_mem_zone = NULL; 1654 1655 bnxt_free_vf_info(bp); 1656 bnxt_free_pf_info(bp); 1657 1658 rte_free(bp->grp_info); 1659 bp->grp_info = NULL; 1660 } 1661 1662 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 1663 { 1664 struct bnxt *bp = eth_dev->data->dev_private; 1665 int ret = 0; 1666 1667 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1668 return 0; 1669 1670 pthread_mutex_lock(&bp->err_recovery_lock); 1671 if (bp->flags & BNXT_FLAG_FW_RESET) { 1672 PMD_DRV_LOG(ERR, 1673 "Adapter recovering from error...Please retry\n"); 1674 pthread_mutex_unlock(&bp->err_recovery_lock); 1675 return -EAGAIN; 1676 } 1677 pthread_mutex_unlock(&bp->err_recovery_lock); 1678 1679 /* cancel the recovery handler before remove dev */ 1680 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); 1681 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); 1682 bnxt_cancel_fc_thread(bp); 1683 1684 if (eth_dev->data->dev_started) 1685 ret = bnxt_dev_stop(eth_dev); 1686 1687 bnxt_uninit_resources(bp, false); 1688 1689 bnxt_drv_uninit(bp); 1690 1691 return ret; 1692 } 1693 1694 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1695 uint32_t index) 1696 { 1697 struct bnxt *bp = eth_dev->data->dev_private; 1698 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1699 struct bnxt_vnic_info *vnic; 1700 struct bnxt_filter_info *filter, *temp_filter; 1701 uint32_t i; 1702 1703 if (is_bnxt_in_error(bp)) 1704 return; 1705 1706 /* 1707 * Loop through all VNICs from the specified filter flow pools to 1708 * remove the corresponding MAC addr filter 1709 */ 1710 for (i = 0; i < bp->nr_vnics; i++) { 1711 if (!(pool_mask & (1ULL << i))) 1712 continue; 1713 1714 vnic = &bp->vnic_info[i]; 1715 filter = STAILQ_FIRST(&vnic->filter); 1716 while (filter) { 1717 temp_filter = STAILQ_NEXT(filter, next); 1718 if (filter->mac_index == index) { 1719 STAILQ_REMOVE(&vnic->filter, filter, 1720 bnxt_filter_info, next); 1721 bnxt_hwrm_clear_l2_filter(bp, filter); 1722 bnxt_free_filter(bp, filter); 1723 } 1724 filter = temp_filter; 1725 } 1726 } 1727 } 1728 1729 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1730 struct rte_ether_addr *mac_addr, uint32_t index, 1731 uint32_t pool) 1732 { 1733 struct bnxt_filter_info *filter; 1734 int rc = 0; 1735 1736 /* Attach requested MAC address to the new l2_filter */ 1737 STAILQ_FOREACH(filter, &vnic->filter, next) { 1738 if (filter->mac_index == index) { 1739 PMD_DRV_LOG(DEBUG, 1740 "MAC addr already existed for pool %d\n", 1741 pool); 1742 return 0; 1743 } 1744 } 1745 1746 filter = bnxt_alloc_filter(bp); 1747 if (!filter) { 1748 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1749 return -ENODEV; 1750 } 1751 1752 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1753 * if the MAC that's been programmed now is a different one, then, 1754 * copy that addr to filter->l2_addr 1755 */ 1756 if (mac_addr) 1757 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1758 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1759 1760 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1761 if (!rc) { 1762 filter->mac_index = index; 1763 if (filter->mac_index == 0) 1764 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1765 else 1766 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1767 } else { 1768 bnxt_free_filter(bp, filter); 1769 } 1770 1771 return rc; 1772 } 1773 1774 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1775 struct rte_ether_addr *mac_addr, 1776 uint32_t index, uint32_t pool) 1777 { 1778 struct bnxt *bp = eth_dev->data->dev_private; 1779 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1780 int rc = 0; 1781 1782 rc = is_bnxt_in_error(bp); 1783 if (rc) 1784 return rc; 1785 1786 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 1787 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1788 return -ENOTSUP; 1789 } 1790 1791 if (!vnic) { 1792 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1793 return -EINVAL; 1794 } 1795 1796 /* Filter settings will get applied when port is started */ 1797 if (!eth_dev->data->dev_started) 1798 return 0; 1799 1800 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1801 1802 return rc; 1803 } 1804 1805 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 1806 { 1807 int rc = 0; 1808 struct bnxt *bp = eth_dev->data->dev_private; 1809 struct rte_eth_link new; 1810 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT : 1811 BNXT_MIN_LINK_WAIT_CNT; 1812 1813 rc = is_bnxt_in_error(bp); 1814 if (rc) 1815 return rc; 1816 1817 memset(&new, 0, sizeof(new)); 1818 1819 if (bp->link_info == NULL) 1820 goto out; 1821 1822 do { 1823 /* Retrieve link info from hardware */ 1824 rc = bnxt_get_hwrm_link_config(bp, &new); 1825 if (rc) { 1826 new.link_speed = RTE_ETH_LINK_SPEED_100M; 1827 new.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 1828 PMD_DRV_LOG(ERR, 1829 "Failed to retrieve link rc = 0x%x!\n", rc); 1830 goto out; 1831 } 1832 1833 if (!wait_to_complete || new.link_status) 1834 break; 1835 1836 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1837 } while (cnt--); 1838 1839 /* Only single function PF can bring phy down. 1840 * When port is stopped, report link down for VF/MH/NPAR functions. 1841 */ 1842 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started) 1843 memset(&new, 0, sizeof(new)); 1844 1845 out: 1846 /* Timed out or success */ 1847 if (new.link_status != eth_dev->data->dev_link.link_status || 1848 new.link_speed != eth_dev->data->dev_link.link_speed) { 1849 rte_eth_linkstatus_set(eth_dev, &new); 1850 bnxt_print_link_info(eth_dev); 1851 } 1852 1853 return rc; 1854 } 1855 1856 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1857 { 1858 struct bnxt *bp = eth_dev->data->dev_private; 1859 struct bnxt_vnic_info *vnic; 1860 uint32_t old_flags; 1861 int rc; 1862 1863 rc = is_bnxt_in_error(bp); 1864 if (rc) 1865 return rc; 1866 1867 /* Filter settings will get applied when port is started */ 1868 if (!eth_dev->data->dev_started) 1869 return 0; 1870 1871 if (bp->vnic_info == NULL) 1872 return 0; 1873 1874 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1875 1876 old_flags = vnic->flags; 1877 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1878 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1879 if (rc != 0) 1880 vnic->flags = old_flags; 1881 1882 return rc; 1883 } 1884 1885 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1886 { 1887 struct bnxt *bp = eth_dev->data->dev_private; 1888 struct bnxt_vnic_info *vnic; 1889 uint32_t old_flags; 1890 int rc; 1891 1892 rc = is_bnxt_in_error(bp); 1893 if (rc) 1894 return rc; 1895 1896 /* Filter settings will get applied when port is started */ 1897 if (!eth_dev->data->dev_started) 1898 return 0; 1899 1900 if (bp->vnic_info == NULL) 1901 return 0; 1902 1903 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1904 1905 old_flags = vnic->flags; 1906 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1907 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1908 if (rc != 0) 1909 vnic->flags = old_flags; 1910 1911 return rc; 1912 } 1913 1914 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1915 { 1916 struct bnxt *bp = eth_dev->data->dev_private; 1917 struct bnxt_vnic_info *vnic; 1918 uint32_t old_flags; 1919 int rc; 1920 1921 rc = is_bnxt_in_error(bp); 1922 if (rc) 1923 return rc; 1924 1925 /* Filter settings will get applied when port is started */ 1926 if (!eth_dev->data->dev_started) 1927 return 0; 1928 1929 if (bp->vnic_info == NULL) 1930 return 0; 1931 1932 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1933 1934 old_flags = vnic->flags; 1935 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1936 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1937 if (rc != 0) 1938 vnic->flags = old_flags; 1939 1940 return rc; 1941 } 1942 1943 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1944 { 1945 struct bnxt *bp = eth_dev->data->dev_private; 1946 struct bnxt_vnic_info *vnic; 1947 uint32_t old_flags; 1948 int rc; 1949 1950 rc = is_bnxt_in_error(bp); 1951 if (rc) 1952 return rc; 1953 1954 /* Filter settings will get applied when port is started */ 1955 if (!eth_dev->data->dev_started) 1956 return 0; 1957 1958 if (bp->vnic_info == NULL) 1959 return 0; 1960 1961 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1962 1963 old_flags = vnic->flags; 1964 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1965 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1966 if (rc != 0) 1967 vnic->flags = old_flags; 1968 1969 return rc; 1970 } 1971 1972 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1973 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1974 { 1975 if (qid >= bp->rx_nr_rings) 1976 return NULL; 1977 1978 return bp->eth_dev->data->rx_queues[qid]; 1979 } 1980 1981 /* Return rxq corresponding to a given rss table ring/group ID. */ 1982 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1983 { 1984 struct bnxt_rx_queue *rxq; 1985 unsigned int i; 1986 1987 if (!BNXT_HAS_RING_GRPS(bp)) { 1988 for (i = 0; i < bp->rx_nr_rings; i++) { 1989 rxq = bp->eth_dev->data->rx_queues[i]; 1990 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1991 return rxq->index; 1992 } 1993 } else { 1994 for (i = 0; i < bp->rx_nr_rings; i++) { 1995 if (bp->grp_info[i].fw_grp_id == fwr) 1996 return i; 1997 } 1998 } 1999 2000 return INVALID_HW_RING_ID; 2001 } 2002 2003 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 2004 struct rte_eth_rss_reta_entry64 *reta_conf, 2005 uint16_t reta_size) 2006 { 2007 struct bnxt *bp = eth_dev->data->dev_private; 2008 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 2009 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2010 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 2011 uint16_t idx, sft; 2012 int i, rc; 2013 2014 rc = is_bnxt_in_error(bp); 2015 if (rc) 2016 return rc; 2017 2018 if (!vnic->rss_table) 2019 return -EINVAL; 2020 2021 if (!(dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 2022 return -EINVAL; 2023 2024 if (reta_size != tbl_size) { 2025 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 2026 "(%d) must equal the size supported by the hardware " 2027 "(%d)\n", reta_size, tbl_size); 2028 return -EINVAL; 2029 } 2030 2031 for (i = 0; i < reta_size; i++) { 2032 struct bnxt_rx_queue *rxq; 2033 2034 idx = i / RTE_ETH_RETA_GROUP_SIZE; 2035 sft = i % RTE_ETH_RETA_GROUP_SIZE; 2036 2037 if (!(reta_conf[idx].mask & (1ULL << sft))) 2038 continue; 2039 2040 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 2041 if (!rxq) { 2042 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 2043 return -EINVAL; 2044 } 2045 2046 if (BNXT_CHIP_P5(bp)) { 2047 vnic->rss_table[i * 2] = 2048 rxq->rx_ring->rx_ring_struct->fw_ring_id; 2049 vnic->rss_table[i * 2 + 1] = 2050 rxq->cp_ring->cp_ring_struct->fw_ring_id; 2051 } else { 2052 vnic->rss_table[i] = 2053 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 2054 } 2055 } 2056 2057 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 2058 return rc; 2059 } 2060 2061 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 2062 struct rte_eth_rss_reta_entry64 *reta_conf, 2063 uint16_t reta_size) 2064 { 2065 struct bnxt *bp = eth_dev->data->dev_private; 2066 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2067 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 2068 uint16_t idx, sft, i; 2069 int rc; 2070 2071 rc = is_bnxt_in_error(bp); 2072 if (rc) 2073 return rc; 2074 2075 if (!vnic) 2076 return -EINVAL; 2077 if (!vnic->rss_table) 2078 return -EINVAL; 2079 2080 if (reta_size != tbl_size) { 2081 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 2082 "(%d) must equal the size supported by the hardware " 2083 "(%d)\n", reta_size, tbl_size); 2084 return -EINVAL; 2085 } 2086 2087 for (idx = 0, i = 0; i < reta_size; i++) { 2088 idx = i / RTE_ETH_RETA_GROUP_SIZE; 2089 sft = i % RTE_ETH_RETA_GROUP_SIZE; 2090 2091 if (reta_conf[idx].mask & (1ULL << sft)) { 2092 uint16_t qid; 2093 2094 if (BNXT_CHIP_P5(bp)) 2095 qid = bnxt_rss_to_qid(bp, 2096 vnic->rss_table[i * 2]); 2097 else 2098 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 2099 2100 if (qid == INVALID_HW_RING_ID) { 2101 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 2102 return -EINVAL; 2103 } 2104 reta_conf[idx].reta[sft] = qid; 2105 } 2106 } 2107 2108 return 0; 2109 } 2110 2111 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 2112 struct rte_eth_rss_conf *rss_conf) 2113 { 2114 struct bnxt *bp = eth_dev->data->dev_private; 2115 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 2116 struct bnxt_vnic_info *vnic; 2117 int rc; 2118 2119 rc = is_bnxt_in_error(bp); 2120 if (rc) 2121 return rc; 2122 2123 /* 2124 * If RSS enablement were different than dev_configure, 2125 * then return -EINVAL 2126 */ 2127 if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) { 2128 if (!rss_conf->rss_hf) 2129 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 2130 } else { 2131 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 2132 return -EINVAL; 2133 } 2134 2135 bp->flags |= BNXT_FLAG_UPDATE_HASH; 2136 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf, 2137 rss_conf, 2138 sizeof(*rss_conf)); 2139 2140 /* Update the default RSS VNIC(s) */ 2141 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2142 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 2143 vnic->hash_mode = 2144 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf, 2145 RTE_ETH_RSS_LEVEL(rss_conf->rss_hf)); 2146 2147 /* 2148 * If hashkey is not specified, use the previously configured 2149 * hashkey 2150 */ 2151 if (!rss_conf->rss_key) 2152 goto rss_config; 2153 2154 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 2155 PMD_DRV_LOG(ERR, 2156 "Invalid hashkey length, should be %d bytes\n", 2157 HW_HASH_KEY_SIZE); 2158 return -EINVAL; 2159 } 2160 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 2161 2162 rss_config: 2163 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 2164 return rc; 2165 } 2166 2167 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 2168 struct rte_eth_rss_conf *rss_conf) 2169 { 2170 struct bnxt *bp = eth_dev->data->dev_private; 2171 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2172 int len, rc; 2173 uint32_t hash_types; 2174 2175 rc = is_bnxt_in_error(bp); 2176 if (rc) 2177 return rc; 2178 2179 /* RSS configuration is the same for all VNICs */ 2180 if (vnic && vnic->rss_hash_key) { 2181 if (rss_conf->rss_key) { 2182 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 2183 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 2184 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 2185 } 2186 2187 hash_types = vnic->hash_type; 2188 rss_conf->rss_hf = 0; 2189 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 2190 rss_conf->rss_hf |= RTE_ETH_RSS_IPV4; 2191 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 2192 } 2193 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 2194 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP; 2195 hash_types &= 2196 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 2197 } 2198 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 2199 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP; 2200 hash_types &= 2201 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 2202 } 2203 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 2204 rss_conf->rss_hf |= RTE_ETH_RSS_IPV6; 2205 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 2206 } 2207 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 2208 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP; 2209 hash_types &= 2210 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 2211 } 2212 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 2213 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP; 2214 hash_types &= 2215 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 2216 } 2217 2218 rss_conf->rss_hf |= 2219 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode); 2220 2221 if (hash_types) { 2222 PMD_DRV_LOG(ERR, 2223 "Unknown RSS config from firmware (%08x), RSS disabled", 2224 vnic->hash_type); 2225 return -ENOTSUP; 2226 } 2227 } else { 2228 rss_conf->rss_hf = 0; 2229 } 2230 return 0; 2231 } 2232 2233 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 2234 struct rte_eth_fc_conf *fc_conf) 2235 { 2236 struct bnxt *bp = dev->data->dev_private; 2237 struct rte_eth_link link_info; 2238 int rc; 2239 2240 rc = is_bnxt_in_error(bp); 2241 if (rc) 2242 return rc; 2243 2244 rc = bnxt_get_hwrm_link_config(bp, &link_info); 2245 if (rc) 2246 return rc; 2247 2248 memset(fc_conf, 0, sizeof(*fc_conf)); 2249 if (bp->link_info->auto_pause) 2250 fc_conf->autoneg = 1; 2251 switch (bp->link_info->pause) { 2252 case 0: 2253 fc_conf->mode = RTE_ETH_FC_NONE; 2254 break; 2255 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 2256 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 2257 break; 2258 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 2259 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 2260 break; 2261 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 2262 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 2263 fc_conf->mode = RTE_ETH_FC_FULL; 2264 break; 2265 } 2266 return 0; 2267 } 2268 2269 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 2270 struct rte_eth_fc_conf *fc_conf) 2271 { 2272 struct bnxt *bp = dev->data->dev_private; 2273 int rc; 2274 2275 rc = is_bnxt_in_error(bp); 2276 if (rc) 2277 return rc; 2278 2279 if (!BNXT_SINGLE_PF(bp)) { 2280 PMD_DRV_LOG(ERR, 2281 "Flow Control Settings cannot be modified on VF or on shared PF\n"); 2282 return -ENOTSUP; 2283 } 2284 2285 switch (fc_conf->mode) { 2286 case RTE_ETH_FC_NONE: 2287 bp->link_info->auto_pause = 0; 2288 bp->link_info->force_pause = 0; 2289 break; 2290 case RTE_ETH_FC_RX_PAUSE: 2291 if (fc_conf->autoneg) { 2292 bp->link_info->auto_pause = 2293 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2294 bp->link_info->force_pause = 0; 2295 } else { 2296 bp->link_info->auto_pause = 0; 2297 bp->link_info->force_pause = 2298 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2299 } 2300 break; 2301 case RTE_ETH_FC_TX_PAUSE: 2302 if (fc_conf->autoneg) { 2303 bp->link_info->auto_pause = 2304 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 2305 bp->link_info->force_pause = 0; 2306 } else { 2307 bp->link_info->auto_pause = 0; 2308 bp->link_info->force_pause = 2309 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 2310 } 2311 break; 2312 case RTE_ETH_FC_FULL: 2313 if (fc_conf->autoneg) { 2314 bp->link_info->auto_pause = 2315 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 2316 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2317 bp->link_info->force_pause = 0; 2318 } else { 2319 bp->link_info->auto_pause = 0; 2320 bp->link_info->force_pause = 2321 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 2322 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2323 } 2324 break; 2325 } 2326 return bnxt_set_hwrm_link_config(bp, true); 2327 } 2328 2329 /* Add UDP tunneling port */ 2330 static int 2331 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 2332 struct rte_eth_udp_tunnel *udp_tunnel) 2333 { 2334 struct bnxt *bp = eth_dev->data->dev_private; 2335 uint16_t tunnel_type = 0; 2336 int rc = 0; 2337 2338 rc = is_bnxt_in_error(bp); 2339 if (rc) 2340 return rc; 2341 2342 switch (udp_tunnel->prot_type) { 2343 case RTE_ETH_TUNNEL_TYPE_VXLAN: 2344 if (bp->vxlan_port_cnt) { 2345 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2346 udp_tunnel->udp_port); 2347 if (bp->vxlan_port != udp_tunnel->udp_port) { 2348 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2349 return -ENOSPC; 2350 } 2351 bp->vxlan_port_cnt++; 2352 return 0; 2353 } 2354 tunnel_type = 2355 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 2356 break; 2357 case RTE_ETH_TUNNEL_TYPE_GENEVE: 2358 if (bp->geneve_port_cnt) { 2359 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2360 udp_tunnel->udp_port); 2361 if (bp->geneve_port != udp_tunnel->udp_port) { 2362 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2363 return -ENOSPC; 2364 } 2365 bp->geneve_port_cnt++; 2366 return 0; 2367 } 2368 tunnel_type = 2369 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 2370 break; 2371 default: 2372 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2373 return -ENOTSUP; 2374 } 2375 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 2376 tunnel_type); 2377 2378 if (rc != 0) 2379 return rc; 2380 2381 if (tunnel_type == 2382 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN) 2383 bp->vxlan_port_cnt++; 2384 2385 if (tunnel_type == 2386 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE) 2387 bp->geneve_port_cnt++; 2388 2389 return rc; 2390 } 2391 2392 static int 2393 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 2394 struct rte_eth_udp_tunnel *udp_tunnel) 2395 { 2396 struct bnxt *bp = eth_dev->data->dev_private; 2397 uint16_t tunnel_type = 0; 2398 uint16_t port = 0; 2399 int rc = 0; 2400 2401 rc = is_bnxt_in_error(bp); 2402 if (rc) 2403 return rc; 2404 2405 switch (udp_tunnel->prot_type) { 2406 case RTE_ETH_TUNNEL_TYPE_VXLAN: 2407 if (!bp->vxlan_port_cnt) { 2408 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2409 return -EINVAL; 2410 } 2411 if (bp->vxlan_port != udp_tunnel->udp_port) { 2412 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2413 udp_tunnel->udp_port, bp->vxlan_port); 2414 return -EINVAL; 2415 } 2416 if (--bp->vxlan_port_cnt) 2417 return 0; 2418 2419 tunnel_type = 2420 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 2421 port = bp->vxlan_fw_dst_port_id; 2422 break; 2423 case RTE_ETH_TUNNEL_TYPE_GENEVE: 2424 if (!bp->geneve_port_cnt) { 2425 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2426 return -EINVAL; 2427 } 2428 if (bp->geneve_port != udp_tunnel->udp_port) { 2429 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2430 udp_tunnel->udp_port, bp->geneve_port); 2431 return -EINVAL; 2432 } 2433 if (--bp->geneve_port_cnt) 2434 return 0; 2435 2436 tunnel_type = 2437 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 2438 port = bp->geneve_fw_dst_port_id; 2439 break; 2440 default: 2441 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2442 return -ENOTSUP; 2443 } 2444 2445 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 2446 return rc; 2447 } 2448 2449 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2450 { 2451 struct bnxt_filter_info *filter; 2452 struct bnxt_vnic_info *vnic; 2453 int rc = 0; 2454 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2455 2456 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2457 filter = STAILQ_FIRST(&vnic->filter); 2458 while (filter) { 2459 /* Search for this matching MAC+VLAN filter */ 2460 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 2461 /* Delete the filter */ 2462 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2463 if (rc) 2464 return rc; 2465 STAILQ_REMOVE(&vnic->filter, filter, 2466 bnxt_filter_info, next); 2467 bnxt_free_filter(bp, filter); 2468 PMD_DRV_LOG(INFO, 2469 "Deleted vlan filter for %d\n", 2470 vlan_id); 2471 return 0; 2472 } 2473 filter = STAILQ_NEXT(filter, next); 2474 } 2475 return -ENOENT; 2476 } 2477 2478 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2479 { 2480 struct bnxt_filter_info *filter; 2481 struct bnxt_vnic_info *vnic; 2482 int rc = 0; 2483 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 2484 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 2485 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2486 2487 /* Implementation notes on the use of VNIC in this command: 2488 * 2489 * By default, these filters belong to default vnic for the function. 2490 * Once these filters are set up, only destination VNIC can be modified. 2491 * If the destination VNIC is not specified in this command, 2492 * then the HWRM shall only create an l2 context id. 2493 */ 2494 2495 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2496 filter = STAILQ_FIRST(&vnic->filter); 2497 /* Check if the VLAN has already been added */ 2498 while (filter) { 2499 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 2500 return -EEXIST; 2501 2502 filter = STAILQ_NEXT(filter, next); 2503 } 2504 2505 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 2506 * command to create MAC+VLAN filter with the right flags, enables set. 2507 */ 2508 filter = bnxt_alloc_filter(bp); 2509 if (!filter) { 2510 PMD_DRV_LOG(ERR, 2511 "MAC/VLAN filter alloc failed\n"); 2512 return -ENOMEM; 2513 } 2514 /* MAC + VLAN ID filter */ 2515 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 2516 * untagged packets are received 2517 * 2518 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 2519 * packets and only the programmed vlan's packets are received 2520 */ 2521 filter->l2_ivlan = vlan_id; 2522 filter->l2_ivlan_mask = 0x0FFF; 2523 filter->enables |= en; 2524 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2525 2526 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2527 if (rc) { 2528 /* Free the newly allocated filter as we were 2529 * not able to create the filter in hardware. 2530 */ 2531 bnxt_free_filter(bp, filter); 2532 return rc; 2533 } 2534 2535 filter->mac_index = 0; 2536 /* Add this new filter to the list */ 2537 if (vlan_id == 0) 2538 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 2539 else 2540 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2541 2542 PMD_DRV_LOG(INFO, 2543 "Added Vlan filter for %d\n", vlan_id); 2544 return rc; 2545 } 2546 2547 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 2548 uint16_t vlan_id, int on) 2549 { 2550 struct bnxt *bp = eth_dev->data->dev_private; 2551 int rc; 2552 2553 rc = is_bnxt_in_error(bp); 2554 if (rc) 2555 return rc; 2556 2557 if (!eth_dev->data->dev_started) { 2558 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n"); 2559 return -EINVAL; 2560 } 2561 2562 /* These operations apply to ALL existing MAC/VLAN filters */ 2563 if (on) 2564 return bnxt_add_vlan_filter(bp, vlan_id); 2565 else 2566 return bnxt_del_vlan_filter(bp, vlan_id); 2567 } 2568 2569 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 2570 struct bnxt_vnic_info *vnic) 2571 { 2572 struct bnxt_filter_info *filter; 2573 int rc; 2574 2575 filter = STAILQ_FIRST(&vnic->filter); 2576 while (filter) { 2577 if (filter->mac_index == 0 && 2578 !memcmp(filter->l2_addr, bp->mac_addr, 2579 RTE_ETHER_ADDR_LEN)) { 2580 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2581 if (!rc) { 2582 STAILQ_REMOVE(&vnic->filter, filter, 2583 bnxt_filter_info, next); 2584 bnxt_free_filter(bp, filter); 2585 } 2586 return rc; 2587 } 2588 filter = STAILQ_NEXT(filter, next); 2589 } 2590 return 0; 2591 } 2592 2593 static int 2594 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 2595 { 2596 struct bnxt_vnic_info *vnic; 2597 unsigned int i; 2598 int rc; 2599 2600 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2601 if (!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) { 2602 /* Remove any VLAN filters programmed */ 2603 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2604 bnxt_del_vlan_filter(bp, i); 2605 2606 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2607 if (rc) 2608 return rc; 2609 } else { 2610 /* Default filter will allow packets that match the 2611 * dest mac. So, it has to be deleted, otherwise, we 2612 * will endup receiving vlan packets for which the 2613 * filter is not programmed, when hw-vlan-filter 2614 * configuration is ON 2615 */ 2616 bnxt_del_dflt_mac_filter(bp, vnic); 2617 /* This filter will allow only untagged packets */ 2618 bnxt_add_vlan_filter(bp, 0); 2619 } 2620 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 2621 !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)); 2622 2623 return 0; 2624 } 2625 2626 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 2627 { 2628 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2629 unsigned int i; 2630 int rc; 2631 2632 /* Destroy vnic filters and vnic */ 2633 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2634 RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 2635 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2636 bnxt_del_vlan_filter(bp, i); 2637 } 2638 bnxt_del_dflt_mac_filter(bp, vnic); 2639 2640 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic); 2641 if (rc) 2642 return rc; 2643 2644 rc = bnxt_hwrm_vnic_free(bp, vnic); 2645 if (rc) 2646 return rc; 2647 2648 rte_free(vnic->fw_grp_ids); 2649 vnic->fw_grp_ids = NULL; 2650 2651 vnic->rx_queue_cnt = 0; 2652 2653 return 0; 2654 } 2655 2656 static int 2657 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 2658 { 2659 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2660 int rc; 2661 2662 /* Destroy, recreate and reconfigure the default vnic */ 2663 rc = bnxt_free_one_vnic(bp, 0); 2664 if (rc) 2665 return rc; 2666 2667 /* default vnic 0 */ 2668 rc = bnxt_setup_one_vnic(bp, 0); 2669 if (rc) 2670 return rc; 2671 2672 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2673 RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 2674 rc = bnxt_add_vlan_filter(bp, 0); 2675 if (rc) 2676 return rc; 2677 rc = bnxt_restore_vlan_filters(bp); 2678 if (rc) 2679 return rc; 2680 } else { 2681 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2682 if (rc) 2683 return rc; 2684 } 2685 2686 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2687 if (rc) 2688 return rc; 2689 2690 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 2691 !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)); 2692 2693 return rc; 2694 } 2695 2696 static int 2697 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 2698 { 2699 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 2700 struct bnxt *bp = dev->data->dev_private; 2701 int rc; 2702 2703 rc = is_bnxt_in_error(bp); 2704 if (rc) 2705 return rc; 2706 2707 /* Filter settings will get applied when port is started */ 2708 if (!dev->data->dev_started) 2709 return 0; 2710 2711 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 2712 /* Enable or disable VLAN filtering */ 2713 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 2714 if (rc) 2715 return rc; 2716 } 2717 2718 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 2719 /* Enable or disable VLAN stripping */ 2720 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2721 if (rc) 2722 return rc; 2723 } 2724 2725 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 2726 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) 2727 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2728 else 2729 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2730 } 2731 2732 return 0; 2733 } 2734 2735 static int 2736 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2737 uint16_t tpid) 2738 { 2739 struct bnxt *bp = dev->data->dev_private; 2740 int qinq = dev->data->dev_conf.rxmode.offloads & 2741 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; 2742 2743 if (vlan_type != RTE_ETH_VLAN_TYPE_INNER && 2744 vlan_type != RTE_ETH_VLAN_TYPE_OUTER) { 2745 PMD_DRV_LOG(ERR, 2746 "Unsupported vlan type."); 2747 return -EINVAL; 2748 } 2749 if (!qinq) { 2750 PMD_DRV_LOG(ERR, 2751 "QinQ not enabled. Needs to be ON as we can " 2752 "accelerate only outer vlan\n"); 2753 return -EINVAL; 2754 } 2755 2756 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) { 2757 switch (tpid) { 2758 case RTE_ETHER_TYPE_QINQ: 2759 bp->outer_tpid_bd = 2760 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2761 break; 2762 case RTE_ETHER_TYPE_VLAN: 2763 bp->outer_tpid_bd = 2764 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2765 break; 2766 case RTE_ETHER_TYPE_QINQ1: 2767 bp->outer_tpid_bd = 2768 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2769 break; 2770 case RTE_ETHER_TYPE_QINQ2: 2771 bp->outer_tpid_bd = 2772 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2773 break; 2774 case RTE_ETHER_TYPE_QINQ3: 2775 bp->outer_tpid_bd = 2776 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2777 break; 2778 default: 2779 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2780 return -EINVAL; 2781 } 2782 bp->outer_tpid_bd |= tpid; 2783 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2784 } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) { 2785 PMD_DRV_LOG(ERR, 2786 "Can accelerate only outer vlan in QinQ\n"); 2787 return -EINVAL; 2788 } 2789 2790 return 0; 2791 } 2792 2793 static int 2794 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2795 struct rte_ether_addr *addr) 2796 { 2797 struct bnxt *bp = dev->data->dev_private; 2798 /* Default Filter is tied to VNIC 0 */ 2799 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2800 int rc; 2801 2802 rc = is_bnxt_in_error(bp); 2803 if (rc) 2804 return rc; 2805 2806 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2807 return -EPERM; 2808 2809 if (rte_is_zero_ether_addr(addr)) 2810 return -EINVAL; 2811 2812 /* Filter settings will get applied when port is started */ 2813 if (!dev->data->dev_started) 2814 return 0; 2815 2816 /* Check if the requested MAC is already added */ 2817 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2818 return 0; 2819 2820 /* Destroy filter and re-create it */ 2821 bnxt_del_dflt_mac_filter(bp, vnic); 2822 2823 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2824 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 2825 /* This filter will allow only untagged packets */ 2826 rc = bnxt_add_vlan_filter(bp, 0); 2827 } else { 2828 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2829 } 2830 2831 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2832 return rc; 2833 } 2834 2835 static int 2836 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2837 struct rte_ether_addr *mc_addr_set, 2838 uint32_t nb_mc_addr) 2839 { 2840 struct bnxt *bp = eth_dev->data->dev_private; 2841 char *mc_addr_list = (char *)mc_addr_set; 2842 struct bnxt_vnic_info *vnic; 2843 uint32_t off = 0, i = 0; 2844 int rc; 2845 2846 rc = is_bnxt_in_error(bp); 2847 if (rc) 2848 return rc; 2849 2850 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2851 2852 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2853 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2854 goto allmulti; 2855 } 2856 2857 /* TODO Check for Duplicate mcast addresses */ 2858 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2859 for (i = 0; i < nb_mc_addr; i++) { 2860 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2861 RTE_ETHER_ADDR_LEN); 2862 off += RTE_ETHER_ADDR_LEN; 2863 } 2864 2865 vnic->mc_addr_cnt = i; 2866 if (vnic->mc_addr_cnt) 2867 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2868 else 2869 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2870 2871 allmulti: 2872 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2873 } 2874 2875 static int 2876 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2877 { 2878 struct bnxt *bp = dev->data->dev_private; 2879 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2880 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2881 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2882 uint8_t fw_rsvd = bp->fw_ver & 0xff; 2883 int ret; 2884 2885 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", 2886 fw_major, fw_minor, fw_updt, fw_rsvd); 2887 if (ret < 0) 2888 return -EINVAL; 2889 2890 ret += 1; /* add the size of '\0' */ 2891 if (fw_size < (size_t)ret) 2892 return ret; 2893 else 2894 return 0; 2895 } 2896 2897 static void 2898 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2899 struct rte_eth_rxq_info *qinfo) 2900 { 2901 struct bnxt *bp = dev->data->dev_private; 2902 struct bnxt_rx_queue *rxq; 2903 2904 if (is_bnxt_in_error(bp)) 2905 return; 2906 2907 rxq = dev->data->rx_queues[queue_id]; 2908 2909 qinfo->mp = rxq->mb_pool; 2910 qinfo->scattered_rx = dev->data->scattered_rx; 2911 qinfo->nb_desc = rxq->nb_rx_desc; 2912 2913 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2914 qinfo->conf.rx_drop_en = rxq->drop_en; 2915 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2916 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 2917 } 2918 2919 static void 2920 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2921 struct rte_eth_txq_info *qinfo) 2922 { 2923 struct bnxt *bp = dev->data->dev_private; 2924 struct bnxt_tx_queue *txq; 2925 2926 if (is_bnxt_in_error(bp)) 2927 return; 2928 2929 txq = dev->data->tx_queues[queue_id]; 2930 2931 qinfo->nb_desc = txq->nb_tx_desc; 2932 2933 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2934 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2935 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2936 2937 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2938 qinfo->conf.tx_rs_thresh = 0; 2939 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2940 qinfo->conf.offloads = txq->offloads; 2941 } 2942 2943 static const struct { 2944 eth_rx_burst_t pkt_burst; 2945 const char *info; 2946 } bnxt_rx_burst_info[] = { 2947 {bnxt_recv_pkts, "Scalar"}, 2948 #if defined(RTE_ARCH_X86) 2949 {bnxt_recv_pkts_vec, "Vector SSE"}, 2950 #endif 2951 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 2952 {bnxt_recv_pkts_vec_avx2, "Vector AVX2"}, 2953 #endif 2954 #if defined(RTE_ARCH_ARM64) 2955 {bnxt_recv_pkts_vec, "Vector Neon"}, 2956 #endif 2957 }; 2958 2959 static int 2960 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2961 struct rte_eth_burst_mode *mode) 2962 { 2963 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 2964 size_t i; 2965 2966 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) { 2967 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) { 2968 snprintf(mode->info, sizeof(mode->info), "%s", 2969 bnxt_rx_burst_info[i].info); 2970 return 0; 2971 } 2972 } 2973 2974 return -EINVAL; 2975 } 2976 2977 static const struct { 2978 eth_tx_burst_t pkt_burst; 2979 const char *info; 2980 } bnxt_tx_burst_info[] = { 2981 {bnxt_xmit_pkts, "Scalar"}, 2982 #if defined(RTE_ARCH_X86) 2983 {bnxt_xmit_pkts_vec, "Vector SSE"}, 2984 #endif 2985 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 2986 {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"}, 2987 #endif 2988 #if defined(RTE_ARCH_ARM64) 2989 {bnxt_xmit_pkts_vec, "Vector Neon"}, 2990 #endif 2991 }; 2992 2993 static int 2994 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2995 struct rte_eth_burst_mode *mode) 2996 { 2997 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 2998 size_t i; 2999 3000 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) { 3001 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) { 3002 snprintf(mode->info, sizeof(mode->info), "%s", 3003 bnxt_tx_burst_info[i].info); 3004 return 0; 3005 } 3006 } 3007 3008 return -EINVAL; 3009 } 3010 3011 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 3012 { 3013 uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU; 3014 struct bnxt *bp = eth_dev->data->dev_private; 3015 uint32_t new_pkt_size; 3016 uint32_t rc; 3017 uint32_t i; 3018 3019 rc = is_bnxt_in_error(bp); 3020 if (rc) 3021 return rc; 3022 3023 /* Exit if receive queues are not configured yet */ 3024 if (!eth_dev->data->nb_rx_queues) 3025 return rc; 3026 3027 new_pkt_size = new_mtu + overhead; 3028 3029 /* 3030 * Disallow any MTU change that would require scattered receive support 3031 * if it is not already enabled. 3032 */ 3033 if (eth_dev->data->dev_started && 3034 !eth_dev->data->scattered_rx && 3035 (new_pkt_size > 3036 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 3037 PMD_DRV_LOG(ERR, 3038 "MTU change would require scattered rx support. "); 3039 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 3040 return -EINVAL; 3041 } 3042 3043 if (new_mtu > RTE_ETHER_MTU) 3044 bp->flags |= BNXT_FLAG_JUMBO; 3045 else 3046 bp->flags &= ~BNXT_FLAG_JUMBO; 3047 3048 /* Is there a change in mtu setting? */ 3049 if (eth_dev->data->mtu == new_mtu) 3050 return rc; 3051 3052 for (i = 0; i < bp->nr_vnics; i++) { 3053 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3054 uint16_t size = 0; 3055 3056 vnic->mru = BNXT_VNIC_MRU(new_mtu); 3057 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 3058 if (rc) 3059 break; 3060 3061 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 3062 size -= RTE_PKTMBUF_HEADROOM; 3063 3064 if (size < new_mtu) { 3065 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 3066 if (rc) 3067 return rc; 3068 } 3069 } 3070 3071 if (bnxt_hwrm_config_host_mtu(bp)) 3072 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n"); 3073 3074 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 3075 3076 return rc; 3077 } 3078 3079 static int 3080 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 3081 { 3082 struct bnxt *bp = dev->data->dev_private; 3083 uint16_t vlan = bp->vlan; 3084 int rc; 3085 3086 rc = is_bnxt_in_error(bp); 3087 if (rc) 3088 return rc; 3089 3090 if (!BNXT_SINGLE_PF(bp)) { 3091 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n"); 3092 return -ENOTSUP; 3093 } 3094 bp->vlan = on ? pvid : 0; 3095 3096 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 3097 if (rc) 3098 bp->vlan = vlan; 3099 return rc; 3100 } 3101 3102 static int 3103 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 3104 { 3105 struct bnxt *bp = dev->data->dev_private; 3106 int rc; 3107 3108 rc = is_bnxt_in_error(bp); 3109 if (rc) 3110 return rc; 3111 3112 return bnxt_hwrm_port_led_cfg(bp, true); 3113 } 3114 3115 static int 3116 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 3117 { 3118 struct bnxt *bp = dev->data->dev_private; 3119 int rc; 3120 3121 rc = is_bnxt_in_error(bp); 3122 if (rc) 3123 return rc; 3124 3125 return bnxt_hwrm_port_led_cfg(bp, false); 3126 } 3127 3128 static uint32_t 3129 bnxt_rx_queue_count_op(void *rx_queue) 3130 { 3131 struct bnxt *bp; 3132 struct bnxt_cp_ring_info *cpr; 3133 uint32_t desc = 0, raw_cons, cp_ring_size; 3134 struct bnxt_rx_queue *rxq; 3135 struct rx_pkt_cmpl *rxcmp; 3136 int rc; 3137 3138 rxq = rx_queue; 3139 bp = rxq->bp; 3140 3141 rc = is_bnxt_in_error(bp); 3142 if (rc) 3143 return rc; 3144 3145 cpr = rxq->cp_ring; 3146 raw_cons = cpr->cp_raw_cons; 3147 cp_ring_size = cpr->cp_ring_struct->ring_size; 3148 3149 while (1) { 3150 uint32_t agg_cnt, cons, cmpl_type; 3151 3152 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3153 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3154 3155 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size)) 3156 break; 3157 3158 cmpl_type = CMP_TYPE(rxcmp); 3159 3160 switch (cmpl_type) { 3161 case CMPL_BASE_TYPE_RX_L2: 3162 case CMPL_BASE_TYPE_RX_L2_V2: 3163 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3164 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3165 desc++; 3166 break; 3167 3168 case CMPL_BASE_TYPE_RX_TPA_END: 3169 if (BNXT_CHIP_P5(rxq->bp)) { 3170 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3171 3172 p5_tpa_end = (void *)rxcmp; 3173 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3174 } else { 3175 struct rx_tpa_end_cmpl *tpa_end; 3176 3177 tpa_end = (void *)rxcmp; 3178 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3179 } 3180 3181 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3182 desc++; 3183 break; 3184 3185 default: 3186 raw_cons += CMP_LEN(cmpl_type); 3187 } 3188 } 3189 3190 return desc; 3191 } 3192 3193 static int 3194 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 3195 { 3196 struct bnxt_rx_queue *rxq = rx_queue; 3197 struct bnxt_cp_ring_info *cpr; 3198 struct bnxt_rx_ring_info *rxr; 3199 uint32_t desc, raw_cons, cp_ring_size; 3200 struct bnxt *bp = rxq->bp; 3201 struct rx_pkt_cmpl *rxcmp; 3202 int rc; 3203 3204 rc = is_bnxt_in_error(bp); 3205 if (rc) 3206 return rc; 3207 3208 if (offset >= rxq->nb_rx_desc) 3209 return -EINVAL; 3210 3211 rxr = rxq->rx_ring; 3212 cpr = rxq->cp_ring; 3213 cp_ring_size = cpr->cp_ring_struct->ring_size; 3214 3215 /* 3216 * For the vector receive case, the completion at the requested 3217 * offset can be indexed directly. 3218 */ 3219 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 3220 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) { 3221 struct rx_pkt_cmpl *rxcmp; 3222 uint32_t cons; 3223 3224 /* Check status of completion descriptor. */ 3225 raw_cons = cpr->cp_raw_cons + 3226 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2); 3227 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3228 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3229 3230 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size)) 3231 return RTE_ETH_RX_DESC_DONE; 3232 3233 /* Check whether rx desc has an mbuf attached. */ 3234 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2); 3235 if (cons >= rxq->rxrearm_start && 3236 cons < rxq->rxrearm_start + rxq->rxrearm_nb) { 3237 return RTE_ETH_RX_DESC_UNAVAIL; 3238 } 3239 3240 return RTE_ETH_RX_DESC_AVAIL; 3241 } 3242 #endif 3243 3244 /* 3245 * For the non-vector receive case, scan the completion ring to 3246 * locate the completion descriptor for the requested offset. 3247 */ 3248 raw_cons = cpr->cp_raw_cons; 3249 desc = 0; 3250 while (1) { 3251 uint32_t agg_cnt, cons, cmpl_type; 3252 3253 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3254 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3255 3256 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size)) 3257 break; 3258 3259 cmpl_type = CMP_TYPE(rxcmp); 3260 3261 switch (cmpl_type) { 3262 case CMPL_BASE_TYPE_RX_L2: 3263 case CMPL_BASE_TYPE_RX_L2_V2: 3264 if (desc == offset) { 3265 cons = rxcmp->opaque; 3266 if (rxr->rx_buf_ring[cons]) 3267 return RTE_ETH_RX_DESC_DONE; 3268 else 3269 return RTE_ETH_RX_DESC_UNAVAIL; 3270 } 3271 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3272 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3273 desc++; 3274 break; 3275 3276 case CMPL_BASE_TYPE_RX_TPA_END: 3277 if (desc == offset) 3278 return RTE_ETH_RX_DESC_DONE; 3279 3280 if (BNXT_CHIP_P5(rxq->bp)) { 3281 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3282 3283 p5_tpa_end = (void *)rxcmp; 3284 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3285 } else { 3286 struct rx_tpa_end_cmpl *tpa_end; 3287 3288 tpa_end = (void *)rxcmp; 3289 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3290 } 3291 3292 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3293 desc++; 3294 break; 3295 3296 default: 3297 raw_cons += CMP_LEN(cmpl_type); 3298 } 3299 } 3300 3301 return RTE_ETH_RX_DESC_AVAIL; 3302 } 3303 3304 static int 3305 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 3306 { 3307 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 3308 struct bnxt_cp_ring_info *cpr = txq->cp_ring; 3309 uint32_t ring_mask, raw_cons, nb_tx_pkts = 0; 3310 struct cmpl_base *cp_desc_ring; 3311 int rc; 3312 3313 rc = is_bnxt_in_error(txq->bp); 3314 if (rc) 3315 return rc; 3316 3317 if (offset >= txq->nb_tx_desc) 3318 return -EINVAL; 3319 3320 /* Return "desc done" if descriptor is available for use. */ 3321 if (bnxt_tx_bds_in_hw(txq) <= offset) 3322 return RTE_ETH_TX_DESC_DONE; 3323 3324 raw_cons = cpr->cp_raw_cons; 3325 cp_desc_ring = cpr->cp_desc_ring; 3326 ring_mask = cpr->cp_ring_struct->ring_mask; 3327 3328 /* Check to see if hw has posted a completion for the descriptor. */ 3329 while (1) { 3330 struct tx_cmpl *txcmp; 3331 uint32_t cons; 3332 3333 cons = RING_CMPL(ring_mask, raw_cons); 3334 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons]; 3335 3336 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1)) 3337 break; 3338 3339 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2) 3340 nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque); 3341 3342 if (nb_tx_pkts > offset) 3343 return RTE_ETH_TX_DESC_DONE; 3344 3345 raw_cons = NEXT_RAW_CMP(raw_cons); 3346 } 3347 3348 /* Descriptor is pending transmit, not yet completed by hardware. */ 3349 return RTE_ETH_TX_DESC_FULL; 3350 } 3351 3352 int 3353 bnxt_flow_ops_get_op(struct rte_eth_dev *dev, 3354 const struct rte_flow_ops **ops) 3355 { 3356 struct bnxt *bp = dev->data->dev_private; 3357 int ret = 0; 3358 3359 if (!bp) 3360 return -EIO; 3361 3362 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) { 3363 struct bnxt_representor *vfr = dev->data->dev_private; 3364 bp = vfr->parent_dev->data->dev_private; 3365 /* parent is deleted while children are still valid */ 3366 if (!bp) { 3367 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n", 3368 dev->data->port_id); 3369 return -EIO; 3370 } 3371 } 3372 3373 ret = is_bnxt_in_error(bp); 3374 if (ret) 3375 return ret; 3376 3377 /* PMD supports thread-safe flow operations. rte_flow API 3378 * functions can avoid mutex for multi-thread safety. 3379 */ 3380 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 3381 3382 if (BNXT_TRUFLOW_EN(bp)) 3383 *ops = &bnxt_ulp_rte_flow_ops; 3384 else 3385 *ops = &bnxt_flow_ops; 3386 3387 return ret; 3388 } 3389 3390 static const uint32_t * 3391 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3392 { 3393 static const uint32_t ptypes[] = { 3394 RTE_PTYPE_L2_ETHER_VLAN, 3395 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3396 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3397 RTE_PTYPE_L4_ICMP, 3398 RTE_PTYPE_L4_TCP, 3399 RTE_PTYPE_L4_UDP, 3400 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3401 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3402 RTE_PTYPE_INNER_L4_ICMP, 3403 RTE_PTYPE_INNER_L4_TCP, 3404 RTE_PTYPE_INNER_L4_UDP, 3405 RTE_PTYPE_UNKNOWN 3406 }; 3407 3408 if (!dev->rx_pkt_burst) 3409 return NULL; 3410 3411 return ptypes; 3412 } 3413 3414 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3415 int reg_win) 3416 { 3417 uint32_t reg_base = *reg_arr & 0xfffff000; 3418 uint32_t win_off; 3419 int i; 3420 3421 for (i = 0; i < count; i++) { 3422 if ((reg_arr[i] & 0xfffff000) != reg_base) 3423 return -ERANGE; 3424 } 3425 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3426 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3427 return 0; 3428 } 3429 3430 static int bnxt_map_ptp_regs(struct bnxt *bp) 3431 { 3432 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3433 uint32_t *reg_arr; 3434 int rc, i; 3435 3436 reg_arr = ptp->rx_regs; 3437 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3438 if (rc) 3439 return rc; 3440 3441 reg_arr = ptp->tx_regs; 3442 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3443 if (rc) 3444 return rc; 3445 3446 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3447 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3448 3449 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3450 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3451 3452 return 0; 3453 } 3454 3455 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3456 { 3457 rte_write32(0, (uint8_t *)bp->bar0 + 3458 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3459 rte_write32(0, (uint8_t *)bp->bar0 + 3460 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3461 } 3462 3463 static uint64_t bnxt_cc_read(struct bnxt *bp) 3464 { 3465 uint64_t ns; 3466 3467 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3468 BNXT_GRCPF_REG_SYNC_TIME)); 3469 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3470 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3471 return ns; 3472 } 3473 3474 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3475 { 3476 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3477 uint32_t fifo; 3478 3479 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3480 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3481 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3482 return -EAGAIN; 3483 3484 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3485 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3486 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3487 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3488 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3489 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3490 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]); 3491 3492 return 0; 3493 } 3494 3495 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts) 3496 { 3497 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3498 struct bnxt_pf_info *pf = bp->pf; 3499 uint16_t port_id; 3500 int i = 0; 3501 uint32_t fifo; 3502 3503 if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5)) 3504 return -EINVAL; 3505 3506 port_id = pf->port_id; 3507 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3508 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3509 while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) { 3510 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3511 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3512 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3513 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3514 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3515 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3516 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3517 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3518 i++; 3519 } 3520 3521 if (i >= BNXT_PTP_RX_PND_CNT) 3522 return -EBUSY; 3523 3524 return 0; 3525 } 3526 3527 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3528 { 3529 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3530 struct bnxt_pf_info *pf = bp->pf; 3531 uint16_t port_id; 3532 uint32_t fifo; 3533 3534 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3535 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3536 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3537 return -EAGAIN; 3538 3539 port_id = pf->port_id; 3540 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3541 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3542 3543 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3544 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3545 if (fifo & BNXT_PTP_RX_FIFO_PENDING) 3546 return bnxt_clr_rx_ts(bp, ts); 3547 3548 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3549 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3550 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3551 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3552 3553 return 0; 3554 } 3555 3556 static int 3557 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3558 { 3559 uint64_t ns; 3560 struct bnxt *bp = dev->data->dev_private; 3561 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3562 3563 if (!ptp) 3564 return -ENOTSUP; 3565 3566 ns = rte_timespec_to_ns(ts); 3567 /* Set the timecounters to a new value. */ 3568 ptp->tc.nsec = ns; 3569 ptp->tx_tstamp_tc.nsec = ns; 3570 ptp->rx_tstamp_tc.nsec = ns; 3571 3572 return 0; 3573 } 3574 3575 static int 3576 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3577 { 3578 struct bnxt *bp = dev->data->dev_private; 3579 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3580 uint64_t ns, systime_cycles = 0; 3581 int rc = 0; 3582 3583 if (!ptp) 3584 return -ENOTSUP; 3585 3586 if (BNXT_CHIP_P5(bp)) 3587 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3588 &systime_cycles); 3589 else 3590 systime_cycles = bnxt_cc_read(bp); 3591 3592 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3593 *ts = rte_ns_to_timespec(ns); 3594 3595 return rc; 3596 } 3597 static int 3598 bnxt_timesync_enable(struct rte_eth_dev *dev) 3599 { 3600 struct bnxt *bp = dev->data->dev_private; 3601 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3602 uint32_t shift = 0; 3603 int rc; 3604 3605 if (!ptp) 3606 return -ENOTSUP; 3607 3608 ptp->rx_filter = 1; 3609 ptp->tx_tstamp_en = 1; 3610 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3611 3612 rc = bnxt_hwrm_ptp_cfg(bp); 3613 if (rc) 3614 return rc; 3615 3616 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3617 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3618 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3619 3620 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3621 ptp->tc.cc_shift = shift; 3622 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3623 3624 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3625 ptp->rx_tstamp_tc.cc_shift = shift; 3626 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3627 3628 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3629 ptp->tx_tstamp_tc.cc_shift = shift; 3630 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3631 3632 if (!BNXT_CHIP_P5(bp)) 3633 bnxt_map_ptp_regs(bp); 3634 else 3635 rc = bnxt_ptp_start(bp); 3636 3637 return rc; 3638 } 3639 3640 static int 3641 bnxt_timesync_disable(struct rte_eth_dev *dev) 3642 { 3643 struct bnxt *bp = dev->data->dev_private; 3644 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3645 3646 if (!ptp) 3647 return -ENOTSUP; 3648 3649 ptp->rx_filter = 0; 3650 ptp->tx_tstamp_en = 0; 3651 ptp->rxctl = 0; 3652 3653 bnxt_hwrm_ptp_cfg(bp); 3654 3655 if (!BNXT_CHIP_P5(bp)) 3656 bnxt_unmap_ptp_regs(bp); 3657 else 3658 bnxt_ptp_stop(bp); 3659 3660 return 0; 3661 } 3662 3663 static int 3664 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3665 struct timespec *timestamp, 3666 uint32_t flags __rte_unused) 3667 { 3668 struct bnxt *bp = dev->data->dev_private; 3669 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3670 uint64_t rx_tstamp_cycles = 0; 3671 uint64_t ns; 3672 3673 if (!ptp) 3674 return -ENOTSUP; 3675 3676 if (BNXT_CHIP_P5(bp)) 3677 rx_tstamp_cycles = ptp->rx_timestamp; 3678 else 3679 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3680 3681 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3682 *timestamp = rte_ns_to_timespec(ns); 3683 return 0; 3684 } 3685 3686 static int 3687 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3688 struct timespec *timestamp) 3689 { 3690 struct bnxt *bp = dev->data->dev_private; 3691 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3692 uint64_t tx_tstamp_cycles = 0; 3693 uint64_t ns; 3694 int rc = 0; 3695 3696 if (!ptp) 3697 return -ENOTSUP; 3698 3699 if (BNXT_CHIP_P5(bp)) 3700 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3701 &tx_tstamp_cycles); 3702 else 3703 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3704 3705 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3706 *timestamp = rte_ns_to_timespec(ns); 3707 3708 return rc; 3709 } 3710 3711 static int 3712 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3713 { 3714 struct bnxt *bp = dev->data->dev_private; 3715 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3716 3717 if (!ptp) 3718 return -ENOTSUP; 3719 3720 ptp->tc.nsec += delta; 3721 ptp->tx_tstamp_tc.nsec += delta; 3722 ptp->rx_tstamp_tc.nsec += delta; 3723 3724 return 0; 3725 } 3726 3727 static int 3728 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3729 { 3730 struct bnxt *bp = dev->data->dev_private; 3731 int rc; 3732 uint32_t dir_entries; 3733 uint32_t entry_length; 3734 3735 rc = is_bnxt_in_error(bp); 3736 if (rc) 3737 return rc; 3738 3739 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 3740 bp->pdev->addr.domain, bp->pdev->addr.bus, 3741 bp->pdev->addr.devid, bp->pdev->addr.function); 3742 3743 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3744 if (rc != 0) 3745 return rc; 3746 3747 return dir_entries * entry_length; 3748 } 3749 3750 static int 3751 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3752 struct rte_dev_eeprom_info *in_eeprom) 3753 { 3754 struct bnxt *bp = dev->data->dev_private; 3755 uint32_t index; 3756 uint32_t offset; 3757 int rc; 3758 3759 rc = is_bnxt_in_error(bp); 3760 if (rc) 3761 return rc; 3762 3763 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3764 bp->pdev->addr.domain, bp->pdev->addr.bus, 3765 bp->pdev->addr.devid, bp->pdev->addr.function, 3766 in_eeprom->offset, in_eeprom->length); 3767 3768 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3769 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3770 in_eeprom->data); 3771 3772 index = in_eeprom->offset >> 24; 3773 offset = in_eeprom->offset & 0xffffff; 3774 3775 if (index != 0) 3776 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3777 in_eeprom->length, in_eeprom->data); 3778 3779 return 0; 3780 } 3781 3782 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3783 { 3784 switch (dir_type) { 3785 case BNX_DIR_TYPE_CHIMP_PATCH: 3786 case BNX_DIR_TYPE_BOOTCODE: 3787 case BNX_DIR_TYPE_BOOTCODE_2: 3788 case BNX_DIR_TYPE_APE_FW: 3789 case BNX_DIR_TYPE_APE_PATCH: 3790 case BNX_DIR_TYPE_KONG_FW: 3791 case BNX_DIR_TYPE_KONG_PATCH: 3792 case BNX_DIR_TYPE_BONO_FW: 3793 case BNX_DIR_TYPE_BONO_PATCH: 3794 /* FALLTHROUGH */ 3795 return true; 3796 } 3797 3798 return false; 3799 } 3800 3801 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3802 { 3803 switch (dir_type) { 3804 case BNX_DIR_TYPE_AVS: 3805 case BNX_DIR_TYPE_EXP_ROM_MBA: 3806 case BNX_DIR_TYPE_PCIE: 3807 case BNX_DIR_TYPE_TSCF_UCODE: 3808 case BNX_DIR_TYPE_EXT_PHY: 3809 case BNX_DIR_TYPE_CCM: 3810 case BNX_DIR_TYPE_ISCSI_BOOT: 3811 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3812 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3813 /* FALLTHROUGH */ 3814 return true; 3815 } 3816 3817 return false; 3818 } 3819 3820 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3821 { 3822 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3823 bnxt_dir_type_is_other_exec_format(dir_type); 3824 } 3825 3826 static int 3827 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3828 struct rte_dev_eeprom_info *in_eeprom) 3829 { 3830 struct bnxt *bp = dev->data->dev_private; 3831 uint8_t index, dir_op; 3832 uint16_t type, ext, ordinal, attr; 3833 int rc; 3834 3835 rc = is_bnxt_in_error(bp); 3836 if (rc) 3837 return rc; 3838 3839 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3840 bp->pdev->addr.domain, bp->pdev->addr.bus, 3841 bp->pdev->addr.devid, bp->pdev->addr.function, 3842 in_eeprom->offset, in_eeprom->length); 3843 3844 if (!BNXT_PF(bp)) { 3845 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3846 return -EINVAL; 3847 } 3848 3849 type = in_eeprom->magic >> 16; 3850 3851 if (type == 0xffff) { /* special value for directory operations */ 3852 index = in_eeprom->magic & 0xff; 3853 dir_op = in_eeprom->magic >> 8; 3854 if (index == 0) 3855 return -EINVAL; 3856 switch (dir_op) { 3857 case 0x0e: /* erase */ 3858 if (in_eeprom->offset != ~in_eeprom->magic) 3859 return -EINVAL; 3860 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3861 default: 3862 return -EINVAL; 3863 } 3864 } 3865 3866 /* Create or re-write an NVM item: */ 3867 if (bnxt_dir_type_is_executable(type) == true) 3868 return -EOPNOTSUPP; 3869 ext = in_eeprom->magic & 0xffff; 3870 ordinal = in_eeprom->offset >> 16; 3871 attr = in_eeprom->offset & 0xffff; 3872 3873 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3874 in_eeprom->data, in_eeprom->length); 3875 } 3876 3877 static int bnxt_get_module_info(struct rte_eth_dev *dev, 3878 struct rte_eth_dev_module_info *modinfo) 3879 { 3880 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1]; 3881 struct bnxt *bp = dev->data->dev_private; 3882 int rc; 3883 3884 /* No point in going further if phy status indicates 3885 * module is not inserted or if it is powered down or 3886 * if it is of type 10GBase-T 3887 */ 3888 if (bp->link_info->module_status > 3889 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) { 3890 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n", 3891 dev->data->port_id); 3892 return -ENOTSUP; 3893 } 3894 3895 /* This feature is not supported in older firmware versions */ 3896 if (bp->hwrm_spec_code < 0x10202) { 3897 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n", 3898 dev->data->port_id); 3899 return -ENOTSUP; 3900 } 3901 3902 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3903 SFF_DIAG_SUPPORT_OFFSET + 1, 3904 module_info); 3905 3906 if (rc) 3907 return rc; 3908 3909 switch (module_info[0]) { 3910 case SFF_MODULE_ID_SFP: 3911 modinfo->type = RTE_ETH_MODULE_SFF_8472; 3912 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 3913 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0) 3914 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN; 3915 break; 3916 case SFF_MODULE_ID_QSFP: 3917 case SFF_MODULE_ID_QSFP_PLUS: 3918 modinfo->type = RTE_ETH_MODULE_SFF_8436; 3919 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN; 3920 break; 3921 case SFF_MODULE_ID_QSFP28: 3922 modinfo->type = RTE_ETH_MODULE_SFF_8636; 3923 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 3924 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) 3925 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN; 3926 break; 3927 default: 3928 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id); 3929 return -ENOTSUP; 3930 } 3931 3932 PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n", 3933 dev->data->port_id, modinfo->type, modinfo->eeprom_len); 3934 3935 return 0; 3936 } 3937 3938 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev, 3939 struct rte_dev_eeprom_info *info) 3940 { 3941 uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 }; 3942 uint32_t offset = info->offset, length = info->length; 3943 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1]; 3944 struct bnxt *bp = dev->data->dev_private; 3945 uint8_t *data = info->data; 3946 uint8_t page = offset >> 7; 3947 uint8_t max_pages = 2; 3948 uint8_t opt_pages; 3949 int rc; 3950 3951 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3952 SFF_DIAG_SUPPORT_OFFSET + 1, 3953 module_info); 3954 if (rc) 3955 return rc; 3956 3957 switch (module_info[0]) { 3958 case SFF_MODULE_ID_SFP: 3959 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0; 3960 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) { 3961 pg_addr[2] = I2C_DEV_ADDR_A2; 3962 pg_addr[3] = I2C_DEV_ADDR_A2; 3963 max_pages = 4; 3964 } 3965 break; 3966 case SFF_MODULE_ID_QSFP28: 3967 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 3968 SFF8636_OPT_PAGES_OFFSET, 3969 1, &opt_pages); 3970 if (rc) 3971 return rc; 3972 3973 if (opt_pages & SFF8636_PAGE1_MASK) { 3974 pg_addr[2] = I2C_DEV_ADDR_A0; 3975 max_pages = 3; 3976 } 3977 if (opt_pages & SFF8636_PAGE2_MASK) { 3978 pg_addr[3] = I2C_DEV_ADDR_A0; 3979 max_pages = 4; 3980 } 3981 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) { 3982 pg_addr[4] = I2C_DEV_ADDR_A0; 3983 max_pages = 5; 3984 } 3985 break; 3986 default: 3987 break; 3988 } 3989 3990 memset(data, 0, length); 3991 3992 offset &= 0xff; 3993 while (length && page < max_pages) { 3994 uint8_t raw_page = page ? page - 1 : 0; 3995 uint16_t chunk; 3996 3997 if (pg_addr[page] == I2C_DEV_ADDR_A2) 3998 raw_page = 0; 3999 else if (page) 4000 offset |= 0x80; 4001 chunk = RTE_MIN(length, 256 - offset); 4002 4003 if (pg_addr[page]) { 4004 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page], 4005 raw_page, offset, 4006 chunk, data); 4007 if (rc) 4008 return rc; 4009 } 4010 4011 data += chunk; 4012 length -= chunk; 4013 offset = 0; 4014 page += 1 + (chunk > 128); 4015 } 4016 4017 return length ? -EINVAL : 0; 4018 } 4019 4020 /* 4021 * Initialization 4022 */ 4023 4024 static const struct eth_dev_ops bnxt_dev_ops = { 4025 .dev_infos_get = bnxt_dev_info_get_op, 4026 .dev_close = bnxt_dev_close_op, 4027 .dev_configure = bnxt_dev_configure_op, 4028 .dev_start = bnxt_dev_start_op, 4029 .dev_stop = bnxt_dev_stop_op, 4030 .dev_set_link_up = bnxt_dev_set_link_up_op, 4031 .dev_set_link_down = bnxt_dev_set_link_down_op, 4032 .stats_get = bnxt_stats_get_op, 4033 .stats_reset = bnxt_stats_reset_op, 4034 .rx_queue_setup = bnxt_rx_queue_setup_op, 4035 .rx_queue_release = bnxt_rx_queue_release_op, 4036 .tx_queue_setup = bnxt_tx_queue_setup_op, 4037 .tx_queue_release = bnxt_tx_queue_release_op, 4038 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 4039 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 4040 .reta_update = bnxt_reta_update_op, 4041 .reta_query = bnxt_reta_query_op, 4042 .rss_hash_update = bnxt_rss_hash_update_op, 4043 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 4044 .link_update = bnxt_link_update_op, 4045 .promiscuous_enable = bnxt_promiscuous_enable_op, 4046 .promiscuous_disable = bnxt_promiscuous_disable_op, 4047 .allmulticast_enable = bnxt_allmulticast_enable_op, 4048 .allmulticast_disable = bnxt_allmulticast_disable_op, 4049 .mac_addr_add = bnxt_mac_addr_add_op, 4050 .mac_addr_remove = bnxt_mac_addr_remove_op, 4051 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 4052 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 4053 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 4054 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 4055 .vlan_filter_set = bnxt_vlan_filter_set_op, 4056 .vlan_offload_set = bnxt_vlan_offload_set_op, 4057 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 4058 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 4059 .mtu_set = bnxt_mtu_set_op, 4060 .mac_addr_set = bnxt_set_default_mac_addr_op, 4061 .xstats_get = bnxt_dev_xstats_get_op, 4062 .xstats_get_names = bnxt_dev_xstats_get_names_op, 4063 .xstats_reset = bnxt_dev_xstats_reset_op, 4064 .fw_version_get = bnxt_fw_version_get, 4065 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 4066 .rxq_info_get = bnxt_rxq_info_get_op, 4067 .txq_info_get = bnxt_txq_info_get_op, 4068 .rx_burst_mode_get = bnxt_rx_burst_mode_get, 4069 .tx_burst_mode_get = bnxt_tx_burst_mode_get, 4070 .dev_led_on = bnxt_dev_led_on_op, 4071 .dev_led_off = bnxt_dev_led_off_op, 4072 .rx_queue_start = bnxt_rx_queue_start, 4073 .rx_queue_stop = bnxt_rx_queue_stop, 4074 .tx_queue_start = bnxt_tx_queue_start, 4075 .tx_queue_stop = bnxt_tx_queue_stop, 4076 .flow_ops_get = bnxt_flow_ops_get_op, 4077 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 4078 .get_eeprom_length = bnxt_get_eeprom_length_op, 4079 .get_eeprom = bnxt_get_eeprom_op, 4080 .set_eeprom = bnxt_set_eeprom_op, 4081 .get_module_info = bnxt_get_module_info, 4082 .get_module_eeprom = bnxt_get_module_eeprom, 4083 .timesync_enable = bnxt_timesync_enable, 4084 .timesync_disable = bnxt_timesync_disable, 4085 .timesync_read_time = bnxt_timesync_read_time, 4086 .timesync_write_time = bnxt_timesync_write_time, 4087 .timesync_adjust_time = bnxt_timesync_adjust_time, 4088 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 4089 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 4090 }; 4091 4092 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 4093 { 4094 uint32_t offset; 4095 4096 /* Only pre-map the reset GRC registers using window 3 */ 4097 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 4098 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 4099 4100 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 4101 4102 return offset; 4103 } 4104 4105 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 4106 { 4107 struct bnxt_error_recovery_info *info = bp->recovery_info; 4108 uint32_t reg_base = 0xffffffff; 4109 int i; 4110 4111 /* Only pre-map the monitoring GRC registers using window 2 */ 4112 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 4113 uint32_t reg = info->status_regs[i]; 4114 4115 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 4116 continue; 4117 4118 if (reg_base == 0xffffffff) 4119 reg_base = reg & 0xfffff000; 4120 if ((reg & 0xfffff000) != reg_base) 4121 return -ERANGE; 4122 4123 /* Use mask 0xffc as the Lower 2 bits indicates 4124 * address space location 4125 */ 4126 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 4127 (reg & 0xffc); 4128 } 4129 4130 if (reg_base == 0xffffffff) 4131 return 0; 4132 4133 rte_write32(reg_base, (uint8_t *)bp->bar0 + 4134 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4135 4136 return 0; 4137 } 4138 4139 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 4140 { 4141 struct bnxt_error_recovery_info *info = bp->recovery_info; 4142 uint32_t delay = info->delay_after_reset[index]; 4143 uint32_t val = info->reset_reg_val[index]; 4144 uint32_t reg = info->reset_reg[index]; 4145 uint32_t type, offset; 4146 int ret; 4147 4148 type = BNXT_FW_STATUS_REG_TYPE(reg); 4149 offset = BNXT_FW_STATUS_REG_OFF(reg); 4150 4151 switch (type) { 4152 case BNXT_FW_STATUS_REG_TYPE_CFG: 4153 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 4154 if (ret < 0) { 4155 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x", 4156 val, offset); 4157 return; 4158 } 4159 break; 4160 case BNXT_FW_STATUS_REG_TYPE_GRC: 4161 offset = bnxt_map_reset_regs(bp, offset); 4162 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4163 break; 4164 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4165 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4166 break; 4167 } 4168 /* wait on a specific interval of time until core reset is complete */ 4169 if (delay) 4170 rte_delay_ms(delay); 4171 } 4172 4173 static void bnxt_dev_cleanup(struct bnxt *bp) 4174 { 4175 bp->eth_dev->data->dev_link.link_status = 0; 4176 bp->link_info->link_up = 0; 4177 if (bp->eth_dev->data->dev_started) 4178 bnxt_dev_stop(bp->eth_dev); 4179 4180 bnxt_uninit_resources(bp, true); 4181 } 4182 4183 static int 4184 bnxt_check_fw_reset_done(struct bnxt *bp) 4185 { 4186 int timeout = bp->fw_reset_max_msecs; 4187 uint16_t val = 0; 4188 int rc; 4189 4190 do { 4191 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 4192 if (rc < 0) { 4193 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 4194 return rc; 4195 } 4196 if (val != 0xffff) 4197 break; 4198 rte_delay_ms(1); 4199 } while (timeout--); 4200 4201 if (val == 0xffff) { 4202 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); 4203 return -1; 4204 } 4205 4206 return 0; 4207 } 4208 4209 static int bnxt_restore_vlan_filters(struct bnxt *bp) 4210 { 4211 struct rte_eth_dev *dev = bp->eth_dev; 4212 struct rte_vlan_filter_conf *vfc; 4213 int vidx, vbit, rc; 4214 uint16_t vlan_id; 4215 4216 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 4217 vfc = &dev->data->vlan_filter_conf; 4218 vidx = vlan_id / 64; 4219 vbit = vlan_id % 64; 4220 4221 /* Each bit corresponds to a VLAN id */ 4222 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 4223 rc = bnxt_add_vlan_filter(bp, vlan_id); 4224 if (rc) 4225 return rc; 4226 } 4227 } 4228 4229 return 0; 4230 } 4231 4232 static int bnxt_restore_mac_filters(struct bnxt *bp) 4233 { 4234 struct rte_eth_dev *dev = bp->eth_dev; 4235 struct rte_eth_dev_info dev_info; 4236 struct rte_ether_addr *addr; 4237 uint64_t pool_mask; 4238 uint32_t pool = 0; 4239 uint32_t i; 4240 int rc; 4241 4242 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4243 return 0; 4244 4245 rc = bnxt_dev_info_get_op(dev, &dev_info); 4246 if (rc) 4247 return rc; 4248 4249 /* replay MAC address configuration */ 4250 for (i = 1; i < dev_info.max_mac_addrs; i++) { 4251 addr = &dev->data->mac_addrs[i]; 4252 4253 /* skip zero address */ 4254 if (rte_is_zero_ether_addr(addr)) 4255 continue; 4256 4257 pool = 0; 4258 pool_mask = dev->data->mac_pool_sel[i]; 4259 4260 do { 4261 if (pool_mask & 1ULL) { 4262 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 4263 if (rc) 4264 return rc; 4265 } 4266 pool_mask >>= 1; 4267 pool++; 4268 } while (pool_mask); 4269 } 4270 4271 return 0; 4272 } 4273 4274 static int bnxt_restore_filters(struct bnxt *bp) 4275 { 4276 struct rte_eth_dev *dev = bp->eth_dev; 4277 int ret = 0; 4278 4279 if (dev->data->all_multicast) { 4280 ret = bnxt_allmulticast_enable_op(dev); 4281 if (ret) 4282 return ret; 4283 } 4284 if (dev->data->promiscuous) { 4285 ret = bnxt_promiscuous_enable_op(dev); 4286 if (ret) 4287 return ret; 4288 } 4289 4290 ret = bnxt_restore_mac_filters(bp); 4291 if (ret) 4292 return ret; 4293 4294 ret = bnxt_restore_vlan_filters(bp); 4295 /* TODO restore other filters as well */ 4296 return ret; 4297 } 4298 4299 static int bnxt_check_fw_ready(struct bnxt *bp) 4300 { 4301 int timeout = bp->fw_reset_max_msecs; 4302 int rc = 0; 4303 4304 do { 4305 rc = bnxt_hwrm_poll_ver_get(bp); 4306 if (rc == 0) 4307 break; 4308 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 4309 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 4310 } while (rc && timeout > 0); 4311 4312 if (rc) 4313 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 4314 4315 return rc; 4316 } 4317 4318 static void bnxt_dev_recover(void *arg) 4319 { 4320 struct bnxt *bp = arg; 4321 int rc = 0; 4322 4323 pthread_mutex_lock(&bp->err_recovery_lock); 4324 4325 if (!bp->fw_reset_min_msecs) { 4326 rc = bnxt_check_fw_reset_done(bp); 4327 if (rc) 4328 goto err; 4329 } 4330 4331 /* Clear Error flag so that device re-init should happen */ 4332 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 4333 4334 rc = bnxt_check_fw_ready(bp); 4335 if (rc) 4336 goto err; 4337 4338 rc = bnxt_init_resources(bp, true); 4339 if (rc) { 4340 PMD_DRV_LOG(ERR, 4341 "Failed to initialize resources after reset\n"); 4342 goto err; 4343 } 4344 /* clear reset flag as the device is initialized now */ 4345 bp->flags &= ~BNXT_FLAG_FW_RESET; 4346 4347 rc = bnxt_dev_start_op(bp->eth_dev); 4348 if (rc) { 4349 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 4350 goto err_start; 4351 } 4352 4353 rc = bnxt_restore_filters(bp); 4354 if (rc) 4355 goto err_start; 4356 4357 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 4358 pthread_mutex_unlock(&bp->err_recovery_lock); 4359 4360 return; 4361 err_start: 4362 bnxt_dev_stop(bp->eth_dev); 4363 err: 4364 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4365 bnxt_uninit_resources(bp, false); 4366 if (bp->eth_dev->data->dev_conf.intr_conf.rmv) 4367 rte_eth_dev_callback_process(bp->eth_dev, 4368 RTE_ETH_EVENT_INTR_RMV, 4369 NULL); 4370 pthread_mutex_unlock(&bp->err_recovery_lock); 4371 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 4372 } 4373 4374 void bnxt_dev_reset_and_resume(void *arg) 4375 { 4376 struct bnxt *bp = arg; 4377 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; 4378 uint16_t val = 0; 4379 int rc; 4380 4381 bnxt_dev_cleanup(bp); 4382 4383 bnxt_wait_for_device_shutdown(bp); 4384 4385 /* During some fatal firmware error conditions, the PCI config space 4386 * register 0x2e which normally contains the subsystem ID will become 4387 * 0xffff. This register will revert back to the normal value after 4388 * the chip has completed core reset. If we detect this condition, 4389 * we can poll this config register immediately for the value to revert. 4390 */ 4391 if (bp->flags & BNXT_FLAG_FATAL_ERROR) { 4392 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 4393 if (rc < 0) { 4394 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 4395 return; 4396 } 4397 if (val == 0xffff) { 4398 bp->fw_reset_min_msecs = 0; 4399 us = 1; 4400 } 4401 } 4402 4403 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); 4404 if (rc) 4405 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 4406 } 4407 4408 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 4409 { 4410 struct bnxt_error_recovery_info *info = bp->recovery_info; 4411 uint32_t reg = info->status_regs[index]; 4412 uint32_t type, offset, val = 0; 4413 int ret = 0; 4414 4415 type = BNXT_FW_STATUS_REG_TYPE(reg); 4416 offset = BNXT_FW_STATUS_REG_OFF(reg); 4417 4418 switch (type) { 4419 case BNXT_FW_STATUS_REG_TYPE_CFG: 4420 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 4421 if (ret < 0) 4422 PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x", 4423 offset); 4424 break; 4425 case BNXT_FW_STATUS_REG_TYPE_GRC: 4426 offset = info->mapped_status_regs[index]; 4427 /* FALLTHROUGH */ 4428 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4429 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4430 offset)); 4431 break; 4432 } 4433 4434 return val; 4435 } 4436 4437 static int bnxt_fw_reset_all(struct bnxt *bp) 4438 { 4439 struct bnxt_error_recovery_info *info = bp->recovery_info; 4440 uint32_t i; 4441 int rc = 0; 4442 4443 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4444 /* Reset through primary function driver */ 4445 for (i = 0; i < info->reg_array_cnt; i++) 4446 bnxt_write_fw_reset_reg(bp, i); 4447 /* Wait for time specified by FW after triggering reset */ 4448 rte_delay_ms(info->primary_func_wait_period_after_reset); 4449 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 4450 /* Reset with the help of Kong processor */ 4451 rc = bnxt_hwrm_fw_reset(bp); 4452 if (rc) 4453 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 4454 } 4455 4456 return rc; 4457 } 4458 4459 static void bnxt_fw_reset_cb(void *arg) 4460 { 4461 struct bnxt *bp = arg; 4462 struct bnxt_error_recovery_info *info = bp->recovery_info; 4463 int rc = 0; 4464 4465 /* Only Primary function can do FW reset */ 4466 if (bnxt_is_primary_func(bp) && 4467 bnxt_is_recovery_enabled(bp)) { 4468 rc = bnxt_fw_reset_all(bp); 4469 if (rc) { 4470 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 4471 return; 4472 } 4473 } 4474 4475 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 4476 * EXCEPTION_FATAL_ASYNC event to all the functions 4477 * (including MASTER FUNC). After receiving this Async, all the active 4478 * drivers should treat this case as FW initiated recovery 4479 */ 4480 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4481 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 4482 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 4483 4484 /* To recover from error */ 4485 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 4486 (void *)bp); 4487 } 4488 } 4489 4490 /* Driver should poll FW heartbeat, reset_counter with the frequency 4491 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 4492 * When the driver detects heartbeat stop or change in reset_counter, 4493 * it has to trigger a reset to recover from the error condition. 4494 * A “primary function” is the function who will have the privilege to 4495 * initiate the chimp reset. The primary function will be elected by the 4496 * firmware and will be notified through async message. 4497 */ 4498 static void bnxt_check_fw_health(void *arg) 4499 { 4500 struct bnxt *bp = arg; 4501 struct bnxt_error_recovery_info *info = bp->recovery_info; 4502 uint32_t val = 0, wait_msec; 4503 4504 if (!info || !bnxt_is_recovery_enabled(bp) || 4505 is_bnxt_in_error(bp)) 4506 return; 4507 4508 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4509 if (val == info->last_heart_beat) 4510 goto reset; 4511 4512 info->last_heart_beat = val; 4513 4514 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4515 if (val != info->last_reset_counter) 4516 goto reset; 4517 4518 info->last_reset_counter = val; 4519 4520 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4521 bnxt_check_fw_health, (void *)bp); 4522 4523 return; 4524 reset: 4525 /* Stop DMA to/from device */ 4526 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4527 bp->flags |= BNXT_FLAG_FW_RESET; 4528 4529 bnxt_stop_rxtx(bp); 4530 4531 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4532 4533 if (bnxt_is_primary_func(bp)) 4534 wait_msec = info->primary_func_wait_period; 4535 else 4536 wait_msec = info->normal_func_wait_period; 4537 4538 rte_eal_alarm_set(US_PER_MS * wait_msec, 4539 bnxt_fw_reset_cb, (void *)bp); 4540 } 4541 4542 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4543 { 4544 uint32_t polling_freq; 4545 4546 pthread_mutex_lock(&bp->health_check_lock); 4547 4548 if (!bnxt_is_recovery_enabled(bp)) 4549 goto done; 4550 4551 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4552 goto done; 4553 4554 polling_freq = bp->recovery_info->driver_polling_freq; 4555 4556 rte_eal_alarm_set(US_PER_MS * polling_freq, 4557 bnxt_check_fw_health, (void *)bp); 4558 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4559 4560 done: 4561 pthread_mutex_unlock(&bp->health_check_lock); 4562 } 4563 4564 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4565 { 4566 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4567 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4568 } 4569 4570 static bool bnxt_vf_pciid(uint16_t device_id) 4571 { 4572 switch (device_id) { 4573 case BROADCOM_DEV_ID_57304_VF: 4574 case BROADCOM_DEV_ID_57406_VF: 4575 case BROADCOM_DEV_ID_5731X_VF: 4576 case BROADCOM_DEV_ID_5741X_VF: 4577 case BROADCOM_DEV_ID_57414_VF: 4578 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4579 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4580 case BROADCOM_DEV_ID_58802_VF: 4581 case BROADCOM_DEV_ID_57500_VF1: 4582 case BROADCOM_DEV_ID_57500_VF2: 4583 case BROADCOM_DEV_ID_58818_VF: 4584 /* FALLTHROUGH */ 4585 return true; 4586 default: 4587 return false; 4588 } 4589 } 4590 4591 /* Phase 5 device */ 4592 static bool bnxt_p5_device(uint16_t device_id) 4593 { 4594 switch (device_id) { 4595 case BROADCOM_DEV_ID_57508: 4596 case BROADCOM_DEV_ID_57504: 4597 case BROADCOM_DEV_ID_57502: 4598 case BROADCOM_DEV_ID_57508_MF1: 4599 case BROADCOM_DEV_ID_57504_MF1: 4600 case BROADCOM_DEV_ID_57502_MF1: 4601 case BROADCOM_DEV_ID_57508_MF2: 4602 case BROADCOM_DEV_ID_57504_MF2: 4603 case BROADCOM_DEV_ID_57502_MF2: 4604 case BROADCOM_DEV_ID_57500_VF1: 4605 case BROADCOM_DEV_ID_57500_VF2: 4606 case BROADCOM_DEV_ID_58812: 4607 case BROADCOM_DEV_ID_58814: 4608 case BROADCOM_DEV_ID_58818: 4609 case BROADCOM_DEV_ID_58818_VF: 4610 /* FALLTHROUGH */ 4611 return true; 4612 default: 4613 return false; 4614 } 4615 } 4616 4617 bool bnxt_stratus_device(struct bnxt *bp) 4618 { 4619 uint16_t device_id = bp->pdev->id.device_id; 4620 4621 switch (device_id) { 4622 case BROADCOM_DEV_ID_STRATUS_NIC: 4623 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4624 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4625 /* FALLTHROUGH */ 4626 return true; 4627 default: 4628 return false; 4629 } 4630 } 4631 4632 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev) 4633 { 4634 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4635 struct bnxt *bp = eth_dev->data->dev_private; 4636 4637 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4638 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4639 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4640 if (!bp->bar0 || !bp->doorbell_base) { 4641 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4642 return -ENODEV; 4643 } 4644 4645 bp->eth_dev = eth_dev; 4646 bp->pdev = pci_dev; 4647 4648 return 0; 4649 } 4650 4651 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4652 struct bnxt_ctx_pg_info *ctx_pg, 4653 uint32_t mem_size, 4654 const char *suffix, 4655 uint16_t idx) 4656 { 4657 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4658 const struct rte_memzone *mz = NULL; 4659 char mz_name[RTE_MEMZONE_NAMESIZE]; 4660 rte_iova_t mz_phys_addr; 4661 uint64_t valid_bits = 0; 4662 uint32_t sz; 4663 int i; 4664 4665 if (!mem_size) 4666 return 0; 4667 4668 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4669 BNXT_PAGE_SIZE; 4670 rmem->page_size = BNXT_PAGE_SIZE; 4671 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4672 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4673 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4674 4675 valid_bits = PTU_PTE_VALID; 4676 4677 if (rmem->nr_pages > 1) { 4678 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4679 "bnxt_ctx_pg_tbl%s_%x_%d", 4680 suffix, idx, bp->eth_dev->data->port_id); 4681 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4682 mz = rte_memzone_lookup(mz_name); 4683 if (!mz) { 4684 mz = rte_memzone_reserve_aligned(mz_name, 4685 rmem->nr_pages * 8, 4686 bp->eth_dev->device->numa_node, 4687 RTE_MEMZONE_2MB | 4688 RTE_MEMZONE_SIZE_HINT_ONLY | 4689 RTE_MEMZONE_IOVA_CONTIG, 4690 BNXT_PAGE_SIZE); 4691 if (mz == NULL) 4692 return -ENOMEM; 4693 } 4694 4695 memset(mz->addr, 0, mz->len); 4696 mz_phys_addr = mz->iova; 4697 4698 rmem->pg_tbl = mz->addr; 4699 rmem->pg_tbl_map = mz_phys_addr; 4700 rmem->pg_tbl_mz = mz; 4701 } 4702 4703 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4704 suffix, idx, bp->eth_dev->data->port_id); 4705 mz = rte_memzone_lookup(mz_name); 4706 if (!mz) { 4707 mz = rte_memzone_reserve_aligned(mz_name, 4708 mem_size, 4709 bp->eth_dev->device->numa_node, 4710 RTE_MEMZONE_1GB | 4711 RTE_MEMZONE_SIZE_HINT_ONLY | 4712 RTE_MEMZONE_IOVA_CONTIG, 4713 BNXT_PAGE_SIZE); 4714 if (mz == NULL) 4715 return -ENOMEM; 4716 } 4717 4718 memset(mz->addr, 0, mz->len); 4719 mz_phys_addr = mz->iova; 4720 4721 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4722 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4723 rmem->dma_arr[i] = mz_phys_addr + sz; 4724 4725 if (rmem->nr_pages > 1) { 4726 if (i == rmem->nr_pages - 2 && 4727 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4728 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4729 else if (i == rmem->nr_pages - 1 && 4730 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4731 valid_bits |= PTU_PTE_LAST; 4732 4733 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4734 valid_bits); 4735 } 4736 } 4737 4738 rmem->mz = mz; 4739 if (rmem->vmem_size) 4740 rmem->vmem = (void **)mz->addr; 4741 rmem->dma_arr[0] = mz_phys_addr; 4742 return 0; 4743 } 4744 4745 static void bnxt_free_ctx_mem(struct bnxt *bp) 4746 { 4747 int i; 4748 4749 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4750 return; 4751 4752 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4753 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4754 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4755 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4756 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4757 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4758 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4759 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4760 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4761 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4762 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4763 4764 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) { 4765 if (bp->ctx->tqm_mem[i]) 4766 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4767 } 4768 4769 rte_free(bp->ctx); 4770 bp->ctx = NULL; 4771 } 4772 4773 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4774 4775 #define min_t(type, x, y) ({ \ 4776 type __min1 = (x); \ 4777 type __min2 = (y); \ 4778 __min1 < __min2 ? __min1 : __min2; }) 4779 4780 #define max_t(type, x, y) ({ \ 4781 type __max1 = (x); \ 4782 type __max2 = (y); \ 4783 __max1 > __max2 ? __max1 : __max2; }) 4784 4785 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4786 4787 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4788 { 4789 struct bnxt_ctx_pg_info *ctx_pg; 4790 struct bnxt_ctx_mem_info *ctx; 4791 uint32_t mem_size, ena, entries; 4792 uint32_t entries_sp, min; 4793 int i, rc; 4794 4795 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4796 if (rc) { 4797 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4798 return rc; 4799 } 4800 ctx = bp->ctx; 4801 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4802 return 0; 4803 4804 ctx_pg = &ctx->qp_mem; 4805 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4806 if (ctx->qp_entry_size) { 4807 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4808 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4809 if (rc) 4810 return rc; 4811 } 4812 4813 ctx_pg = &ctx->srq_mem; 4814 ctx_pg->entries = ctx->srq_max_l2_entries; 4815 if (ctx->srq_entry_size) { 4816 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4817 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4818 if (rc) 4819 return rc; 4820 } 4821 4822 ctx_pg = &ctx->cq_mem; 4823 ctx_pg->entries = ctx->cq_max_l2_entries; 4824 if (ctx->cq_entry_size) { 4825 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4826 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4827 if (rc) 4828 return rc; 4829 } 4830 4831 ctx_pg = &ctx->vnic_mem; 4832 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4833 ctx->vnic_max_ring_table_entries; 4834 if (ctx->vnic_entry_size) { 4835 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4836 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4837 if (rc) 4838 return rc; 4839 } 4840 4841 ctx_pg = &ctx->stat_mem; 4842 ctx_pg->entries = ctx->stat_max_entries; 4843 if (ctx->stat_entry_size) { 4844 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4845 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4846 if (rc) 4847 return rc; 4848 } 4849 4850 min = ctx->tqm_min_entries_per_ring; 4851 4852 entries_sp = ctx->qp_max_l2_entries + 4853 ctx->vnic_max_vnic_entries + 4854 2 * ctx->qp_min_qp1_entries + min; 4855 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple); 4856 4857 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries; 4858 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4859 entries = clamp_t(uint32_t, entries, min, 4860 ctx->tqm_max_entries_per_ring); 4861 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 4862 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7. 4863 * i > 8 is other ext rings. 4864 */ 4865 ctx_pg = ctx->tqm_mem[i]; 4866 ctx_pg->entries = i ? entries : entries_sp; 4867 if (ctx->tqm_entry_size) { 4868 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4869 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, 4870 "tqm_mem", i); 4871 if (rc) 4872 return rc; 4873 } 4874 if (i < BNXT_MAX_TQM_LEGACY_RINGS) 4875 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4876 else 4877 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8; 4878 } 4879 4880 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4881 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4882 if (rc) 4883 PMD_DRV_LOG(ERR, 4884 "Failed to configure context mem: rc = %d\n", rc); 4885 else 4886 ctx->flags |= BNXT_CTX_FLAG_INITED; 4887 4888 return rc; 4889 } 4890 4891 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4892 { 4893 struct rte_pci_device *pci_dev = bp->pdev; 4894 char mz_name[RTE_MEMZONE_NAMESIZE]; 4895 const struct rte_memzone *mz = NULL; 4896 uint32_t total_alloc_len; 4897 rte_iova_t mz_phys_addr; 4898 4899 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4900 return 0; 4901 4902 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4903 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4904 pci_dev->addr.bus, pci_dev->addr.devid, 4905 pci_dev->addr.function, "rx_port_stats"); 4906 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4907 mz = rte_memzone_lookup(mz_name); 4908 total_alloc_len = 4909 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4910 sizeof(struct rx_port_stats_ext) + 512); 4911 if (!mz) { 4912 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4913 SOCKET_ID_ANY, 4914 RTE_MEMZONE_2MB | 4915 RTE_MEMZONE_SIZE_HINT_ONLY | 4916 RTE_MEMZONE_IOVA_CONTIG); 4917 if (mz == NULL) 4918 return -ENOMEM; 4919 } 4920 memset(mz->addr, 0, mz->len); 4921 mz_phys_addr = mz->iova; 4922 4923 bp->rx_mem_zone = (const void *)mz; 4924 bp->hw_rx_port_stats = mz->addr; 4925 bp->hw_rx_port_stats_map = mz_phys_addr; 4926 4927 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4928 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4929 pci_dev->addr.bus, pci_dev->addr.devid, 4930 pci_dev->addr.function, "tx_port_stats"); 4931 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4932 mz = rte_memzone_lookup(mz_name); 4933 total_alloc_len = 4934 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4935 sizeof(struct tx_port_stats_ext) + 512); 4936 if (!mz) { 4937 mz = rte_memzone_reserve(mz_name, 4938 total_alloc_len, 4939 SOCKET_ID_ANY, 4940 RTE_MEMZONE_2MB | 4941 RTE_MEMZONE_SIZE_HINT_ONLY | 4942 RTE_MEMZONE_IOVA_CONTIG); 4943 if (mz == NULL) 4944 return -ENOMEM; 4945 } 4946 memset(mz->addr, 0, mz->len); 4947 mz_phys_addr = mz->iova; 4948 4949 bp->tx_mem_zone = (const void *)mz; 4950 bp->hw_tx_port_stats = mz->addr; 4951 bp->hw_tx_port_stats_map = mz_phys_addr; 4952 bp->flags |= BNXT_FLAG_PORT_STATS; 4953 4954 /* Display extended statistics if FW supports it */ 4955 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4956 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4957 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4958 return 0; 4959 4960 bp->hw_rx_port_stats_ext = (void *) 4961 ((uint8_t *)bp->hw_rx_port_stats + 4962 sizeof(struct rx_port_stats)); 4963 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4964 sizeof(struct rx_port_stats); 4965 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4966 4967 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4968 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4969 bp->hw_tx_port_stats_ext = (void *) 4970 ((uint8_t *)bp->hw_tx_port_stats + 4971 sizeof(struct tx_port_stats)); 4972 bp->hw_tx_port_stats_ext_map = 4973 bp->hw_tx_port_stats_map + 4974 sizeof(struct tx_port_stats); 4975 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4976 } 4977 4978 return 0; 4979 } 4980 4981 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4982 { 4983 struct bnxt *bp = eth_dev->data->dev_private; 4984 int rc = 0; 4985 4986 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4987 RTE_ETHER_ADDR_LEN * 4988 bp->max_l2_ctx, 4989 0); 4990 if (eth_dev->data->mac_addrs == NULL) { 4991 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4992 return -ENOMEM; 4993 } 4994 4995 if (!BNXT_HAS_DFLT_MAC_SET(bp)) { 4996 if (BNXT_PF(bp)) 4997 return -EINVAL; 4998 4999 /* Generate a random MAC address, if none was assigned by PF */ 5000 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 5001 bnxt_eth_hw_addr_random(bp->mac_addr); 5002 PMD_DRV_LOG(INFO, 5003 "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n", 5004 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 5005 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 5006 5007 rc = bnxt_hwrm_set_mac(bp); 5008 if (rc) 5009 return rc; 5010 } 5011 5012 /* Copy the permanent MAC from the FUNC_QCAPS response */ 5013 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 5014 5015 return rc; 5016 } 5017 5018 static int bnxt_restore_dflt_mac(struct bnxt *bp) 5019 { 5020 int rc = 0; 5021 5022 /* MAC is already configured in FW */ 5023 if (BNXT_HAS_DFLT_MAC_SET(bp)) 5024 return 0; 5025 5026 /* Restore the old MAC configured */ 5027 rc = bnxt_hwrm_set_mac(bp); 5028 if (rc) 5029 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 5030 5031 return rc; 5032 } 5033 5034 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 5035 { 5036 if (!BNXT_PF(bp)) 5037 return; 5038 5039 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd)); 5040 5041 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN)) 5042 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG); 5043 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG); 5044 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG); 5045 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC); 5046 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); 5047 } 5048 5049 struct bnxt * 5050 bnxt_get_bp(uint16_t port) 5051 { 5052 struct bnxt *bp; 5053 struct rte_eth_dev *dev; 5054 5055 if (!rte_eth_dev_is_valid_port(port)) { 5056 PMD_DRV_LOG(ERR, "Invalid port %d\n", port); 5057 return NULL; 5058 } 5059 5060 dev = &rte_eth_devices[port]; 5061 if (!is_bnxt_supported(dev)) { 5062 PMD_DRV_LOG(ERR, "Device %d not supported\n", port); 5063 return NULL; 5064 } 5065 5066 bp = (struct bnxt *)dev->data->dev_private; 5067 if (!BNXT_TRUFLOW_EN(bp)) { 5068 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); 5069 return NULL; 5070 } 5071 5072 return bp; 5073 } 5074 5075 uint16_t 5076 bnxt_get_svif(uint16_t port_id, bool func_svif, 5077 enum bnxt_ulp_intf_type type) 5078 { 5079 struct rte_eth_dev *eth_dev; 5080 struct bnxt *bp; 5081 5082 eth_dev = &rte_eth_devices[port_id]; 5083 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5084 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5085 if (!vfr) 5086 return 0; 5087 5088 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5089 return vfr->svif; 5090 5091 eth_dev = vfr->parent_dev; 5092 } 5093 5094 bp = eth_dev->data->dev_private; 5095 5096 return func_svif ? bp->func_svif : bp->port_svif; 5097 } 5098 5099 void 5100 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, 5101 uint8_t *mac, uint8_t *parent_mac) 5102 { 5103 struct rte_eth_dev *eth_dev; 5104 struct bnxt *bp; 5105 5106 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && 5107 type != BNXT_ULP_INTF_TYPE_PF) 5108 return; 5109 5110 eth_dev = &rte_eth_devices[port]; 5111 bp = eth_dev->data->dev_private; 5112 memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); 5113 5114 if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) 5115 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); 5116 } 5117 5118 uint16_t 5119 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 5120 { 5121 struct rte_eth_dev *eth_dev; 5122 struct bnxt *bp; 5123 5124 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) 5125 return 0; 5126 5127 eth_dev = &rte_eth_devices[port]; 5128 bp = eth_dev->data->dev_private; 5129 5130 return bp->parent->vnic; 5131 } 5132 uint16_t 5133 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 5134 { 5135 struct rte_eth_dev *eth_dev; 5136 struct bnxt_vnic_info *vnic; 5137 struct bnxt *bp; 5138 5139 eth_dev = &rte_eth_devices[port]; 5140 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5141 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5142 if (!vfr) 5143 return 0; 5144 5145 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5146 return vfr->dflt_vnic_id; 5147 5148 eth_dev = vfr->parent_dev; 5149 } 5150 5151 bp = eth_dev->data->dev_private; 5152 5153 vnic = BNXT_GET_DEFAULT_VNIC(bp); 5154 5155 return vnic->fw_vnic_id; 5156 } 5157 5158 uint16_t 5159 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) 5160 { 5161 struct rte_eth_dev *eth_dev; 5162 struct bnxt *bp; 5163 5164 eth_dev = &rte_eth_devices[port]; 5165 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5166 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5167 if (!vfr) 5168 return 0; 5169 5170 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5171 return vfr->fw_fid; 5172 5173 eth_dev = vfr->parent_dev; 5174 } 5175 5176 bp = eth_dev->data->dev_private; 5177 5178 return bp->fw_fid; 5179 } 5180 5181 enum bnxt_ulp_intf_type 5182 bnxt_get_interface_type(uint16_t port) 5183 { 5184 struct rte_eth_dev *eth_dev; 5185 struct bnxt *bp; 5186 5187 eth_dev = &rte_eth_devices[port]; 5188 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) 5189 return BNXT_ULP_INTF_TYPE_VF_REP; 5190 5191 bp = eth_dev->data->dev_private; 5192 if (BNXT_PF(bp)) 5193 return BNXT_ULP_INTF_TYPE_PF; 5194 else if (BNXT_VF_IS_TRUSTED(bp)) 5195 return BNXT_ULP_INTF_TYPE_TRUSTED_VF; 5196 else if (BNXT_VF(bp)) 5197 return BNXT_ULP_INTF_TYPE_VF; 5198 5199 return BNXT_ULP_INTF_TYPE_INVALID; 5200 } 5201 5202 uint16_t 5203 bnxt_get_phy_port_id(uint16_t port_id) 5204 { 5205 struct bnxt_representor *vfr; 5206 struct rte_eth_dev *eth_dev; 5207 struct bnxt *bp; 5208 5209 eth_dev = &rte_eth_devices[port_id]; 5210 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5211 vfr = eth_dev->data->dev_private; 5212 if (!vfr) 5213 return 0; 5214 5215 eth_dev = vfr->parent_dev; 5216 } 5217 5218 bp = eth_dev->data->dev_private; 5219 5220 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; 5221 } 5222 5223 uint16_t 5224 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) 5225 { 5226 struct rte_eth_dev *eth_dev; 5227 struct bnxt *bp; 5228 5229 eth_dev = &rte_eth_devices[port_id]; 5230 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5231 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5232 if (!vfr) 5233 return 0; 5234 5235 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5236 return vfr->fw_fid - 1; 5237 5238 eth_dev = vfr->parent_dev; 5239 } 5240 5241 bp = eth_dev->data->dev_private; 5242 5243 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; 5244 } 5245 5246 uint16_t 5247 bnxt_get_vport(uint16_t port_id) 5248 { 5249 return (1 << bnxt_get_phy_port_id(port_id)); 5250 } 5251 5252 static void bnxt_alloc_error_recovery_info(struct bnxt *bp) 5253 { 5254 struct bnxt_error_recovery_info *info = bp->recovery_info; 5255 5256 if (info) { 5257 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)) 5258 memset(info, 0, sizeof(*info)); 5259 return; 5260 } 5261 5262 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 5263 return; 5264 5265 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5266 sizeof(*info), 0); 5267 if (!info) 5268 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5269 5270 bp->recovery_info = info; 5271 } 5272 5273 static void bnxt_check_fw_status(struct bnxt *bp) 5274 { 5275 uint32_t fw_status; 5276 5277 if (!(bp->recovery_info && 5278 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))) 5279 return; 5280 5281 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG); 5282 if (fw_status != BNXT_FW_STATUS_HEALTHY) 5283 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n", 5284 fw_status); 5285 } 5286 5287 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) 5288 { 5289 struct bnxt_error_recovery_info *info = bp->recovery_info; 5290 uint32_t status_loc; 5291 uint32_t sig_ver; 5292 5293 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 + 5294 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5295 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5296 BNXT_GRCP_WINDOW_2_BASE + 5297 offsetof(struct hcomm_status, 5298 sig_ver))); 5299 /* If the signature is absent, then FW does not support this feature */ 5300 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) != 5301 HCOMM_STATUS_SIGNATURE_VAL) 5302 return 0; 5303 5304 if (!info) { 5305 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5306 sizeof(*info), 0); 5307 if (!info) 5308 return -ENOMEM; 5309 bp->recovery_info = info; 5310 } else { 5311 memset(info, 0, sizeof(*info)); 5312 } 5313 5314 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5315 BNXT_GRCP_WINDOW_2_BASE + 5316 offsetof(struct hcomm_status, 5317 fw_status_loc))); 5318 5319 /* Only pre-map the FW health status GRC register */ 5320 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC) 5321 return 0; 5322 5323 info->status_regs[BNXT_FW_STATUS_REG] = status_loc; 5324 info->mapped_status_regs[BNXT_FW_STATUS_REG] = 5325 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK); 5326 5327 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 + 5328 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5329 5330 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS; 5331 5332 return 0; 5333 } 5334 5335 /* This function gets the FW version along with the 5336 * capabilities(MAX and current) of the function, vnic, 5337 * error recovery, phy and other chip related info 5338 */ 5339 static int bnxt_get_config(struct bnxt *bp) 5340 { 5341 uint16_t mtu; 5342 int rc = 0; 5343 5344 bp->fw_cap = 0; 5345 5346 rc = bnxt_map_hcomm_fw_status_reg(bp); 5347 if (rc) 5348 return rc; 5349 5350 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT); 5351 if (rc) { 5352 bnxt_check_fw_status(bp); 5353 return rc; 5354 } 5355 5356 rc = bnxt_hwrm_func_reset(bp); 5357 if (rc) 5358 return -EIO; 5359 5360 rc = bnxt_hwrm_vnic_qcaps(bp); 5361 if (rc) 5362 return rc; 5363 5364 rc = bnxt_hwrm_queue_qportcfg(bp); 5365 if (rc) 5366 return rc; 5367 5368 /* Get the MAX capabilities for this function. 5369 * This function also allocates context memory for TQM rings and 5370 * informs the firmware about this allocated backing store memory. 5371 */ 5372 rc = bnxt_hwrm_func_qcaps(bp); 5373 if (rc) 5374 return rc; 5375 5376 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 5377 if (rc) 5378 return rc; 5379 5380 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 5381 if (rc) 5382 return rc; 5383 5384 bnxt_hwrm_port_mac_qcfg(bp); 5385 5386 bnxt_hwrm_parent_pf_qcfg(bp); 5387 5388 bnxt_hwrm_port_phy_qcaps(bp); 5389 5390 bnxt_alloc_error_recovery_info(bp); 5391 /* Get the adapter error recovery support info */ 5392 rc = bnxt_hwrm_error_recovery_qcfg(bp); 5393 if (rc) 5394 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5395 5396 bnxt_hwrm_port_led_qcaps(bp); 5397 5398 return 0; 5399 } 5400 5401 static int 5402 bnxt_init_locks(struct bnxt *bp) 5403 { 5404 int err; 5405 5406 err = pthread_mutex_init(&bp->flow_lock, NULL); 5407 if (err) { 5408 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 5409 return err; 5410 } 5411 5412 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 5413 if (err) { 5414 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 5415 return err; 5416 } 5417 5418 err = pthread_mutex_init(&bp->health_check_lock, NULL); 5419 if (err) { 5420 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n"); 5421 return err; 5422 } 5423 5424 err = pthread_mutex_init(&bp->err_recovery_lock, NULL); 5425 if (err) 5426 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n"); 5427 5428 return err; 5429 } 5430 5431 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 5432 { 5433 int rc = 0; 5434 5435 rc = bnxt_get_config(bp); 5436 if (rc) 5437 return rc; 5438 5439 if (!reconfig_dev) { 5440 rc = bnxt_setup_mac_addr(bp->eth_dev); 5441 if (rc) 5442 return rc; 5443 } else { 5444 rc = bnxt_restore_dflt_mac(bp); 5445 if (rc) 5446 return rc; 5447 } 5448 5449 bnxt_config_vf_req_fwd(bp); 5450 5451 rc = bnxt_hwrm_func_driver_register(bp); 5452 if (rc) { 5453 PMD_DRV_LOG(ERR, "Failed to register driver"); 5454 return -EBUSY; 5455 } 5456 5457 if (BNXT_PF(bp)) { 5458 if (bp->pdev->max_vfs) { 5459 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 5460 if (rc) { 5461 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 5462 return rc; 5463 } 5464 } else { 5465 rc = bnxt_hwrm_allocate_pf_only(bp); 5466 if (rc) { 5467 PMD_DRV_LOG(ERR, 5468 "Failed to allocate PF resources"); 5469 return rc; 5470 } 5471 } 5472 } 5473 5474 rc = bnxt_alloc_mem(bp, reconfig_dev); 5475 if (rc) 5476 return rc; 5477 5478 rc = bnxt_setup_int(bp); 5479 if (rc) 5480 return rc; 5481 5482 rc = bnxt_request_int(bp); 5483 if (rc) 5484 return rc; 5485 5486 rc = bnxt_init_ctx_mem(bp); 5487 if (rc) { 5488 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n"); 5489 return rc; 5490 } 5491 5492 return 0; 5493 } 5494 5495 static int 5496 bnxt_parse_devarg_accum_stats(__rte_unused const char *key, 5497 const char *value, void *opaque_arg) 5498 { 5499 struct bnxt *bp = opaque_arg; 5500 unsigned long accum_stats; 5501 char *end = NULL; 5502 5503 if (!value || !opaque_arg) { 5504 PMD_DRV_LOG(ERR, 5505 "Invalid parameter passed to accum-stats devargs.\n"); 5506 return -EINVAL; 5507 } 5508 5509 accum_stats = strtoul(value, &end, 10); 5510 if (end == NULL || *end != '\0' || 5511 (accum_stats == ULONG_MAX && errno == ERANGE)) { 5512 PMD_DRV_LOG(ERR, 5513 "Invalid parameter passed to accum-stats devargs.\n"); 5514 return -EINVAL; 5515 } 5516 5517 if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) { 5518 PMD_DRV_LOG(ERR, 5519 "Invalid value passed to accum-stats devargs.\n"); 5520 return -EINVAL; 5521 } 5522 5523 if (accum_stats) { 5524 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN; 5525 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n"); 5526 } else { 5527 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN; 5528 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n"); 5529 } 5530 5531 return 0; 5532 } 5533 5534 static int 5535 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, 5536 const char *value, void *opaque_arg) 5537 { 5538 struct bnxt *bp = opaque_arg; 5539 unsigned long flow_xstat; 5540 char *end = NULL; 5541 5542 if (!value || !opaque_arg) { 5543 PMD_DRV_LOG(ERR, 5544 "Invalid parameter passed to flow_xstat devarg.\n"); 5545 return -EINVAL; 5546 } 5547 5548 flow_xstat = strtoul(value, &end, 10); 5549 if (end == NULL || *end != '\0' || 5550 (flow_xstat == ULONG_MAX && errno == ERANGE)) { 5551 PMD_DRV_LOG(ERR, 5552 "Invalid parameter passed to flow_xstat devarg.\n"); 5553 return -EINVAL; 5554 } 5555 5556 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) { 5557 PMD_DRV_LOG(ERR, 5558 "Invalid value passed to flow_xstat devarg.\n"); 5559 return -EINVAL; 5560 } 5561 5562 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN; 5563 if (BNXT_FLOW_XSTATS_EN(bp)) 5564 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n"); 5565 5566 return 0; 5567 } 5568 5569 static int 5570 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, 5571 const char *value, void *opaque_arg) 5572 { 5573 struct bnxt *bp = opaque_arg; 5574 unsigned long max_num_kflows; 5575 char *end = NULL; 5576 5577 if (!value || !opaque_arg) { 5578 PMD_DRV_LOG(ERR, 5579 "Invalid parameter passed to max_num_kflows devarg.\n"); 5580 return -EINVAL; 5581 } 5582 5583 max_num_kflows = strtoul(value, &end, 10); 5584 if (end == NULL || *end != '\0' || 5585 (max_num_kflows == ULONG_MAX && errno == ERANGE)) { 5586 PMD_DRV_LOG(ERR, 5587 "Invalid parameter passed to max_num_kflows devarg.\n"); 5588 return -EINVAL; 5589 } 5590 5591 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) { 5592 PMD_DRV_LOG(ERR, 5593 "Invalid value passed to max_num_kflows devarg.\n"); 5594 return -EINVAL; 5595 } 5596 5597 bp->max_num_kflows = max_num_kflows; 5598 if (bp->max_num_kflows) 5599 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n", 5600 max_num_kflows); 5601 5602 return 0; 5603 } 5604 5605 static int 5606 bnxt_parse_devarg_app_id(__rte_unused const char *key, 5607 const char *value, void *opaque_arg) 5608 { 5609 struct bnxt *bp = opaque_arg; 5610 unsigned long app_id; 5611 char *end = NULL; 5612 5613 if (!value || !opaque_arg) { 5614 PMD_DRV_LOG(ERR, 5615 "Invalid parameter passed to app-id " 5616 "devargs.\n"); 5617 return -EINVAL; 5618 } 5619 5620 app_id = strtoul(value, &end, 10); 5621 if (end == NULL || *end != '\0' || 5622 (app_id == ULONG_MAX && errno == ERANGE)) { 5623 PMD_DRV_LOG(ERR, 5624 "Invalid parameter passed to app_id " 5625 "devargs.\n"); 5626 return -EINVAL; 5627 } 5628 5629 if (BNXT_DEVARG_APP_ID_INVALID(app_id)) { 5630 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n", 5631 (uint16_t)app_id); 5632 return -EINVAL; 5633 } 5634 5635 bp->app_id = app_id; 5636 PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id); 5637 5638 return 0; 5639 } 5640 5641 static int 5642 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key, 5643 const char *value, void *opaque_arg) 5644 { 5645 struct bnxt_representor *vfr_bp = opaque_arg; 5646 unsigned long rep_is_pf; 5647 char *end = NULL; 5648 5649 if (!value || !opaque_arg) { 5650 PMD_DRV_LOG(ERR, 5651 "Invalid parameter passed to rep_is_pf devargs.\n"); 5652 return -EINVAL; 5653 } 5654 5655 rep_is_pf = strtoul(value, &end, 10); 5656 if (end == NULL || *end != '\0' || 5657 (rep_is_pf == ULONG_MAX && errno == ERANGE)) { 5658 PMD_DRV_LOG(ERR, 5659 "Invalid parameter passed to rep_is_pf devargs.\n"); 5660 return -EINVAL; 5661 } 5662 5663 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) { 5664 PMD_DRV_LOG(ERR, 5665 "Invalid value passed to rep_is_pf devargs.\n"); 5666 return -EINVAL; 5667 } 5668 5669 vfr_bp->flags |= rep_is_pf; 5670 if (BNXT_REP_PF(vfr_bp)) 5671 PMD_DRV_LOG(INFO, "PF representor\n"); 5672 else 5673 PMD_DRV_LOG(INFO, "VF representor\n"); 5674 5675 return 0; 5676 } 5677 5678 static int 5679 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key, 5680 const char *value, void *opaque_arg) 5681 { 5682 struct bnxt_representor *vfr_bp = opaque_arg; 5683 unsigned long rep_based_pf; 5684 char *end = NULL; 5685 5686 if (!value || !opaque_arg) { 5687 PMD_DRV_LOG(ERR, 5688 "Invalid parameter passed to rep_based_pf " 5689 "devargs.\n"); 5690 return -EINVAL; 5691 } 5692 5693 rep_based_pf = strtoul(value, &end, 10); 5694 if (end == NULL || *end != '\0' || 5695 (rep_based_pf == ULONG_MAX && errno == ERANGE)) { 5696 PMD_DRV_LOG(ERR, 5697 "Invalid parameter passed to rep_based_pf " 5698 "devargs.\n"); 5699 return -EINVAL; 5700 } 5701 5702 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) { 5703 PMD_DRV_LOG(ERR, 5704 "Invalid value passed to rep_based_pf devargs.\n"); 5705 return -EINVAL; 5706 } 5707 5708 vfr_bp->rep_based_pf = rep_based_pf; 5709 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID; 5710 5711 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf); 5712 5713 return 0; 5714 } 5715 5716 static int 5717 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key, 5718 const char *value, void *opaque_arg) 5719 { 5720 struct bnxt_representor *vfr_bp = opaque_arg; 5721 unsigned long rep_q_r2f; 5722 char *end = NULL; 5723 5724 if (!value || !opaque_arg) { 5725 PMD_DRV_LOG(ERR, 5726 "Invalid parameter passed to rep_q_r2f " 5727 "devargs.\n"); 5728 return -EINVAL; 5729 } 5730 5731 rep_q_r2f = strtoul(value, &end, 10); 5732 if (end == NULL || *end != '\0' || 5733 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) { 5734 PMD_DRV_LOG(ERR, 5735 "Invalid parameter passed to rep_q_r2f " 5736 "devargs.\n"); 5737 return -EINVAL; 5738 } 5739 5740 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) { 5741 PMD_DRV_LOG(ERR, 5742 "Invalid value passed to rep_q_r2f devargs.\n"); 5743 return -EINVAL; 5744 } 5745 5746 vfr_bp->rep_q_r2f = rep_q_r2f; 5747 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID; 5748 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f); 5749 5750 return 0; 5751 } 5752 5753 static int 5754 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key, 5755 const char *value, void *opaque_arg) 5756 { 5757 struct bnxt_representor *vfr_bp = opaque_arg; 5758 unsigned long rep_q_f2r; 5759 char *end = NULL; 5760 5761 if (!value || !opaque_arg) { 5762 PMD_DRV_LOG(ERR, 5763 "Invalid parameter passed to rep_q_f2r " 5764 "devargs.\n"); 5765 return -EINVAL; 5766 } 5767 5768 rep_q_f2r = strtoul(value, &end, 10); 5769 if (end == NULL || *end != '\0' || 5770 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) { 5771 PMD_DRV_LOG(ERR, 5772 "Invalid parameter passed to rep_q_f2r " 5773 "devargs.\n"); 5774 return -EINVAL; 5775 } 5776 5777 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) { 5778 PMD_DRV_LOG(ERR, 5779 "Invalid value passed to rep_q_f2r devargs.\n"); 5780 return -EINVAL; 5781 } 5782 5783 vfr_bp->rep_q_f2r = rep_q_f2r; 5784 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID; 5785 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r); 5786 5787 return 0; 5788 } 5789 5790 static int 5791 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key, 5792 const char *value, void *opaque_arg) 5793 { 5794 struct bnxt_representor *vfr_bp = opaque_arg; 5795 unsigned long rep_fc_r2f; 5796 char *end = NULL; 5797 5798 if (!value || !opaque_arg) { 5799 PMD_DRV_LOG(ERR, 5800 "Invalid parameter passed to rep_fc_r2f " 5801 "devargs.\n"); 5802 return -EINVAL; 5803 } 5804 5805 rep_fc_r2f = strtoul(value, &end, 10); 5806 if (end == NULL || *end != '\0' || 5807 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) { 5808 PMD_DRV_LOG(ERR, 5809 "Invalid parameter passed to rep_fc_r2f " 5810 "devargs.\n"); 5811 return -EINVAL; 5812 } 5813 5814 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) { 5815 PMD_DRV_LOG(ERR, 5816 "Invalid value passed to rep_fc_r2f devargs.\n"); 5817 return -EINVAL; 5818 } 5819 5820 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID; 5821 vfr_bp->rep_fc_r2f = rep_fc_r2f; 5822 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f); 5823 5824 return 0; 5825 } 5826 5827 static int 5828 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key, 5829 const char *value, void *opaque_arg) 5830 { 5831 struct bnxt_representor *vfr_bp = opaque_arg; 5832 unsigned long rep_fc_f2r; 5833 char *end = NULL; 5834 5835 if (!value || !opaque_arg) { 5836 PMD_DRV_LOG(ERR, 5837 "Invalid parameter passed to rep_fc_f2r " 5838 "devargs.\n"); 5839 return -EINVAL; 5840 } 5841 5842 rep_fc_f2r = strtoul(value, &end, 10); 5843 if (end == NULL || *end != '\0' || 5844 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) { 5845 PMD_DRV_LOG(ERR, 5846 "Invalid parameter passed to rep_fc_f2r " 5847 "devargs.\n"); 5848 return -EINVAL; 5849 } 5850 5851 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) { 5852 PMD_DRV_LOG(ERR, 5853 "Invalid value passed to rep_fc_f2r devargs.\n"); 5854 return -EINVAL; 5855 } 5856 5857 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID; 5858 vfr_bp->rep_fc_f2r = rep_fc_f2r; 5859 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r); 5860 5861 return 0; 5862 } 5863 5864 static int 5865 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) 5866 { 5867 struct rte_kvargs *kvlist; 5868 int ret; 5869 5870 if (devargs == NULL) 5871 return 0; 5872 5873 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); 5874 if (kvlist == NULL) 5875 return -EINVAL; 5876 5877 /* 5878 * Handler for "flow_xstat" devarg. 5879 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1" 5880 */ 5881 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, 5882 bnxt_parse_devarg_flow_xstat, bp); 5883 if (ret) 5884 goto err; 5885 5886 /* 5887 * Handler for "accum-stats" devarg. 5888 * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1" 5889 */ 5890 rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS, 5891 bnxt_parse_devarg_accum_stats, bp); 5892 /* 5893 * Handler for "max_num_kflows" devarg. 5894 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" 5895 */ 5896 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, 5897 bnxt_parse_devarg_max_num_kflows, bp); 5898 if (ret) 5899 goto err; 5900 5901 err: 5902 /* 5903 * Handler for "app-id" devarg. 5904 * Invoked as for ex: "-a 000:00:0d.0,app-id=1" 5905 */ 5906 rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID, 5907 bnxt_parse_devarg_app_id, bp); 5908 5909 rte_kvargs_free(kvlist); 5910 return ret; 5911 } 5912 5913 static int bnxt_alloc_switch_domain(struct bnxt *bp) 5914 { 5915 int rc = 0; 5916 5917 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 5918 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id); 5919 if (rc) 5920 PMD_DRV_LOG(ERR, 5921 "Failed to alloc switch domain: %d\n", rc); 5922 else 5923 PMD_DRV_LOG(INFO, 5924 "Switch domain allocated %d\n", 5925 bp->switch_domain_id); 5926 } 5927 5928 return rc; 5929 } 5930 5931 /* Allocate and initialize various fields in bnxt struct that 5932 * need to be allocated/destroyed only once in the lifetime of the driver 5933 */ 5934 static int bnxt_drv_init(struct rte_eth_dev *eth_dev) 5935 { 5936 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5937 struct bnxt *bp = eth_dev->data->dev_private; 5938 int rc = 0; 5939 5940 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 5941 5942 if (bnxt_vf_pciid(pci_dev->id.device_id)) 5943 bp->flags |= BNXT_FLAG_VF; 5944 5945 if (bnxt_p5_device(pci_dev->id.device_id)) 5946 bp->flags |= BNXT_FLAG_CHIP_P5; 5947 5948 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 5949 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 5950 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 5951 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 5952 bp->flags |= BNXT_FLAG_STINGRAY; 5953 5954 if (BNXT_TRUFLOW_EN(bp)) { 5955 /* extra mbuf field is required to store CFA code from mark */ 5956 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = { 5957 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME, 5958 .size = sizeof(bnxt_cfa_code_dynfield_t), 5959 .align = __alignof__(bnxt_cfa_code_dynfield_t), 5960 }; 5961 bnxt_cfa_code_dynfield_offset = 5962 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc); 5963 if (bnxt_cfa_code_dynfield_offset < 0) { 5964 PMD_DRV_LOG(ERR, 5965 "Failed to register mbuf field for TruFlow mark\n"); 5966 return -rte_errno; 5967 } 5968 } 5969 5970 rc = bnxt_map_pci_bars(eth_dev); 5971 if (rc) { 5972 PMD_DRV_LOG(ERR, 5973 "Failed to initialize board rc: %x\n", rc); 5974 return rc; 5975 } 5976 5977 rc = bnxt_alloc_pf_info(bp); 5978 if (rc) 5979 return rc; 5980 5981 rc = bnxt_alloc_link_info(bp); 5982 if (rc) 5983 return rc; 5984 5985 rc = bnxt_alloc_parent_info(bp); 5986 if (rc) 5987 return rc; 5988 5989 rc = bnxt_alloc_hwrm_resources(bp); 5990 if (rc) { 5991 PMD_DRV_LOG(ERR, 5992 "Failed to allocate response buffer rc: %x\n", rc); 5993 return rc; 5994 } 5995 rc = bnxt_alloc_leds_info(bp); 5996 if (rc) 5997 return rc; 5998 5999 rc = bnxt_alloc_cos_queues(bp); 6000 if (rc) 6001 return rc; 6002 6003 rc = bnxt_init_locks(bp); 6004 if (rc) 6005 return rc; 6006 6007 rc = bnxt_alloc_switch_domain(bp); 6008 if (rc) 6009 return rc; 6010 6011 return rc; 6012 } 6013 6014 static int 6015 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) 6016 { 6017 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 6018 static int version_printed; 6019 struct bnxt *bp; 6020 int rc; 6021 6022 if (version_printed++ == 0) 6023 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 6024 6025 eth_dev->dev_ops = &bnxt_dev_ops; 6026 eth_dev->rx_queue_count = bnxt_rx_queue_count_op; 6027 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; 6028 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; 6029 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 6030 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 6031 6032 /* 6033 * For secondary processes, we don't initialise any further 6034 * as primary has already done this work. 6035 */ 6036 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 6037 return 0; 6038 6039 rte_eth_copy_pci_info(eth_dev, pci_dev); 6040 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 6041 6042 bp = eth_dev->data->dev_private; 6043 6044 /* Parse dev arguments passed on when starting the DPDK application. */ 6045 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs); 6046 if (rc) 6047 goto error_free; 6048 6049 rc = bnxt_drv_init(eth_dev); 6050 if (rc) 6051 goto error_free; 6052 6053 rc = bnxt_init_resources(bp, false); 6054 if (rc) 6055 goto error_free; 6056 6057 rc = bnxt_alloc_stats_mem(bp); 6058 if (rc) 6059 goto error_free; 6060 6061 PMD_DRV_LOG(INFO, 6062 "Found %s device at mem %" PRIX64 ", node addr %pM\n", 6063 DRV_MODULE_NAME, 6064 pci_dev->mem_resource[0].phys_addr, 6065 pci_dev->mem_resource[0].addr); 6066 6067 return 0; 6068 6069 error_free: 6070 bnxt_dev_uninit(eth_dev); 6071 return rc; 6072 } 6073 6074 6075 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx) 6076 { 6077 if (!ctx) 6078 return; 6079 6080 if (ctx->va) 6081 rte_free(ctx->va); 6082 6083 ctx->va = NULL; 6084 ctx->dma = RTE_BAD_IOVA; 6085 ctx->ctx_id = BNXT_CTX_VAL_INVAL; 6086 } 6087 6088 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp) 6089 { 6090 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 6091 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 6092 bp->flow_stat->rx_fc_out_tbl.ctx_id, 6093 bp->flow_stat->max_fc, 6094 false); 6095 6096 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 6097 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 6098 bp->flow_stat->tx_fc_out_tbl.ctx_id, 6099 bp->flow_stat->max_fc, 6100 false); 6101 6102 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6103 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id); 6104 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6105 6106 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6107 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id); 6108 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6109 6110 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6111 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id); 6112 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6113 6114 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6115 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id); 6116 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6117 } 6118 6119 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp) 6120 { 6121 bnxt_unregister_fc_ctx_mem(bp); 6122 6123 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl); 6124 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl); 6125 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl); 6126 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl); 6127 } 6128 6129 static void bnxt_uninit_ctx_mem(struct bnxt *bp) 6130 { 6131 if (BNXT_FLOW_XSTATS_EN(bp)) 6132 bnxt_uninit_fc_ctx_mem(bp); 6133 } 6134 6135 static void 6136 bnxt_free_error_recovery_info(struct bnxt *bp) 6137 { 6138 rte_free(bp->recovery_info); 6139 bp->recovery_info = NULL; 6140 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 6141 } 6142 6143 static int 6144 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 6145 { 6146 int rc; 6147 6148 bnxt_free_int(bp); 6149 bnxt_free_mem(bp, reconfig_dev); 6150 6151 bnxt_hwrm_func_buf_unrgtr(bp); 6152 if (bp->pf != NULL) { 6153 rte_free(bp->pf->vf_req_buf); 6154 bp->pf->vf_req_buf = NULL; 6155 } 6156 6157 rc = bnxt_hwrm_func_driver_unregister(bp); 6158 bp->flags &= ~BNXT_FLAG_REGISTERED; 6159 bnxt_free_ctx_mem(bp); 6160 if (!reconfig_dev) { 6161 bnxt_free_hwrm_resources(bp); 6162 bnxt_free_error_recovery_info(bp); 6163 } 6164 6165 bnxt_uninit_ctx_mem(bp); 6166 6167 bnxt_free_flow_stats_info(bp); 6168 if (bp->rep_info != NULL) 6169 bnxt_free_switch_domain(bp); 6170 bnxt_free_rep_info(bp); 6171 rte_free(bp->ptp_cfg); 6172 bp->ptp_cfg = NULL; 6173 return rc; 6174 } 6175 6176 static int 6177 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 6178 { 6179 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 6180 return -EPERM; 6181 6182 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 6183 6184 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 6185 bnxt_dev_close_op(eth_dev); 6186 6187 return 0; 6188 } 6189 6190 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev) 6191 { 6192 struct bnxt *bp = eth_dev->data->dev_private; 6193 struct rte_eth_dev *vf_rep_eth_dev; 6194 int ret = 0, i; 6195 6196 if (!bp) 6197 return -EINVAL; 6198 6199 for (i = 0; i < bp->num_reps; i++) { 6200 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev; 6201 if (!vf_rep_eth_dev) 6202 continue; 6203 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n", 6204 vf_rep_eth_dev->data->port_id); 6205 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit); 6206 } 6207 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", 6208 eth_dev->data->port_id); 6209 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit); 6210 6211 return ret; 6212 } 6213 6214 static void bnxt_free_rep_info(struct bnxt *bp) 6215 { 6216 rte_free(bp->rep_info); 6217 bp->rep_info = NULL; 6218 rte_free(bp->cfa_code_map); 6219 bp->cfa_code_map = NULL; 6220 } 6221 6222 static int bnxt_init_rep_info(struct bnxt *bp) 6223 { 6224 int i = 0, rc; 6225 6226 if (bp->rep_info) 6227 return 0; 6228 6229 bp->rep_info = rte_zmalloc("bnxt_rep_info", 6230 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, 6231 0); 6232 if (!bp->rep_info) { 6233 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); 6234 return -ENOMEM; 6235 } 6236 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map", 6237 sizeof(*bp->cfa_code_map) * 6238 BNXT_MAX_CFA_CODE, 0); 6239 if (!bp->cfa_code_map) { 6240 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n"); 6241 bnxt_free_rep_info(bp); 6242 return -ENOMEM; 6243 } 6244 6245 for (i = 0; i < BNXT_MAX_CFA_CODE; i++) 6246 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID; 6247 6248 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL); 6249 if (rc) { 6250 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n"); 6251 bnxt_free_rep_info(bp); 6252 return rc; 6253 } 6254 6255 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL); 6256 if (rc) { 6257 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n"); 6258 bnxt_free_rep_info(bp); 6259 return rc; 6260 } 6261 6262 return rc; 6263 } 6264 6265 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, 6266 struct rte_eth_devargs *eth_da, 6267 struct rte_eth_dev *backing_eth_dev, 6268 const char *dev_args) 6269 { 6270 struct rte_eth_dev *vf_rep_eth_dev; 6271 char name[RTE_ETH_NAME_MAX_LEN]; 6272 struct bnxt *backing_bp; 6273 uint16_t num_rep; 6274 int i, ret = 0; 6275 struct rte_kvargs *kvlist = NULL; 6276 6277 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) 6278 return 0; 6279 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) { 6280 PMD_DRV_LOG(ERR, "unsupported representor type %d\n", 6281 eth_da->type); 6282 return -ENOTSUP; 6283 } 6284 num_rep = eth_da->nb_representor_ports; 6285 if (num_rep > BNXT_MAX_VF_REPS) { 6286 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", 6287 num_rep, BNXT_MAX_VF_REPS); 6288 return -EINVAL; 6289 } 6290 6291 if (num_rep >= RTE_MAX_ETHPORTS) { 6292 PMD_DRV_LOG(ERR, 6293 "nb_representor_ports = %d > %d MAX ETHPORTS\n", 6294 num_rep, RTE_MAX_ETHPORTS); 6295 return -EINVAL; 6296 } 6297 6298 backing_bp = backing_eth_dev->data->dev_private; 6299 6300 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { 6301 PMD_DRV_LOG(ERR, 6302 "Not a PF or trusted VF. No Representor support\n"); 6303 /* Returning an error is not an option. 6304 * Applications are not handling this correctly 6305 */ 6306 return 0; 6307 } 6308 6309 if (bnxt_init_rep_info(backing_bp)) 6310 return 0; 6311 6312 for (i = 0; i < num_rep; i++) { 6313 struct bnxt_representor representor = { 6314 .vf_id = eth_da->representor_ports[i], 6315 .switch_domain_id = backing_bp->switch_domain_id, 6316 .parent_dev = backing_eth_dev 6317 }; 6318 6319 if (representor.vf_id >= BNXT_MAX_VF_REPS) { 6320 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", 6321 representor.vf_id, BNXT_MAX_VF_REPS); 6322 continue; 6323 } 6324 6325 /* representor port net_bdf_port */ 6326 snprintf(name, sizeof(name), "net_%s_representor_%d", 6327 pci_dev->device.name, eth_da->representor_ports[i]); 6328 6329 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args); 6330 if (kvlist) { 6331 /* 6332 * Handler for "rep_is_pf" devarg. 6333 * Invoked as for ex: "-a 000:00:0d.0, 6334 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6335 */ 6336 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF, 6337 bnxt_parse_devarg_rep_is_pf, 6338 (void *)&representor); 6339 if (ret) { 6340 ret = -EINVAL; 6341 goto err; 6342 } 6343 /* 6344 * Handler for "rep_based_pf" devarg. 6345 * Invoked as for ex: "-a 000:00:0d.0, 6346 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6347 */ 6348 ret = rte_kvargs_process(kvlist, 6349 BNXT_DEVARG_REP_BASED_PF, 6350 bnxt_parse_devarg_rep_based_pf, 6351 (void *)&representor); 6352 if (ret) { 6353 ret = -EINVAL; 6354 goto err; 6355 } 6356 /* 6357 * Handler for "rep_based_pf" devarg. 6358 * Invoked as for ex: "-a 000:00:0d.0, 6359 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6360 */ 6361 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F, 6362 bnxt_parse_devarg_rep_q_r2f, 6363 (void *)&representor); 6364 if (ret) { 6365 ret = -EINVAL; 6366 goto err; 6367 } 6368 /* 6369 * Handler for "rep_based_pf" devarg. 6370 * Invoked as for ex: "-a 000:00:0d.0, 6371 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6372 */ 6373 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R, 6374 bnxt_parse_devarg_rep_q_f2r, 6375 (void *)&representor); 6376 if (ret) { 6377 ret = -EINVAL; 6378 goto err; 6379 } 6380 /* 6381 * Handler for "rep_based_pf" devarg. 6382 * Invoked as for ex: "-a 000:00:0d.0, 6383 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6384 */ 6385 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F, 6386 bnxt_parse_devarg_rep_fc_r2f, 6387 (void *)&representor); 6388 if (ret) { 6389 ret = -EINVAL; 6390 goto err; 6391 } 6392 /* 6393 * Handler for "rep_based_pf" devarg. 6394 * Invoked as for ex: "-a 000:00:0d.0, 6395 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6396 */ 6397 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R, 6398 bnxt_parse_devarg_rep_fc_f2r, 6399 (void *)&representor); 6400 if (ret) { 6401 ret = -EINVAL; 6402 goto err; 6403 } 6404 } 6405 6406 ret = rte_eth_dev_create(&pci_dev->device, name, 6407 sizeof(struct bnxt_representor), 6408 NULL, NULL, 6409 bnxt_representor_init, 6410 &representor); 6411 if (ret) { 6412 PMD_DRV_LOG(ERR, "failed to create bnxt vf " 6413 "representor %s.", name); 6414 goto err; 6415 } 6416 6417 vf_rep_eth_dev = rte_eth_dev_allocated(name); 6418 if (!vf_rep_eth_dev) { 6419 PMD_DRV_LOG(ERR, "Failed to find the eth_dev" 6420 " for VF-Rep: %s.", name); 6421 ret = -ENODEV; 6422 goto err; 6423 } 6424 6425 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n", 6426 backing_eth_dev->data->port_id); 6427 backing_bp->rep_info[representor.vf_id].vfr_eth_dev = 6428 vf_rep_eth_dev; 6429 backing_bp->num_reps++; 6430 6431 } 6432 6433 rte_kvargs_free(kvlist); 6434 return 0; 6435 6436 err: 6437 /* If num_rep > 1, then rollback already created 6438 * ports, since we'll be failing the probe anyway 6439 */ 6440 if (num_rep > 1) 6441 bnxt_pci_remove_dev_with_reps(backing_eth_dev); 6442 rte_errno = -ret; 6443 rte_kvargs_free(kvlist); 6444 6445 return ret; 6446 } 6447 6448 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 6449 struct rte_pci_device *pci_dev) 6450 { 6451 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 6452 struct rte_eth_dev *backing_eth_dev; 6453 uint16_t num_rep; 6454 int ret = 0; 6455 6456 if (pci_dev->device.devargs) { 6457 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, 6458 ð_da); 6459 if (ret) 6460 return ret; 6461 } 6462 6463 num_rep = eth_da.nb_representor_ports; 6464 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n", 6465 num_rep); 6466 6467 /* We could come here after first level of probe is already invoked 6468 * as part of an application bringup(OVS-DPDK vswitchd), so first check 6469 * for already allocated eth_dev for the backing device (PF/Trusted VF) 6470 */ 6471 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6472 if (backing_eth_dev == NULL) { 6473 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 6474 sizeof(struct bnxt), 6475 eth_dev_pci_specific_init, pci_dev, 6476 bnxt_dev_init, NULL); 6477 6478 if (ret || !num_rep) 6479 return ret; 6480 6481 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6482 } 6483 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n", 6484 backing_eth_dev->data->port_id); 6485 6486 if (!num_rep) 6487 return ret; 6488 6489 /* probe representor ports now */ 6490 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev, 6491 pci_dev->device.devargs->args); 6492 6493 return ret; 6494 } 6495 6496 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 6497 { 6498 struct rte_eth_dev *eth_dev; 6499 6500 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6501 if (!eth_dev) 6502 return 0; /* Invoked typically only by OVS-DPDK, by the 6503 * time it comes here the eth_dev is already 6504 * deleted by rte_eth_dev_close(), so returning 6505 * +ve value will at least help in proper cleanup 6506 */ 6507 6508 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id); 6509 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 6510 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 6511 return rte_eth_dev_destroy(eth_dev, 6512 bnxt_representor_uninit); 6513 else 6514 return rte_eth_dev_destroy(eth_dev, 6515 bnxt_dev_uninit); 6516 } else { 6517 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 6518 } 6519 } 6520 6521 static struct rte_pci_driver bnxt_rte_pmd = { 6522 .id_table = bnxt_pci_id_map, 6523 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 6524 RTE_PCI_DRV_INTR_RMV | 6525 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs 6526 * and OVS-DPDK 6527 */ 6528 .probe = bnxt_pci_probe, 6529 .remove = bnxt_pci_remove, 6530 }; 6531 6532 static bool 6533 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 6534 { 6535 if (strcmp(dev->device->driver->name, drv->driver.name)) 6536 return false; 6537 6538 return true; 6539 } 6540 6541 bool is_bnxt_supported(struct rte_eth_dev *dev) 6542 { 6543 return is_device_supported(dev, &bnxt_rte_pmd); 6544 } 6545 6546 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE); 6547 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 6548 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 6549 6550