1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <rte_ethdev_driver.h> 11 #include <rte_ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 15 #include "bnxt.h" 16 #include "bnxt_cpr.h" 17 #include "bnxt_filter.h" 18 #include "bnxt_hwrm.h" 19 #include "bnxt_irq.h" 20 #include "bnxt_ring.h" 21 #include "bnxt_rxq.h" 22 #include "bnxt_rxr.h" 23 #include "bnxt_stats.h" 24 #include "bnxt_txq.h" 25 #include "bnxt_txr.h" 26 #include "bnxt_vnic.h" 27 #include "hsi_struct_def_dpdk.h" 28 #include "bnxt_nvm_defs.h" 29 #include "bnxt_util.h" 30 31 #define DRV_MODULE_NAME "bnxt" 32 static const char bnxt_version[] = 33 "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n"; 34 int bnxt_logtype_driver; 35 36 #define PCI_VENDOR_ID_BROADCOM 0x14E4 37 38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 41 #define BROADCOM_DEV_ID_57414_VF 0x16c1 42 #define BROADCOM_DEV_ID_57301 0x16c8 43 #define BROADCOM_DEV_ID_57302 0x16c9 44 #define BROADCOM_DEV_ID_57304_PF 0x16ca 45 #define BROADCOM_DEV_ID_57304_VF 0x16cb 46 #define BROADCOM_DEV_ID_57417_MF 0x16cc 47 #define BROADCOM_DEV_ID_NS2 0x16cd 48 #define BROADCOM_DEV_ID_57311 0x16ce 49 #define BROADCOM_DEV_ID_57312 0x16cf 50 #define BROADCOM_DEV_ID_57402 0x16d0 51 #define BROADCOM_DEV_ID_57404 0x16d1 52 #define BROADCOM_DEV_ID_57406_PF 0x16d2 53 #define BROADCOM_DEV_ID_57406_VF 0x16d3 54 #define BROADCOM_DEV_ID_57402_MF 0x16d4 55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5 56 #define BROADCOM_DEV_ID_57412 0x16d6 57 #define BROADCOM_DEV_ID_57414 0x16d7 58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 61 #define BROADCOM_DEV_ID_57412_MF 0x16de 62 #define BROADCOM_DEV_ID_57314 0x16df 63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 68 #define BROADCOM_DEV_ID_57404_MF 0x16e7 69 #define BROADCOM_DEV_ID_57406_MF 0x16e8 70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9 71 #define BROADCOM_DEV_ID_57407_MF 0x16ea 72 #define BROADCOM_DEV_ID_57414_MF 0x16ec 73 #define BROADCOM_DEV_ID_57416_MF 0x16ee 74 #define BROADCOM_DEV_ID_58802 0xd802 75 #define BROADCOM_DEV_ID_58804 0xd804 76 #define BROADCOM_DEV_ID_58808 0x16f0 77 #define BROADCOM_DEV_ID_58802_VF 0xd800 78 79 static const struct rte_pci_id bnxt_pci_id_map[] = { 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 81 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 83 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, 96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, 97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, 98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, 100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, 106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, 107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 122 { .vendor_id = 0, /* sentinel */ }, 123 }; 124 125 #define BNXT_ETH_RSS_SUPPORT ( \ 126 ETH_RSS_IPV4 | \ 127 ETH_RSS_NONFRAG_IPV4_TCP | \ 128 ETH_RSS_NONFRAG_IPV4_UDP | \ 129 ETH_RSS_IPV6 | \ 130 ETH_RSS_NONFRAG_IPV6_TCP | \ 131 ETH_RSS_NONFRAG_IPV6_UDP) 132 133 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 134 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 135 DEV_TX_OFFLOAD_TCP_CKSUM | \ 136 DEV_TX_OFFLOAD_UDP_CKSUM | \ 137 DEV_TX_OFFLOAD_TCP_TSO | \ 138 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 139 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 140 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 141 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 142 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 143 DEV_TX_OFFLOAD_MULTI_SEGS) 144 145 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 146 DEV_RX_OFFLOAD_VLAN_STRIP | \ 147 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 148 DEV_RX_OFFLOAD_UDP_CKSUM | \ 149 DEV_RX_OFFLOAD_TCP_CKSUM | \ 150 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 151 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 152 DEV_RX_OFFLOAD_KEEP_CRC | \ 153 DEV_RX_OFFLOAD_TCP_LRO) 154 155 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 156 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 157 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 158 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 159 160 /***********************/ 161 162 /* 163 * High level utility functions 164 */ 165 166 static void bnxt_free_mem(struct bnxt *bp) 167 { 168 bnxt_free_filter_mem(bp); 169 bnxt_free_vnic_attributes(bp); 170 bnxt_free_vnic_mem(bp); 171 172 bnxt_free_stats(bp); 173 bnxt_free_tx_rings(bp); 174 bnxt_free_rx_rings(bp); 175 } 176 177 static int bnxt_alloc_mem(struct bnxt *bp) 178 { 179 int rc; 180 181 rc = bnxt_alloc_vnic_mem(bp); 182 if (rc) 183 goto alloc_mem_err; 184 185 rc = bnxt_alloc_vnic_attributes(bp); 186 if (rc) 187 goto alloc_mem_err; 188 189 rc = bnxt_alloc_filter_mem(bp); 190 if (rc) 191 goto alloc_mem_err; 192 193 return 0; 194 195 alloc_mem_err: 196 bnxt_free_mem(bp); 197 return rc; 198 } 199 200 static int bnxt_init_chip(struct bnxt *bp) 201 { 202 struct bnxt_rx_queue *rxq; 203 struct rte_eth_link new; 204 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 205 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 206 uint32_t intr_vector = 0; 207 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 208 uint32_t vec = BNXT_MISC_VEC_ID; 209 unsigned int i, j; 210 int rc; 211 212 /* disable uio/vfio intr/eventfd mapping */ 213 rte_intr_disable(intr_handle); 214 215 if (bp->eth_dev->data->mtu > ETHER_MTU) { 216 bp->eth_dev->data->dev_conf.rxmode.offloads |= 217 DEV_RX_OFFLOAD_JUMBO_FRAME; 218 bp->flags |= BNXT_FLAG_JUMBO; 219 } else { 220 bp->eth_dev->data->dev_conf.rxmode.offloads &= 221 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 222 bp->flags &= ~BNXT_FLAG_JUMBO; 223 } 224 225 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 226 if (rc) { 227 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 228 goto err_out; 229 } 230 231 rc = bnxt_alloc_hwrm_rings(bp); 232 if (rc) { 233 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 234 goto err_out; 235 } 236 237 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 238 if (rc) { 239 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 240 goto err_out; 241 } 242 243 rc = bnxt_mq_rx_configure(bp); 244 if (rc) { 245 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 246 goto err_out; 247 } 248 249 /* VNIC configuration */ 250 for (i = 0; i < bp->nr_vnics; i++) { 251 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 252 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 253 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps; 254 255 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0); 256 if (!vnic->fw_grp_ids) { 257 PMD_DRV_LOG(ERR, 258 "Failed to alloc %d bytes for group ids\n", 259 size); 260 rc = -ENOMEM; 261 goto err_out; 262 } 263 memset(vnic->fw_grp_ids, -1, size); 264 265 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 266 if (rc) { 267 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n", 268 i, rc); 269 goto err_out; 270 } 271 272 /* Alloc RSS context only if RSS mode is enabled */ 273 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 274 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic); 275 if (rc) { 276 PMD_DRV_LOG(ERR, 277 "HWRM vnic %d ctx alloc failure rc: %x\n", 278 i, rc); 279 goto err_out; 280 } 281 } 282 283 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 284 if (rc) { 285 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 286 i, rc); 287 goto err_out; 288 } 289 290 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 291 if (rc) { 292 PMD_DRV_LOG(ERR, 293 "HWRM vnic %d filter failure rc: %x\n", 294 i, rc); 295 goto err_out; 296 } 297 298 for (j = 0; j < bp->rx_nr_rings; j++) { 299 rxq = bp->eth_dev->data->rx_queues[j]; 300 301 if (rxq->rx_deferred_start) 302 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 303 } 304 305 rc = bnxt_vnic_rss_configure(bp, vnic); 306 if (rc) { 307 PMD_DRV_LOG(ERR, 308 "HWRM vnic set RSS failure rc: %x\n", rc); 309 goto err_out; 310 } 311 312 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 313 314 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 315 DEV_RX_OFFLOAD_TCP_LRO) 316 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 317 else 318 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 319 } 320 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 321 if (rc) { 322 PMD_DRV_LOG(ERR, 323 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 324 goto err_out; 325 } 326 327 /* check and configure queue intr-vector mapping */ 328 if ((rte_intr_cap_multiple(intr_handle) || 329 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 330 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 331 intr_vector = bp->eth_dev->data->nb_rx_queues; 332 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 333 if (intr_vector > bp->rx_cp_nr_rings) { 334 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 335 bp->rx_cp_nr_rings); 336 return -ENOTSUP; 337 } 338 if (rte_intr_efd_enable(intr_handle, intr_vector)) 339 return -1; 340 } 341 342 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 343 intr_handle->intr_vec = 344 rte_zmalloc("intr_vec", 345 bp->eth_dev->data->nb_rx_queues * 346 sizeof(int), 0); 347 if (intr_handle->intr_vec == NULL) { 348 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 349 " intr_vec", bp->eth_dev->data->nb_rx_queues); 350 return -ENOMEM; 351 } 352 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 353 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 354 intr_handle->intr_vec, intr_handle->nb_efd, 355 intr_handle->max_intr); 356 } 357 358 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 359 queue_id++) { 360 intr_handle->intr_vec[queue_id] = vec; 361 if (vec < base + intr_handle->nb_efd - 1) 362 vec++; 363 } 364 365 /* enable uio/vfio intr/eventfd mapping */ 366 rte_intr_enable(intr_handle); 367 368 rc = bnxt_get_hwrm_link_config(bp, &new); 369 if (rc) { 370 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc); 371 goto err_out; 372 } 373 374 if (!bp->link_info.link_up) { 375 rc = bnxt_set_hwrm_link_config(bp, true); 376 if (rc) { 377 PMD_DRV_LOG(ERR, 378 "HWRM link config failure rc: %x\n", rc); 379 goto err_out; 380 } 381 } 382 bnxt_print_link_info(bp->eth_dev); 383 384 return 0; 385 386 err_out: 387 bnxt_free_all_hwrm_resources(bp); 388 389 /* Some of the error status returned by FW may not be from errno.h */ 390 if (rc > 0) 391 rc = -EIO; 392 393 return rc; 394 } 395 396 static int bnxt_shutdown_nic(struct bnxt *bp) 397 { 398 bnxt_free_all_hwrm_resources(bp); 399 bnxt_free_all_filters(bp); 400 bnxt_free_all_vnics(bp); 401 return 0; 402 } 403 404 static int bnxt_init_nic(struct bnxt *bp) 405 { 406 int rc; 407 408 rc = bnxt_init_ring_grps(bp); 409 if (rc) 410 return rc; 411 412 bnxt_init_vnics(bp); 413 bnxt_init_filters(bp); 414 415 return 0; 416 } 417 418 /* 419 * Device configuration and status function 420 */ 421 422 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 423 struct rte_eth_dev_info *dev_info) 424 { 425 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 426 uint16_t max_vnics, i, j, vpool, vrxq; 427 unsigned int max_rx_rings; 428 429 /* MAC Specifics */ 430 dev_info->max_mac_addrs = bp->max_l2_ctx; 431 dev_info->max_hash_mac_addrs = 0; 432 433 /* PF/VF specifics */ 434 if (BNXT_PF(bp)) 435 dev_info->max_vfs = bp->pdev->max_vfs; 436 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx); 437 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 438 dev_info->max_rx_queues = max_rx_rings; 439 dev_info->max_tx_queues = max_rx_rings; 440 dev_info->reta_size = HW_HASH_INDEX_SIZE; 441 dev_info->hash_key_size = 40; 442 max_vnics = bp->max_vnics; 443 444 /* Fast path specifics */ 445 dev_info->min_rx_bufsize = 1; 446 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN 447 + VLAN_TAG_SIZE; 448 449 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 450 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 451 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 452 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT; 453 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 454 455 /* *INDENT-OFF* */ 456 dev_info->default_rxconf = (struct rte_eth_rxconf) { 457 .rx_thresh = { 458 .pthresh = 8, 459 .hthresh = 8, 460 .wthresh = 0, 461 }, 462 .rx_free_thresh = 32, 463 /* If no descriptors available, pkts are dropped by default */ 464 .rx_drop_en = 1, 465 }; 466 467 dev_info->default_txconf = (struct rte_eth_txconf) { 468 .tx_thresh = { 469 .pthresh = 32, 470 .hthresh = 0, 471 .wthresh = 0, 472 }, 473 .tx_free_thresh = 32, 474 .tx_rs_thresh = 32, 475 }; 476 eth_dev->data->dev_conf.intr_conf.lsc = 1; 477 478 eth_dev->data->dev_conf.intr_conf.rxq = 1; 479 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 480 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 481 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 482 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 483 484 /* *INDENT-ON* */ 485 486 /* 487 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 488 * need further investigation. 489 */ 490 491 /* VMDq resources */ 492 vpool = 64; /* ETH_64_POOLS */ 493 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 494 for (i = 0; i < 4; vpool >>= 1, i++) { 495 if (max_vnics > vpool) { 496 for (j = 0; j < 5; vrxq >>= 1, j++) { 497 if (dev_info->max_rx_queues > vrxq) { 498 if (vpool > vrxq) 499 vpool = vrxq; 500 goto found; 501 } 502 } 503 /* Not enough resources to support VMDq */ 504 break; 505 } 506 } 507 /* Not enough resources to support VMDq */ 508 vpool = 0; 509 vrxq = 0; 510 found: 511 dev_info->max_vmdq_pools = vpool; 512 dev_info->vmdq_queue_num = vrxq; 513 514 dev_info->vmdq_pool_base = 0; 515 dev_info->vmdq_queue_base = 0; 516 } 517 518 /* Configure the device based on the configuration provided */ 519 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 520 { 521 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 522 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 523 int rc; 524 525 bp->rx_queues = (void *)eth_dev->data->rx_queues; 526 bp->tx_queues = (void *)eth_dev->data->tx_queues; 527 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 528 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 529 530 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 531 rc = bnxt_hwrm_check_vf_rings(bp); 532 if (rc) { 533 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 534 return -ENOSPC; 535 } 536 537 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 538 if (rc) { 539 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 540 return -ENOSPC; 541 } 542 } else { 543 /* legacy driver needs to get updated values */ 544 rc = bnxt_hwrm_func_qcaps(bp); 545 if (rc) { 546 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc); 547 return rc; 548 } 549 } 550 551 /* Inherit new configurations */ 552 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 553 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 554 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 555 bp->max_cp_rings || 556 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 557 bp->max_stat_ctx || 558 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps || 559 (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 560 bp->max_vnics < eth_dev->data->nb_rx_queues)) { 561 PMD_DRV_LOG(ERR, 562 "Insufficient resources to support requested config\n"); 563 PMD_DRV_LOG(ERR, 564 "Num Queues Requested: Tx %d, Rx %d\n", 565 eth_dev->data->nb_tx_queues, 566 eth_dev->data->nb_rx_queues); 567 PMD_DRV_LOG(ERR, 568 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 569 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 570 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 571 return -ENOSPC; 572 } 573 574 bp->rx_cp_nr_rings = bp->rx_nr_rings; 575 bp->tx_cp_nr_rings = bp->tx_nr_rings; 576 577 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 578 eth_dev->data->mtu = 579 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 580 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 581 BNXT_NUM_VLANS; 582 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 583 } 584 return 0; 585 } 586 587 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 588 { 589 struct rte_eth_link *link = ð_dev->data->dev_link; 590 591 if (link->link_status) 592 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 593 eth_dev->data->port_id, 594 (uint32_t)link->link_speed, 595 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 596 ("full-duplex") : ("half-duplex\n")); 597 else 598 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 599 eth_dev->data->port_id); 600 } 601 602 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev) 603 { 604 bnxt_print_link_info(eth_dev); 605 return 0; 606 } 607 608 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 609 { 610 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 611 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 612 int vlan_mask = 0; 613 int rc; 614 615 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) { 616 PMD_DRV_LOG(ERR, 617 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 618 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 619 } 620 bp->dev_stopped = 0; 621 622 rc = bnxt_init_chip(bp); 623 if (rc) 624 goto error; 625 626 bnxt_link_update_op(eth_dev, 1); 627 628 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 629 vlan_mask |= ETH_VLAN_FILTER_MASK; 630 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 631 vlan_mask |= ETH_VLAN_STRIP_MASK; 632 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 633 if (rc) 634 goto error; 635 636 bp->flags |= BNXT_FLAG_INIT_DONE; 637 return 0; 638 639 error: 640 bnxt_shutdown_nic(bp); 641 bnxt_free_tx_mbufs(bp); 642 bnxt_free_rx_mbufs(bp); 643 return rc; 644 } 645 646 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 647 { 648 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 649 int rc = 0; 650 651 if (!bp->link_info.link_up) 652 rc = bnxt_set_hwrm_link_config(bp, true); 653 if (!rc) 654 eth_dev->data->dev_link.link_status = 1; 655 656 bnxt_print_link_info(eth_dev); 657 return 0; 658 } 659 660 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 661 { 662 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 663 664 eth_dev->data->dev_link.link_status = 0; 665 bnxt_set_hwrm_link_config(bp, false); 666 bp->link_info.link_up = 0; 667 668 return 0; 669 } 670 671 /* Unload the driver, release resources */ 672 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 673 { 674 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 675 676 bp->flags &= ~BNXT_FLAG_INIT_DONE; 677 if (bp->eth_dev->data->dev_started) { 678 /* TBD: STOP HW queues DMA */ 679 eth_dev->data->dev_link.link_status = 0; 680 } 681 bnxt_set_hwrm_link_config(bp, false); 682 bnxt_hwrm_port_clr_stats(bp); 683 bnxt_free_tx_mbufs(bp); 684 bnxt_free_rx_mbufs(bp); 685 bnxt_shutdown_nic(bp); 686 bp->dev_stopped = 1; 687 } 688 689 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 690 { 691 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 692 693 if (bp->dev_stopped == 0) 694 bnxt_dev_stop_op(eth_dev); 695 696 bnxt_free_mem(bp); 697 if (eth_dev->data->mac_addrs != NULL) { 698 rte_free(eth_dev->data->mac_addrs); 699 eth_dev->data->mac_addrs = NULL; 700 } 701 if (bp->grp_info != NULL) { 702 rte_free(bp->grp_info); 703 bp->grp_info = NULL; 704 } 705 706 bnxt_dev_uninit(eth_dev); 707 } 708 709 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 710 uint32_t index) 711 { 712 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 713 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 714 struct bnxt_vnic_info *vnic; 715 struct bnxt_filter_info *filter, *temp_filter; 716 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS); 717 uint32_t i; 718 719 /* 720 * Loop through all VNICs from the specified filter flow pools to 721 * remove the corresponding MAC addr filter 722 */ 723 for (i = 0; i < pool; i++) { 724 if (!(pool_mask & (1ULL << i))) 725 continue; 726 727 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 728 filter = STAILQ_FIRST(&vnic->filter); 729 while (filter) { 730 temp_filter = STAILQ_NEXT(filter, next); 731 if (filter->mac_index == index) { 732 STAILQ_REMOVE(&vnic->filter, filter, 733 bnxt_filter_info, next); 734 bnxt_hwrm_clear_l2_filter(bp, filter); 735 filter->mac_index = INVALID_MAC_INDEX; 736 memset(&filter->l2_addr, 0, 737 ETHER_ADDR_LEN); 738 STAILQ_INSERT_TAIL( 739 &bp->free_filter_list, 740 filter, next); 741 } 742 filter = temp_filter; 743 } 744 } 745 } 746 } 747 748 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 749 struct ether_addr *mac_addr, 750 uint32_t index, uint32_t pool) 751 { 752 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 753 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]); 754 struct bnxt_filter_info *filter; 755 756 if (BNXT_VF(bp)) { 757 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 758 return -ENOTSUP; 759 } 760 761 if (!vnic) { 762 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 763 return -EINVAL; 764 } 765 /* Attach requested MAC address to the new l2_filter */ 766 STAILQ_FOREACH(filter, &vnic->filter, next) { 767 if (filter->mac_index == index) { 768 PMD_DRV_LOG(ERR, 769 "MAC addr already existed for pool %d\n", pool); 770 return 0; 771 } 772 } 773 filter = bnxt_alloc_filter(bp); 774 if (!filter) { 775 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 776 return -ENODEV; 777 } 778 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 779 filter->mac_index = index; 780 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN); 781 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 782 } 783 784 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 785 { 786 int rc = 0; 787 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 788 struct rte_eth_link new; 789 unsigned int cnt = BNXT_LINK_WAIT_CNT; 790 791 memset(&new, 0, sizeof(new)); 792 do { 793 /* Retrieve link info from hardware */ 794 rc = bnxt_get_hwrm_link_config(bp, &new); 795 if (rc) { 796 new.link_speed = ETH_LINK_SPEED_100M; 797 new.link_duplex = ETH_LINK_FULL_DUPLEX; 798 PMD_DRV_LOG(ERR, 799 "Failed to retrieve link rc = 0x%x!\n", rc); 800 goto out; 801 } 802 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 803 804 if (!wait_to_complete) 805 break; 806 } while (!new.link_status && cnt--); 807 808 out: 809 /* Timed out or success */ 810 if (new.link_status != eth_dev->data->dev_link.link_status || 811 new.link_speed != eth_dev->data->dev_link.link_speed) { 812 memcpy(ð_dev->data->dev_link, &new, 813 sizeof(struct rte_eth_link)); 814 815 _rte_eth_dev_callback_process(eth_dev, 816 RTE_ETH_EVENT_INTR_LSC, 817 NULL); 818 819 bnxt_print_link_info(eth_dev); 820 } 821 822 return rc; 823 } 824 825 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 826 { 827 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 828 struct bnxt_vnic_info *vnic; 829 830 if (bp->vnic_info == NULL) 831 return; 832 833 vnic = &bp->vnic_info[0]; 834 835 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 836 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 837 } 838 839 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 840 { 841 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 842 struct bnxt_vnic_info *vnic; 843 844 if (bp->vnic_info == NULL) 845 return; 846 847 vnic = &bp->vnic_info[0]; 848 849 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 850 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 851 } 852 853 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 854 { 855 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 856 struct bnxt_vnic_info *vnic; 857 858 if (bp->vnic_info == NULL) 859 return; 860 861 vnic = &bp->vnic_info[0]; 862 863 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 864 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 865 } 866 867 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 868 { 869 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 870 struct bnxt_vnic_info *vnic; 871 872 if (bp->vnic_info == NULL) 873 return; 874 875 vnic = &bp->vnic_info[0]; 876 877 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 878 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 879 } 880 881 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 882 struct rte_eth_rss_reta_entry64 *reta_conf, 883 uint16_t reta_size) 884 { 885 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 886 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 887 struct bnxt_vnic_info *vnic; 888 int i; 889 890 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 891 return -EINVAL; 892 893 if (reta_size != HW_HASH_INDEX_SIZE) { 894 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 895 "(%d) must equal the size supported by the hardware " 896 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE); 897 return -EINVAL; 898 } 899 /* Update the RSS VNIC(s) */ 900 for (i = 0; i < MAX_FF_POOLS; i++) { 901 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 902 memcpy(vnic->rss_table, reta_conf, reta_size); 903 904 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 905 } 906 } 907 return 0; 908 } 909 910 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 911 struct rte_eth_rss_reta_entry64 *reta_conf, 912 uint16_t reta_size) 913 { 914 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 915 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 916 struct rte_intr_handle *intr_handle 917 = &bp->pdev->intr_handle; 918 919 /* Retrieve from the default VNIC */ 920 if (!vnic) 921 return -EINVAL; 922 if (!vnic->rss_table) 923 return -EINVAL; 924 925 if (reta_size != HW_HASH_INDEX_SIZE) { 926 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 927 "(%d) must equal the size supported by the hardware " 928 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE); 929 return -EINVAL; 930 } 931 /* EW - need to revisit here copying from uint64_t to uint16_t */ 932 memcpy(reta_conf, vnic->rss_table, reta_size); 933 934 if (rte_intr_allow_others(intr_handle)) { 935 if (eth_dev->data->dev_conf.intr_conf.lsc != 0) 936 bnxt_dev_lsc_intr_setup(eth_dev); 937 } 938 939 return 0; 940 } 941 942 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 943 struct rte_eth_rss_conf *rss_conf) 944 { 945 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 946 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 947 struct bnxt_vnic_info *vnic; 948 uint16_t hash_type = 0; 949 int i; 950 951 /* 952 * If RSS enablement were different than dev_configure, 953 * then return -EINVAL 954 */ 955 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 956 if (!rss_conf->rss_hf) 957 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 958 } else { 959 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 960 return -EINVAL; 961 } 962 963 bp->flags |= BNXT_FLAG_UPDATE_HASH; 964 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf)); 965 966 if (rss_conf->rss_hf & ETH_RSS_IPV4) 967 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 968 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 969 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 970 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 971 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 972 if (rss_conf->rss_hf & ETH_RSS_IPV6) 973 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 974 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 975 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 976 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 977 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 978 979 /* Update the RSS VNIC(s) */ 980 for (i = 0; i < MAX_FF_POOLS; i++) { 981 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 982 vnic->hash_type = hash_type; 983 984 /* 985 * Use the supplied key if the key length is 986 * acceptable and the rss_key is not NULL 987 */ 988 if (rss_conf->rss_key && 989 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE) 990 memcpy(vnic->rss_hash_key, rss_conf->rss_key, 991 rss_conf->rss_key_len); 992 993 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 994 } 995 } 996 return 0; 997 } 998 999 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 1000 struct rte_eth_rss_conf *rss_conf) 1001 { 1002 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1003 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1004 int len; 1005 uint32_t hash_types; 1006 1007 /* RSS configuration is the same for all VNICs */ 1008 if (vnic && vnic->rss_hash_key) { 1009 if (rss_conf->rss_key) { 1010 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 1011 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 1012 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 1013 } 1014 1015 hash_types = vnic->hash_type; 1016 rss_conf->rss_hf = 0; 1017 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 1018 rss_conf->rss_hf |= ETH_RSS_IPV4; 1019 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 1020 } 1021 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 1022 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 1023 hash_types &= 1024 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1025 } 1026 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 1027 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 1028 hash_types &= 1029 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1030 } 1031 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 1032 rss_conf->rss_hf |= ETH_RSS_IPV6; 1033 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1034 } 1035 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 1036 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 1037 hash_types &= 1038 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1039 } 1040 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 1041 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 1042 hash_types &= 1043 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1044 } 1045 if (hash_types) { 1046 PMD_DRV_LOG(ERR, 1047 "Unknwon RSS config from firmware (%08x), RSS disabled", 1048 vnic->hash_type); 1049 return -ENOTSUP; 1050 } 1051 } else { 1052 rss_conf->rss_hf = 0; 1053 } 1054 return 0; 1055 } 1056 1057 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 1058 struct rte_eth_fc_conf *fc_conf) 1059 { 1060 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1061 struct rte_eth_link link_info; 1062 int rc; 1063 1064 rc = bnxt_get_hwrm_link_config(bp, &link_info); 1065 if (rc) 1066 return rc; 1067 1068 memset(fc_conf, 0, sizeof(*fc_conf)); 1069 if (bp->link_info.auto_pause) 1070 fc_conf->autoneg = 1; 1071 switch (bp->link_info.pause) { 1072 case 0: 1073 fc_conf->mode = RTE_FC_NONE; 1074 break; 1075 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 1076 fc_conf->mode = RTE_FC_TX_PAUSE; 1077 break; 1078 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 1079 fc_conf->mode = RTE_FC_RX_PAUSE; 1080 break; 1081 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 1082 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 1083 fc_conf->mode = RTE_FC_FULL; 1084 break; 1085 } 1086 return 0; 1087 } 1088 1089 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 1090 struct rte_eth_fc_conf *fc_conf) 1091 { 1092 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1093 1094 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1095 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 1096 return -ENOTSUP; 1097 } 1098 1099 switch (fc_conf->mode) { 1100 case RTE_FC_NONE: 1101 bp->link_info.auto_pause = 0; 1102 bp->link_info.force_pause = 0; 1103 break; 1104 case RTE_FC_RX_PAUSE: 1105 if (fc_conf->autoneg) { 1106 bp->link_info.auto_pause = 1107 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1108 bp->link_info.force_pause = 0; 1109 } else { 1110 bp->link_info.auto_pause = 0; 1111 bp->link_info.force_pause = 1112 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1113 } 1114 break; 1115 case RTE_FC_TX_PAUSE: 1116 if (fc_conf->autoneg) { 1117 bp->link_info.auto_pause = 1118 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 1119 bp->link_info.force_pause = 0; 1120 } else { 1121 bp->link_info.auto_pause = 0; 1122 bp->link_info.force_pause = 1123 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 1124 } 1125 break; 1126 case RTE_FC_FULL: 1127 if (fc_conf->autoneg) { 1128 bp->link_info.auto_pause = 1129 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 1130 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1131 bp->link_info.force_pause = 0; 1132 } else { 1133 bp->link_info.auto_pause = 0; 1134 bp->link_info.force_pause = 1135 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 1136 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1137 } 1138 break; 1139 } 1140 return bnxt_set_hwrm_link_config(bp, true); 1141 } 1142 1143 /* Add UDP tunneling port */ 1144 static int 1145 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 1146 struct rte_eth_udp_tunnel *udp_tunnel) 1147 { 1148 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1149 uint16_t tunnel_type = 0; 1150 int rc = 0; 1151 1152 switch (udp_tunnel->prot_type) { 1153 case RTE_TUNNEL_TYPE_VXLAN: 1154 if (bp->vxlan_port_cnt) { 1155 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1156 udp_tunnel->udp_port); 1157 if (bp->vxlan_port != udp_tunnel->udp_port) { 1158 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1159 return -ENOSPC; 1160 } 1161 bp->vxlan_port_cnt++; 1162 return 0; 1163 } 1164 tunnel_type = 1165 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 1166 bp->vxlan_port_cnt++; 1167 break; 1168 case RTE_TUNNEL_TYPE_GENEVE: 1169 if (bp->geneve_port_cnt) { 1170 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1171 udp_tunnel->udp_port); 1172 if (bp->geneve_port != udp_tunnel->udp_port) { 1173 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1174 return -ENOSPC; 1175 } 1176 bp->geneve_port_cnt++; 1177 return 0; 1178 } 1179 tunnel_type = 1180 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 1181 bp->geneve_port_cnt++; 1182 break; 1183 default: 1184 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1185 return -ENOTSUP; 1186 } 1187 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 1188 tunnel_type); 1189 return rc; 1190 } 1191 1192 static int 1193 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 1194 struct rte_eth_udp_tunnel *udp_tunnel) 1195 { 1196 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1197 uint16_t tunnel_type = 0; 1198 uint16_t port = 0; 1199 int rc = 0; 1200 1201 switch (udp_tunnel->prot_type) { 1202 case RTE_TUNNEL_TYPE_VXLAN: 1203 if (!bp->vxlan_port_cnt) { 1204 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1205 return -EINVAL; 1206 } 1207 if (bp->vxlan_port != udp_tunnel->udp_port) { 1208 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1209 udp_tunnel->udp_port, bp->vxlan_port); 1210 return -EINVAL; 1211 } 1212 if (--bp->vxlan_port_cnt) 1213 return 0; 1214 1215 tunnel_type = 1216 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 1217 port = bp->vxlan_fw_dst_port_id; 1218 break; 1219 case RTE_TUNNEL_TYPE_GENEVE: 1220 if (!bp->geneve_port_cnt) { 1221 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1222 return -EINVAL; 1223 } 1224 if (bp->geneve_port != udp_tunnel->udp_port) { 1225 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1226 udp_tunnel->udp_port, bp->geneve_port); 1227 return -EINVAL; 1228 } 1229 if (--bp->geneve_port_cnt) 1230 return 0; 1231 1232 tunnel_type = 1233 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 1234 port = bp->geneve_fw_dst_port_id; 1235 break; 1236 default: 1237 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1238 return -ENOTSUP; 1239 } 1240 1241 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 1242 if (!rc) { 1243 if (tunnel_type == 1244 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) 1245 bp->vxlan_port = 0; 1246 if (tunnel_type == 1247 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) 1248 bp->geneve_port = 0; 1249 } 1250 return rc; 1251 } 1252 1253 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1254 { 1255 struct bnxt_filter_info *filter, *temp_filter, *new_filter; 1256 struct bnxt_vnic_info *vnic; 1257 unsigned int i; 1258 int rc = 0; 1259 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN; 1260 1261 /* Cycle through all VNICs */ 1262 for (i = 0; i < bp->nr_vnics; i++) { 1263 /* 1264 * For each VNIC and each associated filter(s) 1265 * if VLAN exists && VLAN matches vlan_id 1266 * remove the MAC+VLAN filter 1267 * add a new MAC only filter 1268 * else 1269 * VLAN filter doesn't exist, just skip and continue 1270 */ 1271 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 1272 filter = STAILQ_FIRST(&vnic->filter); 1273 while (filter) { 1274 temp_filter = STAILQ_NEXT(filter, next); 1275 1276 if (filter->enables & chk && 1277 filter->l2_ovlan == vlan_id) { 1278 /* Must delete the filter */ 1279 STAILQ_REMOVE(&vnic->filter, filter, 1280 bnxt_filter_info, next); 1281 bnxt_hwrm_clear_l2_filter(bp, filter); 1282 STAILQ_INSERT_TAIL( 1283 &bp->free_filter_list, 1284 filter, next); 1285 1286 /* 1287 * Need to examine to see if the MAC 1288 * filter already existed or not before 1289 * allocating a new one 1290 */ 1291 1292 new_filter = bnxt_alloc_filter(bp); 1293 if (!new_filter) { 1294 PMD_DRV_LOG(ERR, 1295 "MAC/VLAN filter alloc failed\n"); 1296 rc = -ENOMEM; 1297 goto exit; 1298 } 1299 STAILQ_INSERT_TAIL(&vnic->filter, 1300 new_filter, next); 1301 /* Inherit MAC from previous filter */ 1302 new_filter->mac_index = 1303 filter->mac_index; 1304 memcpy(new_filter->l2_addr, 1305 filter->l2_addr, ETHER_ADDR_LEN); 1306 /* MAC only filter */ 1307 rc = bnxt_hwrm_set_l2_filter(bp, 1308 vnic->fw_vnic_id, 1309 new_filter); 1310 if (rc) 1311 goto exit; 1312 PMD_DRV_LOG(INFO, 1313 "Del Vlan filter for %d\n", 1314 vlan_id); 1315 } 1316 filter = temp_filter; 1317 } 1318 } 1319 } 1320 exit: 1321 return rc; 1322 } 1323 1324 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1325 { 1326 struct bnxt_filter_info *filter, *temp_filter, *new_filter; 1327 struct bnxt_vnic_info *vnic; 1328 unsigned int i; 1329 int rc = 0; 1330 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 1331 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 1332 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 1333 1334 /* Cycle through all VNICs */ 1335 for (i = 0; i < bp->nr_vnics; i++) { 1336 /* 1337 * For each VNIC and each associated filter(s) 1338 * if VLAN exists: 1339 * if VLAN matches vlan_id 1340 * VLAN filter already exists, just skip and continue 1341 * else 1342 * add a new MAC+VLAN filter 1343 * else 1344 * Remove the old MAC only filter 1345 * Add a new MAC+VLAN filter 1346 */ 1347 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 1348 filter = STAILQ_FIRST(&vnic->filter); 1349 while (filter) { 1350 temp_filter = STAILQ_NEXT(filter, next); 1351 1352 if (filter->enables & chk) { 1353 if (filter->l2_ovlan == vlan_id) 1354 goto cont; 1355 } else { 1356 /* Must delete the MAC filter */ 1357 STAILQ_REMOVE(&vnic->filter, filter, 1358 bnxt_filter_info, next); 1359 bnxt_hwrm_clear_l2_filter(bp, filter); 1360 filter->l2_ovlan = 0; 1361 STAILQ_INSERT_TAIL( 1362 &bp->free_filter_list, 1363 filter, next); 1364 } 1365 new_filter = bnxt_alloc_filter(bp); 1366 if (!new_filter) { 1367 PMD_DRV_LOG(ERR, 1368 "MAC/VLAN filter alloc failed\n"); 1369 rc = -ENOMEM; 1370 goto exit; 1371 } 1372 STAILQ_INSERT_TAIL(&vnic->filter, new_filter, 1373 next); 1374 /* Inherit MAC from the previous filter */ 1375 new_filter->mac_index = filter->mac_index; 1376 memcpy(new_filter->l2_addr, filter->l2_addr, 1377 ETHER_ADDR_LEN); 1378 /* MAC + VLAN ID filter */ 1379 new_filter->l2_ivlan = vlan_id; 1380 new_filter->l2_ivlan_mask = 0xF000; 1381 new_filter->enables |= en; 1382 rc = bnxt_hwrm_set_l2_filter(bp, 1383 vnic->fw_vnic_id, 1384 new_filter); 1385 if (rc) 1386 goto exit; 1387 PMD_DRV_LOG(INFO, 1388 "Added Vlan filter for %d\n", vlan_id); 1389 cont: 1390 filter = temp_filter; 1391 } 1392 } 1393 } 1394 exit: 1395 return rc; 1396 } 1397 1398 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 1399 uint16_t vlan_id, int on) 1400 { 1401 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1402 1403 /* These operations apply to ALL existing MAC/VLAN filters */ 1404 if (on) 1405 return bnxt_add_vlan_filter(bp, vlan_id); 1406 else 1407 return bnxt_del_vlan_filter(bp, vlan_id); 1408 } 1409 1410 static int 1411 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 1412 { 1413 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1414 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1415 unsigned int i; 1416 1417 if (mask & ETH_VLAN_FILTER_MASK) { 1418 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 1419 /* Remove any VLAN filters programmed */ 1420 for (i = 0; i < 4095; i++) 1421 bnxt_del_vlan_filter(bp, i); 1422 } 1423 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 1424 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 1425 } 1426 1427 if (mask & ETH_VLAN_STRIP_MASK) { 1428 /* Enable or disable VLAN stripping */ 1429 for (i = 0; i < bp->nr_vnics; i++) { 1430 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1431 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1432 vnic->vlan_strip = true; 1433 else 1434 vnic->vlan_strip = false; 1435 bnxt_hwrm_vnic_cfg(bp, vnic); 1436 } 1437 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 1438 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 1439 } 1440 1441 if (mask & ETH_VLAN_EXTEND_MASK) 1442 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n"); 1443 1444 return 0; 1445 } 1446 1447 static int 1448 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr) 1449 { 1450 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1451 /* Default Filter is tied to VNIC 0 */ 1452 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1453 struct bnxt_filter_info *filter; 1454 int rc; 1455 1456 if (BNXT_VF(bp)) 1457 return -EPERM; 1458 1459 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr)); 1460 1461 STAILQ_FOREACH(filter, &vnic->filter, next) { 1462 /* Default Filter is at Index 0 */ 1463 if (filter->mac_index != 0) 1464 continue; 1465 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 1466 if (rc) 1467 return rc; 1468 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN); 1469 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN); 1470 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX; 1471 filter->enables |= 1472 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR | 1473 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK; 1474 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1475 if (rc) 1476 return rc; 1477 filter->mac_index = 0; 1478 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 1479 } 1480 1481 return 0; 1482 } 1483 1484 static int 1485 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 1486 struct ether_addr *mc_addr_set, 1487 uint32_t nb_mc_addr) 1488 { 1489 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1490 char *mc_addr_list = (char *)mc_addr_set; 1491 struct bnxt_vnic_info *vnic; 1492 uint32_t off = 0, i = 0; 1493 1494 vnic = &bp->vnic_info[0]; 1495 1496 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 1497 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1498 goto allmulti; 1499 } 1500 1501 /* TODO Check for Duplicate mcast addresses */ 1502 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1503 for (i = 0; i < nb_mc_addr; i++) { 1504 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN); 1505 off += ETHER_ADDR_LEN; 1506 } 1507 1508 vnic->mc_addr_cnt = i; 1509 1510 allmulti: 1511 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1512 } 1513 1514 static int 1515 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 1516 { 1517 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1518 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 1519 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 1520 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 1521 int ret; 1522 1523 ret = snprintf(fw_version, fw_size, "%d.%d.%d", 1524 fw_major, fw_minor, fw_updt); 1525 1526 ret += 1; /* add the size of '\0' */ 1527 if (fw_size < (uint32_t)ret) 1528 return ret; 1529 else 1530 return 0; 1531 } 1532 1533 static void 1534 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 1535 struct rte_eth_rxq_info *qinfo) 1536 { 1537 struct bnxt_rx_queue *rxq; 1538 1539 rxq = dev->data->rx_queues[queue_id]; 1540 1541 qinfo->mp = rxq->mb_pool; 1542 qinfo->scattered_rx = dev->data->scattered_rx; 1543 qinfo->nb_desc = rxq->nb_rx_desc; 1544 1545 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 1546 qinfo->conf.rx_drop_en = 0; 1547 qinfo->conf.rx_deferred_start = 0; 1548 } 1549 1550 static void 1551 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 1552 struct rte_eth_txq_info *qinfo) 1553 { 1554 struct bnxt_tx_queue *txq; 1555 1556 txq = dev->data->tx_queues[queue_id]; 1557 1558 qinfo->nb_desc = txq->nb_tx_desc; 1559 1560 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 1561 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 1562 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 1563 1564 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 1565 qinfo->conf.tx_rs_thresh = 0; 1566 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1567 } 1568 1569 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 1570 { 1571 struct bnxt *bp = eth_dev->data->dev_private; 1572 struct rte_eth_dev_info dev_info; 1573 uint32_t max_dev_mtu; 1574 uint32_t rc = 0; 1575 uint32_t i; 1576 1577 bnxt_dev_info_get_op(eth_dev, &dev_info); 1578 max_dev_mtu = dev_info.max_rx_pktlen - 1579 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2; 1580 1581 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) { 1582 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n", 1583 ETHER_MIN_MTU, max_dev_mtu); 1584 return -EINVAL; 1585 } 1586 1587 1588 if (new_mtu > ETHER_MTU) { 1589 bp->flags |= BNXT_FLAG_JUMBO; 1590 bp->eth_dev->data->dev_conf.rxmode.offloads |= 1591 DEV_RX_OFFLOAD_JUMBO_FRAME; 1592 } else { 1593 bp->eth_dev->data->dev_conf.rxmode.offloads &= 1594 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1595 bp->flags &= ~BNXT_FLAG_JUMBO; 1596 } 1597 1598 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = 1599 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; 1600 1601 eth_dev->data->mtu = new_mtu; 1602 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu); 1603 1604 for (i = 0; i < bp->nr_vnics; i++) { 1605 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1606 uint16_t size = 0; 1607 1608 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN + 1609 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; 1610 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 1611 if (rc) 1612 break; 1613 1614 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 1615 size -= RTE_PKTMBUF_HEADROOM; 1616 1617 if (size < new_mtu) { 1618 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 1619 if (rc) 1620 return rc; 1621 } 1622 } 1623 1624 return rc; 1625 } 1626 1627 static int 1628 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 1629 { 1630 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1631 uint16_t vlan = bp->vlan; 1632 int rc; 1633 1634 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1635 PMD_DRV_LOG(ERR, 1636 "PVID cannot be modified for this function\n"); 1637 return -ENOTSUP; 1638 } 1639 bp->vlan = on ? pvid : 0; 1640 1641 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 1642 if (rc) 1643 bp->vlan = vlan; 1644 return rc; 1645 } 1646 1647 static int 1648 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 1649 { 1650 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1651 1652 return bnxt_hwrm_port_led_cfg(bp, true); 1653 } 1654 1655 static int 1656 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 1657 { 1658 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1659 1660 return bnxt_hwrm_port_led_cfg(bp, false); 1661 } 1662 1663 static uint32_t 1664 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1665 { 1666 uint32_t desc = 0, raw_cons = 0, cons; 1667 struct bnxt_cp_ring_info *cpr; 1668 struct bnxt_rx_queue *rxq; 1669 struct rx_pkt_cmpl *rxcmp; 1670 uint16_t cmp_type; 1671 uint8_t cmp = 1; 1672 bool valid; 1673 1674 rxq = dev->data->rx_queues[rx_queue_id]; 1675 cpr = rxq->cp_ring; 1676 valid = cpr->valid; 1677 1678 while (raw_cons < rxq->nb_rx_desc) { 1679 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 1680 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1681 1682 if (!CMPL_VALID(rxcmp, valid)) 1683 goto nothing_to_do; 1684 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid); 1685 cmp_type = CMP_TYPE(rxcmp); 1686 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) { 1687 cmp = (rte_le_to_cpu_32( 1688 ((struct rx_tpa_end_cmpl *) 1689 (rxcmp))->agg_bufs_v1) & 1690 RX_TPA_END_CMPL_AGG_BUFS_MASK) >> 1691 RX_TPA_END_CMPL_AGG_BUFS_SFT; 1692 desc++; 1693 } else if (cmp_type == 0x11) { 1694 desc++; 1695 cmp = (rxcmp->agg_bufs_v1 & 1696 RX_PKT_CMPL_AGG_BUFS_MASK) >> 1697 RX_PKT_CMPL_AGG_BUFS_SFT; 1698 } else { 1699 cmp = 1; 1700 } 1701 nothing_to_do: 1702 raw_cons += cmp ? cmp : 2; 1703 } 1704 1705 return desc; 1706 } 1707 1708 static int 1709 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 1710 { 1711 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 1712 struct bnxt_rx_ring_info *rxr; 1713 struct bnxt_cp_ring_info *cpr; 1714 struct bnxt_sw_rx_bd *rx_buf; 1715 struct rx_pkt_cmpl *rxcmp; 1716 uint32_t cons, cp_cons; 1717 1718 if (!rxq) 1719 return -EINVAL; 1720 1721 cpr = rxq->cp_ring; 1722 rxr = rxq->rx_ring; 1723 1724 if (offset >= rxq->nb_rx_desc) 1725 return -EINVAL; 1726 1727 cons = RING_CMP(cpr->cp_ring_struct, offset); 1728 cp_cons = cpr->cp_raw_cons; 1729 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1730 1731 if (cons > cp_cons) { 1732 if (CMPL_VALID(rxcmp, cpr->valid)) 1733 return RTE_ETH_RX_DESC_DONE; 1734 } else { 1735 if (CMPL_VALID(rxcmp, !cpr->valid)) 1736 return RTE_ETH_RX_DESC_DONE; 1737 } 1738 rx_buf = &rxr->rx_buf_ring[cons]; 1739 if (rx_buf->mbuf == NULL) 1740 return RTE_ETH_RX_DESC_UNAVAIL; 1741 1742 1743 return RTE_ETH_RX_DESC_AVAIL; 1744 } 1745 1746 static int 1747 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 1748 { 1749 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 1750 struct bnxt_tx_ring_info *txr; 1751 struct bnxt_cp_ring_info *cpr; 1752 struct bnxt_sw_tx_bd *tx_buf; 1753 struct tx_pkt_cmpl *txcmp; 1754 uint32_t cons, cp_cons; 1755 1756 if (!txq) 1757 return -EINVAL; 1758 1759 cpr = txq->cp_ring; 1760 txr = txq->tx_ring; 1761 1762 if (offset >= txq->nb_tx_desc) 1763 return -EINVAL; 1764 1765 cons = RING_CMP(cpr->cp_ring_struct, offset); 1766 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1767 cp_cons = cpr->cp_raw_cons; 1768 1769 if (cons > cp_cons) { 1770 if (CMPL_VALID(txcmp, cpr->valid)) 1771 return RTE_ETH_TX_DESC_UNAVAIL; 1772 } else { 1773 if (CMPL_VALID(txcmp, !cpr->valid)) 1774 return RTE_ETH_TX_DESC_UNAVAIL; 1775 } 1776 tx_buf = &txr->tx_buf_ring[cons]; 1777 if (tx_buf->mbuf == NULL) 1778 return RTE_ETH_TX_DESC_DONE; 1779 1780 return RTE_ETH_TX_DESC_FULL; 1781 } 1782 1783 static struct bnxt_filter_info * 1784 bnxt_match_and_validate_ether_filter(struct bnxt *bp, 1785 struct rte_eth_ethertype_filter *efilter, 1786 struct bnxt_vnic_info *vnic0, 1787 struct bnxt_vnic_info *vnic, 1788 int *ret) 1789 { 1790 struct bnxt_filter_info *mfilter = NULL; 1791 int match = 0; 1792 *ret = 0; 1793 1794 if (efilter->ether_type == ETHER_TYPE_IPv4 || 1795 efilter->ether_type == ETHER_TYPE_IPv6) { 1796 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in" 1797 " ethertype filter.", efilter->ether_type); 1798 *ret = -EINVAL; 1799 goto exit; 1800 } 1801 if (efilter->queue >= bp->rx_nr_rings) { 1802 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 1803 *ret = -EINVAL; 1804 goto exit; 1805 } 1806 1807 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); 1808 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]); 1809 if (vnic == NULL) { 1810 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 1811 *ret = -EINVAL; 1812 goto exit; 1813 } 1814 1815 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 1816 STAILQ_FOREACH(mfilter, &vnic0->filter, next) { 1817 if ((!memcmp(efilter->mac_addr.addr_bytes, 1818 mfilter->l2_addr, ETHER_ADDR_LEN) && 1819 mfilter->flags == 1820 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP && 1821 mfilter->ethertype == efilter->ether_type)) { 1822 match = 1; 1823 break; 1824 } 1825 } 1826 } else { 1827 STAILQ_FOREACH(mfilter, &vnic->filter, next) 1828 if ((!memcmp(efilter->mac_addr.addr_bytes, 1829 mfilter->l2_addr, ETHER_ADDR_LEN) && 1830 mfilter->ethertype == efilter->ether_type && 1831 mfilter->flags == 1832 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) { 1833 match = 1; 1834 break; 1835 } 1836 } 1837 1838 if (match) 1839 *ret = -EEXIST; 1840 1841 exit: 1842 return mfilter; 1843 } 1844 1845 static int 1846 bnxt_ethertype_filter(struct rte_eth_dev *dev, 1847 enum rte_filter_op filter_op, 1848 void *arg) 1849 { 1850 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1851 struct rte_eth_ethertype_filter *efilter = 1852 (struct rte_eth_ethertype_filter *)arg; 1853 struct bnxt_filter_info *bfilter, *filter1; 1854 struct bnxt_vnic_info *vnic, *vnic0; 1855 int ret; 1856 1857 if (filter_op == RTE_ETH_FILTER_NOP) 1858 return 0; 1859 1860 if (arg == NULL) { 1861 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 1862 filter_op); 1863 return -EINVAL; 1864 } 1865 1866 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); 1867 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]); 1868 1869 switch (filter_op) { 1870 case RTE_ETH_FILTER_ADD: 1871 bnxt_match_and_validate_ether_filter(bp, efilter, 1872 vnic0, vnic, &ret); 1873 if (ret < 0) 1874 return ret; 1875 1876 bfilter = bnxt_get_unused_filter(bp); 1877 if (bfilter == NULL) { 1878 PMD_DRV_LOG(ERR, 1879 "Not enough resources for a new filter.\n"); 1880 return -ENOMEM; 1881 } 1882 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 1883 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes, 1884 ETHER_ADDR_LEN); 1885 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes, 1886 ETHER_ADDR_LEN); 1887 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 1888 bfilter->ethertype = efilter->ether_type; 1889 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 1890 1891 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0); 1892 if (filter1 == NULL) { 1893 ret = -1; 1894 goto cleanup; 1895 } 1896 bfilter->enables |= 1897 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 1898 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 1899 1900 bfilter->dst_id = vnic->fw_vnic_id; 1901 1902 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 1903 bfilter->flags = 1904 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 1905 } 1906 1907 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 1908 if (ret) 1909 goto cleanup; 1910 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 1911 break; 1912 case RTE_ETH_FILTER_DELETE: 1913 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter, 1914 vnic0, vnic, &ret); 1915 if (ret == -EEXIST) { 1916 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1); 1917 1918 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info, 1919 next); 1920 bnxt_free_filter(bp, filter1); 1921 } else if (ret == 0) { 1922 PMD_DRV_LOG(ERR, "No matching filter found\n"); 1923 } 1924 break; 1925 default: 1926 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 1927 ret = -EINVAL; 1928 goto error; 1929 } 1930 return ret; 1931 cleanup: 1932 bnxt_free_filter(bp, bfilter); 1933 error: 1934 return ret; 1935 } 1936 1937 static inline int 1938 parse_ntuple_filter(struct bnxt *bp, 1939 struct rte_eth_ntuple_filter *nfilter, 1940 struct bnxt_filter_info *bfilter) 1941 { 1942 uint32_t en = 0; 1943 1944 if (nfilter->queue >= bp->rx_nr_rings) { 1945 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue); 1946 return -EINVAL; 1947 } 1948 1949 switch (nfilter->dst_port_mask) { 1950 case UINT16_MAX: 1951 bfilter->dst_port_mask = -1; 1952 bfilter->dst_port = nfilter->dst_port; 1953 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT | 1954 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 1955 break; 1956 default: 1957 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 1958 return -EINVAL; 1959 } 1960 1961 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 1962 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 1963 1964 switch (nfilter->proto_mask) { 1965 case UINT8_MAX: 1966 if (nfilter->proto == 17) /* IPPROTO_UDP */ 1967 bfilter->ip_protocol = 17; 1968 else if (nfilter->proto == 6) /* IPPROTO_TCP */ 1969 bfilter->ip_protocol = 6; 1970 else 1971 return -EINVAL; 1972 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 1973 break; 1974 default: 1975 PMD_DRV_LOG(ERR, "invalid protocol mask."); 1976 return -EINVAL; 1977 } 1978 1979 switch (nfilter->dst_ip_mask) { 1980 case UINT32_MAX: 1981 bfilter->dst_ipaddr_mask[0] = -1; 1982 bfilter->dst_ipaddr[0] = nfilter->dst_ip; 1983 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR | 1984 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 1985 break; 1986 default: 1987 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 1988 return -EINVAL; 1989 } 1990 1991 switch (nfilter->src_ip_mask) { 1992 case UINT32_MAX: 1993 bfilter->src_ipaddr_mask[0] = -1; 1994 bfilter->src_ipaddr[0] = nfilter->src_ip; 1995 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR | 1996 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 1997 break; 1998 default: 1999 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 2000 return -EINVAL; 2001 } 2002 2003 switch (nfilter->src_port_mask) { 2004 case UINT16_MAX: 2005 bfilter->src_port_mask = -1; 2006 bfilter->src_port = nfilter->src_port; 2007 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT | 2008 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2009 break; 2010 default: 2011 PMD_DRV_LOG(ERR, "invalid src_port mask."); 2012 return -EINVAL; 2013 } 2014 2015 //TODO Priority 2016 //nfilter->priority = (uint8_t)filter->priority; 2017 2018 bfilter->enables = en; 2019 return 0; 2020 } 2021 2022 static struct bnxt_filter_info* 2023 bnxt_match_ntuple_filter(struct bnxt *bp, 2024 struct bnxt_filter_info *bfilter, 2025 struct bnxt_vnic_info **mvnic) 2026 { 2027 struct bnxt_filter_info *mfilter = NULL; 2028 int i; 2029 2030 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2031 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2032 STAILQ_FOREACH(mfilter, &vnic->filter, next) { 2033 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] && 2034 bfilter->src_ipaddr_mask[0] == 2035 mfilter->src_ipaddr_mask[0] && 2036 bfilter->src_port == mfilter->src_port && 2037 bfilter->src_port_mask == mfilter->src_port_mask && 2038 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] && 2039 bfilter->dst_ipaddr_mask[0] == 2040 mfilter->dst_ipaddr_mask[0] && 2041 bfilter->dst_port == mfilter->dst_port && 2042 bfilter->dst_port_mask == mfilter->dst_port_mask && 2043 bfilter->flags == mfilter->flags && 2044 bfilter->enables == mfilter->enables) { 2045 if (mvnic) 2046 *mvnic = vnic; 2047 return mfilter; 2048 } 2049 } 2050 } 2051 return NULL; 2052 } 2053 2054 static int 2055 bnxt_cfg_ntuple_filter(struct bnxt *bp, 2056 struct rte_eth_ntuple_filter *nfilter, 2057 enum rte_filter_op filter_op) 2058 { 2059 struct bnxt_filter_info *bfilter, *mfilter, *filter1; 2060 struct bnxt_vnic_info *vnic, *vnic0, *mvnic; 2061 int ret; 2062 2063 if (nfilter->flags != RTE_5TUPLE_FLAGS) { 2064 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 2065 return -EINVAL; 2066 } 2067 2068 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) { 2069 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n"); 2070 return -EINVAL; 2071 } 2072 2073 bfilter = bnxt_get_unused_filter(bp); 2074 if (bfilter == NULL) { 2075 PMD_DRV_LOG(ERR, 2076 "Not enough resources for a new filter.\n"); 2077 return -ENOMEM; 2078 } 2079 ret = parse_ntuple_filter(bp, nfilter, bfilter); 2080 if (ret < 0) 2081 goto free_filter; 2082 2083 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]); 2084 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); 2085 filter1 = STAILQ_FIRST(&vnic0->filter); 2086 if (filter1 == NULL) { 2087 ret = -1; 2088 goto free_filter; 2089 } 2090 2091 bfilter->dst_id = vnic->fw_vnic_id; 2092 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2093 bfilter->enables |= 2094 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2095 bfilter->ethertype = 0x800; 2096 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2097 2098 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic); 2099 2100 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2101 bfilter->dst_id == mfilter->dst_id) { 2102 PMD_DRV_LOG(ERR, "filter exists.\n"); 2103 ret = -EEXIST; 2104 goto free_filter; 2105 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2106 bfilter->dst_id != mfilter->dst_id) { 2107 mfilter->dst_id = vnic->fw_vnic_id; 2108 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter); 2109 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next); 2110 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next); 2111 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n"); 2112 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n"); 2113 goto free_filter; 2114 } 2115 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2116 PMD_DRV_LOG(ERR, "filter doesn't exist."); 2117 ret = -ENOENT; 2118 goto free_filter; 2119 } 2120 2121 if (filter_op == RTE_ETH_FILTER_ADD) { 2122 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2123 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2124 if (ret) 2125 goto free_filter; 2126 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2127 } else { 2128 if (mfilter == NULL) { 2129 /* This should not happen. But for Coverity! */ 2130 ret = -ENOENT; 2131 goto free_filter; 2132 } 2133 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter); 2134 2135 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next); 2136 bnxt_free_filter(bp, mfilter); 2137 mfilter->fw_l2_filter_id = -1; 2138 bnxt_free_filter(bp, bfilter); 2139 bfilter->fw_l2_filter_id = -1; 2140 } 2141 2142 return 0; 2143 free_filter: 2144 bfilter->fw_l2_filter_id = -1; 2145 bnxt_free_filter(bp, bfilter); 2146 return ret; 2147 } 2148 2149 static int 2150 bnxt_ntuple_filter(struct rte_eth_dev *dev, 2151 enum rte_filter_op filter_op, 2152 void *arg) 2153 { 2154 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2155 int ret; 2156 2157 if (filter_op == RTE_ETH_FILTER_NOP) 2158 return 0; 2159 2160 if (arg == NULL) { 2161 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2162 filter_op); 2163 return -EINVAL; 2164 } 2165 2166 switch (filter_op) { 2167 case RTE_ETH_FILTER_ADD: 2168 ret = bnxt_cfg_ntuple_filter(bp, 2169 (struct rte_eth_ntuple_filter *)arg, 2170 filter_op); 2171 break; 2172 case RTE_ETH_FILTER_DELETE: 2173 ret = bnxt_cfg_ntuple_filter(bp, 2174 (struct rte_eth_ntuple_filter *)arg, 2175 filter_op); 2176 break; 2177 default: 2178 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2179 ret = -EINVAL; 2180 break; 2181 } 2182 return ret; 2183 } 2184 2185 static int 2186 bnxt_parse_fdir_filter(struct bnxt *bp, 2187 struct rte_eth_fdir_filter *fdir, 2188 struct bnxt_filter_info *filter) 2189 { 2190 enum rte_fdir_mode fdir_mode = 2191 bp->eth_dev->data->dev_conf.fdir_conf.mode; 2192 struct bnxt_vnic_info *vnic0, *vnic; 2193 struct bnxt_filter_info *filter1; 2194 uint32_t en = 0; 2195 int i; 2196 2197 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 2198 return -EINVAL; 2199 2200 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci; 2201 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID; 2202 2203 switch (fdir->input.flow_type) { 2204 case RTE_ETH_FLOW_IPV4: 2205 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 2206 /* FALLTHROUGH */ 2207 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip; 2208 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2209 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip; 2210 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2211 filter->ip_protocol = fdir->input.flow.ip4_flow.proto; 2212 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2213 filter->ip_addr_type = 2214 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2215 filter->src_ipaddr_mask[0] = 0xffffffff; 2216 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2217 filter->dst_ipaddr_mask[0] = 0xffffffff; 2218 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2219 filter->ethertype = 0x800; 2220 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2221 break; 2222 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 2223 filter->src_port = fdir->input.flow.tcp4_flow.src_port; 2224 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2225 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port; 2226 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2227 filter->dst_port_mask = 0xffff; 2228 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2229 filter->src_port_mask = 0xffff; 2230 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2231 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip; 2232 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2233 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip; 2234 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2235 filter->ip_protocol = 6; 2236 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2237 filter->ip_addr_type = 2238 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2239 filter->src_ipaddr_mask[0] = 0xffffffff; 2240 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2241 filter->dst_ipaddr_mask[0] = 0xffffffff; 2242 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2243 filter->ethertype = 0x800; 2244 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2245 break; 2246 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 2247 filter->src_port = fdir->input.flow.udp4_flow.src_port; 2248 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2249 filter->dst_port = fdir->input.flow.udp4_flow.dst_port; 2250 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2251 filter->dst_port_mask = 0xffff; 2252 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2253 filter->src_port_mask = 0xffff; 2254 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2255 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip; 2256 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2257 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip; 2258 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2259 filter->ip_protocol = 17; 2260 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2261 filter->ip_addr_type = 2262 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2263 filter->src_ipaddr_mask[0] = 0xffffffff; 2264 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2265 filter->dst_ipaddr_mask[0] = 0xffffffff; 2266 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2267 filter->ethertype = 0x800; 2268 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2269 break; 2270 case RTE_ETH_FLOW_IPV6: 2271 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 2272 /* FALLTHROUGH */ 2273 filter->ip_addr_type = 2274 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2275 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto; 2276 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2277 rte_memcpy(filter->src_ipaddr, 2278 fdir->input.flow.ipv6_flow.src_ip, 16); 2279 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2280 rte_memcpy(filter->dst_ipaddr, 2281 fdir->input.flow.ipv6_flow.dst_ip, 16); 2282 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2283 memset(filter->dst_ipaddr_mask, 0xff, 16); 2284 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2285 memset(filter->src_ipaddr_mask, 0xff, 16); 2286 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2287 filter->ethertype = 0x86dd; 2288 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2289 break; 2290 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 2291 filter->src_port = fdir->input.flow.tcp6_flow.src_port; 2292 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2293 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port; 2294 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2295 filter->dst_port_mask = 0xffff; 2296 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2297 filter->src_port_mask = 0xffff; 2298 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2299 filter->ip_addr_type = 2300 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2301 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto; 2302 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2303 rte_memcpy(filter->src_ipaddr, 2304 fdir->input.flow.tcp6_flow.ip.src_ip, 16); 2305 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2306 rte_memcpy(filter->dst_ipaddr, 2307 fdir->input.flow.tcp6_flow.ip.dst_ip, 16); 2308 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2309 memset(filter->dst_ipaddr_mask, 0xff, 16); 2310 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2311 memset(filter->src_ipaddr_mask, 0xff, 16); 2312 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2313 filter->ethertype = 0x86dd; 2314 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2315 break; 2316 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 2317 filter->src_port = fdir->input.flow.udp6_flow.src_port; 2318 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2319 filter->dst_port = fdir->input.flow.udp6_flow.dst_port; 2320 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2321 filter->dst_port_mask = 0xffff; 2322 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2323 filter->src_port_mask = 0xffff; 2324 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2325 filter->ip_addr_type = 2326 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2327 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto; 2328 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2329 rte_memcpy(filter->src_ipaddr, 2330 fdir->input.flow.udp6_flow.ip.src_ip, 16); 2331 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2332 rte_memcpy(filter->dst_ipaddr, 2333 fdir->input.flow.udp6_flow.ip.dst_ip, 16); 2334 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2335 memset(filter->dst_ipaddr_mask, 0xff, 16); 2336 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2337 memset(filter->src_ipaddr_mask, 0xff, 16); 2338 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2339 filter->ethertype = 0x86dd; 2340 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2341 break; 2342 case RTE_ETH_FLOW_L2_PAYLOAD: 2343 filter->ethertype = fdir->input.flow.l2_flow.ether_type; 2344 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2345 break; 2346 case RTE_ETH_FLOW_VXLAN: 2347 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2348 return -EINVAL; 2349 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2350 filter->tunnel_type = 2351 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN; 2352 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2353 break; 2354 case RTE_ETH_FLOW_NVGRE: 2355 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2356 return -EINVAL; 2357 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2358 filter->tunnel_type = 2359 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE; 2360 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2361 break; 2362 case RTE_ETH_FLOW_UNKNOWN: 2363 case RTE_ETH_FLOW_RAW: 2364 case RTE_ETH_FLOW_FRAG_IPV4: 2365 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 2366 case RTE_ETH_FLOW_FRAG_IPV6: 2367 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 2368 case RTE_ETH_FLOW_IPV6_EX: 2369 case RTE_ETH_FLOW_IPV6_TCP_EX: 2370 case RTE_ETH_FLOW_IPV6_UDP_EX: 2371 case RTE_ETH_FLOW_GENEVE: 2372 /* FALLTHROUGH */ 2373 default: 2374 return -EINVAL; 2375 } 2376 2377 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); 2378 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]); 2379 if (vnic == NULL) { 2380 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue); 2381 return -EINVAL; 2382 } 2383 2384 2385 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 2386 rte_memcpy(filter->dst_macaddr, 2387 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6); 2388 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2389 } 2390 2391 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) { 2392 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2393 filter1 = STAILQ_FIRST(&vnic0->filter); 2394 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0); 2395 } else { 2396 filter->dst_id = vnic->fw_vnic_id; 2397 for (i = 0; i < ETHER_ADDR_LEN; i++) 2398 if (filter->dst_macaddr[i] == 0x00) 2399 filter1 = STAILQ_FIRST(&vnic0->filter); 2400 else 2401 filter1 = bnxt_get_l2_filter(bp, filter, vnic); 2402 } 2403 2404 if (filter1 == NULL) 2405 return -EINVAL; 2406 2407 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2408 filter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2409 2410 filter->enables = en; 2411 2412 return 0; 2413 } 2414 2415 static struct bnxt_filter_info * 2416 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf, 2417 struct bnxt_vnic_info **mvnic) 2418 { 2419 struct bnxt_filter_info *mf = NULL; 2420 int i; 2421 2422 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2423 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2424 2425 STAILQ_FOREACH(mf, &vnic->filter, next) { 2426 if (mf->filter_type == nf->filter_type && 2427 mf->flags == nf->flags && 2428 mf->src_port == nf->src_port && 2429 mf->src_port_mask == nf->src_port_mask && 2430 mf->dst_port == nf->dst_port && 2431 mf->dst_port_mask == nf->dst_port_mask && 2432 mf->ip_protocol == nf->ip_protocol && 2433 mf->ip_addr_type == nf->ip_addr_type && 2434 mf->ethertype == nf->ethertype && 2435 mf->vni == nf->vni && 2436 mf->tunnel_type == nf->tunnel_type && 2437 mf->l2_ovlan == nf->l2_ovlan && 2438 mf->l2_ovlan_mask == nf->l2_ovlan_mask && 2439 mf->l2_ivlan == nf->l2_ivlan && 2440 mf->l2_ivlan_mask == nf->l2_ivlan_mask && 2441 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) && 2442 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask, 2443 ETHER_ADDR_LEN) && 2444 !memcmp(mf->src_macaddr, nf->src_macaddr, 2445 ETHER_ADDR_LEN) && 2446 !memcmp(mf->dst_macaddr, nf->dst_macaddr, 2447 ETHER_ADDR_LEN) && 2448 !memcmp(mf->src_ipaddr, nf->src_ipaddr, 2449 sizeof(nf->src_ipaddr)) && 2450 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask, 2451 sizeof(nf->src_ipaddr_mask)) && 2452 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr, 2453 sizeof(nf->dst_ipaddr)) && 2454 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask, 2455 sizeof(nf->dst_ipaddr_mask))) { 2456 if (mvnic) 2457 *mvnic = vnic; 2458 return mf; 2459 } 2460 } 2461 } 2462 return NULL; 2463 } 2464 2465 static int 2466 bnxt_fdir_filter(struct rte_eth_dev *dev, 2467 enum rte_filter_op filter_op, 2468 void *arg) 2469 { 2470 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2471 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg; 2472 struct bnxt_filter_info *filter, *match; 2473 struct bnxt_vnic_info *vnic, *mvnic; 2474 int ret = 0, i; 2475 2476 if (filter_op == RTE_ETH_FILTER_NOP) 2477 return 0; 2478 2479 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 2480 return -EINVAL; 2481 2482 switch (filter_op) { 2483 case RTE_ETH_FILTER_ADD: 2484 case RTE_ETH_FILTER_DELETE: 2485 /* FALLTHROUGH */ 2486 filter = bnxt_get_unused_filter(bp); 2487 if (filter == NULL) { 2488 PMD_DRV_LOG(ERR, 2489 "Not enough resources for a new flow.\n"); 2490 return -ENOMEM; 2491 } 2492 2493 ret = bnxt_parse_fdir_filter(bp, fdir, filter); 2494 if (ret != 0) 2495 goto free_filter; 2496 filter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2497 2498 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2499 vnic = STAILQ_FIRST(&bp->ff_pool[0]); 2500 else 2501 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]); 2502 2503 match = bnxt_match_fdir(bp, filter, &mvnic); 2504 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { 2505 if (match->dst_id == vnic->fw_vnic_id) { 2506 PMD_DRV_LOG(ERR, "Flow already exists.\n"); 2507 ret = -EEXIST; 2508 goto free_filter; 2509 } else { 2510 match->dst_id = vnic->fw_vnic_id; 2511 ret = bnxt_hwrm_set_ntuple_filter(bp, 2512 match->dst_id, 2513 match); 2514 STAILQ_REMOVE(&mvnic->filter, match, 2515 bnxt_filter_info, next); 2516 STAILQ_INSERT_TAIL(&vnic->filter, match, next); 2517 PMD_DRV_LOG(ERR, 2518 "Filter with matching pattern exist\n"); 2519 PMD_DRV_LOG(ERR, 2520 "Updated it to new destination q\n"); 2521 goto free_filter; 2522 } 2523 } 2524 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2525 PMD_DRV_LOG(ERR, "Flow does not exist.\n"); 2526 ret = -ENOENT; 2527 goto free_filter; 2528 } 2529 2530 if (filter_op == RTE_ETH_FILTER_ADD) { 2531 ret = bnxt_hwrm_set_ntuple_filter(bp, 2532 filter->dst_id, 2533 filter); 2534 if (ret) 2535 goto free_filter; 2536 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2537 } else { 2538 ret = bnxt_hwrm_clear_ntuple_filter(bp, match); 2539 STAILQ_REMOVE(&vnic->filter, match, 2540 bnxt_filter_info, next); 2541 bnxt_free_filter(bp, match); 2542 filter->fw_l2_filter_id = -1; 2543 bnxt_free_filter(bp, filter); 2544 } 2545 break; 2546 case RTE_ETH_FILTER_FLUSH: 2547 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2548 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2549 2550 STAILQ_FOREACH(filter, &vnic->filter, next) { 2551 if (filter->filter_type == 2552 HWRM_CFA_NTUPLE_FILTER) { 2553 ret = 2554 bnxt_hwrm_clear_ntuple_filter(bp, 2555 filter); 2556 STAILQ_REMOVE(&vnic->filter, filter, 2557 bnxt_filter_info, next); 2558 } 2559 } 2560 } 2561 return ret; 2562 case RTE_ETH_FILTER_UPDATE: 2563 case RTE_ETH_FILTER_STATS: 2564 case RTE_ETH_FILTER_INFO: 2565 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op); 2566 break; 2567 default: 2568 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 2569 ret = -EINVAL; 2570 break; 2571 } 2572 return ret; 2573 2574 free_filter: 2575 filter->fw_l2_filter_id = -1; 2576 bnxt_free_filter(bp, filter); 2577 return ret; 2578 } 2579 2580 static int 2581 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused, 2582 enum rte_filter_type filter_type, 2583 enum rte_filter_op filter_op, void *arg) 2584 { 2585 int ret = 0; 2586 2587 switch (filter_type) { 2588 case RTE_ETH_FILTER_TUNNEL: 2589 PMD_DRV_LOG(ERR, 2590 "filter type: %d: To be implemented\n", filter_type); 2591 break; 2592 case RTE_ETH_FILTER_FDIR: 2593 ret = bnxt_fdir_filter(dev, filter_op, arg); 2594 break; 2595 case RTE_ETH_FILTER_NTUPLE: 2596 ret = bnxt_ntuple_filter(dev, filter_op, arg); 2597 break; 2598 case RTE_ETH_FILTER_ETHERTYPE: 2599 ret = bnxt_ethertype_filter(dev, filter_op, arg); 2600 break; 2601 case RTE_ETH_FILTER_GENERIC: 2602 if (filter_op != RTE_ETH_FILTER_GET) 2603 return -EINVAL; 2604 *(const void **)arg = &bnxt_flow_ops; 2605 break; 2606 default: 2607 PMD_DRV_LOG(ERR, 2608 "Filter type (%d) not supported", filter_type); 2609 ret = -EINVAL; 2610 break; 2611 } 2612 return ret; 2613 } 2614 2615 static const uint32_t * 2616 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 2617 { 2618 static const uint32_t ptypes[] = { 2619 RTE_PTYPE_L2_ETHER_VLAN, 2620 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 2621 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 2622 RTE_PTYPE_L4_ICMP, 2623 RTE_PTYPE_L4_TCP, 2624 RTE_PTYPE_L4_UDP, 2625 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 2626 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 2627 RTE_PTYPE_INNER_L4_ICMP, 2628 RTE_PTYPE_INNER_L4_TCP, 2629 RTE_PTYPE_INNER_L4_UDP, 2630 RTE_PTYPE_UNKNOWN 2631 }; 2632 2633 if (dev->rx_pkt_burst == bnxt_recv_pkts) 2634 return ptypes; 2635 return NULL; 2636 } 2637 2638 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 2639 int reg_win) 2640 { 2641 uint32_t reg_base = *reg_arr & 0xfffff000; 2642 uint32_t win_off; 2643 int i; 2644 2645 for (i = 0; i < count; i++) { 2646 if ((reg_arr[i] & 0xfffff000) != reg_base) 2647 return -ERANGE; 2648 } 2649 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 2650 rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off)); 2651 return 0; 2652 } 2653 2654 static int bnxt_map_ptp_regs(struct bnxt *bp) 2655 { 2656 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2657 uint32_t *reg_arr; 2658 int rc, i; 2659 2660 reg_arr = ptp->rx_regs; 2661 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 2662 if (rc) 2663 return rc; 2664 2665 reg_arr = ptp->tx_regs; 2666 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 2667 if (rc) 2668 return rc; 2669 2670 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 2671 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 2672 2673 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 2674 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 2675 2676 return 0; 2677 } 2678 2679 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 2680 { 2681 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 + 2682 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16)); 2683 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 + 2684 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20)); 2685 } 2686 2687 static uint64_t bnxt_cc_read(struct bnxt *bp) 2688 { 2689 uint64_t ns; 2690 2691 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2692 BNXT_GRCPF_REG_SYNC_TIME)); 2693 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2694 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 2695 return ns; 2696 } 2697 2698 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 2699 { 2700 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2701 uint32_t fifo; 2702 2703 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2704 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 2705 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 2706 return -EAGAIN; 2707 2708 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2709 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 2710 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2711 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 2712 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2713 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 2714 2715 return 0; 2716 } 2717 2718 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 2719 { 2720 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2721 struct bnxt_pf_info *pf = &bp->pf; 2722 uint16_t port_id; 2723 uint32_t fifo; 2724 2725 if (!ptp) 2726 return -ENODEV; 2727 2728 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2729 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 2730 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 2731 return -EAGAIN; 2732 2733 port_id = pf->port_id; 2734 rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 2735 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV])); 2736 2737 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2738 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 2739 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 2740 /* bnxt_clr_rx_ts(bp); TBD */ 2741 return -EBUSY; 2742 } 2743 2744 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2745 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 2746 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2747 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 2748 2749 return 0; 2750 } 2751 2752 static int 2753 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 2754 { 2755 uint64_t ns; 2756 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2757 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2758 2759 if (!ptp) 2760 return 0; 2761 2762 ns = rte_timespec_to_ns(ts); 2763 /* Set the timecounters to a new value. */ 2764 ptp->tc.nsec = ns; 2765 2766 return 0; 2767 } 2768 2769 static int 2770 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 2771 { 2772 uint64_t ns, systime_cycles; 2773 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2774 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2775 2776 if (!ptp) 2777 return 0; 2778 2779 systime_cycles = bnxt_cc_read(bp); 2780 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 2781 *ts = rte_ns_to_timespec(ns); 2782 2783 return 0; 2784 } 2785 static int 2786 bnxt_timesync_enable(struct rte_eth_dev *dev) 2787 { 2788 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2789 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2790 uint32_t shift = 0; 2791 2792 if (!ptp) 2793 return 0; 2794 2795 ptp->rx_filter = 1; 2796 ptp->tx_tstamp_en = 1; 2797 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 2798 2799 if (!bnxt_hwrm_ptp_cfg(bp)) 2800 bnxt_map_ptp_regs(bp); 2801 2802 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 2803 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 2804 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 2805 2806 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 2807 ptp->tc.cc_shift = shift; 2808 ptp->tc.nsec_mask = (1ULL << shift) - 1; 2809 2810 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 2811 ptp->rx_tstamp_tc.cc_shift = shift; 2812 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 2813 2814 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 2815 ptp->tx_tstamp_tc.cc_shift = shift; 2816 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 2817 2818 return 0; 2819 } 2820 2821 static int 2822 bnxt_timesync_disable(struct rte_eth_dev *dev) 2823 { 2824 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2825 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2826 2827 if (!ptp) 2828 return 0; 2829 2830 ptp->rx_filter = 0; 2831 ptp->tx_tstamp_en = 0; 2832 ptp->rxctl = 0; 2833 2834 bnxt_hwrm_ptp_cfg(bp); 2835 2836 bnxt_unmap_ptp_regs(bp); 2837 2838 return 0; 2839 } 2840 2841 static int 2842 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 2843 struct timespec *timestamp, 2844 uint32_t flags __rte_unused) 2845 { 2846 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2847 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2848 uint64_t rx_tstamp_cycles = 0; 2849 uint64_t ns; 2850 2851 if (!ptp) 2852 return 0; 2853 2854 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 2855 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 2856 *timestamp = rte_ns_to_timespec(ns); 2857 return 0; 2858 } 2859 2860 static int 2861 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 2862 struct timespec *timestamp) 2863 { 2864 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2865 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2866 uint64_t tx_tstamp_cycles = 0; 2867 uint64_t ns; 2868 2869 if (!ptp) 2870 return 0; 2871 2872 bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 2873 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 2874 *timestamp = rte_ns_to_timespec(ns); 2875 2876 return 0; 2877 } 2878 2879 static int 2880 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 2881 { 2882 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2883 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2884 2885 if (!ptp) 2886 return 0; 2887 2888 ptp->tc.nsec += delta; 2889 2890 return 0; 2891 } 2892 2893 static int 2894 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 2895 { 2896 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2897 int rc; 2898 uint32_t dir_entries; 2899 uint32_t entry_length; 2900 2901 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n", 2902 bp->pdev->addr.domain, bp->pdev->addr.bus, 2903 bp->pdev->addr.devid, bp->pdev->addr.function); 2904 2905 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 2906 if (rc != 0) 2907 return rc; 2908 2909 return dir_entries * entry_length; 2910 } 2911 2912 static int 2913 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 2914 struct rte_dev_eeprom_info *in_eeprom) 2915 { 2916 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2917 uint32_t index; 2918 uint32_t offset; 2919 2920 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 2921 "len = %d\n", bp->pdev->addr.domain, 2922 bp->pdev->addr.bus, bp->pdev->addr.devid, 2923 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 2924 2925 if (in_eeprom->offset == 0) /* special offset value to get directory */ 2926 return bnxt_get_nvram_directory(bp, in_eeprom->length, 2927 in_eeprom->data); 2928 2929 index = in_eeprom->offset >> 24; 2930 offset = in_eeprom->offset & 0xffffff; 2931 2932 if (index != 0) 2933 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 2934 in_eeprom->length, in_eeprom->data); 2935 2936 return 0; 2937 } 2938 2939 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 2940 { 2941 switch (dir_type) { 2942 case BNX_DIR_TYPE_CHIMP_PATCH: 2943 case BNX_DIR_TYPE_BOOTCODE: 2944 case BNX_DIR_TYPE_BOOTCODE_2: 2945 case BNX_DIR_TYPE_APE_FW: 2946 case BNX_DIR_TYPE_APE_PATCH: 2947 case BNX_DIR_TYPE_KONG_FW: 2948 case BNX_DIR_TYPE_KONG_PATCH: 2949 case BNX_DIR_TYPE_BONO_FW: 2950 case BNX_DIR_TYPE_BONO_PATCH: 2951 /* FALLTHROUGH */ 2952 return true; 2953 } 2954 2955 return false; 2956 } 2957 2958 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 2959 { 2960 switch (dir_type) { 2961 case BNX_DIR_TYPE_AVS: 2962 case BNX_DIR_TYPE_EXP_ROM_MBA: 2963 case BNX_DIR_TYPE_PCIE: 2964 case BNX_DIR_TYPE_TSCF_UCODE: 2965 case BNX_DIR_TYPE_EXT_PHY: 2966 case BNX_DIR_TYPE_CCM: 2967 case BNX_DIR_TYPE_ISCSI_BOOT: 2968 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2969 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2970 /* FALLTHROUGH */ 2971 return true; 2972 } 2973 2974 return false; 2975 } 2976 2977 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 2978 { 2979 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2980 bnxt_dir_type_is_other_exec_format(dir_type); 2981 } 2982 2983 static int 2984 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 2985 struct rte_dev_eeprom_info *in_eeprom) 2986 { 2987 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2988 uint8_t index, dir_op; 2989 uint16_t type, ext, ordinal, attr; 2990 2991 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 2992 "len = %d\n", bp->pdev->addr.domain, 2993 bp->pdev->addr.bus, bp->pdev->addr.devid, 2994 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 2995 2996 if (!BNXT_PF(bp)) { 2997 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 2998 return -EINVAL; 2999 } 3000 3001 type = in_eeprom->magic >> 16; 3002 3003 if (type == 0xffff) { /* special value for directory operations */ 3004 index = in_eeprom->magic & 0xff; 3005 dir_op = in_eeprom->magic >> 8; 3006 if (index == 0) 3007 return -EINVAL; 3008 switch (dir_op) { 3009 case 0x0e: /* erase */ 3010 if (in_eeprom->offset != ~in_eeprom->magic) 3011 return -EINVAL; 3012 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3013 default: 3014 return -EINVAL; 3015 } 3016 } 3017 3018 /* Create or re-write an NVM item: */ 3019 if (bnxt_dir_type_is_executable(type) == true) 3020 return -EOPNOTSUPP; 3021 ext = in_eeprom->magic & 0xffff; 3022 ordinal = in_eeprom->offset >> 16; 3023 attr = in_eeprom->offset & 0xffff; 3024 3025 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3026 in_eeprom->data, in_eeprom->length); 3027 return 0; 3028 } 3029 3030 /* 3031 * Initialization 3032 */ 3033 3034 static const struct eth_dev_ops bnxt_dev_ops = { 3035 .dev_infos_get = bnxt_dev_info_get_op, 3036 .dev_close = bnxt_dev_close_op, 3037 .dev_configure = bnxt_dev_configure_op, 3038 .dev_start = bnxt_dev_start_op, 3039 .dev_stop = bnxt_dev_stop_op, 3040 .dev_set_link_up = bnxt_dev_set_link_up_op, 3041 .dev_set_link_down = bnxt_dev_set_link_down_op, 3042 .stats_get = bnxt_stats_get_op, 3043 .stats_reset = bnxt_stats_reset_op, 3044 .rx_queue_setup = bnxt_rx_queue_setup_op, 3045 .rx_queue_release = bnxt_rx_queue_release_op, 3046 .tx_queue_setup = bnxt_tx_queue_setup_op, 3047 .tx_queue_release = bnxt_tx_queue_release_op, 3048 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3049 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3050 .reta_update = bnxt_reta_update_op, 3051 .reta_query = bnxt_reta_query_op, 3052 .rss_hash_update = bnxt_rss_hash_update_op, 3053 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3054 .link_update = bnxt_link_update_op, 3055 .promiscuous_enable = bnxt_promiscuous_enable_op, 3056 .promiscuous_disable = bnxt_promiscuous_disable_op, 3057 .allmulticast_enable = bnxt_allmulticast_enable_op, 3058 .allmulticast_disable = bnxt_allmulticast_disable_op, 3059 .mac_addr_add = bnxt_mac_addr_add_op, 3060 .mac_addr_remove = bnxt_mac_addr_remove_op, 3061 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3062 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3063 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3064 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3065 .vlan_filter_set = bnxt_vlan_filter_set_op, 3066 .vlan_offload_set = bnxt_vlan_offload_set_op, 3067 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3068 .mtu_set = bnxt_mtu_set_op, 3069 .mac_addr_set = bnxt_set_default_mac_addr_op, 3070 .xstats_get = bnxt_dev_xstats_get_op, 3071 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3072 .xstats_reset = bnxt_dev_xstats_reset_op, 3073 .fw_version_get = bnxt_fw_version_get, 3074 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3075 .rxq_info_get = bnxt_rxq_info_get_op, 3076 .txq_info_get = bnxt_txq_info_get_op, 3077 .dev_led_on = bnxt_dev_led_on_op, 3078 .dev_led_off = bnxt_dev_led_off_op, 3079 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op, 3080 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op, 3081 .rx_queue_count = bnxt_rx_queue_count_op, 3082 .rx_descriptor_status = bnxt_rx_descriptor_status_op, 3083 .tx_descriptor_status = bnxt_tx_descriptor_status_op, 3084 .rx_queue_start = bnxt_rx_queue_start, 3085 .rx_queue_stop = bnxt_rx_queue_stop, 3086 .tx_queue_start = bnxt_tx_queue_start, 3087 .tx_queue_stop = bnxt_tx_queue_stop, 3088 .filter_ctrl = bnxt_filter_ctrl_op, 3089 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3090 .get_eeprom_length = bnxt_get_eeprom_length_op, 3091 .get_eeprom = bnxt_get_eeprom_op, 3092 .set_eeprom = bnxt_set_eeprom_op, 3093 .timesync_enable = bnxt_timesync_enable, 3094 .timesync_disable = bnxt_timesync_disable, 3095 .timesync_read_time = bnxt_timesync_read_time, 3096 .timesync_write_time = bnxt_timesync_write_time, 3097 .timesync_adjust_time = bnxt_timesync_adjust_time, 3098 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3099 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3100 }; 3101 3102 static bool bnxt_vf_pciid(uint16_t id) 3103 { 3104 if (id == BROADCOM_DEV_ID_57304_VF || 3105 id == BROADCOM_DEV_ID_57406_VF || 3106 id == BROADCOM_DEV_ID_5731X_VF || 3107 id == BROADCOM_DEV_ID_5741X_VF || 3108 id == BROADCOM_DEV_ID_57414_VF || 3109 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 || 3110 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 || 3111 id == BROADCOM_DEV_ID_58802_VF) 3112 return true; 3113 return false; 3114 } 3115 3116 bool bnxt_stratus_device(struct bnxt *bp) 3117 { 3118 uint16_t id = bp->pdev->id.device_id; 3119 3120 if (id == BROADCOM_DEV_ID_STRATUS_NIC || 3121 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 || 3122 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2) 3123 return true; 3124 return false; 3125 } 3126 3127 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 3128 { 3129 struct bnxt *bp = eth_dev->data->dev_private; 3130 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3131 int rc; 3132 3133 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 3134 if (!pci_dev->mem_resource[0].addr) { 3135 PMD_DRV_LOG(ERR, 3136 "Cannot find PCI device base address, aborting\n"); 3137 rc = -ENODEV; 3138 goto init_err_disable; 3139 } 3140 3141 bp->eth_dev = eth_dev; 3142 bp->pdev = pci_dev; 3143 3144 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 3145 if (!bp->bar0) { 3146 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n"); 3147 rc = -ENOMEM; 3148 goto init_err_release; 3149 } 3150 3151 if (!pci_dev->mem_resource[2].addr) { 3152 PMD_DRV_LOG(ERR, 3153 "Cannot find PCI device BAR 2 address, aborting\n"); 3154 rc = -ENODEV; 3155 goto init_err_release; 3156 } else { 3157 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 3158 } 3159 3160 return 0; 3161 3162 init_err_release: 3163 if (bp->bar0) 3164 bp->bar0 = NULL; 3165 if (bp->doorbell_base) 3166 bp->doorbell_base = NULL; 3167 3168 init_err_disable: 3169 3170 return rc; 3171 } 3172 3173 3174 #define ALLOW_FUNC(x) \ 3175 { \ 3176 typeof(x) arg = (x); \ 3177 bp->pf.vf_req_fwd[((arg) >> 5)] &= \ 3178 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \ 3179 } 3180 static int 3181 bnxt_dev_init(struct rte_eth_dev *eth_dev) 3182 { 3183 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3184 char mz_name[RTE_MEMZONE_NAMESIZE]; 3185 const struct rte_memzone *mz = NULL; 3186 static int version_printed; 3187 uint32_t total_alloc_len; 3188 rte_iova_t mz_phys_addr; 3189 struct bnxt *bp; 3190 int rc; 3191 3192 if (version_printed++ == 0) 3193 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 3194 3195 rte_eth_copy_pci_info(eth_dev, pci_dev); 3196 3197 bp = eth_dev->data->dev_private; 3198 3199 bp->dev_stopped = 1; 3200 3201 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3202 goto skip_init; 3203 3204 if (bnxt_vf_pciid(pci_dev->id.device_id)) 3205 bp->flags |= BNXT_FLAG_VF; 3206 3207 rc = bnxt_init_board(eth_dev); 3208 if (rc) { 3209 PMD_DRV_LOG(ERR, 3210 "Board initialization failed rc: %x\n", rc); 3211 goto error; 3212 } 3213 skip_init: 3214 eth_dev->dev_ops = &bnxt_dev_ops; 3215 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 3216 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 3217 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3218 return 0; 3219 3220 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) { 3221 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 3222 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain, 3223 pci_dev->addr.bus, pci_dev->addr.devid, 3224 pci_dev->addr.function, "rx_port_stats"); 3225 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 3226 mz = rte_memzone_lookup(mz_name); 3227 total_alloc_len = RTE_CACHE_LINE_ROUNDUP( 3228 sizeof(struct rx_port_stats) + 512); 3229 if (!mz) { 3230 mz = rte_memzone_reserve(mz_name, total_alloc_len, 3231 SOCKET_ID_ANY, 3232 RTE_MEMZONE_2MB | 3233 RTE_MEMZONE_SIZE_HINT_ONLY | 3234 RTE_MEMZONE_IOVA_CONTIG); 3235 if (mz == NULL) 3236 return -ENOMEM; 3237 } 3238 memset(mz->addr, 0, mz->len); 3239 mz_phys_addr = mz->iova; 3240 if ((unsigned long)mz->addr == mz_phys_addr) { 3241 PMD_DRV_LOG(WARNING, 3242 "Memzone physical address same as virtual.\n"); 3243 PMD_DRV_LOG(WARNING, 3244 "Using rte_mem_virt2iova()\n"); 3245 mz_phys_addr = rte_mem_virt2iova(mz->addr); 3246 if (mz_phys_addr == 0) { 3247 PMD_DRV_LOG(ERR, 3248 "unable to map address to physical memory\n"); 3249 return -ENOMEM; 3250 } 3251 } 3252 3253 bp->rx_mem_zone = (const void *)mz; 3254 bp->hw_rx_port_stats = mz->addr; 3255 bp->hw_rx_port_stats_map = mz_phys_addr; 3256 3257 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 3258 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain, 3259 pci_dev->addr.bus, pci_dev->addr.devid, 3260 pci_dev->addr.function, "tx_port_stats"); 3261 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 3262 mz = rte_memzone_lookup(mz_name); 3263 total_alloc_len = RTE_CACHE_LINE_ROUNDUP( 3264 sizeof(struct tx_port_stats) + 512); 3265 if (!mz) { 3266 mz = rte_memzone_reserve(mz_name, 3267 total_alloc_len, 3268 SOCKET_ID_ANY, 3269 RTE_MEMZONE_2MB | 3270 RTE_MEMZONE_SIZE_HINT_ONLY | 3271 RTE_MEMZONE_IOVA_CONTIG); 3272 if (mz == NULL) 3273 return -ENOMEM; 3274 } 3275 memset(mz->addr, 0, mz->len); 3276 mz_phys_addr = mz->iova; 3277 if ((unsigned long)mz->addr == mz_phys_addr) { 3278 PMD_DRV_LOG(WARNING, 3279 "Memzone physical address same as virtual.\n"); 3280 PMD_DRV_LOG(WARNING, 3281 "Using rte_mem_virt2iova()\n"); 3282 mz_phys_addr = rte_mem_virt2iova(mz->addr); 3283 if (mz_phys_addr == 0) { 3284 PMD_DRV_LOG(ERR, 3285 "unable to map address to physical memory\n"); 3286 return -ENOMEM; 3287 } 3288 } 3289 3290 bp->tx_mem_zone = (const void *)mz; 3291 bp->hw_tx_port_stats = mz->addr; 3292 bp->hw_tx_port_stats_map = mz_phys_addr; 3293 3294 bp->flags |= BNXT_FLAG_PORT_STATS; 3295 } 3296 3297 rc = bnxt_alloc_hwrm_resources(bp); 3298 if (rc) { 3299 PMD_DRV_LOG(ERR, 3300 "hwrm resource allocation failure rc: %x\n", rc); 3301 goto error_free; 3302 } 3303 rc = bnxt_hwrm_ver_get(bp); 3304 if (rc) 3305 goto error_free; 3306 rc = bnxt_hwrm_queue_qportcfg(bp); 3307 if (rc) { 3308 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n"); 3309 goto error_free; 3310 } 3311 3312 rc = bnxt_hwrm_func_qcfg(bp); 3313 if (rc) { 3314 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n"); 3315 goto error_free; 3316 } 3317 3318 /* Get the MAX capabilities for this function */ 3319 rc = bnxt_hwrm_func_qcaps(bp); 3320 if (rc) { 3321 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc); 3322 goto error_free; 3323 } 3324 if (bp->max_tx_rings == 0) { 3325 PMD_DRV_LOG(ERR, "No TX rings available!\n"); 3326 rc = -EBUSY; 3327 goto error_free; 3328 } 3329 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 3330 ETHER_ADDR_LEN * bp->max_l2_ctx, 0); 3331 if (eth_dev->data->mac_addrs == NULL) { 3332 PMD_DRV_LOG(ERR, 3333 "Failed to alloc %u bytes needed to store MAC addr tbl", 3334 ETHER_ADDR_LEN * bp->max_l2_ctx); 3335 rc = -ENOMEM; 3336 goto error_free; 3337 } 3338 3339 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) { 3340 PMD_DRV_LOG(ERR, 3341 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n", 3342 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1], 3343 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3], 3344 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]); 3345 rc = -EINVAL; 3346 goto error_free; 3347 } 3348 /* Copy the permanent MAC from the qcap response address now. */ 3349 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr)); 3350 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN); 3351 3352 if (bp->max_ring_grps < bp->rx_cp_nr_rings) { 3353 /* 1 ring is for default completion ring */ 3354 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n"); 3355 rc = -ENOSPC; 3356 goto error_free; 3357 } 3358 3359 bp->grp_info = rte_zmalloc("bnxt_grp_info", 3360 sizeof(*bp->grp_info) * bp->max_ring_grps, 0); 3361 if (!bp->grp_info) { 3362 PMD_DRV_LOG(ERR, 3363 "Failed to alloc %zu bytes to store group info table\n", 3364 sizeof(*bp->grp_info) * bp->max_ring_grps); 3365 rc = -ENOMEM; 3366 goto error_free; 3367 } 3368 3369 /* Forward all requests if firmware is new enough */ 3370 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) && 3371 (bp->fw_ver < ((20 << 24) | (7 << 16)))) || 3372 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) { 3373 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd)); 3374 } else { 3375 PMD_DRV_LOG(WARNING, 3376 "Firmware too old for VF mailbox functionality\n"); 3377 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd)); 3378 } 3379 3380 /* 3381 * The following are used for driver cleanup. If we disallow these, 3382 * VF drivers can't clean up cleanly. 3383 */ 3384 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR); 3385 ALLOW_FUNC(HWRM_VNIC_FREE); 3386 ALLOW_FUNC(HWRM_RING_FREE); 3387 ALLOW_FUNC(HWRM_RING_GRP_FREE); 3388 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE); 3389 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE); 3390 ALLOW_FUNC(HWRM_STAT_CTX_FREE); 3391 ALLOW_FUNC(HWRM_PORT_PHY_QCFG); 3392 ALLOW_FUNC(HWRM_VNIC_TPA_CFG); 3393 rc = bnxt_hwrm_func_driver_register(bp); 3394 if (rc) { 3395 PMD_DRV_LOG(ERR, 3396 "Failed to register driver"); 3397 rc = -EBUSY; 3398 goto error_free; 3399 } 3400 3401 PMD_DRV_LOG(INFO, 3402 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n", 3403 pci_dev->mem_resource[0].phys_addr, 3404 pci_dev->mem_resource[0].addr); 3405 3406 rc = bnxt_hwrm_func_reset(bp); 3407 if (rc) { 3408 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc); 3409 rc = -EIO; 3410 goto error_free; 3411 } 3412 3413 if (BNXT_PF(bp)) { 3414 //if (bp->pf.active_vfs) { 3415 // TODO: Deallocate VF resources? 3416 //} 3417 if (bp->pdev->max_vfs) { 3418 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 3419 if (rc) { 3420 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 3421 goto error_free; 3422 } 3423 } else { 3424 rc = bnxt_hwrm_allocate_pf_only(bp); 3425 if (rc) { 3426 PMD_DRV_LOG(ERR, 3427 "Failed to allocate PF resources\n"); 3428 goto error_free; 3429 } 3430 } 3431 } 3432 3433 bnxt_hwrm_port_led_qcaps(bp); 3434 3435 rc = bnxt_setup_int(bp); 3436 if (rc) 3437 goto error_free; 3438 3439 rc = bnxt_alloc_mem(bp); 3440 if (rc) 3441 goto error_free_int; 3442 3443 rc = bnxt_request_int(bp); 3444 if (rc) 3445 goto error_free_int; 3446 3447 bnxt_enable_int(bp); 3448 bnxt_init_nic(bp); 3449 3450 return 0; 3451 3452 error_free_int: 3453 bnxt_disable_int(bp); 3454 bnxt_hwrm_func_buf_unrgtr(bp); 3455 bnxt_free_int(bp); 3456 bnxt_free_mem(bp); 3457 error_free: 3458 bnxt_dev_uninit(eth_dev); 3459 error: 3460 return rc; 3461 } 3462 3463 static int 3464 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 3465 { 3466 struct bnxt *bp = eth_dev->data->dev_private; 3467 int rc; 3468 3469 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3470 return -EPERM; 3471 3472 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 3473 bnxt_disable_int(bp); 3474 bnxt_free_int(bp); 3475 bnxt_free_mem(bp); 3476 if (eth_dev->data->mac_addrs != NULL) { 3477 rte_free(eth_dev->data->mac_addrs); 3478 eth_dev->data->mac_addrs = NULL; 3479 } 3480 if (bp->grp_info != NULL) { 3481 rte_free(bp->grp_info); 3482 bp->grp_info = NULL; 3483 } 3484 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 3485 bnxt_free_hwrm_resources(bp); 3486 3487 if (bp->tx_mem_zone) { 3488 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 3489 bp->tx_mem_zone = NULL; 3490 } 3491 3492 if (bp->rx_mem_zone) { 3493 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 3494 bp->rx_mem_zone = NULL; 3495 } 3496 3497 if (bp->dev_stopped == 0) 3498 bnxt_dev_close_op(eth_dev); 3499 if (bp->pf.vf_info) 3500 rte_free(bp->pf.vf_info); 3501 eth_dev->dev_ops = NULL; 3502 eth_dev->rx_pkt_burst = NULL; 3503 eth_dev->tx_pkt_burst = NULL; 3504 3505 return rc; 3506 } 3507 3508 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3509 struct rte_pci_device *pci_dev) 3510 { 3511 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt), 3512 bnxt_dev_init); 3513 } 3514 3515 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 3516 { 3517 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit); 3518 } 3519 3520 static struct rte_pci_driver bnxt_rte_pmd = { 3521 .id_table = bnxt_pci_id_map, 3522 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | 3523 RTE_PCI_DRV_INTR_LSC, 3524 .probe = bnxt_pci_probe, 3525 .remove = bnxt_pci_remove, 3526 }; 3527 3528 static bool 3529 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 3530 { 3531 if (strcmp(dev->device->driver->name, drv->driver.name)) 3532 return false; 3533 3534 return true; 3535 } 3536 3537 bool is_bnxt_supported(struct rte_eth_dev *dev) 3538 { 3539 return is_device_supported(dev, &bnxt_rte_pmd); 3540 } 3541 3542 RTE_INIT(bnxt_init_log) 3543 { 3544 bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver"); 3545 if (bnxt_logtype_driver >= 0) 3546 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO); 3547 } 3548 3549 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 3550 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 3551 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 3552