1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <ethdev_driver.h> 11 #include <ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 #include <rte_kvargs.h> 16 #include <rte_vect.h> 17 18 #include "bnxt.h" 19 #include "bnxt_filter.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_irq.h" 22 #include "bnxt_reps.h" 23 #include "bnxt_ring.h" 24 #include "bnxt_rxq.h" 25 #include "bnxt_rxr.h" 26 #include "bnxt_stats.h" 27 #include "bnxt_txq.h" 28 #include "bnxt_txr.h" 29 #include "bnxt_vnic.h" 30 #include "hsi_struct_def_dpdk.h" 31 #include "bnxt_nvm_defs.h" 32 #include "bnxt_tf_common.h" 33 #include "ulp_flow_db.h" 34 #include "rte_pmd_bnxt.h" 35 36 #define DRV_MODULE_NAME "bnxt" 37 static const char bnxt_version[] = 38 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 39 40 /* 41 * The set of PCI devices this driver supports 42 */ 43 static const struct rte_pci_id bnxt_pci_id_map[] = { 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) }, 87 { .vendor_id = 0, /* sentinel */ }, 88 }; 89 90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow" 91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" 92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" 93 #define BNXT_DEVARG_REPRESENTOR "representor" 94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf" 95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf" 96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f" 97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r" 98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f" 99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r" 100 101 static const char *const bnxt_dev_args[] = { 102 BNXT_DEVARG_REPRESENTOR, 103 BNXT_DEVARG_TRUFLOW, 104 BNXT_DEVARG_FLOW_XSTAT, 105 BNXT_DEVARG_MAX_NUM_KFLOWS, 106 BNXT_DEVARG_REP_BASED_PF, 107 BNXT_DEVARG_REP_IS_PF, 108 BNXT_DEVARG_REP_Q_R2F, 109 BNXT_DEVARG_REP_Q_F2R, 110 BNXT_DEVARG_REP_FC_R2F, 111 BNXT_DEVARG_REP_FC_F2R, 112 NULL 113 }; 114 115 /* 116 * truflow == false to disable the feature 117 * truflow == true to enable the feature 118 */ 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1) 120 121 /* 122 * flow_xstat == false to disable the feature 123 * flow_xstat == true to enable the feature 124 */ 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1) 126 127 /* 128 * rep_is_pf == false to indicate VF representor 129 * rep_is_pf == true to indicate PF representor 130 */ 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1) 132 133 /* 134 * rep_based_pf == Physical index of the PF 135 */ 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15) 137 /* 138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction 139 */ 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3) 141 142 /* 143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction 144 */ 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3) 146 147 /* 148 * rep_fc_r2f == Flow control for the representor to endpoint direction 149 */ 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1) 151 152 /* 153 * rep_fc_f2r == Flow control for the endpoint to representor direction 154 */ 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1) 156 157 int bnxt_cfa_code_dynfield_offset = -1; 158 159 /* 160 * max_num_kflows must be >= 32 161 * and must be a power-of-2 supported value 162 * return: 1 -> invalid 163 * 0 -> valid 164 */ 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows) 166 { 167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows)) 168 return 1; 169 return 0; 170 } 171 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 177 static int bnxt_restore_vlan_filters(struct bnxt *bp); 178 static void bnxt_dev_recover(void *arg); 179 static void bnxt_free_error_recovery_info(struct bnxt *bp); 180 static void bnxt_free_rep_info(struct bnxt *bp); 181 182 int is_bnxt_in_error(struct bnxt *bp) 183 { 184 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 185 return -EIO; 186 if (bp->flags & BNXT_FLAG_FW_RESET) 187 return -EBUSY; 188 189 return 0; 190 } 191 192 /***********************/ 193 194 /* 195 * High level utility functions 196 */ 197 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 199 { 200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings, 201 BNXT_RSS_TBL_SIZE_P5); 202 203 if (!BNXT_CHIP_P5(bp)) 204 return 1; 205 206 return RTE_ALIGN_MUL_CEIL(num_rss_rings, 207 BNXT_RSS_ENTRIES_PER_CTX_P5) / 208 BNXT_RSS_ENTRIES_PER_CTX_P5; 209 } 210 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 212 { 213 if (!BNXT_CHIP_P5(bp)) 214 return HW_HASH_INDEX_SIZE; 215 216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5; 217 } 218 219 static void bnxt_free_parent_info(struct bnxt *bp) 220 { 221 rte_free(bp->parent); 222 bp->parent = NULL; 223 } 224 225 static void bnxt_free_pf_info(struct bnxt *bp) 226 { 227 rte_free(bp->pf); 228 bp->pf = NULL; 229 } 230 231 static void bnxt_free_link_info(struct bnxt *bp) 232 { 233 rte_free(bp->link_info); 234 bp->link_info = NULL; 235 } 236 237 static void bnxt_free_leds_info(struct bnxt *bp) 238 { 239 if (BNXT_VF(bp)) 240 return; 241 242 rte_free(bp->leds); 243 bp->leds = NULL; 244 } 245 246 static void bnxt_free_flow_stats_info(struct bnxt *bp) 247 { 248 rte_free(bp->flow_stat); 249 bp->flow_stat = NULL; 250 } 251 252 static void bnxt_free_cos_queues(struct bnxt *bp) 253 { 254 rte_free(bp->rx_cos_queue); 255 bp->rx_cos_queue = NULL; 256 rte_free(bp->tx_cos_queue); 257 bp->tx_cos_queue = NULL; 258 } 259 260 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 261 { 262 bnxt_free_filter_mem(bp); 263 bnxt_free_vnic_attributes(bp); 264 bnxt_free_vnic_mem(bp); 265 266 /* tx/rx rings are configured as part of *_queue_setup callbacks. 267 * If the number of rings change across fw update, 268 * we don't have much choice except to warn the user. 269 */ 270 if (!reconfig) { 271 bnxt_free_stats(bp); 272 bnxt_free_tx_rings(bp); 273 bnxt_free_rx_rings(bp); 274 } 275 bnxt_free_async_cp_ring(bp); 276 bnxt_free_rxtx_nq_ring(bp); 277 278 rte_free(bp->grp_info); 279 bp->grp_info = NULL; 280 } 281 282 static int bnxt_alloc_parent_info(struct bnxt *bp) 283 { 284 bp->parent = rte_zmalloc("bnxt_parent_info", 285 sizeof(struct bnxt_parent_info), 0); 286 if (bp->parent == NULL) 287 return -ENOMEM; 288 289 return 0; 290 } 291 292 static int bnxt_alloc_pf_info(struct bnxt *bp) 293 { 294 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0); 295 if (bp->pf == NULL) 296 return -ENOMEM; 297 298 return 0; 299 } 300 301 static int bnxt_alloc_link_info(struct bnxt *bp) 302 { 303 bp->link_info = 304 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0); 305 if (bp->link_info == NULL) 306 return -ENOMEM; 307 308 return 0; 309 } 310 311 static int bnxt_alloc_leds_info(struct bnxt *bp) 312 { 313 if (BNXT_VF(bp)) 314 return 0; 315 316 bp->leds = rte_zmalloc("bnxt_leds", 317 BNXT_MAX_LED * sizeof(struct bnxt_led_info), 318 0); 319 if (bp->leds == NULL) 320 return -ENOMEM; 321 322 return 0; 323 } 324 325 static int bnxt_alloc_cos_queues(struct bnxt *bp) 326 { 327 bp->rx_cos_queue = 328 rte_zmalloc("bnxt_rx_cosq", 329 BNXT_COS_QUEUE_COUNT * 330 sizeof(struct bnxt_cos_queue_info), 331 0); 332 if (bp->rx_cos_queue == NULL) 333 return -ENOMEM; 334 335 bp->tx_cos_queue = 336 rte_zmalloc("bnxt_tx_cosq", 337 BNXT_COS_QUEUE_COUNT * 338 sizeof(struct bnxt_cos_queue_info), 339 0); 340 if (bp->tx_cos_queue == NULL) 341 return -ENOMEM; 342 343 return 0; 344 } 345 346 static int bnxt_alloc_flow_stats_info(struct bnxt *bp) 347 { 348 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat", 349 sizeof(struct bnxt_flow_stat_info), 0); 350 if (bp->flow_stat == NULL) 351 return -ENOMEM; 352 353 return 0; 354 } 355 356 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 357 { 358 int rc; 359 360 rc = bnxt_alloc_ring_grps(bp); 361 if (rc) 362 goto alloc_mem_err; 363 364 rc = bnxt_alloc_async_ring_struct(bp); 365 if (rc) 366 goto alloc_mem_err; 367 368 rc = bnxt_alloc_vnic_mem(bp); 369 if (rc) 370 goto alloc_mem_err; 371 372 rc = bnxt_alloc_vnic_attributes(bp); 373 if (rc) 374 goto alloc_mem_err; 375 376 rc = bnxt_alloc_filter_mem(bp); 377 if (rc) 378 goto alloc_mem_err; 379 380 rc = bnxt_alloc_async_cp_ring(bp); 381 if (rc) 382 goto alloc_mem_err; 383 384 rc = bnxt_alloc_rxtx_nq_ring(bp); 385 if (rc) 386 goto alloc_mem_err; 387 388 if (BNXT_FLOW_XSTATS_EN(bp)) { 389 rc = bnxt_alloc_flow_stats_info(bp); 390 if (rc) 391 goto alloc_mem_err; 392 } 393 394 return 0; 395 396 alloc_mem_err: 397 bnxt_free_mem(bp, reconfig); 398 return rc; 399 } 400 401 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 402 { 403 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 404 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 405 uint64_t rx_offloads = dev_conf->rxmode.offloads; 406 struct bnxt_rx_queue *rxq; 407 unsigned int j; 408 int rc; 409 410 rc = bnxt_vnic_grp_alloc(bp, vnic); 411 if (rc) 412 goto err_out; 413 414 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 415 vnic_id, vnic, vnic->fw_grp_ids); 416 417 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 418 if (rc) 419 goto err_out; 420 421 /* Alloc RSS context only if RSS mode is enabled */ 422 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 423 int j, nr_ctxs = bnxt_rss_ctxts(bp); 424 425 /* RSS table size in Thor is 512. 426 * Cap max Rx rings to same value 427 */ 428 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) { 429 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n", 430 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5); 431 goto err_out; 432 } 433 434 rc = 0; 435 for (j = 0; j < nr_ctxs; j++) { 436 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 437 if (rc) 438 break; 439 } 440 if (rc) { 441 PMD_DRV_LOG(ERR, 442 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 443 vnic_id, j, rc); 444 goto err_out; 445 } 446 vnic->num_lb_ctxts = nr_ctxs; 447 } 448 449 /* 450 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 451 * setting is not available at this time, it will not be 452 * configured correctly in the CFA. 453 */ 454 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 455 vnic->vlan_strip = true; 456 else 457 vnic->vlan_strip = false; 458 459 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 460 if (rc) 461 goto err_out; 462 463 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 464 if (rc) 465 goto err_out; 466 467 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 468 rxq = bp->eth_dev->data->rx_queues[j]; 469 470 PMD_DRV_LOG(DEBUG, 471 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 472 j, rxq->vnic, rxq->vnic->fw_grp_ids); 473 474 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 475 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 476 else 477 vnic->rx_queue_cnt++; 478 } 479 480 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 481 482 rc = bnxt_vnic_rss_configure(bp, vnic); 483 if (rc) 484 goto err_out; 485 486 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 487 488 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 489 (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ? 490 true : false); 491 if (rc) 492 goto err_out; 493 494 return 0; 495 err_out: 496 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 497 vnic_id, rc); 498 return rc; 499 } 500 501 static int bnxt_register_fc_ctx_mem(struct bnxt *bp) 502 { 503 int rc = 0; 504 505 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma, 506 &bp->flow_stat->rx_fc_in_tbl.ctx_id); 507 if (rc) 508 return rc; 509 510 PMD_DRV_LOG(DEBUG, 511 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p" 512 " rx_fc_in_tbl.ctx_id = %d\n", 513 bp->flow_stat->rx_fc_in_tbl.va, 514 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma), 515 bp->flow_stat->rx_fc_in_tbl.ctx_id); 516 517 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma, 518 &bp->flow_stat->rx_fc_out_tbl.ctx_id); 519 if (rc) 520 return rc; 521 522 PMD_DRV_LOG(DEBUG, 523 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p" 524 " rx_fc_out_tbl.ctx_id = %d\n", 525 bp->flow_stat->rx_fc_out_tbl.va, 526 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma), 527 bp->flow_stat->rx_fc_out_tbl.ctx_id); 528 529 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma, 530 &bp->flow_stat->tx_fc_in_tbl.ctx_id); 531 if (rc) 532 return rc; 533 534 PMD_DRV_LOG(DEBUG, 535 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p" 536 " tx_fc_in_tbl.ctx_id = %d\n", 537 bp->flow_stat->tx_fc_in_tbl.va, 538 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma), 539 bp->flow_stat->tx_fc_in_tbl.ctx_id); 540 541 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma, 542 &bp->flow_stat->tx_fc_out_tbl.ctx_id); 543 if (rc) 544 return rc; 545 546 PMD_DRV_LOG(DEBUG, 547 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p" 548 " tx_fc_out_tbl.ctx_id = %d\n", 549 bp->flow_stat->tx_fc_out_tbl.va, 550 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma), 551 bp->flow_stat->tx_fc_out_tbl.ctx_id); 552 553 memset(bp->flow_stat->rx_fc_out_tbl.va, 554 0, 555 bp->flow_stat->rx_fc_out_tbl.size); 556 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 557 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 558 bp->flow_stat->rx_fc_out_tbl.ctx_id, 559 bp->flow_stat->max_fc, 560 true); 561 if (rc) 562 return rc; 563 564 memset(bp->flow_stat->tx_fc_out_tbl.va, 565 0, 566 bp->flow_stat->tx_fc_out_tbl.size); 567 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 568 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 569 bp->flow_stat->tx_fc_out_tbl.ctx_id, 570 bp->flow_stat->max_fc, 571 true); 572 573 return rc; 574 } 575 576 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size, 577 struct bnxt_ctx_mem_buf_info *ctx) 578 { 579 if (!ctx) 580 return -EINVAL; 581 582 ctx->va = rte_zmalloc(type, size, 0); 583 if (ctx->va == NULL) 584 return -ENOMEM; 585 rte_mem_lock_page(ctx->va); 586 ctx->size = size; 587 ctx->dma = rte_mem_virt2iova(ctx->va); 588 if (ctx->dma == RTE_BAD_IOVA) 589 return -ENOMEM; 590 591 return 0; 592 } 593 594 static int bnxt_init_fc_ctx_mem(struct bnxt *bp) 595 { 596 struct rte_pci_device *pdev = bp->pdev; 597 char type[RTE_MEMZONE_NAMESIZE]; 598 uint16_t max_fc; 599 int rc = 0; 600 601 max_fc = bp->flow_stat->max_fc; 602 603 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 604 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 605 /* 4 bytes for each counter-id */ 606 rc = bnxt_alloc_ctx_mem_buf(type, 607 max_fc * 4, 608 &bp->flow_stat->rx_fc_in_tbl); 609 if (rc) 610 return rc; 611 612 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 613 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 614 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 615 rc = bnxt_alloc_ctx_mem_buf(type, 616 max_fc * 16, 617 &bp->flow_stat->rx_fc_out_tbl); 618 if (rc) 619 return rc; 620 621 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 622 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 623 /* 4 bytes for each counter-id */ 624 rc = bnxt_alloc_ctx_mem_buf(type, 625 max_fc * 4, 626 &bp->flow_stat->tx_fc_in_tbl); 627 if (rc) 628 return rc; 629 630 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 631 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 632 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 633 rc = bnxt_alloc_ctx_mem_buf(type, 634 max_fc * 16, 635 &bp->flow_stat->tx_fc_out_tbl); 636 if (rc) 637 return rc; 638 639 rc = bnxt_register_fc_ctx_mem(bp); 640 641 return rc; 642 } 643 644 static int bnxt_init_ctx_mem(struct bnxt *bp) 645 { 646 int rc = 0; 647 648 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) || 649 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) || 650 !BNXT_FLOW_XSTATS_EN(bp)) 651 return 0; 652 653 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc); 654 if (rc) 655 return rc; 656 657 rc = bnxt_init_fc_ctx_mem(bp); 658 659 return rc; 660 } 661 662 static int bnxt_update_phy_setting(struct bnxt *bp) 663 { 664 struct rte_eth_link new; 665 int rc; 666 667 rc = bnxt_get_hwrm_link_config(bp, &new); 668 if (rc) { 669 PMD_DRV_LOG(ERR, "Failed to get link settings\n"); 670 return rc; 671 } 672 673 /* 674 * On BCM957508-N2100 adapters, FW will not allow any user other 675 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call 676 * always returns link up. Force phy update always in that case. 677 */ 678 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) { 679 rc = bnxt_set_hwrm_link_config(bp, true); 680 if (rc) { 681 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n"); 682 return rc; 683 } 684 } 685 686 return rc; 687 } 688 689 static int bnxt_start_nic(struct bnxt *bp) 690 { 691 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 692 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 693 uint32_t intr_vector = 0; 694 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 695 uint32_t vec = BNXT_MISC_VEC_ID; 696 unsigned int i, j; 697 int rc; 698 699 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 700 bp->eth_dev->data->dev_conf.rxmode.offloads |= 701 DEV_RX_OFFLOAD_JUMBO_FRAME; 702 bp->flags |= BNXT_FLAG_JUMBO; 703 } else { 704 bp->eth_dev->data->dev_conf.rxmode.offloads &= 705 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 706 bp->flags &= ~BNXT_FLAG_JUMBO; 707 } 708 709 /* THOR does not support ring groups. 710 * But we will use the array to save RSS context IDs. 711 */ 712 if (BNXT_CHIP_P5(bp)) 713 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; 714 715 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 716 if (rc) { 717 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 718 goto err_out; 719 } 720 721 rc = bnxt_alloc_hwrm_rings(bp); 722 if (rc) { 723 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 724 goto err_out; 725 } 726 727 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 728 if (rc) { 729 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 730 goto err_out; 731 } 732 733 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 734 goto skip_cosq_cfg; 735 736 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 737 if (bp->rx_cos_queue[i].id != 0xff) { 738 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 739 740 if (!vnic) { 741 PMD_DRV_LOG(ERR, 742 "Num pools more than FW profile\n"); 743 rc = -EINVAL; 744 goto err_out; 745 } 746 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 747 bp->rx_cosq_cnt++; 748 } 749 } 750 751 skip_cosq_cfg: 752 rc = bnxt_mq_rx_configure(bp); 753 if (rc) { 754 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 755 goto err_out; 756 } 757 758 /* default vnic 0 */ 759 rc = bnxt_setup_one_vnic(bp, 0); 760 if (rc) 761 goto err_out; 762 /* VNIC configuration */ 763 if (BNXT_RFS_NEEDS_VNIC(bp)) { 764 for (i = 1; i < bp->nr_vnics; i++) { 765 rc = bnxt_setup_one_vnic(bp, i); 766 if (rc) 767 goto err_out; 768 } 769 } 770 771 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 772 if (rc) { 773 PMD_DRV_LOG(ERR, 774 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 775 goto err_out; 776 } 777 778 /* check and configure queue intr-vector mapping */ 779 if ((rte_intr_cap_multiple(intr_handle) || 780 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 781 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 782 intr_vector = bp->eth_dev->data->nb_rx_queues; 783 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 784 if (intr_vector > bp->rx_cp_nr_rings) { 785 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 786 bp->rx_cp_nr_rings); 787 return -ENOTSUP; 788 } 789 rc = rte_intr_efd_enable(intr_handle, intr_vector); 790 if (rc) 791 return rc; 792 } 793 794 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 795 intr_handle->intr_vec = 796 rte_zmalloc("intr_vec", 797 bp->eth_dev->data->nb_rx_queues * 798 sizeof(int), 0); 799 if (intr_handle->intr_vec == NULL) { 800 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 801 " intr_vec", bp->eth_dev->data->nb_rx_queues); 802 rc = -ENOMEM; 803 goto err_out; 804 } 805 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 806 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 807 intr_handle->intr_vec, intr_handle->nb_efd, 808 intr_handle->max_intr); 809 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 810 queue_id++) { 811 intr_handle->intr_vec[queue_id] = 812 vec + BNXT_RX_VEC_START; 813 if (vec < base + intr_handle->nb_efd - 1) 814 vec++; 815 } 816 } 817 818 /* enable uio/vfio intr/eventfd mapping */ 819 rc = rte_intr_enable(intr_handle); 820 #ifndef RTE_EXEC_ENV_FREEBSD 821 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 822 if (rc) 823 goto err_out; 824 #endif 825 826 rc = bnxt_update_phy_setting(bp); 827 if (rc) 828 goto err_out; 829 830 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 831 if (!bp->mark_table) 832 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 833 834 return 0; 835 836 err_out: 837 /* Some of the error status returned by FW may not be from errno.h */ 838 if (rc > 0) 839 rc = -EIO; 840 841 return rc; 842 } 843 844 static int bnxt_shutdown_nic(struct bnxt *bp) 845 { 846 bnxt_free_all_hwrm_resources(bp); 847 bnxt_free_all_filters(bp); 848 bnxt_free_all_vnics(bp); 849 return 0; 850 } 851 852 /* 853 * Device configuration and status function 854 */ 855 856 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) 857 { 858 uint32_t link_speed = 0; 859 uint32_t speed_capa = 0; 860 861 if (bp->link_info == NULL) 862 return 0; 863 864 link_speed = bp->link_info->support_speeds; 865 866 /* If PAM4 is configured, use PAM4 supported speed */ 867 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0) 868 link_speed = bp->link_info->support_pam4_speeds; 869 870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) 871 speed_capa |= ETH_LINK_SPEED_100M; 872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) 873 speed_capa |= ETH_LINK_SPEED_100M_HD; 874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) 875 speed_capa |= ETH_LINK_SPEED_1G; 876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 877 speed_capa |= ETH_LINK_SPEED_2_5G; 878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) 879 speed_capa |= ETH_LINK_SPEED_10G; 880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 881 speed_capa |= ETH_LINK_SPEED_20G; 882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) 883 speed_capa |= ETH_LINK_SPEED_25G; 884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) 885 speed_capa |= ETH_LINK_SPEED_40G; 886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) 887 speed_capa |= ETH_LINK_SPEED_50G; 888 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) 889 speed_capa |= ETH_LINK_SPEED_100G; 890 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) 891 speed_capa |= ETH_LINK_SPEED_50G; 892 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) 893 speed_capa |= ETH_LINK_SPEED_100G; 894 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G) 895 speed_capa |= ETH_LINK_SPEED_200G; 896 897 if (bp->link_info->auto_mode == 898 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 899 speed_capa |= ETH_LINK_SPEED_FIXED; 900 901 return speed_capa; 902 } 903 904 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 905 struct rte_eth_dev_info *dev_info) 906 { 907 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 908 struct bnxt *bp = eth_dev->data->dev_private; 909 uint16_t max_vnics, i, j, vpool, vrxq; 910 unsigned int max_rx_rings; 911 int rc; 912 913 rc = is_bnxt_in_error(bp); 914 if (rc) 915 return rc; 916 917 /* MAC Specifics */ 918 dev_info->max_mac_addrs = bp->max_l2_ctx; 919 dev_info->max_hash_mac_addrs = 0; 920 921 /* PF/VF specifics */ 922 if (BNXT_PF(bp)) 923 dev_info->max_vfs = pdev->max_vfs; 924 925 max_rx_rings = bnxt_max_rings(bp); 926 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 927 dev_info->max_rx_queues = max_rx_rings; 928 dev_info->max_tx_queues = max_rx_rings; 929 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 930 dev_info->hash_key_size = 40; 931 max_vnics = bp->max_vnics; 932 933 /* MTU specifics */ 934 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 935 dev_info->max_mtu = BNXT_MAX_MTU; 936 937 /* Fast path specifics */ 938 dev_info->min_rx_bufsize = 1; 939 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 940 941 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 942 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 943 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 944 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 945 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT | 946 dev_info->tx_queue_offload_capa; 947 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 948 949 dev_info->speed_capa = bnxt_get_speed_capabilities(bp); 950 951 /* *INDENT-OFF* */ 952 dev_info->default_rxconf = (struct rte_eth_rxconf) { 953 .rx_thresh = { 954 .pthresh = 8, 955 .hthresh = 8, 956 .wthresh = 0, 957 }, 958 .rx_free_thresh = 32, 959 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN, 960 }; 961 962 dev_info->default_txconf = (struct rte_eth_txconf) { 963 .tx_thresh = { 964 .pthresh = 32, 965 .hthresh = 0, 966 .wthresh = 0, 967 }, 968 .tx_free_thresh = 32, 969 .tx_rs_thresh = 32, 970 }; 971 eth_dev->data->dev_conf.intr_conf.lsc = 1; 972 973 eth_dev->data->dev_conf.intr_conf.rxq = 1; 974 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 975 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 976 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 977 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 978 979 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 980 dev_info->switch_info.name = eth_dev->device->name; 981 dev_info->switch_info.domain_id = bp->switch_domain_id; 982 dev_info->switch_info.port_id = 983 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF : 984 BNXT_SWITCH_PORT_ID_TRUSTED_VF; 985 } 986 987 /* *INDENT-ON* */ 988 989 /* 990 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 991 * need further investigation. 992 */ 993 994 /* VMDq resources */ 995 vpool = 64; /* ETH_64_POOLS */ 996 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 997 for (i = 0; i < 4; vpool >>= 1, i++) { 998 if (max_vnics > vpool) { 999 for (j = 0; j < 5; vrxq >>= 1, j++) { 1000 if (dev_info->max_rx_queues > vrxq) { 1001 if (vpool > vrxq) 1002 vpool = vrxq; 1003 goto found; 1004 } 1005 } 1006 /* Not enough resources to support VMDq */ 1007 break; 1008 } 1009 } 1010 /* Not enough resources to support VMDq */ 1011 vpool = 0; 1012 vrxq = 0; 1013 found: 1014 dev_info->max_vmdq_pools = vpool; 1015 dev_info->vmdq_queue_num = vrxq; 1016 1017 dev_info->vmdq_pool_base = 0; 1018 dev_info->vmdq_queue_base = 0; 1019 1020 return 0; 1021 } 1022 1023 /* Configure the device based on the configuration provided */ 1024 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 1025 { 1026 struct bnxt *bp = eth_dev->data->dev_private; 1027 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1028 int rc; 1029 1030 bp->rx_queues = (void *)eth_dev->data->rx_queues; 1031 bp->tx_queues = (void *)eth_dev->data->tx_queues; 1032 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 1033 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 1034 1035 rc = is_bnxt_in_error(bp); 1036 if (rc) 1037 return rc; 1038 1039 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 1040 rc = bnxt_hwrm_check_vf_rings(bp); 1041 if (rc) { 1042 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 1043 return -ENOSPC; 1044 } 1045 1046 /* If a resource has already been allocated - in this case 1047 * it is the async completion ring, free it. Reallocate it after 1048 * resource reservation. This will ensure the resource counts 1049 * are calculated correctly. 1050 */ 1051 1052 pthread_mutex_lock(&bp->def_cp_lock); 1053 1054 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1055 bnxt_disable_int(bp); 1056 bnxt_free_cp_ring(bp, bp->async_cp_ring); 1057 } 1058 1059 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 1060 if (rc) { 1061 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 1062 pthread_mutex_unlock(&bp->def_cp_lock); 1063 return -ENOSPC; 1064 } 1065 1066 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1067 rc = bnxt_alloc_async_cp_ring(bp); 1068 if (rc) { 1069 pthread_mutex_unlock(&bp->def_cp_lock); 1070 return rc; 1071 } 1072 bnxt_enable_int(bp); 1073 } 1074 1075 pthread_mutex_unlock(&bp->def_cp_lock); 1076 } 1077 1078 /* Inherit new configurations */ 1079 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 1080 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 1081 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 1082 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 1083 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 1084 bp->max_stat_ctx) 1085 goto resource_error; 1086 1087 if (BNXT_HAS_RING_GRPS(bp) && 1088 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 1089 goto resource_error; 1090 1091 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 1092 bp->max_vnics < eth_dev->data->nb_rx_queues) 1093 goto resource_error; 1094 1095 bp->rx_cp_nr_rings = bp->rx_nr_rings; 1096 bp->tx_cp_nr_rings = bp->tx_nr_rings; 1097 1098 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1099 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1100 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 1101 1102 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1103 eth_dev->data->mtu = 1104 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1105 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 1106 BNXT_NUM_VLANS; 1107 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 1108 } 1109 return 0; 1110 1111 resource_error: 1112 PMD_DRV_LOG(ERR, 1113 "Insufficient resources to support requested config\n"); 1114 PMD_DRV_LOG(ERR, 1115 "Num Queues Requested: Tx %d, Rx %d\n", 1116 eth_dev->data->nb_tx_queues, 1117 eth_dev->data->nb_rx_queues); 1118 PMD_DRV_LOG(ERR, 1119 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 1120 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 1121 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 1122 return -ENOSPC; 1123 } 1124 1125 void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 1126 { 1127 struct rte_eth_link *link = ð_dev->data->dev_link; 1128 1129 if (link->link_status) 1130 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 1131 eth_dev->data->port_id, 1132 (uint32_t)link->link_speed, 1133 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 1134 ("full-duplex") : ("half-duplex\n")); 1135 else 1136 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 1137 eth_dev->data->port_id); 1138 } 1139 1140 /* 1141 * Determine whether the current configuration requires support for scattered 1142 * receive; return 1 if scattered receive is required and 0 if not. 1143 */ 1144 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 1145 { 1146 uint16_t buf_size; 1147 int i; 1148 1149 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 1150 return 1; 1151 1152 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) 1153 return 1; 1154 1155 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 1156 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 1157 1158 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1159 RTE_PKTMBUF_HEADROOM); 1160 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 1161 return 1; 1162 } 1163 return 0; 1164 } 1165 1166 static eth_rx_burst_t 1167 bnxt_receive_function(struct rte_eth_dev *eth_dev) 1168 { 1169 struct bnxt *bp = eth_dev->data->dev_private; 1170 1171 /* Disable vector mode RX for Stingray2 for now */ 1172 if (BNXT_CHIP_SR2(bp)) { 1173 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1174 return bnxt_recv_pkts; 1175 } 1176 1177 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 1178 #ifndef RTE_LIBRTE_IEEE1588 1179 /* 1180 * Vector mode receive can be enabled only if scatter rx is not 1181 * in use and rx offloads are limited to VLAN stripping and 1182 * CRC stripping. 1183 */ 1184 if (!eth_dev->data->scattered_rx && 1185 !(eth_dev->data->dev_conf.rxmode.offloads & 1186 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 1187 DEV_RX_OFFLOAD_KEEP_CRC | 1188 DEV_RX_OFFLOAD_JUMBO_FRAME | 1189 DEV_RX_OFFLOAD_IPV4_CKSUM | 1190 DEV_RX_OFFLOAD_UDP_CKSUM | 1191 DEV_RX_OFFLOAD_TCP_CKSUM | 1192 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1193 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 1194 DEV_RX_OFFLOAD_RSS_HASH | 1195 DEV_RX_OFFLOAD_VLAN_FILTER)) && 1196 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) && 1197 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1198 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 1199 eth_dev->data->port_id); 1200 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1201 return bnxt_recv_pkts_vec; 1202 } 1203 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 1204 eth_dev->data->port_id); 1205 PMD_DRV_LOG(INFO, 1206 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 1207 eth_dev->data->port_id, 1208 eth_dev->data->scattered_rx, 1209 eth_dev->data->dev_conf.rxmode.offloads); 1210 #endif 1211 #endif 1212 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1213 return bnxt_recv_pkts; 1214 } 1215 1216 static eth_tx_burst_t 1217 bnxt_transmit_function(struct rte_eth_dev *eth_dev) 1218 { 1219 struct bnxt *bp = eth_dev->data->dev_private; 1220 1221 /* Disable vector mode TX for Stingray2 for now */ 1222 if (BNXT_CHIP_SR2(bp)) 1223 return bnxt_xmit_pkts; 1224 1225 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 1226 #ifndef RTE_LIBRTE_IEEE1588 1227 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; 1228 1229 /* 1230 * Vector mode transmit can be enabled only if not using scatter rx 1231 * or tx offloads. 1232 */ 1233 if (!eth_dev->data->scattered_rx && 1234 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) && 1235 !BNXT_TRUFLOW_EN(bp) && 1236 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1237 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 1238 eth_dev->data->port_id); 1239 return bnxt_xmit_pkts_vec; 1240 } 1241 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 1242 eth_dev->data->port_id); 1243 PMD_DRV_LOG(INFO, 1244 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 1245 eth_dev->data->port_id, 1246 eth_dev->data->scattered_rx, 1247 offloads); 1248 #endif 1249 #endif 1250 return bnxt_xmit_pkts; 1251 } 1252 1253 static int bnxt_handle_if_change_status(struct bnxt *bp) 1254 { 1255 int rc; 1256 1257 /* Since fw has undergone a reset and lost all contexts, 1258 * set fatal flag to not issue hwrm during cleanup 1259 */ 1260 bp->flags |= BNXT_FLAG_FATAL_ERROR; 1261 bnxt_uninit_resources(bp, true); 1262 1263 /* clear fatal flag so that re-init happens */ 1264 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 1265 rc = bnxt_init_resources(bp, true); 1266 1267 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 1268 1269 return rc; 1270 } 1271 1272 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 1273 { 1274 struct bnxt *bp = eth_dev->data->dev_private; 1275 int rc = 0; 1276 1277 if (!BNXT_SINGLE_PF(bp)) 1278 return -ENOTSUP; 1279 1280 if (!bp->link_info->link_up) 1281 rc = bnxt_set_hwrm_link_config(bp, true); 1282 if (!rc) 1283 eth_dev->data->dev_link.link_status = 1; 1284 1285 bnxt_print_link_info(eth_dev); 1286 return rc; 1287 } 1288 1289 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 1290 { 1291 struct bnxt *bp = eth_dev->data->dev_private; 1292 1293 if (!BNXT_SINGLE_PF(bp)) 1294 return -ENOTSUP; 1295 1296 eth_dev->data->dev_link.link_status = 0; 1297 bnxt_set_hwrm_link_config(bp, false); 1298 bp->link_info->link_up = 0; 1299 1300 return 0; 1301 } 1302 1303 static void bnxt_free_switch_domain(struct bnxt *bp) 1304 { 1305 int rc = 0; 1306 1307 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) 1308 return; 1309 1310 rc = rte_eth_switch_domain_free(bp->switch_domain_id); 1311 if (rc) 1312 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n", 1313 bp->switch_domain_id, rc); 1314 } 1315 1316 static void bnxt_ptp_get_current_time(void *arg) 1317 { 1318 struct bnxt *bp = arg; 1319 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1320 int rc; 1321 1322 rc = is_bnxt_in_error(bp); 1323 if (rc) 1324 return; 1325 1326 if (!ptp) 1327 return; 1328 1329 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1330 &ptp->current_time); 1331 1332 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1333 if (rc != 0) { 1334 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n"); 1335 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1336 } 1337 } 1338 1339 static int bnxt_schedule_ptp_alarm(struct bnxt *bp) 1340 { 1341 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1342 int rc; 1343 1344 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) 1345 return 0; 1346 1347 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1348 &ptp->current_time); 1349 1350 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1351 return rc; 1352 } 1353 1354 static void bnxt_cancel_ptp_alarm(struct bnxt *bp) 1355 { 1356 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) { 1357 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp); 1358 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1359 } 1360 } 1361 1362 static void bnxt_ptp_stop(struct bnxt *bp) 1363 { 1364 bnxt_cancel_ptp_alarm(bp); 1365 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1366 } 1367 1368 static int bnxt_ptp_start(struct bnxt *bp) 1369 { 1370 int rc; 1371 1372 rc = bnxt_schedule_ptp_alarm(bp); 1373 if (rc != 0) { 1374 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n"); 1375 } else { 1376 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1377 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1378 } 1379 1380 return rc; 1381 } 1382 1383 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev) 1384 { 1385 struct bnxt *bp = eth_dev->data->dev_private; 1386 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1387 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1388 struct rte_eth_link link; 1389 int ret; 1390 1391 eth_dev->data->dev_started = 0; 1392 eth_dev->data->scattered_rx = 0; 1393 1394 /* Prevent crashes when queues are still in use */ 1395 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 1396 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 1397 1398 bnxt_disable_int(bp); 1399 1400 /* disable uio/vfio intr/eventfd mapping */ 1401 rte_intr_disable(intr_handle); 1402 1403 /* Stop the child representors for this device */ 1404 ret = bnxt_rep_stop_all(bp); 1405 if (ret != 0) 1406 return ret; 1407 1408 /* delete the bnxt ULP port details */ 1409 bnxt_ulp_port_deinit(bp); 1410 1411 bnxt_cancel_fw_health_check(bp); 1412 1413 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1414 bnxt_cancel_ptp_alarm(bp); 1415 1416 /* Do not bring link down during reset recovery */ 1417 if (!is_bnxt_in_error(bp)) { 1418 bnxt_dev_set_link_down_op(eth_dev); 1419 /* Wait for link to be reset */ 1420 if (BNXT_SINGLE_PF(bp)) 1421 rte_delay_ms(500); 1422 /* clear the recorded link status */ 1423 memset(&link, 0, sizeof(link)); 1424 rte_eth_linkstatus_set(eth_dev, &link); 1425 } 1426 1427 /* Clean queue intr-vector mapping */ 1428 rte_intr_efd_disable(intr_handle); 1429 if (intr_handle->intr_vec != NULL) { 1430 rte_free(intr_handle->intr_vec); 1431 intr_handle->intr_vec = NULL; 1432 } 1433 1434 bnxt_hwrm_port_clr_stats(bp); 1435 bnxt_free_tx_mbufs(bp); 1436 bnxt_free_rx_mbufs(bp); 1437 /* Process any remaining notifications in default completion queue */ 1438 bnxt_int_handler(eth_dev); 1439 bnxt_shutdown_nic(bp); 1440 bnxt_hwrm_if_change(bp, false); 1441 1442 rte_free(bp->mark_table); 1443 bp->mark_table = NULL; 1444 1445 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1446 bp->rx_cosq_cnt = 0; 1447 /* All filters are deleted on a port stop. */ 1448 if (BNXT_FLOW_XSTATS_EN(bp)) 1449 bp->flow_stat->flow_count = 0; 1450 1451 return 0; 1452 } 1453 1454 /* Unload the driver, release resources */ 1455 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 1456 { 1457 struct bnxt *bp = eth_dev->data->dev_private; 1458 1459 pthread_mutex_lock(&bp->err_recovery_lock); 1460 if (bp->flags & BNXT_FLAG_FW_RESET) { 1461 PMD_DRV_LOG(ERR, 1462 "Adapter recovering from error..Please retry\n"); 1463 pthread_mutex_unlock(&bp->err_recovery_lock); 1464 return -EAGAIN; 1465 } 1466 pthread_mutex_unlock(&bp->err_recovery_lock); 1467 1468 return bnxt_dev_stop(eth_dev); 1469 } 1470 1471 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 1472 { 1473 struct bnxt *bp = eth_dev->data->dev_private; 1474 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1475 int vlan_mask = 0; 1476 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; 1477 1478 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 1479 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 1480 return -EINVAL; 1481 } 1482 1483 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) 1484 PMD_DRV_LOG(ERR, 1485 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 1486 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1487 1488 do { 1489 rc = bnxt_hwrm_if_change(bp, true); 1490 if (rc == 0 || rc != -EAGAIN) 1491 break; 1492 1493 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); 1494 } while (retry_cnt--); 1495 1496 if (rc) 1497 return rc; 1498 1499 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 1500 rc = bnxt_handle_if_change_status(bp); 1501 if (rc) 1502 return rc; 1503 } 1504 1505 bnxt_enable_int(bp); 1506 1507 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 1508 1509 rc = bnxt_start_nic(bp); 1510 if (rc) 1511 goto error; 1512 1513 eth_dev->data->dev_started = 1; 1514 1515 bnxt_link_update_op(eth_dev, 1); 1516 1517 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1518 vlan_mask |= ETH_VLAN_FILTER_MASK; 1519 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1520 vlan_mask |= ETH_VLAN_STRIP_MASK; 1521 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 1522 if (rc) 1523 goto error; 1524 1525 /* Initialize bnxt ULP port details */ 1526 rc = bnxt_ulp_port_init(bp); 1527 if (rc) 1528 goto error; 1529 1530 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 1531 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 1532 1533 bnxt_schedule_fw_health_check(bp); 1534 1535 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1536 bnxt_schedule_ptp_alarm(bp); 1537 1538 return 0; 1539 1540 error: 1541 bnxt_dev_stop(eth_dev); 1542 return rc; 1543 } 1544 1545 static void 1546 bnxt_uninit_locks(struct bnxt *bp) 1547 { 1548 pthread_mutex_destroy(&bp->flow_lock); 1549 pthread_mutex_destroy(&bp->def_cp_lock); 1550 pthread_mutex_destroy(&bp->health_check_lock); 1551 pthread_mutex_destroy(&bp->err_recovery_lock); 1552 if (bp->rep_info) { 1553 pthread_mutex_destroy(&bp->rep_info->vfr_lock); 1554 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); 1555 } 1556 } 1557 1558 static void bnxt_drv_uninit(struct bnxt *bp) 1559 { 1560 bnxt_free_leds_info(bp); 1561 bnxt_free_cos_queues(bp); 1562 bnxt_free_link_info(bp); 1563 bnxt_free_parent_info(bp); 1564 bnxt_uninit_locks(bp); 1565 1566 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 1567 bp->tx_mem_zone = NULL; 1568 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 1569 bp->rx_mem_zone = NULL; 1570 1571 bnxt_free_vf_info(bp); 1572 bnxt_free_pf_info(bp); 1573 1574 rte_free(bp->grp_info); 1575 bp->grp_info = NULL; 1576 } 1577 1578 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 1579 { 1580 struct bnxt *bp = eth_dev->data->dev_private; 1581 int ret = 0; 1582 1583 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1584 return 0; 1585 1586 pthread_mutex_lock(&bp->err_recovery_lock); 1587 if (bp->flags & BNXT_FLAG_FW_RESET) { 1588 PMD_DRV_LOG(ERR, 1589 "Adapter recovering from error...Please retry\n"); 1590 pthread_mutex_unlock(&bp->err_recovery_lock); 1591 return -EAGAIN; 1592 } 1593 pthread_mutex_unlock(&bp->err_recovery_lock); 1594 1595 /* cancel the recovery handler before remove dev */ 1596 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); 1597 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); 1598 bnxt_cancel_fc_thread(bp); 1599 1600 if (eth_dev->data->dev_started) 1601 ret = bnxt_dev_stop(eth_dev); 1602 1603 bnxt_uninit_resources(bp, false); 1604 1605 bnxt_drv_uninit(bp); 1606 1607 return ret; 1608 } 1609 1610 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1611 uint32_t index) 1612 { 1613 struct bnxt *bp = eth_dev->data->dev_private; 1614 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1615 struct bnxt_vnic_info *vnic; 1616 struct bnxt_filter_info *filter, *temp_filter; 1617 uint32_t i; 1618 1619 if (is_bnxt_in_error(bp)) 1620 return; 1621 1622 /* 1623 * Loop through all VNICs from the specified filter flow pools to 1624 * remove the corresponding MAC addr filter 1625 */ 1626 for (i = 0; i < bp->nr_vnics; i++) { 1627 if (!(pool_mask & (1ULL << i))) 1628 continue; 1629 1630 vnic = &bp->vnic_info[i]; 1631 filter = STAILQ_FIRST(&vnic->filter); 1632 while (filter) { 1633 temp_filter = STAILQ_NEXT(filter, next); 1634 if (filter->mac_index == index) { 1635 STAILQ_REMOVE(&vnic->filter, filter, 1636 bnxt_filter_info, next); 1637 bnxt_hwrm_clear_l2_filter(bp, filter); 1638 bnxt_free_filter(bp, filter); 1639 } 1640 filter = temp_filter; 1641 } 1642 } 1643 } 1644 1645 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1646 struct rte_ether_addr *mac_addr, uint32_t index, 1647 uint32_t pool) 1648 { 1649 struct bnxt_filter_info *filter; 1650 int rc = 0; 1651 1652 /* Attach requested MAC address to the new l2_filter */ 1653 STAILQ_FOREACH(filter, &vnic->filter, next) { 1654 if (filter->mac_index == index) { 1655 PMD_DRV_LOG(DEBUG, 1656 "MAC addr already existed for pool %d\n", 1657 pool); 1658 return 0; 1659 } 1660 } 1661 1662 filter = bnxt_alloc_filter(bp); 1663 if (!filter) { 1664 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1665 return -ENODEV; 1666 } 1667 1668 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1669 * if the MAC that's been programmed now is a different one, then, 1670 * copy that addr to filter->l2_addr 1671 */ 1672 if (mac_addr) 1673 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1674 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1675 1676 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1677 if (!rc) { 1678 filter->mac_index = index; 1679 if (filter->mac_index == 0) 1680 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1681 else 1682 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1683 } else { 1684 bnxt_free_filter(bp, filter); 1685 } 1686 1687 return rc; 1688 } 1689 1690 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1691 struct rte_ether_addr *mac_addr, 1692 uint32_t index, uint32_t pool) 1693 { 1694 struct bnxt *bp = eth_dev->data->dev_private; 1695 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1696 int rc = 0; 1697 1698 rc = is_bnxt_in_error(bp); 1699 if (rc) 1700 return rc; 1701 1702 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 1703 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1704 return -ENOTSUP; 1705 } 1706 1707 if (!vnic) { 1708 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1709 return -EINVAL; 1710 } 1711 1712 /* Filter settings will get applied when port is started */ 1713 if (!eth_dev->data->dev_started) 1714 return 0; 1715 1716 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1717 1718 return rc; 1719 } 1720 1721 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 1722 { 1723 int rc = 0; 1724 struct bnxt *bp = eth_dev->data->dev_private; 1725 struct rte_eth_link new; 1726 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT : 1727 BNXT_MIN_LINK_WAIT_CNT; 1728 1729 rc = is_bnxt_in_error(bp); 1730 if (rc) 1731 return rc; 1732 1733 memset(&new, 0, sizeof(new)); 1734 1735 if (bp->link_info == NULL) 1736 goto out; 1737 1738 do { 1739 /* Retrieve link info from hardware */ 1740 rc = bnxt_get_hwrm_link_config(bp, &new); 1741 if (rc) { 1742 new.link_speed = ETH_LINK_SPEED_100M; 1743 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1744 PMD_DRV_LOG(ERR, 1745 "Failed to retrieve link rc = 0x%x!\n", rc); 1746 goto out; 1747 } 1748 1749 if (!wait_to_complete || new.link_status) 1750 break; 1751 1752 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1753 } while (cnt--); 1754 1755 /* Only single function PF can bring phy down. 1756 * When port is stopped, report link down for VF/MH/NPAR functions. 1757 */ 1758 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started) 1759 memset(&new, 0, sizeof(new)); 1760 1761 out: 1762 /* Timed out or success */ 1763 if (new.link_status != eth_dev->data->dev_link.link_status || 1764 new.link_speed != eth_dev->data->dev_link.link_speed) { 1765 rte_eth_linkstatus_set(eth_dev, &new); 1766 1767 rte_eth_dev_callback_process(eth_dev, 1768 RTE_ETH_EVENT_INTR_LSC, 1769 NULL); 1770 1771 bnxt_print_link_info(eth_dev); 1772 } 1773 1774 return rc; 1775 } 1776 1777 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1778 { 1779 struct bnxt *bp = eth_dev->data->dev_private; 1780 struct bnxt_vnic_info *vnic; 1781 uint32_t old_flags; 1782 int rc; 1783 1784 rc = is_bnxt_in_error(bp); 1785 if (rc) 1786 return rc; 1787 1788 /* Filter settings will get applied when port is started */ 1789 if (!eth_dev->data->dev_started) 1790 return 0; 1791 1792 if (bp->vnic_info == NULL) 1793 return 0; 1794 1795 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1796 1797 old_flags = vnic->flags; 1798 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1799 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1800 if (rc != 0) 1801 vnic->flags = old_flags; 1802 1803 return rc; 1804 } 1805 1806 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1807 { 1808 struct bnxt *bp = eth_dev->data->dev_private; 1809 struct bnxt_vnic_info *vnic; 1810 uint32_t old_flags; 1811 int rc; 1812 1813 rc = is_bnxt_in_error(bp); 1814 if (rc) 1815 return rc; 1816 1817 /* Filter settings will get applied when port is started */ 1818 if (!eth_dev->data->dev_started) 1819 return 0; 1820 1821 if (bp->vnic_info == NULL) 1822 return 0; 1823 1824 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1825 1826 old_flags = vnic->flags; 1827 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1828 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1829 if (rc != 0) 1830 vnic->flags = old_flags; 1831 1832 return rc; 1833 } 1834 1835 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1836 { 1837 struct bnxt *bp = eth_dev->data->dev_private; 1838 struct bnxt_vnic_info *vnic; 1839 uint32_t old_flags; 1840 int rc; 1841 1842 rc = is_bnxt_in_error(bp); 1843 if (rc) 1844 return rc; 1845 1846 /* Filter settings will get applied when port is started */ 1847 if (!eth_dev->data->dev_started) 1848 return 0; 1849 1850 if (bp->vnic_info == NULL) 1851 return 0; 1852 1853 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1854 1855 old_flags = vnic->flags; 1856 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1857 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1858 if (rc != 0) 1859 vnic->flags = old_flags; 1860 1861 return rc; 1862 } 1863 1864 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1865 { 1866 struct bnxt *bp = eth_dev->data->dev_private; 1867 struct bnxt_vnic_info *vnic; 1868 uint32_t old_flags; 1869 int rc; 1870 1871 rc = is_bnxt_in_error(bp); 1872 if (rc) 1873 return rc; 1874 1875 /* Filter settings will get applied when port is started */ 1876 if (!eth_dev->data->dev_started) 1877 return 0; 1878 1879 if (bp->vnic_info == NULL) 1880 return 0; 1881 1882 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1883 1884 old_flags = vnic->flags; 1885 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1886 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1887 if (rc != 0) 1888 vnic->flags = old_flags; 1889 1890 return rc; 1891 } 1892 1893 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1894 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1895 { 1896 if (qid >= bp->rx_nr_rings) 1897 return NULL; 1898 1899 return bp->eth_dev->data->rx_queues[qid]; 1900 } 1901 1902 /* Return rxq corresponding to a given rss table ring/group ID. */ 1903 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1904 { 1905 struct bnxt_rx_queue *rxq; 1906 unsigned int i; 1907 1908 if (!BNXT_HAS_RING_GRPS(bp)) { 1909 for (i = 0; i < bp->rx_nr_rings; i++) { 1910 rxq = bp->eth_dev->data->rx_queues[i]; 1911 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1912 return rxq->index; 1913 } 1914 } else { 1915 for (i = 0; i < bp->rx_nr_rings; i++) { 1916 if (bp->grp_info[i].fw_grp_id == fwr) 1917 return i; 1918 } 1919 } 1920 1921 return INVALID_HW_RING_ID; 1922 } 1923 1924 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1925 struct rte_eth_rss_reta_entry64 *reta_conf, 1926 uint16_t reta_size) 1927 { 1928 struct bnxt *bp = eth_dev->data->dev_private; 1929 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1930 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1931 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1932 uint16_t idx, sft; 1933 int i, rc; 1934 1935 rc = is_bnxt_in_error(bp); 1936 if (rc) 1937 return rc; 1938 1939 if (!vnic->rss_table) 1940 return -EINVAL; 1941 1942 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1943 return -EINVAL; 1944 1945 if (reta_size != tbl_size) { 1946 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1947 "(%d) must equal the size supported by the hardware " 1948 "(%d)\n", reta_size, tbl_size); 1949 return -EINVAL; 1950 } 1951 1952 for (i = 0; i < reta_size; i++) { 1953 struct bnxt_rx_queue *rxq; 1954 1955 idx = i / RTE_RETA_GROUP_SIZE; 1956 sft = i % RTE_RETA_GROUP_SIZE; 1957 1958 if (!(reta_conf[idx].mask & (1ULL << sft))) 1959 continue; 1960 1961 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1962 if (!rxq) { 1963 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1964 return -EINVAL; 1965 } 1966 1967 if (BNXT_CHIP_P5(bp)) { 1968 vnic->rss_table[i * 2] = 1969 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1970 vnic->rss_table[i * 2 + 1] = 1971 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1972 } else { 1973 vnic->rss_table[i] = 1974 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1975 } 1976 } 1977 1978 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1979 return rc; 1980 } 1981 1982 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1983 struct rte_eth_rss_reta_entry64 *reta_conf, 1984 uint16_t reta_size) 1985 { 1986 struct bnxt *bp = eth_dev->data->dev_private; 1987 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1988 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1989 uint16_t idx, sft, i; 1990 int rc; 1991 1992 rc = is_bnxt_in_error(bp); 1993 if (rc) 1994 return rc; 1995 1996 /* Retrieve from the default VNIC */ 1997 if (!vnic) 1998 return -EINVAL; 1999 if (!vnic->rss_table) 2000 return -EINVAL; 2001 2002 if (reta_size != tbl_size) { 2003 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 2004 "(%d) must equal the size supported by the hardware " 2005 "(%d)\n", reta_size, tbl_size); 2006 return -EINVAL; 2007 } 2008 2009 for (idx = 0, i = 0; i < reta_size; i++) { 2010 idx = i / RTE_RETA_GROUP_SIZE; 2011 sft = i % RTE_RETA_GROUP_SIZE; 2012 2013 if (reta_conf[idx].mask & (1ULL << sft)) { 2014 uint16_t qid; 2015 2016 if (BNXT_CHIP_P5(bp)) 2017 qid = bnxt_rss_to_qid(bp, 2018 vnic->rss_table[i * 2]); 2019 else 2020 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 2021 2022 if (qid == INVALID_HW_RING_ID) { 2023 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 2024 return -EINVAL; 2025 } 2026 reta_conf[idx].reta[sft] = qid; 2027 } 2028 } 2029 2030 return 0; 2031 } 2032 2033 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 2034 struct rte_eth_rss_conf *rss_conf) 2035 { 2036 struct bnxt *bp = eth_dev->data->dev_private; 2037 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 2038 struct bnxt_vnic_info *vnic; 2039 int rc; 2040 2041 rc = is_bnxt_in_error(bp); 2042 if (rc) 2043 return rc; 2044 2045 /* 2046 * If RSS enablement were different than dev_configure, 2047 * then return -EINVAL 2048 */ 2049 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 2050 if (!rss_conf->rss_hf) 2051 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 2052 } else { 2053 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 2054 return -EINVAL; 2055 } 2056 2057 bp->flags |= BNXT_FLAG_UPDATE_HASH; 2058 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf, 2059 rss_conf, 2060 sizeof(*rss_conf)); 2061 2062 /* Update the default RSS VNIC(s) */ 2063 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2064 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 2065 vnic->hash_mode = 2066 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf, 2067 ETH_RSS_LEVEL(rss_conf->rss_hf)); 2068 2069 /* 2070 * If hashkey is not specified, use the previously configured 2071 * hashkey 2072 */ 2073 if (!rss_conf->rss_key) 2074 goto rss_config; 2075 2076 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 2077 PMD_DRV_LOG(ERR, 2078 "Invalid hashkey length, should be 16 bytes\n"); 2079 return -EINVAL; 2080 } 2081 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 2082 2083 rss_config: 2084 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 2085 return rc; 2086 } 2087 2088 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 2089 struct rte_eth_rss_conf *rss_conf) 2090 { 2091 struct bnxt *bp = eth_dev->data->dev_private; 2092 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2093 int len, rc; 2094 uint32_t hash_types; 2095 2096 rc = is_bnxt_in_error(bp); 2097 if (rc) 2098 return rc; 2099 2100 /* RSS configuration is the same for all VNICs */ 2101 if (vnic && vnic->rss_hash_key) { 2102 if (rss_conf->rss_key) { 2103 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 2104 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 2105 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 2106 } 2107 2108 hash_types = vnic->hash_type; 2109 rss_conf->rss_hf = 0; 2110 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 2111 rss_conf->rss_hf |= ETH_RSS_IPV4; 2112 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 2113 } 2114 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 2115 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 2116 hash_types &= 2117 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 2118 } 2119 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 2120 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 2121 hash_types &= 2122 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 2123 } 2124 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 2125 rss_conf->rss_hf |= ETH_RSS_IPV6; 2126 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 2127 } 2128 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 2129 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 2130 hash_types &= 2131 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 2132 } 2133 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 2134 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 2135 hash_types &= 2136 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 2137 } 2138 2139 rss_conf->rss_hf |= 2140 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode); 2141 2142 if (hash_types) { 2143 PMD_DRV_LOG(ERR, 2144 "Unknown RSS config from firmware (%08x), RSS disabled", 2145 vnic->hash_type); 2146 return -ENOTSUP; 2147 } 2148 } else { 2149 rss_conf->rss_hf = 0; 2150 } 2151 return 0; 2152 } 2153 2154 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 2155 struct rte_eth_fc_conf *fc_conf) 2156 { 2157 struct bnxt *bp = dev->data->dev_private; 2158 struct rte_eth_link link_info; 2159 int rc; 2160 2161 rc = is_bnxt_in_error(bp); 2162 if (rc) 2163 return rc; 2164 2165 rc = bnxt_get_hwrm_link_config(bp, &link_info); 2166 if (rc) 2167 return rc; 2168 2169 memset(fc_conf, 0, sizeof(*fc_conf)); 2170 if (bp->link_info->auto_pause) 2171 fc_conf->autoneg = 1; 2172 switch (bp->link_info->pause) { 2173 case 0: 2174 fc_conf->mode = RTE_FC_NONE; 2175 break; 2176 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 2177 fc_conf->mode = RTE_FC_TX_PAUSE; 2178 break; 2179 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 2180 fc_conf->mode = RTE_FC_RX_PAUSE; 2181 break; 2182 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 2183 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 2184 fc_conf->mode = RTE_FC_FULL; 2185 break; 2186 } 2187 return 0; 2188 } 2189 2190 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 2191 struct rte_eth_fc_conf *fc_conf) 2192 { 2193 struct bnxt *bp = dev->data->dev_private; 2194 int rc; 2195 2196 rc = is_bnxt_in_error(bp); 2197 if (rc) 2198 return rc; 2199 2200 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2201 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 2202 return -ENOTSUP; 2203 } 2204 2205 switch (fc_conf->mode) { 2206 case RTE_FC_NONE: 2207 bp->link_info->auto_pause = 0; 2208 bp->link_info->force_pause = 0; 2209 break; 2210 case RTE_FC_RX_PAUSE: 2211 if (fc_conf->autoneg) { 2212 bp->link_info->auto_pause = 2213 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2214 bp->link_info->force_pause = 0; 2215 } else { 2216 bp->link_info->auto_pause = 0; 2217 bp->link_info->force_pause = 2218 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2219 } 2220 break; 2221 case RTE_FC_TX_PAUSE: 2222 if (fc_conf->autoneg) { 2223 bp->link_info->auto_pause = 2224 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 2225 bp->link_info->force_pause = 0; 2226 } else { 2227 bp->link_info->auto_pause = 0; 2228 bp->link_info->force_pause = 2229 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 2230 } 2231 break; 2232 case RTE_FC_FULL: 2233 if (fc_conf->autoneg) { 2234 bp->link_info->auto_pause = 2235 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 2236 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2237 bp->link_info->force_pause = 0; 2238 } else { 2239 bp->link_info->auto_pause = 0; 2240 bp->link_info->force_pause = 2241 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 2242 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2243 } 2244 break; 2245 } 2246 return bnxt_set_hwrm_link_config(bp, true); 2247 } 2248 2249 /* Add UDP tunneling port */ 2250 static int 2251 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 2252 struct rte_eth_udp_tunnel *udp_tunnel) 2253 { 2254 struct bnxt *bp = eth_dev->data->dev_private; 2255 uint16_t tunnel_type = 0; 2256 int rc = 0; 2257 2258 rc = is_bnxt_in_error(bp); 2259 if (rc) 2260 return rc; 2261 2262 switch (udp_tunnel->prot_type) { 2263 case RTE_TUNNEL_TYPE_VXLAN: 2264 if (bp->vxlan_port_cnt) { 2265 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2266 udp_tunnel->udp_port); 2267 if (bp->vxlan_port != udp_tunnel->udp_port) { 2268 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2269 return -ENOSPC; 2270 } 2271 bp->vxlan_port_cnt++; 2272 return 0; 2273 } 2274 tunnel_type = 2275 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 2276 bp->vxlan_port_cnt++; 2277 break; 2278 case RTE_TUNNEL_TYPE_GENEVE: 2279 if (bp->geneve_port_cnt) { 2280 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2281 udp_tunnel->udp_port); 2282 if (bp->geneve_port != udp_tunnel->udp_port) { 2283 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2284 return -ENOSPC; 2285 } 2286 bp->geneve_port_cnt++; 2287 return 0; 2288 } 2289 tunnel_type = 2290 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 2291 bp->geneve_port_cnt++; 2292 break; 2293 default: 2294 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2295 return -ENOTSUP; 2296 } 2297 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 2298 tunnel_type); 2299 return rc; 2300 } 2301 2302 static int 2303 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 2304 struct rte_eth_udp_tunnel *udp_tunnel) 2305 { 2306 struct bnxt *bp = eth_dev->data->dev_private; 2307 uint16_t tunnel_type = 0; 2308 uint16_t port = 0; 2309 int rc = 0; 2310 2311 rc = is_bnxt_in_error(bp); 2312 if (rc) 2313 return rc; 2314 2315 switch (udp_tunnel->prot_type) { 2316 case RTE_TUNNEL_TYPE_VXLAN: 2317 if (!bp->vxlan_port_cnt) { 2318 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2319 return -EINVAL; 2320 } 2321 if (bp->vxlan_port != udp_tunnel->udp_port) { 2322 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2323 udp_tunnel->udp_port, bp->vxlan_port); 2324 return -EINVAL; 2325 } 2326 if (--bp->vxlan_port_cnt) 2327 return 0; 2328 2329 tunnel_type = 2330 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 2331 port = bp->vxlan_fw_dst_port_id; 2332 break; 2333 case RTE_TUNNEL_TYPE_GENEVE: 2334 if (!bp->geneve_port_cnt) { 2335 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2336 return -EINVAL; 2337 } 2338 if (bp->geneve_port != udp_tunnel->udp_port) { 2339 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2340 udp_tunnel->udp_port, bp->geneve_port); 2341 return -EINVAL; 2342 } 2343 if (--bp->geneve_port_cnt) 2344 return 0; 2345 2346 tunnel_type = 2347 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 2348 port = bp->geneve_fw_dst_port_id; 2349 break; 2350 default: 2351 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2352 return -ENOTSUP; 2353 } 2354 2355 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 2356 return rc; 2357 } 2358 2359 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2360 { 2361 struct bnxt_filter_info *filter; 2362 struct bnxt_vnic_info *vnic; 2363 int rc = 0; 2364 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2365 2366 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2367 filter = STAILQ_FIRST(&vnic->filter); 2368 while (filter) { 2369 /* Search for this matching MAC+VLAN filter */ 2370 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 2371 /* Delete the filter */ 2372 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2373 if (rc) 2374 return rc; 2375 STAILQ_REMOVE(&vnic->filter, filter, 2376 bnxt_filter_info, next); 2377 bnxt_free_filter(bp, filter); 2378 PMD_DRV_LOG(INFO, 2379 "Deleted vlan filter for %d\n", 2380 vlan_id); 2381 return 0; 2382 } 2383 filter = STAILQ_NEXT(filter, next); 2384 } 2385 return -ENOENT; 2386 } 2387 2388 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2389 { 2390 struct bnxt_filter_info *filter; 2391 struct bnxt_vnic_info *vnic; 2392 int rc = 0; 2393 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 2394 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 2395 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2396 2397 /* Implementation notes on the use of VNIC in this command: 2398 * 2399 * By default, these filters belong to default vnic for the function. 2400 * Once these filters are set up, only destination VNIC can be modified. 2401 * If the destination VNIC is not specified in this command, 2402 * then the HWRM shall only create an l2 context id. 2403 */ 2404 2405 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2406 filter = STAILQ_FIRST(&vnic->filter); 2407 /* Check if the VLAN has already been added */ 2408 while (filter) { 2409 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 2410 return -EEXIST; 2411 2412 filter = STAILQ_NEXT(filter, next); 2413 } 2414 2415 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 2416 * command to create MAC+VLAN filter with the right flags, enables set. 2417 */ 2418 filter = bnxt_alloc_filter(bp); 2419 if (!filter) { 2420 PMD_DRV_LOG(ERR, 2421 "MAC/VLAN filter alloc failed\n"); 2422 return -ENOMEM; 2423 } 2424 /* MAC + VLAN ID filter */ 2425 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 2426 * untagged packets are received 2427 * 2428 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 2429 * packets and only the programmed vlan's packets are received 2430 */ 2431 filter->l2_ivlan = vlan_id; 2432 filter->l2_ivlan_mask = 0x0FFF; 2433 filter->enables |= en; 2434 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2435 2436 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2437 if (rc) { 2438 /* Free the newly allocated filter as we were 2439 * not able to create the filter in hardware. 2440 */ 2441 bnxt_free_filter(bp, filter); 2442 return rc; 2443 } 2444 2445 filter->mac_index = 0; 2446 /* Add this new filter to the list */ 2447 if (vlan_id == 0) 2448 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 2449 else 2450 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2451 2452 PMD_DRV_LOG(INFO, 2453 "Added Vlan filter for %d\n", vlan_id); 2454 return rc; 2455 } 2456 2457 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 2458 uint16_t vlan_id, int on) 2459 { 2460 struct bnxt *bp = eth_dev->data->dev_private; 2461 int rc; 2462 2463 rc = is_bnxt_in_error(bp); 2464 if (rc) 2465 return rc; 2466 2467 if (!eth_dev->data->dev_started) { 2468 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n"); 2469 return -EINVAL; 2470 } 2471 2472 /* These operations apply to ALL existing MAC/VLAN filters */ 2473 if (on) 2474 return bnxt_add_vlan_filter(bp, vlan_id); 2475 else 2476 return bnxt_del_vlan_filter(bp, vlan_id); 2477 } 2478 2479 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 2480 struct bnxt_vnic_info *vnic) 2481 { 2482 struct bnxt_filter_info *filter; 2483 int rc; 2484 2485 filter = STAILQ_FIRST(&vnic->filter); 2486 while (filter) { 2487 if (filter->mac_index == 0 && 2488 !memcmp(filter->l2_addr, bp->mac_addr, 2489 RTE_ETHER_ADDR_LEN)) { 2490 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2491 if (!rc) { 2492 STAILQ_REMOVE(&vnic->filter, filter, 2493 bnxt_filter_info, next); 2494 bnxt_free_filter(bp, filter); 2495 } 2496 return rc; 2497 } 2498 filter = STAILQ_NEXT(filter, next); 2499 } 2500 return 0; 2501 } 2502 2503 static int 2504 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 2505 { 2506 struct bnxt_vnic_info *vnic; 2507 unsigned int i; 2508 int rc; 2509 2510 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2511 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 2512 /* Remove any VLAN filters programmed */ 2513 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2514 bnxt_del_vlan_filter(bp, i); 2515 2516 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2517 if (rc) 2518 return rc; 2519 } else { 2520 /* Default filter will allow packets that match the 2521 * dest mac. So, it has to be deleted, otherwise, we 2522 * will endup receiving vlan packets for which the 2523 * filter is not programmed, when hw-vlan-filter 2524 * configuration is ON 2525 */ 2526 bnxt_del_dflt_mac_filter(bp, vnic); 2527 /* This filter will allow only untagged packets */ 2528 bnxt_add_vlan_filter(bp, 0); 2529 } 2530 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 2531 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 2532 2533 return 0; 2534 } 2535 2536 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 2537 { 2538 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2539 unsigned int i; 2540 int rc; 2541 2542 /* Destroy vnic filters and vnic */ 2543 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2544 DEV_RX_OFFLOAD_VLAN_FILTER) { 2545 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2546 bnxt_del_vlan_filter(bp, i); 2547 } 2548 bnxt_del_dflt_mac_filter(bp, vnic); 2549 2550 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic); 2551 if (rc) 2552 return rc; 2553 2554 rc = bnxt_hwrm_vnic_free(bp, vnic); 2555 if (rc) 2556 return rc; 2557 2558 rte_free(vnic->fw_grp_ids); 2559 vnic->fw_grp_ids = NULL; 2560 2561 vnic->rx_queue_cnt = 0; 2562 2563 return 0; 2564 } 2565 2566 static int 2567 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 2568 { 2569 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2570 int rc; 2571 2572 /* Destroy, recreate and reconfigure the default vnic */ 2573 rc = bnxt_free_one_vnic(bp, 0); 2574 if (rc) 2575 return rc; 2576 2577 /* default vnic 0 */ 2578 rc = bnxt_setup_one_vnic(bp, 0); 2579 if (rc) 2580 return rc; 2581 2582 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2583 DEV_RX_OFFLOAD_VLAN_FILTER) { 2584 rc = bnxt_add_vlan_filter(bp, 0); 2585 if (rc) 2586 return rc; 2587 rc = bnxt_restore_vlan_filters(bp); 2588 if (rc) 2589 return rc; 2590 } else { 2591 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2592 if (rc) 2593 return rc; 2594 } 2595 2596 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2597 if (rc) 2598 return rc; 2599 2600 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 2601 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 2602 2603 return rc; 2604 } 2605 2606 static int 2607 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 2608 { 2609 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 2610 struct bnxt *bp = dev->data->dev_private; 2611 int rc; 2612 2613 rc = is_bnxt_in_error(bp); 2614 if (rc) 2615 return rc; 2616 2617 /* Filter settings will get applied when port is started */ 2618 if (!dev->data->dev_started) 2619 return 0; 2620 2621 if (mask & ETH_VLAN_FILTER_MASK) { 2622 /* Enable or disable VLAN filtering */ 2623 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 2624 if (rc) 2625 return rc; 2626 } 2627 2628 if (mask & ETH_VLAN_STRIP_MASK) { 2629 /* Enable or disable VLAN stripping */ 2630 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2631 if (rc) 2632 return rc; 2633 } 2634 2635 if (mask & ETH_VLAN_EXTEND_MASK) { 2636 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2637 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2638 else 2639 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2640 } 2641 2642 return 0; 2643 } 2644 2645 static int 2646 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2647 uint16_t tpid) 2648 { 2649 struct bnxt *bp = dev->data->dev_private; 2650 int qinq = dev->data->dev_conf.rxmode.offloads & 2651 DEV_RX_OFFLOAD_VLAN_EXTEND; 2652 2653 if (vlan_type != ETH_VLAN_TYPE_INNER && 2654 vlan_type != ETH_VLAN_TYPE_OUTER) { 2655 PMD_DRV_LOG(ERR, 2656 "Unsupported vlan type."); 2657 return -EINVAL; 2658 } 2659 if (!qinq) { 2660 PMD_DRV_LOG(ERR, 2661 "QinQ not enabled. Needs to be ON as we can " 2662 "accelerate only outer vlan\n"); 2663 return -EINVAL; 2664 } 2665 2666 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 2667 switch (tpid) { 2668 case RTE_ETHER_TYPE_QINQ: 2669 bp->outer_tpid_bd = 2670 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2671 break; 2672 case RTE_ETHER_TYPE_VLAN: 2673 bp->outer_tpid_bd = 2674 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2675 break; 2676 case RTE_ETHER_TYPE_QINQ1: 2677 bp->outer_tpid_bd = 2678 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2679 break; 2680 case RTE_ETHER_TYPE_QINQ2: 2681 bp->outer_tpid_bd = 2682 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2683 break; 2684 case RTE_ETHER_TYPE_QINQ3: 2685 bp->outer_tpid_bd = 2686 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2687 break; 2688 default: 2689 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2690 return -EINVAL; 2691 } 2692 bp->outer_tpid_bd |= tpid; 2693 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2694 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 2695 PMD_DRV_LOG(ERR, 2696 "Can accelerate only outer vlan in QinQ\n"); 2697 return -EINVAL; 2698 } 2699 2700 return 0; 2701 } 2702 2703 static int 2704 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2705 struct rte_ether_addr *addr) 2706 { 2707 struct bnxt *bp = dev->data->dev_private; 2708 /* Default Filter is tied to VNIC 0 */ 2709 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2710 int rc; 2711 2712 rc = is_bnxt_in_error(bp); 2713 if (rc) 2714 return rc; 2715 2716 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2717 return -EPERM; 2718 2719 if (rte_is_zero_ether_addr(addr)) 2720 return -EINVAL; 2721 2722 /* Filter settings will get applied when port is started */ 2723 if (!dev->data->dev_started) 2724 return 0; 2725 2726 /* Check if the requested MAC is already added */ 2727 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2728 return 0; 2729 2730 /* Destroy filter and re-create it */ 2731 bnxt_del_dflt_mac_filter(bp, vnic); 2732 2733 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2734 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 2735 /* This filter will allow only untagged packets */ 2736 rc = bnxt_add_vlan_filter(bp, 0); 2737 } else { 2738 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2739 } 2740 2741 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2742 return rc; 2743 } 2744 2745 static int 2746 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2747 struct rte_ether_addr *mc_addr_set, 2748 uint32_t nb_mc_addr) 2749 { 2750 struct bnxt *bp = eth_dev->data->dev_private; 2751 char *mc_addr_list = (char *)mc_addr_set; 2752 struct bnxt_vnic_info *vnic; 2753 uint32_t off = 0, i = 0; 2754 int rc; 2755 2756 rc = is_bnxt_in_error(bp); 2757 if (rc) 2758 return rc; 2759 2760 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2761 2762 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2763 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2764 goto allmulti; 2765 } 2766 2767 /* TODO Check for Duplicate mcast addresses */ 2768 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2769 for (i = 0; i < nb_mc_addr; i++) { 2770 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2771 RTE_ETHER_ADDR_LEN); 2772 off += RTE_ETHER_ADDR_LEN; 2773 } 2774 2775 vnic->mc_addr_cnt = i; 2776 if (vnic->mc_addr_cnt) 2777 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2778 else 2779 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2780 2781 allmulti: 2782 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2783 } 2784 2785 static int 2786 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2787 { 2788 struct bnxt *bp = dev->data->dev_private; 2789 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2790 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2791 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2792 uint8_t fw_rsvd = bp->fw_ver & 0xff; 2793 int ret; 2794 2795 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", 2796 fw_major, fw_minor, fw_updt, fw_rsvd); 2797 2798 ret += 1; /* add the size of '\0' */ 2799 if (fw_size < (uint32_t)ret) 2800 return ret; 2801 else 2802 return 0; 2803 } 2804 2805 static void 2806 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2807 struct rte_eth_rxq_info *qinfo) 2808 { 2809 struct bnxt *bp = dev->data->dev_private; 2810 struct bnxt_rx_queue *rxq; 2811 2812 if (is_bnxt_in_error(bp)) 2813 return; 2814 2815 rxq = dev->data->rx_queues[queue_id]; 2816 2817 qinfo->mp = rxq->mb_pool; 2818 qinfo->scattered_rx = dev->data->scattered_rx; 2819 qinfo->nb_desc = rxq->nb_rx_desc; 2820 2821 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2822 qinfo->conf.rx_drop_en = rxq->drop_en; 2823 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2824 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 2825 } 2826 2827 static void 2828 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2829 struct rte_eth_txq_info *qinfo) 2830 { 2831 struct bnxt *bp = dev->data->dev_private; 2832 struct bnxt_tx_queue *txq; 2833 2834 if (is_bnxt_in_error(bp)) 2835 return; 2836 2837 txq = dev->data->tx_queues[queue_id]; 2838 2839 qinfo->nb_desc = txq->nb_tx_desc; 2840 2841 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2842 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2843 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2844 2845 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2846 qinfo->conf.tx_rs_thresh = 0; 2847 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2848 qinfo->conf.offloads = txq->offloads; 2849 } 2850 2851 static const struct { 2852 eth_rx_burst_t pkt_burst; 2853 const char *info; 2854 } bnxt_rx_burst_info[] = { 2855 {bnxt_recv_pkts, "Scalar"}, 2856 #if defined(RTE_ARCH_X86) 2857 {bnxt_recv_pkts_vec, "Vector SSE"}, 2858 #elif defined(RTE_ARCH_ARM64) 2859 {bnxt_recv_pkts_vec, "Vector Neon"}, 2860 #endif 2861 }; 2862 2863 static int 2864 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2865 struct rte_eth_burst_mode *mode) 2866 { 2867 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 2868 size_t i; 2869 2870 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) { 2871 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) { 2872 snprintf(mode->info, sizeof(mode->info), "%s", 2873 bnxt_rx_burst_info[i].info); 2874 return 0; 2875 } 2876 } 2877 2878 return -EINVAL; 2879 } 2880 2881 static const struct { 2882 eth_tx_burst_t pkt_burst; 2883 const char *info; 2884 } bnxt_tx_burst_info[] = { 2885 {bnxt_xmit_pkts, "Scalar"}, 2886 #if defined(RTE_ARCH_X86) 2887 {bnxt_xmit_pkts_vec, "Vector SSE"}, 2888 #elif defined(RTE_ARCH_ARM64) 2889 {bnxt_xmit_pkts_vec, "Vector Neon"}, 2890 #endif 2891 }; 2892 2893 static int 2894 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2895 struct rte_eth_burst_mode *mode) 2896 { 2897 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 2898 size_t i; 2899 2900 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) { 2901 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) { 2902 snprintf(mode->info, sizeof(mode->info), "%s", 2903 bnxt_tx_burst_info[i].info); 2904 return 0; 2905 } 2906 } 2907 2908 return -EINVAL; 2909 } 2910 2911 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 2912 { 2913 struct bnxt *bp = eth_dev->data->dev_private; 2914 uint32_t new_pkt_size; 2915 uint32_t rc = 0; 2916 uint32_t i; 2917 2918 rc = is_bnxt_in_error(bp); 2919 if (rc) 2920 return rc; 2921 2922 /* Exit if receive queues are not configured yet */ 2923 if (!eth_dev->data->nb_rx_queues) 2924 return rc; 2925 2926 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 2927 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 2928 2929 /* 2930 * Disallow any MTU change that would require scattered receive support 2931 * if it is not already enabled. 2932 */ 2933 if (eth_dev->data->dev_started && 2934 !eth_dev->data->scattered_rx && 2935 (new_pkt_size > 2936 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 2937 PMD_DRV_LOG(ERR, 2938 "MTU change would require scattered rx support. "); 2939 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 2940 return -EINVAL; 2941 } 2942 2943 if (new_mtu > RTE_ETHER_MTU) { 2944 bp->flags |= BNXT_FLAG_JUMBO; 2945 bp->eth_dev->data->dev_conf.rxmode.offloads |= 2946 DEV_RX_OFFLOAD_JUMBO_FRAME; 2947 } else { 2948 bp->eth_dev->data->dev_conf.rxmode.offloads &= 2949 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2950 bp->flags &= ~BNXT_FLAG_JUMBO; 2951 } 2952 2953 /* Is there a change in mtu setting? */ 2954 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) 2955 return rc; 2956 2957 for (i = 0; i < bp->nr_vnics; i++) { 2958 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2959 uint16_t size = 0; 2960 2961 vnic->mru = BNXT_VNIC_MRU(new_mtu); 2962 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 2963 if (rc) 2964 break; 2965 2966 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 2967 size -= RTE_PKTMBUF_HEADROOM; 2968 2969 if (size < new_mtu) { 2970 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 2971 if (rc) 2972 return rc; 2973 } 2974 } 2975 2976 if (!rc) 2977 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 2978 2979 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 2980 2981 return rc; 2982 } 2983 2984 static int 2985 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 2986 { 2987 struct bnxt *bp = dev->data->dev_private; 2988 uint16_t vlan = bp->vlan; 2989 int rc; 2990 2991 rc = is_bnxt_in_error(bp); 2992 if (rc) 2993 return rc; 2994 2995 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2996 PMD_DRV_LOG(ERR, 2997 "PVID cannot be modified for this function\n"); 2998 return -ENOTSUP; 2999 } 3000 bp->vlan = on ? pvid : 0; 3001 3002 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 3003 if (rc) 3004 bp->vlan = vlan; 3005 return rc; 3006 } 3007 3008 static int 3009 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 3010 { 3011 struct bnxt *bp = dev->data->dev_private; 3012 int rc; 3013 3014 rc = is_bnxt_in_error(bp); 3015 if (rc) 3016 return rc; 3017 3018 return bnxt_hwrm_port_led_cfg(bp, true); 3019 } 3020 3021 static int 3022 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 3023 { 3024 struct bnxt *bp = dev->data->dev_private; 3025 int rc; 3026 3027 rc = is_bnxt_in_error(bp); 3028 if (rc) 3029 return rc; 3030 3031 return bnxt_hwrm_port_led_cfg(bp, false); 3032 } 3033 3034 static uint32_t 3035 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 3036 { 3037 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 3038 struct bnxt_cp_ring_info *cpr; 3039 uint32_t desc = 0, raw_cons; 3040 struct bnxt_rx_queue *rxq; 3041 struct rx_pkt_cmpl *rxcmp; 3042 int rc; 3043 3044 rc = is_bnxt_in_error(bp); 3045 if (rc) 3046 return rc; 3047 3048 rxq = dev->data->rx_queues[rx_queue_id]; 3049 cpr = rxq->cp_ring; 3050 raw_cons = cpr->cp_raw_cons; 3051 3052 while (1) { 3053 uint32_t agg_cnt, cons, cmpl_type; 3054 3055 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3056 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3057 3058 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 3059 break; 3060 3061 cmpl_type = CMP_TYPE(rxcmp); 3062 3063 switch (cmpl_type) { 3064 case CMPL_BASE_TYPE_RX_L2: 3065 case CMPL_BASE_TYPE_RX_L2_V2: 3066 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3067 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3068 desc++; 3069 break; 3070 3071 case CMPL_BASE_TYPE_RX_TPA_END: 3072 if (BNXT_CHIP_P5(rxq->bp)) { 3073 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3074 3075 p5_tpa_end = (void *)rxcmp; 3076 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3077 } else { 3078 struct rx_tpa_end_cmpl *tpa_end; 3079 3080 tpa_end = (void *)rxcmp; 3081 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3082 } 3083 3084 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3085 desc++; 3086 break; 3087 3088 default: 3089 raw_cons += CMP_LEN(cmpl_type); 3090 } 3091 } 3092 3093 return desc; 3094 } 3095 3096 static int 3097 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 3098 { 3099 struct bnxt_rx_queue *rxq = rx_queue; 3100 struct bnxt_cp_ring_info *cpr; 3101 struct bnxt_rx_ring_info *rxr; 3102 uint32_t desc, raw_cons; 3103 struct bnxt *bp = rxq->bp; 3104 struct rx_pkt_cmpl *rxcmp; 3105 int rc; 3106 3107 rc = is_bnxt_in_error(bp); 3108 if (rc) 3109 return rc; 3110 3111 if (offset >= rxq->nb_rx_desc) 3112 return -EINVAL; 3113 3114 rxr = rxq->rx_ring; 3115 cpr = rxq->cp_ring; 3116 3117 /* 3118 * For the vector receive case, the completion at the requested 3119 * offset can be indexed directly. 3120 */ 3121 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 3122 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) { 3123 struct rx_pkt_cmpl *rxcmp; 3124 uint32_t cons; 3125 3126 /* Check status of completion descriptor. */ 3127 raw_cons = cpr->cp_raw_cons + 3128 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2); 3129 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3130 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3131 3132 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 3133 return RTE_ETH_RX_DESC_DONE; 3134 3135 /* Check whether rx desc has an mbuf attached. */ 3136 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2); 3137 if (cons >= rxq->rxrearm_start && 3138 cons < rxq->rxrearm_start + rxq->rxrearm_nb) { 3139 return RTE_ETH_RX_DESC_UNAVAIL; 3140 } 3141 3142 return RTE_ETH_RX_DESC_AVAIL; 3143 } 3144 #endif 3145 3146 /* 3147 * For the non-vector receive case, scan the completion ring to 3148 * locate the completion descriptor for the requested offset. 3149 */ 3150 raw_cons = cpr->cp_raw_cons; 3151 desc = 0; 3152 while (1) { 3153 uint32_t agg_cnt, cons, cmpl_type; 3154 3155 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3156 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3157 3158 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 3159 break; 3160 3161 cmpl_type = CMP_TYPE(rxcmp); 3162 3163 switch (cmpl_type) { 3164 case CMPL_BASE_TYPE_RX_L2: 3165 case CMPL_BASE_TYPE_RX_L2_V2: 3166 if (desc == offset) { 3167 cons = rxcmp->opaque; 3168 if (rxr->rx_buf_ring[cons]) 3169 return RTE_ETH_RX_DESC_DONE; 3170 else 3171 return RTE_ETH_RX_DESC_UNAVAIL; 3172 } 3173 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3174 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3175 desc++; 3176 break; 3177 3178 case CMPL_BASE_TYPE_RX_TPA_END: 3179 if (desc == offset) 3180 return RTE_ETH_RX_DESC_DONE; 3181 3182 if (BNXT_CHIP_P5(rxq->bp)) { 3183 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3184 3185 p5_tpa_end = (void *)rxcmp; 3186 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3187 } else { 3188 struct rx_tpa_end_cmpl *tpa_end; 3189 3190 tpa_end = (void *)rxcmp; 3191 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3192 } 3193 3194 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3195 desc++; 3196 break; 3197 3198 default: 3199 raw_cons += CMP_LEN(cmpl_type); 3200 } 3201 } 3202 3203 return RTE_ETH_RX_DESC_AVAIL; 3204 } 3205 3206 static int 3207 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 3208 { 3209 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 3210 struct bnxt_tx_ring_info *txr; 3211 struct bnxt_cp_ring_info *cpr; 3212 struct rte_mbuf **tx_buf; 3213 struct tx_pkt_cmpl *txcmp; 3214 uint32_t cons, cp_cons; 3215 int rc; 3216 3217 if (!txq) 3218 return -EINVAL; 3219 3220 rc = is_bnxt_in_error(txq->bp); 3221 if (rc) 3222 return rc; 3223 3224 cpr = txq->cp_ring; 3225 txr = txq->tx_ring; 3226 3227 if (offset >= txq->nb_tx_desc) 3228 return -EINVAL; 3229 3230 cons = RING_CMP(cpr->cp_ring_struct, offset); 3231 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3232 cp_cons = cpr->cp_raw_cons; 3233 3234 if (cons > cp_cons) { 3235 if (CMPL_VALID(txcmp, cpr->valid)) 3236 return RTE_ETH_TX_DESC_UNAVAIL; 3237 } else { 3238 if (CMPL_VALID(txcmp, !cpr->valid)) 3239 return RTE_ETH_TX_DESC_UNAVAIL; 3240 } 3241 tx_buf = &txr->tx_buf_ring[cons]; 3242 if (*tx_buf == NULL) 3243 return RTE_ETH_TX_DESC_DONE; 3244 3245 return RTE_ETH_TX_DESC_FULL; 3246 } 3247 3248 int 3249 bnxt_flow_ops_get_op(struct rte_eth_dev *dev, 3250 const struct rte_flow_ops **ops) 3251 { 3252 struct bnxt *bp = dev->data->dev_private; 3253 int ret = 0; 3254 3255 if (!bp) 3256 return -EIO; 3257 3258 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) { 3259 struct bnxt_representor *vfr = dev->data->dev_private; 3260 bp = vfr->parent_dev->data->dev_private; 3261 /* parent is deleted while children are still valid */ 3262 if (!bp) { 3263 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n", 3264 dev->data->port_id); 3265 return -EIO; 3266 } 3267 } 3268 3269 ret = is_bnxt_in_error(bp); 3270 if (ret) 3271 return ret; 3272 3273 /* PMD supports thread-safe flow operations. rte_flow API 3274 * functions can avoid mutex for multi-thread safety. 3275 */ 3276 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 3277 3278 if (BNXT_TRUFLOW_EN(bp)) 3279 *ops = &bnxt_ulp_rte_flow_ops; 3280 else 3281 *ops = &bnxt_flow_ops; 3282 3283 return ret; 3284 } 3285 3286 static const uint32_t * 3287 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3288 { 3289 static const uint32_t ptypes[] = { 3290 RTE_PTYPE_L2_ETHER_VLAN, 3291 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3292 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3293 RTE_PTYPE_L4_ICMP, 3294 RTE_PTYPE_L4_TCP, 3295 RTE_PTYPE_L4_UDP, 3296 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3297 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3298 RTE_PTYPE_INNER_L4_ICMP, 3299 RTE_PTYPE_INNER_L4_TCP, 3300 RTE_PTYPE_INNER_L4_UDP, 3301 RTE_PTYPE_UNKNOWN 3302 }; 3303 3304 if (!dev->rx_pkt_burst) 3305 return NULL; 3306 3307 return ptypes; 3308 } 3309 3310 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3311 int reg_win) 3312 { 3313 uint32_t reg_base = *reg_arr & 0xfffff000; 3314 uint32_t win_off; 3315 int i; 3316 3317 for (i = 0; i < count; i++) { 3318 if ((reg_arr[i] & 0xfffff000) != reg_base) 3319 return -ERANGE; 3320 } 3321 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3322 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3323 return 0; 3324 } 3325 3326 static int bnxt_map_ptp_regs(struct bnxt *bp) 3327 { 3328 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3329 uint32_t *reg_arr; 3330 int rc, i; 3331 3332 reg_arr = ptp->rx_regs; 3333 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3334 if (rc) 3335 return rc; 3336 3337 reg_arr = ptp->tx_regs; 3338 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3339 if (rc) 3340 return rc; 3341 3342 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3343 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3344 3345 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3346 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3347 3348 return 0; 3349 } 3350 3351 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3352 { 3353 rte_write32(0, (uint8_t *)bp->bar0 + 3354 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3355 rte_write32(0, (uint8_t *)bp->bar0 + 3356 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3357 } 3358 3359 static uint64_t bnxt_cc_read(struct bnxt *bp) 3360 { 3361 uint64_t ns; 3362 3363 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3364 BNXT_GRCPF_REG_SYNC_TIME)); 3365 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3366 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3367 return ns; 3368 } 3369 3370 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3371 { 3372 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3373 uint32_t fifo; 3374 3375 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3376 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3377 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3378 return -EAGAIN; 3379 3380 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3381 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3382 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3383 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3384 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3385 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3386 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]); 3387 3388 return 0; 3389 } 3390 3391 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3392 { 3393 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3394 struct bnxt_pf_info *pf = bp->pf; 3395 uint16_t port_id; 3396 uint32_t fifo; 3397 3398 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3399 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3400 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3401 return -EAGAIN; 3402 3403 port_id = pf->port_id; 3404 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3405 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3406 3407 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3408 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3409 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 3410 /* bnxt_clr_rx_ts(bp); TBD */ 3411 return -EBUSY; 3412 } 3413 3414 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3415 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3416 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3417 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3418 3419 return 0; 3420 } 3421 3422 static int 3423 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3424 { 3425 uint64_t ns; 3426 struct bnxt *bp = dev->data->dev_private; 3427 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3428 3429 if (!ptp) 3430 return -ENOTSUP; 3431 3432 ns = rte_timespec_to_ns(ts); 3433 /* Set the timecounters to a new value. */ 3434 ptp->tc.nsec = ns; 3435 ptp->tx_tstamp_tc.nsec = ns; 3436 ptp->rx_tstamp_tc.nsec = ns; 3437 3438 return 0; 3439 } 3440 3441 static int 3442 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3443 { 3444 struct bnxt *bp = dev->data->dev_private; 3445 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3446 uint64_t ns, systime_cycles = 0; 3447 int rc = 0; 3448 3449 if (!ptp) 3450 return -ENOTSUP; 3451 3452 if (BNXT_CHIP_P5(bp)) 3453 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3454 &systime_cycles); 3455 else 3456 systime_cycles = bnxt_cc_read(bp); 3457 3458 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3459 *ts = rte_ns_to_timespec(ns); 3460 3461 return rc; 3462 } 3463 static int 3464 bnxt_timesync_enable(struct rte_eth_dev *dev) 3465 { 3466 struct bnxt *bp = dev->data->dev_private; 3467 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3468 uint32_t shift = 0; 3469 int rc; 3470 3471 if (!ptp) 3472 return -ENOTSUP; 3473 3474 ptp->rx_filter = 1; 3475 ptp->tx_tstamp_en = 1; 3476 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3477 3478 rc = bnxt_hwrm_ptp_cfg(bp); 3479 if (rc) 3480 return rc; 3481 3482 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3483 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3484 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3485 3486 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3487 ptp->tc.cc_shift = shift; 3488 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3489 3490 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3491 ptp->rx_tstamp_tc.cc_shift = shift; 3492 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3493 3494 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3495 ptp->tx_tstamp_tc.cc_shift = shift; 3496 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3497 3498 if (!BNXT_CHIP_P5(bp)) 3499 bnxt_map_ptp_regs(bp); 3500 else 3501 rc = bnxt_ptp_start(bp); 3502 3503 return rc; 3504 } 3505 3506 static int 3507 bnxt_timesync_disable(struct rte_eth_dev *dev) 3508 { 3509 struct bnxt *bp = dev->data->dev_private; 3510 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3511 3512 if (!ptp) 3513 return -ENOTSUP; 3514 3515 ptp->rx_filter = 0; 3516 ptp->tx_tstamp_en = 0; 3517 ptp->rxctl = 0; 3518 3519 bnxt_hwrm_ptp_cfg(bp); 3520 3521 if (!BNXT_CHIP_P5(bp)) 3522 bnxt_unmap_ptp_regs(bp); 3523 else 3524 bnxt_ptp_stop(bp); 3525 3526 return 0; 3527 } 3528 3529 static int 3530 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3531 struct timespec *timestamp, 3532 uint32_t flags __rte_unused) 3533 { 3534 struct bnxt *bp = dev->data->dev_private; 3535 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3536 uint64_t rx_tstamp_cycles = 0; 3537 uint64_t ns; 3538 3539 if (!ptp) 3540 return -ENOTSUP; 3541 3542 if (BNXT_CHIP_P5(bp)) 3543 rx_tstamp_cycles = ptp->rx_timestamp; 3544 else 3545 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3546 3547 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3548 *timestamp = rte_ns_to_timespec(ns); 3549 return 0; 3550 } 3551 3552 static int 3553 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3554 struct timespec *timestamp) 3555 { 3556 struct bnxt *bp = dev->data->dev_private; 3557 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3558 uint64_t tx_tstamp_cycles = 0; 3559 uint64_t ns; 3560 int rc = 0; 3561 3562 if (!ptp) 3563 return -ENOTSUP; 3564 3565 if (BNXT_CHIP_P5(bp)) 3566 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3567 &tx_tstamp_cycles); 3568 else 3569 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3570 3571 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3572 *timestamp = rte_ns_to_timespec(ns); 3573 3574 return rc; 3575 } 3576 3577 static int 3578 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3579 { 3580 struct bnxt *bp = dev->data->dev_private; 3581 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3582 3583 if (!ptp) 3584 return -ENOTSUP; 3585 3586 ptp->tc.nsec += delta; 3587 ptp->tx_tstamp_tc.nsec += delta; 3588 ptp->rx_tstamp_tc.nsec += delta; 3589 3590 return 0; 3591 } 3592 3593 static int 3594 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3595 { 3596 struct bnxt *bp = dev->data->dev_private; 3597 int rc; 3598 uint32_t dir_entries; 3599 uint32_t entry_length; 3600 3601 rc = is_bnxt_in_error(bp); 3602 if (rc) 3603 return rc; 3604 3605 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 3606 bp->pdev->addr.domain, bp->pdev->addr.bus, 3607 bp->pdev->addr.devid, bp->pdev->addr.function); 3608 3609 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3610 if (rc != 0) 3611 return rc; 3612 3613 return dir_entries * entry_length; 3614 } 3615 3616 static int 3617 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3618 struct rte_dev_eeprom_info *in_eeprom) 3619 { 3620 struct bnxt *bp = dev->data->dev_private; 3621 uint32_t index; 3622 uint32_t offset; 3623 int rc; 3624 3625 rc = is_bnxt_in_error(bp); 3626 if (rc) 3627 return rc; 3628 3629 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3630 bp->pdev->addr.domain, bp->pdev->addr.bus, 3631 bp->pdev->addr.devid, bp->pdev->addr.function, 3632 in_eeprom->offset, in_eeprom->length); 3633 3634 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3635 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3636 in_eeprom->data); 3637 3638 index = in_eeprom->offset >> 24; 3639 offset = in_eeprom->offset & 0xffffff; 3640 3641 if (index != 0) 3642 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3643 in_eeprom->length, in_eeprom->data); 3644 3645 return 0; 3646 } 3647 3648 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3649 { 3650 switch (dir_type) { 3651 case BNX_DIR_TYPE_CHIMP_PATCH: 3652 case BNX_DIR_TYPE_BOOTCODE: 3653 case BNX_DIR_TYPE_BOOTCODE_2: 3654 case BNX_DIR_TYPE_APE_FW: 3655 case BNX_DIR_TYPE_APE_PATCH: 3656 case BNX_DIR_TYPE_KONG_FW: 3657 case BNX_DIR_TYPE_KONG_PATCH: 3658 case BNX_DIR_TYPE_BONO_FW: 3659 case BNX_DIR_TYPE_BONO_PATCH: 3660 /* FALLTHROUGH */ 3661 return true; 3662 } 3663 3664 return false; 3665 } 3666 3667 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3668 { 3669 switch (dir_type) { 3670 case BNX_DIR_TYPE_AVS: 3671 case BNX_DIR_TYPE_EXP_ROM_MBA: 3672 case BNX_DIR_TYPE_PCIE: 3673 case BNX_DIR_TYPE_TSCF_UCODE: 3674 case BNX_DIR_TYPE_EXT_PHY: 3675 case BNX_DIR_TYPE_CCM: 3676 case BNX_DIR_TYPE_ISCSI_BOOT: 3677 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3678 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3679 /* FALLTHROUGH */ 3680 return true; 3681 } 3682 3683 return false; 3684 } 3685 3686 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3687 { 3688 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3689 bnxt_dir_type_is_other_exec_format(dir_type); 3690 } 3691 3692 static int 3693 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3694 struct rte_dev_eeprom_info *in_eeprom) 3695 { 3696 struct bnxt *bp = dev->data->dev_private; 3697 uint8_t index, dir_op; 3698 uint16_t type, ext, ordinal, attr; 3699 int rc; 3700 3701 rc = is_bnxt_in_error(bp); 3702 if (rc) 3703 return rc; 3704 3705 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3706 bp->pdev->addr.domain, bp->pdev->addr.bus, 3707 bp->pdev->addr.devid, bp->pdev->addr.function, 3708 in_eeprom->offset, in_eeprom->length); 3709 3710 if (!BNXT_PF(bp)) { 3711 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3712 return -EINVAL; 3713 } 3714 3715 type = in_eeprom->magic >> 16; 3716 3717 if (type == 0xffff) { /* special value for directory operations */ 3718 index = in_eeprom->magic & 0xff; 3719 dir_op = in_eeprom->magic >> 8; 3720 if (index == 0) 3721 return -EINVAL; 3722 switch (dir_op) { 3723 case 0x0e: /* erase */ 3724 if (in_eeprom->offset != ~in_eeprom->magic) 3725 return -EINVAL; 3726 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3727 default: 3728 return -EINVAL; 3729 } 3730 } 3731 3732 /* Create or re-write an NVM item: */ 3733 if (bnxt_dir_type_is_executable(type) == true) 3734 return -EOPNOTSUPP; 3735 ext = in_eeprom->magic & 0xffff; 3736 ordinal = in_eeprom->offset >> 16; 3737 attr = in_eeprom->offset & 0xffff; 3738 3739 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3740 in_eeprom->data, in_eeprom->length); 3741 } 3742 3743 /* 3744 * Initialization 3745 */ 3746 3747 static const struct eth_dev_ops bnxt_dev_ops = { 3748 .dev_infos_get = bnxt_dev_info_get_op, 3749 .dev_close = bnxt_dev_close_op, 3750 .dev_configure = bnxt_dev_configure_op, 3751 .dev_start = bnxt_dev_start_op, 3752 .dev_stop = bnxt_dev_stop_op, 3753 .dev_set_link_up = bnxt_dev_set_link_up_op, 3754 .dev_set_link_down = bnxt_dev_set_link_down_op, 3755 .stats_get = bnxt_stats_get_op, 3756 .stats_reset = bnxt_stats_reset_op, 3757 .rx_queue_setup = bnxt_rx_queue_setup_op, 3758 .rx_queue_release = bnxt_rx_queue_release_op, 3759 .tx_queue_setup = bnxt_tx_queue_setup_op, 3760 .tx_queue_release = bnxt_tx_queue_release_op, 3761 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3762 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3763 .reta_update = bnxt_reta_update_op, 3764 .reta_query = bnxt_reta_query_op, 3765 .rss_hash_update = bnxt_rss_hash_update_op, 3766 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3767 .link_update = bnxt_link_update_op, 3768 .promiscuous_enable = bnxt_promiscuous_enable_op, 3769 .promiscuous_disable = bnxt_promiscuous_disable_op, 3770 .allmulticast_enable = bnxt_allmulticast_enable_op, 3771 .allmulticast_disable = bnxt_allmulticast_disable_op, 3772 .mac_addr_add = bnxt_mac_addr_add_op, 3773 .mac_addr_remove = bnxt_mac_addr_remove_op, 3774 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3775 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3776 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3777 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3778 .vlan_filter_set = bnxt_vlan_filter_set_op, 3779 .vlan_offload_set = bnxt_vlan_offload_set_op, 3780 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 3781 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3782 .mtu_set = bnxt_mtu_set_op, 3783 .mac_addr_set = bnxt_set_default_mac_addr_op, 3784 .xstats_get = bnxt_dev_xstats_get_op, 3785 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3786 .xstats_reset = bnxt_dev_xstats_reset_op, 3787 .fw_version_get = bnxt_fw_version_get, 3788 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3789 .rxq_info_get = bnxt_rxq_info_get_op, 3790 .txq_info_get = bnxt_txq_info_get_op, 3791 .rx_burst_mode_get = bnxt_rx_burst_mode_get, 3792 .tx_burst_mode_get = bnxt_tx_burst_mode_get, 3793 .dev_led_on = bnxt_dev_led_on_op, 3794 .dev_led_off = bnxt_dev_led_off_op, 3795 .rx_queue_start = bnxt_rx_queue_start, 3796 .rx_queue_stop = bnxt_rx_queue_stop, 3797 .tx_queue_start = bnxt_tx_queue_start, 3798 .tx_queue_stop = bnxt_tx_queue_stop, 3799 .flow_ops_get = bnxt_flow_ops_get_op, 3800 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3801 .get_eeprom_length = bnxt_get_eeprom_length_op, 3802 .get_eeprom = bnxt_get_eeprom_op, 3803 .set_eeprom = bnxt_set_eeprom_op, 3804 .timesync_enable = bnxt_timesync_enable, 3805 .timesync_disable = bnxt_timesync_disable, 3806 .timesync_read_time = bnxt_timesync_read_time, 3807 .timesync_write_time = bnxt_timesync_write_time, 3808 .timesync_adjust_time = bnxt_timesync_adjust_time, 3809 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3810 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3811 }; 3812 3813 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 3814 { 3815 uint32_t offset; 3816 3817 /* Only pre-map the reset GRC registers using window 3 */ 3818 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 3819 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 3820 3821 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 3822 3823 return offset; 3824 } 3825 3826 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 3827 { 3828 struct bnxt_error_recovery_info *info = bp->recovery_info; 3829 uint32_t reg_base = 0xffffffff; 3830 int i; 3831 3832 /* Only pre-map the monitoring GRC registers using window 2 */ 3833 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 3834 uint32_t reg = info->status_regs[i]; 3835 3836 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 3837 continue; 3838 3839 if (reg_base == 0xffffffff) 3840 reg_base = reg & 0xfffff000; 3841 if ((reg & 0xfffff000) != reg_base) 3842 return -ERANGE; 3843 3844 /* Use mask 0xffc as the Lower 2 bits indicates 3845 * address space location 3846 */ 3847 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 3848 (reg & 0xffc); 3849 } 3850 3851 if (reg_base == 0xffffffff) 3852 return 0; 3853 3854 rte_write32(reg_base, (uint8_t *)bp->bar0 + 3855 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 3856 3857 return 0; 3858 } 3859 3860 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 3861 { 3862 struct bnxt_error_recovery_info *info = bp->recovery_info; 3863 uint32_t delay = info->delay_after_reset[index]; 3864 uint32_t val = info->reset_reg_val[index]; 3865 uint32_t reg = info->reset_reg[index]; 3866 uint32_t type, offset; 3867 int ret; 3868 3869 type = BNXT_FW_STATUS_REG_TYPE(reg); 3870 offset = BNXT_FW_STATUS_REG_OFF(reg); 3871 3872 switch (type) { 3873 case BNXT_FW_STATUS_REG_TYPE_CFG: 3874 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 3875 if (ret < 0) { 3876 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x", 3877 val, offset); 3878 return; 3879 } 3880 break; 3881 case BNXT_FW_STATUS_REG_TYPE_GRC: 3882 offset = bnxt_map_reset_regs(bp, offset); 3883 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3884 break; 3885 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3886 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3887 break; 3888 } 3889 /* wait on a specific interval of time until core reset is complete */ 3890 if (delay) 3891 rte_delay_ms(delay); 3892 } 3893 3894 static void bnxt_dev_cleanup(struct bnxt *bp) 3895 { 3896 bp->eth_dev->data->dev_link.link_status = 0; 3897 bp->link_info->link_up = 0; 3898 if (bp->eth_dev->data->dev_started) 3899 bnxt_dev_stop(bp->eth_dev); 3900 3901 bnxt_uninit_resources(bp, true); 3902 } 3903 3904 static int 3905 bnxt_check_fw_reset_done(struct bnxt *bp) 3906 { 3907 int timeout = bp->fw_reset_max_msecs; 3908 uint16_t val = 0; 3909 int rc; 3910 3911 do { 3912 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 3913 if (rc < 0) { 3914 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 3915 return rc; 3916 } 3917 if (val != 0xffff) 3918 break; 3919 rte_delay_ms(1); 3920 } while (timeout--); 3921 3922 if (val == 0xffff) { 3923 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); 3924 return -1; 3925 } 3926 3927 return 0; 3928 } 3929 3930 static int bnxt_restore_vlan_filters(struct bnxt *bp) 3931 { 3932 struct rte_eth_dev *dev = bp->eth_dev; 3933 struct rte_vlan_filter_conf *vfc; 3934 int vidx, vbit, rc; 3935 uint16_t vlan_id; 3936 3937 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 3938 vfc = &dev->data->vlan_filter_conf; 3939 vidx = vlan_id / 64; 3940 vbit = vlan_id % 64; 3941 3942 /* Each bit corresponds to a VLAN id */ 3943 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 3944 rc = bnxt_add_vlan_filter(bp, vlan_id); 3945 if (rc) 3946 return rc; 3947 } 3948 } 3949 3950 return 0; 3951 } 3952 3953 static int bnxt_restore_mac_filters(struct bnxt *bp) 3954 { 3955 struct rte_eth_dev *dev = bp->eth_dev; 3956 struct rte_eth_dev_info dev_info; 3957 struct rte_ether_addr *addr; 3958 uint64_t pool_mask; 3959 uint32_t pool = 0; 3960 uint16_t i; 3961 int rc; 3962 3963 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 3964 return 0; 3965 3966 rc = bnxt_dev_info_get_op(dev, &dev_info); 3967 if (rc) 3968 return rc; 3969 3970 /* replay MAC address configuration */ 3971 for (i = 1; i < dev_info.max_mac_addrs; i++) { 3972 addr = &dev->data->mac_addrs[i]; 3973 3974 /* skip zero address */ 3975 if (rte_is_zero_ether_addr(addr)) 3976 continue; 3977 3978 pool = 0; 3979 pool_mask = dev->data->mac_pool_sel[i]; 3980 3981 do { 3982 if (pool_mask & 1ULL) { 3983 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 3984 if (rc) 3985 return rc; 3986 } 3987 pool_mask >>= 1; 3988 pool++; 3989 } while (pool_mask); 3990 } 3991 3992 return 0; 3993 } 3994 3995 static int bnxt_restore_filters(struct bnxt *bp) 3996 { 3997 struct rte_eth_dev *dev = bp->eth_dev; 3998 int ret = 0; 3999 4000 if (dev->data->all_multicast) { 4001 ret = bnxt_allmulticast_enable_op(dev); 4002 if (ret) 4003 return ret; 4004 } 4005 if (dev->data->promiscuous) { 4006 ret = bnxt_promiscuous_enable_op(dev); 4007 if (ret) 4008 return ret; 4009 } 4010 4011 ret = bnxt_restore_mac_filters(bp); 4012 if (ret) 4013 return ret; 4014 4015 ret = bnxt_restore_vlan_filters(bp); 4016 /* TODO restore other filters as well */ 4017 return ret; 4018 } 4019 4020 static int bnxt_check_fw_ready(struct bnxt *bp) 4021 { 4022 int timeout = bp->fw_reset_max_msecs; 4023 int rc = 0; 4024 4025 do { 4026 rc = bnxt_hwrm_poll_ver_get(bp); 4027 if (rc == 0) 4028 break; 4029 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 4030 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 4031 } while (rc && timeout > 0); 4032 4033 if (rc) 4034 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 4035 4036 return rc; 4037 } 4038 4039 static void bnxt_dev_recover(void *arg) 4040 { 4041 struct bnxt *bp = arg; 4042 int rc = 0; 4043 4044 pthread_mutex_lock(&bp->err_recovery_lock); 4045 4046 if (!bp->fw_reset_min_msecs) { 4047 rc = bnxt_check_fw_reset_done(bp); 4048 if (rc) 4049 goto err; 4050 } 4051 4052 /* Clear Error flag so that device re-init should happen */ 4053 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 4054 4055 rc = bnxt_check_fw_ready(bp); 4056 if (rc) 4057 goto err; 4058 4059 rc = bnxt_init_resources(bp, true); 4060 if (rc) { 4061 PMD_DRV_LOG(ERR, 4062 "Failed to initialize resources after reset\n"); 4063 goto err; 4064 } 4065 /* clear reset flag as the device is initialized now */ 4066 bp->flags &= ~BNXT_FLAG_FW_RESET; 4067 4068 rc = bnxt_dev_start_op(bp->eth_dev); 4069 if (rc) { 4070 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 4071 goto err_start; 4072 } 4073 4074 rc = bnxt_restore_filters(bp); 4075 if (rc) 4076 goto err_start; 4077 4078 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 4079 pthread_mutex_unlock(&bp->err_recovery_lock); 4080 4081 return; 4082 err_start: 4083 bnxt_dev_stop(bp->eth_dev); 4084 err: 4085 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4086 bnxt_uninit_resources(bp, false); 4087 pthread_mutex_unlock(&bp->err_recovery_lock); 4088 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 4089 } 4090 4091 void bnxt_dev_reset_and_resume(void *arg) 4092 { 4093 struct bnxt *bp = arg; 4094 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; 4095 uint16_t val = 0; 4096 int rc; 4097 4098 bnxt_dev_cleanup(bp); 4099 4100 bnxt_wait_for_device_shutdown(bp); 4101 4102 /* During some fatal firmware error conditions, the PCI config space 4103 * register 0x2e which normally contains the subsystem ID will become 4104 * 0xffff. This register will revert back to the normal value after 4105 * the chip has completed core reset. If we detect this condition, 4106 * we can poll this config register immediately for the value to revert. 4107 */ 4108 if (bp->flags & BNXT_FLAG_FATAL_ERROR) { 4109 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 4110 if (rc < 0) { 4111 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 4112 return; 4113 } 4114 if (val == 0xffff) { 4115 bp->fw_reset_min_msecs = 0; 4116 us = 1; 4117 } 4118 } 4119 4120 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); 4121 if (rc) 4122 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 4123 } 4124 4125 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 4126 { 4127 struct bnxt_error_recovery_info *info = bp->recovery_info; 4128 uint32_t reg = info->status_regs[index]; 4129 uint32_t type, offset, val = 0; 4130 4131 type = BNXT_FW_STATUS_REG_TYPE(reg); 4132 offset = BNXT_FW_STATUS_REG_OFF(reg); 4133 4134 switch (type) { 4135 case BNXT_FW_STATUS_REG_TYPE_CFG: 4136 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 4137 break; 4138 case BNXT_FW_STATUS_REG_TYPE_GRC: 4139 offset = info->mapped_status_regs[index]; 4140 /* FALLTHROUGH */ 4141 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4142 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4143 offset)); 4144 break; 4145 } 4146 4147 return val; 4148 } 4149 4150 static int bnxt_fw_reset_all(struct bnxt *bp) 4151 { 4152 struct bnxt_error_recovery_info *info = bp->recovery_info; 4153 uint32_t i; 4154 int rc = 0; 4155 4156 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4157 /* Reset through master function driver */ 4158 for (i = 0; i < info->reg_array_cnt; i++) 4159 bnxt_write_fw_reset_reg(bp, i); 4160 /* Wait for time specified by FW after triggering reset */ 4161 rte_delay_ms(info->master_func_wait_period_after_reset); 4162 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 4163 /* Reset with the help of Kong processor */ 4164 rc = bnxt_hwrm_fw_reset(bp); 4165 if (rc) 4166 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 4167 } 4168 4169 return rc; 4170 } 4171 4172 static void bnxt_fw_reset_cb(void *arg) 4173 { 4174 struct bnxt *bp = arg; 4175 struct bnxt_error_recovery_info *info = bp->recovery_info; 4176 int rc = 0; 4177 4178 /* Only Master function can do FW reset */ 4179 if (bnxt_is_master_func(bp) && 4180 bnxt_is_recovery_enabled(bp)) { 4181 rc = bnxt_fw_reset_all(bp); 4182 if (rc) { 4183 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 4184 return; 4185 } 4186 } 4187 4188 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 4189 * EXCEPTION_FATAL_ASYNC event to all the functions 4190 * (including MASTER FUNC). After receiving this Async, all the active 4191 * drivers should treat this case as FW initiated recovery 4192 */ 4193 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4194 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 4195 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 4196 4197 /* To recover from error */ 4198 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 4199 (void *)bp); 4200 } 4201 } 4202 4203 /* Driver should poll FW heartbeat, reset_counter with the frequency 4204 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 4205 * When the driver detects heartbeat stop or change in reset_counter, 4206 * it has to trigger a reset to recover from the error condition. 4207 * A “master PF” is the function who will have the privilege to 4208 * initiate the chimp reset. The master PF will be elected by the 4209 * firmware and will be notified through async message. 4210 */ 4211 static void bnxt_check_fw_health(void *arg) 4212 { 4213 struct bnxt *bp = arg; 4214 struct bnxt_error_recovery_info *info = bp->recovery_info; 4215 uint32_t val = 0, wait_msec; 4216 4217 if (!info || !bnxt_is_recovery_enabled(bp) || 4218 is_bnxt_in_error(bp)) 4219 return; 4220 4221 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4222 if (val == info->last_heart_beat) 4223 goto reset; 4224 4225 info->last_heart_beat = val; 4226 4227 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4228 if (val != info->last_reset_counter) 4229 goto reset; 4230 4231 info->last_reset_counter = val; 4232 4233 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4234 bnxt_check_fw_health, (void *)bp); 4235 4236 return; 4237 reset: 4238 /* Stop DMA to/from device */ 4239 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4240 bp->flags |= BNXT_FLAG_FW_RESET; 4241 4242 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4243 4244 if (bnxt_is_master_func(bp)) 4245 wait_msec = info->master_func_wait_period; 4246 else 4247 wait_msec = info->normal_func_wait_period; 4248 4249 rte_eal_alarm_set(US_PER_MS * wait_msec, 4250 bnxt_fw_reset_cb, (void *)bp); 4251 } 4252 4253 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4254 { 4255 uint32_t polling_freq; 4256 4257 pthread_mutex_lock(&bp->health_check_lock); 4258 4259 if (!bnxt_is_recovery_enabled(bp)) 4260 goto done; 4261 4262 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4263 goto done; 4264 4265 polling_freq = bp->recovery_info->driver_polling_freq; 4266 4267 rte_eal_alarm_set(US_PER_MS * polling_freq, 4268 bnxt_check_fw_health, (void *)bp); 4269 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4270 4271 done: 4272 pthread_mutex_unlock(&bp->health_check_lock); 4273 } 4274 4275 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4276 { 4277 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4278 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4279 } 4280 4281 static bool bnxt_vf_pciid(uint16_t device_id) 4282 { 4283 switch (device_id) { 4284 case BROADCOM_DEV_ID_57304_VF: 4285 case BROADCOM_DEV_ID_57406_VF: 4286 case BROADCOM_DEV_ID_5731X_VF: 4287 case BROADCOM_DEV_ID_5741X_VF: 4288 case BROADCOM_DEV_ID_57414_VF: 4289 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4290 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4291 case BROADCOM_DEV_ID_58802_VF: 4292 case BROADCOM_DEV_ID_57500_VF1: 4293 case BROADCOM_DEV_ID_57500_VF2: 4294 case BROADCOM_DEV_ID_58818_VF: 4295 /* FALLTHROUGH */ 4296 return true; 4297 default: 4298 return false; 4299 } 4300 } 4301 4302 /* Phase 5 device */ 4303 static bool bnxt_p5_device(uint16_t device_id) 4304 { 4305 switch (device_id) { 4306 case BROADCOM_DEV_ID_57508: 4307 case BROADCOM_DEV_ID_57504: 4308 case BROADCOM_DEV_ID_57502: 4309 case BROADCOM_DEV_ID_57508_MF1: 4310 case BROADCOM_DEV_ID_57504_MF1: 4311 case BROADCOM_DEV_ID_57502_MF1: 4312 case BROADCOM_DEV_ID_57508_MF2: 4313 case BROADCOM_DEV_ID_57504_MF2: 4314 case BROADCOM_DEV_ID_57502_MF2: 4315 case BROADCOM_DEV_ID_57500_VF1: 4316 case BROADCOM_DEV_ID_57500_VF2: 4317 case BROADCOM_DEV_ID_58812: 4318 case BROADCOM_DEV_ID_58814: 4319 case BROADCOM_DEV_ID_58818: 4320 case BROADCOM_DEV_ID_58818_VF: 4321 /* FALLTHROUGH */ 4322 return true; 4323 default: 4324 return false; 4325 } 4326 } 4327 4328 bool bnxt_stratus_device(struct bnxt *bp) 4329 { 4330 uint16_t device_id = bp->pdev->id.device_id; 4331 4332 switch (device_id) { 4333 case BROADCOM_DEV_ID_STRATUS_NIC: 4334 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4335 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4336 /* FALLTHROUGH */ 4337 return true; 4338 default: 4339 return false; 4340 } 4341 } 4342 4343 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev) 4344 { 4345 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4346 struct bnxt *bp = eth_dev->data->dev_private; 4347 4348 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4349 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4350 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4351 if (!bp->bar0 || !bp->doorbell_base) { 4352 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4353 return -ENODEV; 4354 } 4355 4356 bp->eth_dev = eth_dev; 4357 bp->pdev = pci_dev; 4358 4359 return 0; 4360 } 4361 4362 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4363 struct bnxt_ctx_pg_info *ctx_pg, 4364 uint32_t mem_size, 4365 const char *suffix, 4366 uint16_t idx) 4367 { 4368 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4369 const struct rte_memzone *mz = NULL; 4370 char mz_name[RTE_MEMZONE_NAMESIZE]; 4371 rte_iova_t mz_phys_addr; 4372 uint64_t valid_bits = 0; 4373 uint32_t sz; 4374 int i; 4375 4376 if (!mem_size) 4377 return 0; 4378 4379 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4380 BNXT_PAGE_SIZE; 4381 rmem->page_size = BNXT_PAGE_SIZE; 4382 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4383 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4384 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4385 4386 valid_bits = PTU_PTE_VALID; 4387 4388 if (rmem->nr_pages > 1) { 4389 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4390 "bnxt_ctx_pg_tbl%s_%x_%d", 4391 suffix, idx, bp->eth_dev->data->port_id); 4392 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4393 mz = rte_memzone_lookup(mz_name); 4394 if (!mz) { 4395 mz = rte_memzone_reserve_aligned(mz_name, 4396 rmem->nr_pages * 8, 4397 SOCKET_ID_ANY, 4398 RTE_MEMZONE_2MB | 4399 RTE_MEMZONE_SIZE_HINT_ONLY | 4400 RTE_MEMZONE_IOVA_CONTIG, 4401 BNXT_PAGE_SIZE); 4402 if (mz == NULL) 4403 return -ENOMEM; 4404 } 4405 4406 memset(mz->addr, 0, mz->len); 4407 mz_phys_addr = mz->iova; 4408 4409 rmem->pg_tbl = mz->addr; 4410 rmem->pg_tbl_map = mz_phys_addr; 4411 rmem->pg_tbl_mz = mz; 4412 } 4413 4414 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4415 suffix, idx, bp->eth_dev->data->port_id); 4416 mz = rte_memzone_lookup(mz_name); 4417 if (!mz) { 4418 mz = rte_memzone_reserve_aligned(mz_name, 4419 mem_size, 4420 SOCKET_ID_ANY, 4421 RTE_MEMZONE_1GB | 4422 RTE_MEMZONE_SIZE_HINT_ONLY | 4423 RTE_MEMZONE_IOVA_CONTIG, 4424 BNXT_PAGE_SIZE); 4425 if (mz == NULL) 4426 return -ENOMEM; 4427 } 4428 4429 memset(mz->addr, 0, mz->len); 4430 mz_phys_addr = mz->iova; 4431 4432 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4433 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4434 rmem->dma_arr[i] = mz_phys_addr + sz; 4435 4436 if (rmem->nr_pages > 1) { 4437 if (i == rmem->nr_pages - 2 && 4438 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4439 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4440 else if (i == rmem->nr_pages - 1 && 4441 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4442 valid_bits |= PTU_PTE_LAST; 4443 4444 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4445 valid_bits); 4446 } 4447 } 4448 4449 rmem->mz = mz; 4450 if (rmem->vmem_size) 4451 rmem->vmem = (void **)mz->addr; 4452 rmem->dma_arr[0] = mz_phys_addr; 4453 return 0; 4454 } 4455 4456 static void bnxt_free_ctx_mem(struct bnxt *bp) 4457 { 4458 int i; 4459 4460 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4461 return; 4462 4463 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4464 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4465 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4466 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4467 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4468 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4469 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4470 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4471 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4472 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4473 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4474 4475 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) { 4476 if (bp->ctx->tqm_mem[i]) 4477 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4478 } 4479 4480 rte_free(bp->ctx); 4481 bp->ctx = NULL; 4482 } 4483 4484 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4485 4486 #define min_t(type, x, y) ({ \ 4487 type __min1 = (x); \ 4488 type __min2 = (y); \ 4489 __min1 < __min2 ? __min1 : __min2; }) 4490 4491 #define max_t(type, x, y) ({ \ 4492 type __max1 = (x); \ 4493 type __max2 = (y); \ 4494 __max1 > __max2 ? __max1 : __max2; }) 4495 4496 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4497 4498 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4499 { 4500 struct bnxt_ctx_pg_info *ctx_pg; 4501 struct bnxt_ctx_mem_info *ctx; 4502 uint32_t mem_size, ena, entries; 4503 uint32_t entries_sp, min; 4504 int i, rc; 4505 4506 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4507 if (rc) { 4508 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4509 return rc; 4510 } 4511 ctx = bp->ctx; 4512 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4513 return 0; 4514 4515 ctx_pg = &ctx->qp_mem; 4516 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4517 if (ctx->qp_entry_size) { 4518 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4519 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4520 if (rc) 4521 return rc; 4522 } 4523 4524 ctx_pg = &ctx->srq_mem; 4525 ctx_pg->entries = ctx->srq_max_l2_entries; 4526 if (ctx->srq_entry_size) { 4527 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4528 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4529 if (rc) 4530 return rc; 4531 } 4532 4533 ctx_pg = &ctx->cq_mem; 4534 ctx_pg->entries = ctx->cq_max_l2_entries; 4535 if (ctx->cq_entry_size) { 4536 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4537 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4538 if (rc) 4539 return rc; 4540 } 4541 4542 ctx_pg = &ctx->vnic_mem; 4543 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4544 ctx->vnic_max_ring_table_entries; 4545 if (ctx->vnic_entry_size) { 4546 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4547 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4548 if (rc) 4549 return rc; 4550 } 4551 4552 ctx_pg = &ctx->stat_mem; 4553 ctx_pg->entries = ctx->stat_max_entries; 4554 if (ctx->stat_entry_size) { 4555 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4556 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4557 if (rc) 4558 return rc; 4559 } 4560 4561 min = ctx->tqm_min_entries_per_ring; 4562 4563 entries_sp = ctx->qp_max_l2_entries + 4564 ctx->vnic_max_vnic_entries + 4565 2 * ctx->qp_min_qp1_entries + min; 4566 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple); 4567 4568 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries; 4569 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4570 entries = clamp_t(uint32_t, entries, min, 4571 ctx->tqm_max_entries_per_ring); 4572 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 4573 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7. 4574 * i > 8 is other ext rings. 4575 */ 4576 ctx_pg = ctx->tqm_mem[i]; 4577 ctx_pg->entries = i ? entries : entries_sp; 4578 if (ctx->tqm_entry_size) { 4579 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4580 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, 4581 "tqm_mem", i); 4582 if (rc) 4583 return rc; 4584 } 4585 if (i < BNXT_MAX_TQM_LEGACY_RINGS) 4586 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4587 else 4588 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8; 4589 } 4590 4591 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4592 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4593 if (rc) 4594 PMD_DRV_LOG(ERR, 4595 "Failed to configure context mem: rc = %d\n", rc); 4596 else 4597 ctx->flags |= BNXT_CTX_FLAG_INITED; 4598 4599 return rc; 4600 } 4601 4602 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4603 { 4604 struct rte_pci_device *pci_dev = bp->pdev; 4605 char mz_name[RTE_MEMZONE_NAMESIZE]; 4606 const struct rte_memzone *mz = NULL; 4607 uint32_t total_alloc_len; 4608 rte_iova_t mz_phys_addr; 4609 4610 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4611 return 0; 4612 4613 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4614 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4615 pci_dev->addr.bus, pci_dev->addr.devid, 4616 pci_dev->addr.function, "rx_port_stats"); 4617 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4618 mz = rte_memzone_lookup(mz_name); 4619 total_alloc_len = 4620 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4621 sizeof(struct rx_port_stats_ext) + 512); 4622 if (!mz) { 4623 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4624 SOCKET_ID_ANY, 4625 RTE_MEMZONE_2MB | 4626 RTE_MEMZONE_SIZE_HINT_ONLY | 4627 RTE_MEMZONE_IOVA_CONTIG); 4628 if (mz == NULL) 4629 return -ENOMEM; 4630 } 4631 memset(mz->addr, 0, mz->len); 4632 mz_phys_addr = mz->iova; 4633 4634 bp->rx_mem_zone = (const void *)mz; 4635 bp->hw_rx_port_stats = mz->addr; 4636 bp->hw_rx_port_stats_map = mz_phys_addr; 4637 4638 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4639 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4640 pci_dev->addr.bus, pci_dev->addr.devid, 4641 pci_dev->addr.function, "tx_port_stats"); 4642 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4643 mz = rte_memzone_lookup(mz_name); 4644 total_alloc_len = 4645 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4646 sizeof(struct tx_port_stats_ext) + 512); 4647 if (!mz) { 4648 mz = rte_memzone_reserve(mz_name, 4649 total_alloc_len, 4650 SOCKET_ID_ANY, 4651 RTE_MEMZONE_2MB | 4652 RTE_MEMZONE_SIZE_HINT_ONLY | 4653 RTE_MEMZONE_IOVA_CONTIG); 4654 if (mz == NULL) 4655 return -ENOMEM; 4656 } 4657 memset(mz->addr, 0, mz->len); 4658 mz_phys_addr = mz->iova; 4659 4660 bp->tx_mem_zone = (const void *)mz; 4661 bp->hw_tx_port_stats = mz->addr; 4662 bp->hw_tx_port_stats_map = mz_phys_addr; 4663 bp->flags |= BNXT_FLAG_PORT_STATS; 4664 4665 /* Display extended statistics if FW supports it */ 4666 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4667 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4668 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4669 return 0; 4670 4671 bp->hw_rx_port_stats_ext = (void *) 4672 ((uint8_t *)bp->hw_rx_port_stats + 4673 sizeof(struct rx_port_stats)); 4674 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4675 sizeof(struct rx_port_stats); 4676 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4677 4678 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4679 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4680 bp->hw_tx_port_stats_ext = (void *) 4681 ((uint8_t *)bp->hw_tx_port_stats + 4682 sizeof(struct tx_port_stats)); 4683 bp->hw_tx_port_stats_ext_map = 4684 bp->hw_tx_port_stats_map + 4685 sizeof(struct tx_port_stats); 4686 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4687 } 4688 4689 return 0; 4690 } 4691 4692 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4693 { 4694 struct bnxt *bp = eth_dev->data->dev_private; 4695 int rc = 0; 4696 4697 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4698 RTE_ETHER_ADDR_LEN * 4699 bp->max_l2_ctx, 4700 0); 4701 if (eth_dev->data->mac_addrs == NULL) { 4702 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4703 return -ENOMEM; 4704 } 4705 4706 if (!BNXT_HAS_DFLT_MAC_SET(bp)) { 4707 if (BNXT_PF(bp)) 4708 return -EINVAL; 4709 4710 /* Generate a random MAC address, if none was assigned by PF */ 4711 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 4712 bnxt_eth_hw_addr_random(bp->mac_addr); 4713 PMD_DRV_LOG(INFO, 4714 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 4715 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 4716 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 4717 4718 rc = bnxt_hwrm_set_mac(bp); 4719 if (rc) 4720 return rc; 4721 } 4722 4723 /* Copy the permanent MAC from the FUNC_QCAPS response */ 4724 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 4725 4726 return rc; 4727 } 4728 4729 static int bnxt_restore_dflt_mac(struct bnxt *bp) 4730 { 4731 int rc = 0; 4732 4733 /* MAC is already configured in FW */ 4734 if (BNXT_HAS_DFLT_MAC_SET(bp)) 4735 return 0; 4736 4737 /* Restore the old MAC configured */ 4738 rc = bnxt_hwrm_set_mac(bp); 4739 if (rc) 4740 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 4741 4742 return rc; 4743 } 4744 4745 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 4746 { 4747 if (!BNXT_PF(bp)) 4748 return; 4749 4750 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd)); 4751 4752 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN)) 4753 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG); 4754 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG); 4755 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG); 4756 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC); 4757 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); 4758 } 4759 4760 uint16_t 4761 bnxt_get_svif(uint16_t port_id, bool func_svif, 4762 enum bnxt_ulp_intf_type type) 4763 { 4764 struct rte_eth_dev *eth_dev; 4765 struct bnxt *bp; 4766 4767 eth_dev = &rte_eth_devices[port_id]; 4768 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4769 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4770 if (!vfr) 4771 return 0; 4772 4773 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4774 return vfr->svif; 4775 4776 eth_dev = vfr->parent_dev; 4777 } 4778 4779 bp = eth_dev->data->dev_private; 4780 4781 return func_svif ? bp->func_svif : bp->port_svif; 4782 } 4783 4784 uint16_t 4785 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 4786 { 4787 struct rte_eth_dev *eth_dev; 4788 struct bnxt_vnic_info *vnic; 4789 struct bnxt *bp; 4790 4791 eth_dev = &rte_eth_devices[port]; 4792 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4793 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4794 if (!vfr) 4795 return 0; 4796 4797 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4798 return vfr->dflt_vnic_id; 4799 4800 eth_dev = vfr->parent_dev; 4801 } 4802 4803 bp = eth_dev->data->dev_private; 4804 4805 vnic = BNXT_GET_DEFAULT_VNIC(bp); 4806 4807 return vnic->fw_vnic_id; 4808 } 4809 4810 uint16_t 4811 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) 4812 { 4813 struct rte_eth_dev *eth_dev; 4814 struct bnxt *bp; 4815 4816 eth_dev = &rte_eth_devices[port]; 4817 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4818 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4819 if (!vfr) 4820 return 0; 4821 4822 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4823 return vfr->fw_fid; 4824 4825 eth_dev = vfr->parent_dev; 4826 } 4827 4828 bp = eth_dev->data->dev_private; 4829 4830 return bp->fw_fid; 4831 } 4832 4833 enum bnxt_ulp_intf_type 4834 bnxt_get_interface_type(uint16_t port) 4835 { 4836 struct rte_eth_dev *eth_dev; 4837 struct bnxt *bp; 4838 4839 eth_dev = &rte_eth_devices[port]; 4840 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) 4841 return BNXT_ULP_INTF_TYPE_VF_REP; 4842 4843 bp = eth_dev->data->dev_private; 4844 if (BNXT_PF(bp)) 4845 return BNXT_ULP_INTF_TYPE_PF; 4846 else if (BNXT_VF_IS_TRUSTED(bp)) 4847 return BNXT_ULP_INTF_TYPE_TRUSTED_VF; 4848 else if (BNXT_VF(bp)) 4849 return BNXT_ULP_INTF_TYPE_VF; 4850 4851 return BNXT_ULP_INTF_TYPE_INVALID; 4852 } 4853 4854 uint16_t 4855 bnxt_get_phy_port_id(uint16_t port_id) 4856 { 4857 struct bnxt_representor *vfr; 4858 struct rte_eth_dev *eth_dev; 4859 struct bnxt *bp; 4860 4861 eth_dev = &rte_eth_devices[port_id]; 4862 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4863 vfr = eth_dev->data->dev_private; 4864 if (!vfr) 4865 return 0; 4866 4867 eth_dev = vfr->parent_dev; 4868 } 4869 4870 bp = eth_dev->data->dev_private; 4871 4872 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; 4873 } 4874 4875 uint16_t 4876 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) 4877 { 4878 struct rte_eth_dev *eth_dev; 4879 struct bnxt *bp; 4880 4881 eth_dev = &rte_eth_devices[port_id]; 4882 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4883 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4884 if (!vfr) 4885 return 0; 4886 4887 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4888 return vfr->fw_fid - 1; 4889 4890 eth_dev = vfr->parent_dev; 4891 } 4892 4893 bp = eth_dev->data->dev_private; 4894 4895 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; 4896 } 4897 4898 uint16_t 4899 bnxt_get_vport(uint16_t port_id) 4900 { 4901 return (1 << bnxt_get_phy_port_id(port_id)); 4902 } 4903 4904 static void bnxt_alloc_error_recovery_info(struct bnxt *bp) 4905 { 4906 struct bnxt_error_recovery_info *info = bp->recovery_info; 4907 4908 if (info) { 4909 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)) 4910 memset(info, 0, sizeof(*info)); 4911 return; 4912 } 4913 4914 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 4915 return; 4916 4917 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 4918 sizeof(*info), 0); 4919 if (!info) 4920 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 4921 4922 bp->recovery_info = info; 4923 } 4924 4925 static void bnxt_check_fw_status(struct bnxt *bp) 4926 { 4927 uint32_t fw_status; 4928 4929 if (!(bp->recovery_info && 4930 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))) 4931 return; 4932 4933 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG); 4934 if (fw_status != BNXT_FW_STATUS_HEALTHY) 4935 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n", 4936 fw_status); 4937 } 4938 4939 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) 4940 { 4941 struct bnxt_error_recovery_info *info = bp->recovery_info; 4942 uint32_t status_loc; 4943 uint32_t sig_ver; 4944 4945 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 + 4946 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4947 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4948 BNXT_GRCP_WINDOW_2_BASE + 4949 offsetof(struct hcomm_status, 4950 sig_ver))); 4951 /* If the signature is absent, then FW does not support this feature */ 4952 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) != 4953 HCOMM_STATUS_SIGNATURE_VAL) 4954 return 0; 4955 4956 if (!info) { 4957 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 4958 sizeof(*info), 0); 4959 if (!info) 4960 return -ENOMEM; 4961 bp->recovery_info = info; 4962 } else { 4963 memset(info, 0, sizeof(*info)); 4964 } 4965 4966 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4967 BNXT_GRCP_WINDOW_2_BASE + 4968 offsetof(struct hcomm_status, 4969 fw_status_loc))); 4970 4971 /* Only pre-map the FW health status GRC register */ 4972 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC) 4973 return 0; 4974 4975 info->status_regs[BNXT_FW_STATUS_REG] = status_loc; 4976 info->mapped_status_regs[BNXT_FW_STATUS_REG] = 4977 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK); 4978 4979 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 + 4980 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4981 4982 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS; 4983 4984 return 0; 4985 } 4986 4987 /* This function gets the FW version along with the 4988 * capabilities(MAX and current) of the function, vnic, 4989 * error recovery, phy and other chip related info 4990 */ 4991 static int bnxt_get_config(struct bnxt *bp) 4992 { 4993 uint16_t mtu; 4994 int rc = 0; 4995 4996 bp->fw_cap = 0; 4997 4998 rc = bnxt_map_hcomm_fw_status_reg(bp); 4999 if (rc) 5000 return rc; 5001 5002 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT); 5003 if (rc) { 5004 bnxt_check_fw_status(bp); 5005 return rc; 5006 } 5007 5008 rc = bnxt_hwrm_func_reset(bp); 5009 if (rc) 5010 return -EIO; 5011 5012 rc = bnxt_hwrm_vnic_qcaps(bp); 5013 if (rc) 5014 return rc; 5015 5016 rc = bnxt_hwrm_queue_qportcfg(bp); 5017 if (rc) 5018 return rc; 5019 5020 /* Get the MAX capabilities for this function. 5021 * This function also allocates context memory for TQM rings and 5022 * informs the firmware about this allocated backing store memory. 5023 */ 5024 rc = bnxt_hwrm_func_qcaps(bp); 5025 if (rc) 5026 return rc; 5027 5028 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 5029 if (rc) 5030 return rc; 5031 5032 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 5033 if (rc) 5034 return rc; 5035 5036 bnxt_hwrm_port_mac_qcfg(bp); 5037 5038 bnxt_hwrm_parent_pf_qcfg(bp); 5039 5040 bnxt_hwrm_port_phy_qcaps(bp); 5041 5042 bnxt_alloc_error_recovery_info(bp); 5043 /* Get the adapter error recovery support info */ 5044 rc = bnxt_hwrm_error_recovery_qcfg(bp); 5045 if (rc) 5046 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5047 5048 bnxt_hwrm_port_led_qcaps(bp); 5049 5050 return 0; 5051 } 5052 5053 static int 5054 bnxt_init_locks(struct bnxt *bp) 5055 { 5056 int err; 5057 5058 err = pthread_mutex_init(&bp->flow_lock, NULL); 5059 if (err) { 5060 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 5061 return err; 5062 } 5063 5064 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 5065 if (err) { 5066 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 5067 return err; 5068 } 5069 5070 err = pthread_mutex_init(&bp->health_check_lock, NULL); 5071 if (err) { 5072 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n"); 5073 return err; 5074 } 5075 5076 err = pthread_mutex_init(&bp->err_recovery_lock, NULL); 5077 if (err) 5078 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n"); 5079 5080 return err; 5081 } 5082 5083 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 5084 { 5085 int rc = 0; 5086 5087 rc = bnxt_get_config(bp); 5088 if (rc) 5089 return rc; 5090 5091 if (!reconfig_dev) { 5092 rc = bnxt_setup_mac_addr(bp->eth_dev); 5093 if (rc) 5094 return rc; 5095 } else { 5096 rc = bnxt_restore_dflt_mac(bp); 5097 if (rc) 5098 return rc; 5099 } 5100 5101 bnxt_config_vf_req_fwd(bp); 5102 5103 rc = bnxt_hwrm_func_driver_register(bp); 5104 if (rc) { 5105 PMD_DRV_LOG(ERR, "Failed to register driver"); 5106 return -EBUSY; 5107 } 5108 5109 if (BNXT_PF(bp)) { 5110 if (bp->pdev->max_vfs) { 5111 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 5112 if (rc) { 5113 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 5114 return rc; 5115 } 5116 } else { 5117 rc = bnxt_hwrm_allocate_pf_only(bp); 5118 if (rc) { 5119 PMD_DRV_LOG(ERR, 5120 "Failed to allocate PF resources"); 5121 return rc; 5122 } 5123 } 5124 } 5125 5126 rc = bnxt_alloc_mem(bp, reconfig_dev); 5127 if (rc) 5128 return rc; 5129 5130 rc = bnxt_setup_int(bp); 5131 if (rc) 5132 return rc; 5133 5134 rc = bnxt_request_int(bp); 5135 if (rc) 5136 return rc; 5137 5138 rc = bnxt_init_ctx_mem(bp); 5139 if (rc) { 5140 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n"); 5141 return rc; 5142 } 5143 5144 return 0; 5145 } 5146 5147 static int 5148 bnxt_parse_devarg_truflow(__rte_unused const char *key, 5149 const char *value, void *opaque_arg) 5150 { 5151 struct bnxt *bp = opaque_arg; 5152 unsigned long truflow; 5153 char *end = NULL; 5154 5155 if (!value || !opaque_arg) { 5156 PMD_DRV_LOG(ERR, 5157 "Invalid parameter passed to truflow devargs.\n"); 5158 return -EINVAL; 5159 } 5160 5161 truflow = strtoul(value, &end, 10); 5162 if (end == NULL || *end != '\0' || 5163 (truflow == ULONG_MAX && errno == ERANGE)) { 5164 PMD_DRV_LOG(ERR, 5165 "Invalid parameter passed to truflow devargs.\n"); 5166 return -EINVAL; 5167 } 5168 5169 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) { 5170 PMD_DRV_LOG(ERR, 5171 "Invalid value passed to truflow devargs.\n"); 5172 return -EINVAL; 5173 } 5174 5175 if (truflow) { 5176 bp->flags |= BNXT_FLAG_TRUFLOW_EN; 5177 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n"); 5178 } else { 5179 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN; 5180 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n"); 5181 } 5182 5183 return 0; 5184 } 5185 5186 static int 5187 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, 5188 const char *value, void *opaque_arg) 5189 { 5190 struct bnxt *bp = opaque_arg; 5191 unsigned long flow_xstat; 5192 char *end = NULL; 5193 5194 if (!value || !opaque_arg) { 5195 PMD_DRV_LOG(ERR, 5196 "Invalid parameter passed to flow_xstat devarg.\n"); 5197 return -EINVAL; 5198 } 5199 5200 flow_xstat = strtoul(value, &end, 10); 5201 if (end == NULL || *end != '\0' || 5202 (flow_xstat == ULONG_MAX && errno == ERANGE)) { 5203 PMD_DRV_LOG(ERR, 5204 "Invalid parameter passed to flow_xstat devarg.\n"); 5205 return -EINVAL; 5206 } 5207 5208 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) { 5209 PMD_DRV_LOG(ERR, 5210 "Invalid value passed to flow_xstat devarg.\n"); 5211 return -EINVAL; 5212 } 5213 5214 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN; 5215 if (BNXT_FLOW_XSTATS_EN(bp)) 5216 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n"); 5217 5218 return 0; 5219 } 5220 5221 static int 5222 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, 5223 const char *value, void *opaque_arg) 5224 { 5225 struct bnxt *bp = opaque_arg; 5226 unsigned long max_num_kflows; 5227 char *end = NULL; 5228 5229 if (!value || !opaque_arg) { 5230 PMD_DRV_LOG(ERR, 5231 "Invalid parameter passed to max_num_kflows devarg.\n"); 5232 return -EINVAL; 5233 } 5234 5235 max_num_kflows = strtoul(value, &end, 10); 5236 if (end == NULL || *end != '\0' || 5237 (max_num_kflows == ULONG_MAX && errno == ERANGE)) { 5238 PMD_DRV_LOG(ERR, 5239 "Invalid parameter passed to max_num_kflows devarg.\n"); 5240 return -EINVAL; 5241 } 5242 5243 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) { 5244 PMD_DRV_LOG(ERR, 5245 "Invalid value passed to max_num_kflows devarg.\n"); 5246 return -EINVAL; 5247 } 5248 5249 bp->max_num_kflows = max_num_kflows; 5250 if (bp->max_num_kflows) 5251 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n", 5252 max_num_kflows); 5253 5254 return 0; 5255 } 5256 5257 static int 5258 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key, 5259 const char *value, void *opaque_arg) 5260 { 5261 struct bnxt_representor *vfr_bp = opaque_arg; 5262 unsigned long rep_is_pf; 5263 char *end = NULL; 5264 5265 if (!value || !opaque_arg) { 5266 PMD_DRV_LOG(ERR, 5267 "Invalid parameter passed to rep_is_pf devargs.\n"); 5268 return -EINVAL; 5269 } 5270 5271 rep_is_pf = strtoul(value, &end, 10); 5272 if (end == NULL || *end != '\0' || 5273 (rep_is_pf == ULONG_MAX && errno == ERANGE)) { 5274 PMD_DRV_LOG(ERR, 5275 "Invalid parameter passed to rep_is_pf devargs.\n"); 5276 return -EINVAL; 5277 } 5278 5279 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) { 5280 PMD_DRV_LOG(ERR, 5281 "Invalid value passed to rep_is_pf devargs.\n"); 5282 return -EINVAL; 5283 } 5284 5285 vfr_bp->flags |= rep_is_pf; 5286 if (BNXT_REP_PF(vfr_bp)) 5287 PMD_DRV_LOG(INFO, "PF representor\n"); 5288 else 5289 PMD_DRV_LOG(INFO, "VF representor\n"); 5290 5291 return 0; 5292 } 5293 5294 static int 5295 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key, 5296 const char *value, void *opaque_arg) 5297 { 5298 struct bnxt_representor *vfr_bp = opaque_arg; 5299 unsigned long rep_based_pf; 5300 char *end = NULL; 5301 5302 if (!value || !opaque_arg) { 5303 PMD_DRV_LOG(ERR, 5304 "Invalid parameter passed to rep_based_pf " 5305 "devargs.\n"); 5306 return -EINVAL; 5307 } 5308 5309 rep_based_pf = strtoul(value, &end, 10); 5310 if (end == NULL || *end != '\0' || 5311 (rep_based_pf == ULONG_MAX && errno == ERANGE)) { 5312 PMD_DRV_LOG(ERR, 5313 "Invalid parameter passed to rep_based_pf " 5314 "devargs.\n"); 5315 return -EINVAL; 5316 } 5317 5318 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) { 5319 PMD_DRV_LOG(ERR, 5320 "Invalid value passed to rep_based_pf devargs.\n"); 5321 return -EINVAL; 5322 } 5323 5324 vfr_bp->rep_based_pf = rep_based_pf; 5325 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID; 5326 5327 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf); 5328 5329 return 0; 5330 } 5331 5332 static int 5333 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key, 5334 const char *value, void *opaque_arg) 5335 { 5336 struct bnxt_representor *vfr_bp = opaque_arg; 5337 unsigned long rep_q_r2f; 5338 char *end = NULL; 5339 5340 if (!value || !opaque_arg) { 5341 PMD_DRV_LOG(ERR, 5342 "Invalid parameter passed to rep_q_r2f " 5343 "devargs.\n"); 5344 return -EINVAL; 5345 } 5346 5347 rep_q_r2f = strtoul(value, &end, 10); 5348 if (end == NULL || *end != '\0' || 5349 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) { 5350 PMD_DRV_LOG(ERR, 5351 "Invalid parameter passed to rep_q_r2f " 5352 "devargs.\n"); 5353 return -EINVAL; 5354 } 5355 5356 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) { 5357 PMD_DRV_LOG(ERR, 5358 "Invalid value passed to rep_q_r2f devargs.\n"); 5359 return -EINVAL; 5360 } 5361 5362 vfr_bp->rep_q_r2f = rep_q_r2f; 5363 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID; 5364 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f); 5365 5366 return 0; 5367 } 5368 5369 static int 5370 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key, 5371 const char *value, void *opaque_arg) 5372 { 5373 struct bnxt_representor *vfr_bp = opaque_arg; 5374 unsigned long rep_q_f2r; 5375 char *end = NULL; 5376 5377 if (!value || !opaque_arg) { 5378 PMD_DRV_LOG(ERR, 5379 "Invalid parameter passed to rep_q_f2r " 5380 "devargs.\n"); 5381 return -EINVAL; 5382 } 5383 5384 rep_q_f2r = strtoul(value, &end, 10); 5385 if (end == NULL || *end != '\0' || 5386 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) { 5387 PMD_DRV_LOG(ERR, 5388 "Invalid parameter passed to rep_q_f2r " 5389 "devargs.\n"); 5390 return -EINVAL; 5391 } 5392 5393 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) { 5394 PMD_DRV_LOG(ERR, 5395 "Invalid value passed to rep_q_f2r devargs.\n"); 5396 return -EINVAL; 5397 } 5398 5399 vfr_bp->rep_q_f2r = rep_q_f2r; 5400 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID; 5401 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r); 5402 5403 return 0; 5404 } 5405 5406 static int 5407 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key, 5408 const char *value, void *opaque_arg) 5409 { 5410 struct bnxt_representor *vfr_bp = opaque_arg; 5411 unsigned long rep_fc_r2f; 5412 char *end = NULL; 5413 5414 if (!value || !opaque_arg) { 5415 PMD_DRV_LOG(ERR, 5416 "Invalid parameter passed to rep_fc_r2f " 5417 "devargs.\n"); 5418 return -EINVAL; 5419 } 5420 5421 rep_fc_r2f = strtoul(value, &end, 10); 5422 if (end == NULL || *end != '\0' || 5423 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) { 5424 PMD_DRV_LOG(ERR, 5425 "Invalid parameter passed to rep_fc_r2f " 5426 "devargs.\n"); 5427 return -EINVAL; 5428 } 5429 5430 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) { 5431 PMD_DRV_LOG(ERR, 5432 "Invalid value passed to rep_fc_r2f devargs.\n"); 5433 return -EINVAL; 5434 } 5435 5436 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID; 5437 vfr_bp->rep_fc_r2f = rep_fc_r2f; 5438 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f); 5439 5440 return 0; 5441 } 5442 5443 static int 5444 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key, 5445 const char *value, void *opaque_arg) 5446 { 5447 struct bnxt_representor *vfr_bp = opaque_arg; 5448 unsigned long rep_fc_f2r; 5449 char *end = NULL; 5450 5451 if (!value || !opaque_arg) { 5452 PMD_DRV_LOG(ERR, 5453 "Invalid parameter passed to rep_fc_f2r " 5454 "devargs.\n"); 5455 return -EINVAL; 5456 } 5457 5458 rep_fc_f2r = strtoul(value, &end, 10); 5459 if (end == NULL || *end != '\0' || 5460 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) { 5461 PMD_DRV_LOG(ERR, 5462 "Invalid parameter passed to rep_fc_f2r " 5463 "devargs.\n"); 5464 return -EINVAL; 5465 } 5466 5467 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) { 5468 PMD_DRV_LOG(ERR, 5469 "Invalid value passed to rep_fc_f2r devargs.\n"); 5470 return -EINVAL; 5471 } 5472 5473 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID; 5474 vfr_bp->rep_fc_f2r = rep_fc_f2r; 5475 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r); 5476 5477 return 0; 5478 } 5479 5480 static int 5481 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) 5482 { 5483 struct rte_kvargs *kvlist; 5484 int ret; 5485 5486 if (devargs == NULL) 5487 return 0; 5488 5489 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); 5490 if (kvlist == NULL) 5491 return -EINVAL; 5492 5493 /* 5494 * Handler for "truflow" devarg. 5495 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1" 5496 */ 5497 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW, 5498 bnxt_parse_devarg_truflow, bp); 5499 if (ret) 5500 goto err; 5501 5502 /* 5503 * Handler for "flow_xstat" devarg. 5504 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1" 5505 */ 5506 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, 5507 bnxt_parse_devarg_flow_xstat, bp); 5508 if (ret) 5509 goto err; 5510 5511 /* 5512 * Handler for "max_num_kflows" devarg. 5513 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" 5514 */ 5515 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, 5516 bnxt_parse_devarg_max_num_kflows, bp); 5517 if (ret) 5518 goto err; 5519 5520 err: 5521 rte_kvargs_free(kvlist); 5522 return ret; 5523 } 5524 5525 static int bnxt_alloc_switch_domain(struct bnxt *bp) 5526 { 5527 int rc = 0; 5528 5529 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 5530 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id); 5531 if (rc) 5532 PMD_DRV_LOG(ERR, 5533 "Failed to alloc switch domain: %d\n", rc); 5534 else 5535 PMD_DRV_LOG(INFO, 5536 "Switch domain allocated %d\n", 5537 bp->switch_domain_id); 5538 } 5539 5540 return rc; 5541 } 5542 5543 /* Allocate and initialize various fields in bnxt struct that 5544 * need to be allocated/destroyed only once in the lifetime of the driver 5545 */ 5546 static int bnxt_drv_init(struct rte_eth_dev *eth_dev) 5547 { 5548 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5549 struct bnxt *bp = eth_dev->data->dev_private; 5550 int rc = 0; 5551 5552 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 5553 5554 if (bnxt_vf_pciid(pci_dev->id.device_id)) 5555 bp->flags |= BNXT_FLAG_VF; 5556 5557 if (bnxt_p5_device(pci_dev->id.device_id)) 5558 bp->flags |= BNXT_FLAG_CHIP_P5; 5559 5560 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 5561 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 5562 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 5563 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 5564 bp->flags |= BNXT_FLAG_STINGRAY; 5565 5566 if (BNXT_TRUFLOW_EN(bp)) { 5567 /* extra mbuf field is required to store CFA code from mark */ 5568 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = { 5569 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME, 5570 .size = sizeof(bnxt_cfa_code_dynfield_t), 5571 .align = __alignof__(bnxt_cfa_code_dynfield_t), 5572 }; 5573 bnxt_cfa_code_dynfield_offset = 5574 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc); 5575 if (bnxt_cfa_code_dynfield_offset < 0) { 5576 PMD_DRV_LOG(ERR, 5577 "Failed to register mbuf field for TruFlow mark\n"); 5578 return -rte_errno; 5579 } 5580 } 5581 5582 rc = bnxt_map_pci_bars(eth_dev); 5583 if (rc) { 5584 PMD_DRV_LOG(ERR, 5585 "Failed to initialize board rc: %x\n", rc); 5586 return rc; 5587 } 5588 5589 rc = bnxt_alloc_pf_info(bp); 5590 if (rc) 5591 return rc; 5592 5593 rc = bnxt_alloc_link_info(bp); 5594 if (rc) 5595 return rc; 5596 5597 rc = bnxt_alloc_parent_info(bp); 5598 if (rc) 5599 return rc; 5600 5601 rc = bnxt_alloc_hwrm_resources(bp); 5602 if (rc) { 5603 PMD_DRV_LOG(ERR, 5604 "Failed to allocate response buffer rc: %x\n", rc); 5605 return rc; 5606 } 5607 rc = bnxt_alloc_leds_info(bp); 5608 if (rc) 5609 return rc; 5610 5611 rc = bnxt_alloc_cos_queues(bp); 5612 if (rc) 5613 return rc; 5614 5615 rc = bnxt_init_locks(bp); 5616 if (rc) 5617 return rc; 5618 5619 rc = bnxt_alloc_switch_domain(bp); 5620 if (rc) 5621 return rc; 5622 5623 return rc; 5624 } 5625 5626 static int 5627 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) 5628 { 5629 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5630 static int version_printed; 5631 struct bnxt *bp; 5632 int rc; 5633 5634 if (version_printed++ == 0) 5635 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 5636 5637 eth_dev->dev_ops = &bnxt_dev_ops; 5638 eth_dev->rx_queue_count = bnxt_rx_queue_count_op; 5639 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; 5640 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; 5641 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 5642 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 5643 5644 /* 5645 * For secondary processes, we don't initialise any further 5646 * as primary has already done this work. 5647 */ 5648 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5649 return 0; 5650 5651 rte_eth_copy_pci_info(eth_dev, pci_dev); 5652 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 5653 5654 bp = eth_dev->data->dev_private; 5655 5656 /* Parse dev arguments passed on when starting the DPDK application. */ 5657 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs); 5658 if (rc) 5659 goto error_free; 5660 5661 rc = bnxt_drv_init(eth_dev); 5662 if (rc) 5663 goto error_free; 5664 5665 rc = bnxt_init_resources(bp, false); 5666 if (rc) 5667 goto error_free; 5668 5669 rc = bnxt_alloc_stats_mem(bp); 5670 if (rc) 5671 goto error_free; 5672 5673 PMD_DRV_LOG(INFO, 5674 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", 5675 pci_dev->mem_resource[0].phys_addr, 5676 pci_dev->mem_resource[0].addr); 5677 5678 return 0; 5679 5680 error_free: 5681 bnxt_dev_uninit(eth_dev); 5682 return rc; 5683 } 5684 5685 5686 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx) 5687 { 5688 if (!ctx) 5689 return; 5690 5691 if (ctx->va) 5692 rte_free(ctx->va); 5693 5694 ctx->va = NULL; 5695 ctx->dma = RTE_BAD_IOVA; 5696 ctx->ctx_id = BNXT_CTX_VAL_INVAL; 5697 } 5698 5699 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp) 5700 { 5701 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 5702 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5703 bp->flow_stat->rx_fc_out_tbl.ctx_id, 5704 bp->flow_stat->max_fc, 5705 false); 5706 5707 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 5708 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5709 bp->flow_stat->tx_fc_out_tbl.ctx_id, 5710 bp->flow_stat->max_fc, 5711 false); 5712 5713 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5714 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id); 5715 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5716 5717 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5718 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id); 5719 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5720 5721 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5722 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id); 5723 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5724 5725 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5726 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id); 5727 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5728 } 5729 5730 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp) 5731 { 5732 bnxt_unregister_fc_ctx_mem(bp); 5733 5734 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl); 5735 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl); 5736 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl); 5737 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl); 5738 } 5739 5740 static void bnxt_uninit_ctx_mem(struct bnxt *bp) 5741 { 5742 if (BNXT_FLOW_XSTATS_EN(bp)) 5743 bnxt_uninit_fc_ctx_mem(bp); 5744 } 5745 5746 static void 5747 bnxt_free_error_recovery_info(struct bnxt *bp) 5748 { 5749 rte_free(bp->recovery_info); 5750 bp->recovery_info = NULL; 5751 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5752 } 5753 5754 static int 5755 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 5756 { 5757 int rc; 5758 5759 bnxt_free_int(bp); 5760 bnxt_free_mem(bp, reconfig_dev); 5761 5762 bnxt_hwrm_func_buf_unrgtr(bp); 5763 if (bp->pf != NULL) { 5764 rte_free(bp->pf->vf_req_buf); 5765 bp->pf->vf_req_buf = NULL; 5766 } 5767 5768 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 5769 bp->flags &= ~BNXT_FLAG_REGISTERED; 5770 bnxt_free_ctx_mem(bp); 5771 if (!reconfig_dev) { 5772 bnxt_free_hwrm_resources(bp); 5773 bnxt_free_error_recovery_info(bp); 5774 } 5775 5776 bnxt_uninit_ctx_mem(bp); 5777 5778 bnxt_free_flow_stats_info(bp); 5779 if (bp->rep_info != NULL) 5780 bnxt_free_switch_domain(bp); 5781 bnxt_free_rep_info(bp); 5782 rte_free(bp->ptp_cfg); 5783 bp->ptp_cfg = NULL; 5784 return rc; 5785 } 5786 5787 static int 5788 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 5789 { 5790 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5791 return -EPERM; 5792 5793 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 5794 5795 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 5796 bnxt_dev_close_op(eth_dev); 5797 5798 return 0; 5799 } 5800 5801 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev) 5802 { 5803 struct bnxt *bp = eth_dev->data->dev_private; 5804 struct rte_eth_dev *vf_rep_eth_dev; 5805 int ret = 0, i; 5806 5807 if (!bp) 5808 return -EINVAL; 5809 5810 for (i = 0; i < bp->num_reps; i++) { 5811 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev; 5812 if (!vf_rep_eth_dev) 5813 continue; 5814 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n", 5815 vf_rep_eth_dev->data->port_id); 5816 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit); 5817 } 5818 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", 5819 eth_dev->data->port_id); 5820 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit); 5821 5822 return ret; 5823 } 5824 5825 static void bnxt_free_rep_info(struct bnxt *bp) 5826 { 5827 rte_free(bp->rep_info); 5828 bp->rep_info = NULL; 5829 rte_free(bp->cfa_code_map); 5830 bp->cfa_code_map = NULL; 5831 } 5832 5833 static int bnxt_init_rep_info(struct bnxt *bp) 5834 { 5835 int i = 0, rc; 5836 5837 if (bp->rep_info) 5838 return 0; 5839 5840 bp->rep_info = rte_zmalloc("bnxt_rep_info", 5841 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, 5842 0); 5843 if (!bp->rep_info) { 5844 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); 5845 return -ENOMEM; 5846 } 5847 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map", 5848 sizeof(*bp->cfa_code_map) * 5849 BNXT_MAX_CFA_CODE, 0); 5850 if (!bp->cfa_code_map) { 5851 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n"); 5852 bnxt_free_rep_info(bp); 5853 return -ENOMEM; 5854 } 5855 5856 for (i = 0; i < BNXT_MAX_CFA_CODE; i++) 5857 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID; 5858 5859 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL); 5860 if (rc) { 5861 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n"); 5862 bnxt_free_rep_info(bp); 5863 return rc; 5864 } 5865 5866 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL); 5867 if (rc) { 5868 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n"); 5869 bnxt_free_rep_info(bp); 5870 return rc; 5871 } 5872 5873 return rc; 5874 } 5875 5876 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, 5877 struct rte_eth_devargs *eth_da, 5878 struct rte_eth_dev *backing_eth_dev, 5879 const char *dev_args) 5880 { 5881 struct rte_eth_dev *vf_rep_eth_dev; 5882 char name[RTE_ETH_NAME_MAX_LEN]; 5883 struct bnxt *backing_bp; 5884 uint16_t num_rep; 5885 int i, ret = 0; 5886 struct rte_kvargs *kvlist = NULL; 5887 5888 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) 5889 return 0; 5890 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) { 5891 PMD_DRV_LOG(ERR, "unsupported representor type %d\n", 5892 eth_da->type); 5893 return -ENOTSUP; 5894 } 5895 num_rep = eth_da->nb_representor_ports; 5896 if (num_rep > BNXT_MAX_VF_REPS) { 5897 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", 5898 num_rep, BNXT_MAX_VF_REPS); 5899 return -EINVAL; 5900 } 5901 5902 if (num_rep >= RTE_MAX_ETHPORTS) { 5903 PMD_DRV_LOG(ERR, 5904 "nb_representor_ports = %d > %d MAX ETHPORTS\n", 5905 num_rep, RTE_MAX_ETHPORTS); 5906 return -EINVAL; 5907 } 5908 5909 backing_bp = backing_eth_dev->data->dev_private; 5910 5911 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { 5912 PMD_DRV_LOG(ERR, 5913 "Not a PF or trusted VF. No Representor support\n"); 5914 /* Returning an error is not an option. 5915 * Applications are not handling this correctly 5916 */ 5917 return 0; 5918 } 5919 5920 if (bnxt_init_rep_info(backing_bp)) 5921 return 0; 5922 5923 for (i = 0; i < num_rep; i++) { 5924 struct bnxt_representor representor = { 5925 .vf_id = eth_da->representor_ports[i], 5926 .switch_domain_id = backing_bp->switch_domain_id, 5927 .parent_dev = backing_eth_dev 5928 }; 5929 5930 if (representor.vf_id >= BNXT_MAX_VF_REPS) { 5931 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", 5932 representor.vf_id, BNXT_MAX_VF_REPS); 5933 continue; 5934 } 5935 5936 /* representor port net_bdf_port */ 5937 snprintf(name, sizeof(name), "net_%s_representor_%d", 5938 pci_dev->device.name, eth_da->representor_ports[i]); 5939 5940 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args); 5941 if (kvlist) { 5942 /* 5943 * Handler for "rep_is_pf" devarg. 5944 * Invoked as for ex: "-a 000:00:0d.0, 5945 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5946 */ 5947 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF, 5948 bnxt_parse_devarg_rep_is_pf, 5949 (void *)&representor); 5950 if (ret) { 5951 ret = -EINVAL; 5952 goto err; 5953 } 5954 /* 5955 * Handler for "rep_based_pf" devarg. 5956 * Invoked as for ex: "-a 000:00:0d.0, 5957 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5958 */ 5959 ret = rte_kvargs_process(kvlist, 5960 BNXT_DEVARG_REP_BASED_PF, 5961 bnxt_parse_devarg_rep_based_pf, 5962 (void *)&representor); 5963 if (ret) { 5964 ret = -EINVAL; 5965 goto err; 5966 } 5967 /* 5968 * Handler for "rep_based_pf" devarg. 5969 * Invoked as for ex: "-a 000:00:0d.0, 5970 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5971 */ 5972 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F, 5973 bnxt_parse_devarg_rep_q_r2f, 5974 (void *)&representor); 5975 if (ret) { 5976 ret = -EINVAL; 5977 goto err; 5978 } 5979 /* 5980 * Handler for "rep_based_pf" devarg. 5981 * Invoked as for ex: "-a 000:00:0d.0, 5982 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5983 */ 5984 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R, 5985 bnxt_parse_devarg_rep_q_f2r, 5986 (void *)&representor); 5987 if (ret) { 5988 ret = -EINVAL; 5989 goto err; 5990 } 5991 /* 5992 * Handler for "rep_based_pf" devarg. 5993 * Invoked as for ex: "-a 000:00:0d.0, 5994 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5995 */ 5996 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F, 5997 bnxt_parse_devarg_rep_fc_r2f, 5998 (void *)&representor); 5999 if (ret) { 6000 ret = -EINVAL; 6001 goto err; 6002 } 6003 /* 6004 * Handler for "rep_based_pf" devarg. 6005 * Invoked as for ex: "-a 000:00:0d.0, 6006 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6007 */ 6008 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R, 6009 bnxt_parse_devarg_rep_fc_f2r, 6010 (void *)&representor); 6011 if (ret) { 6012 ret = -EINVAL; 6013 goto err; 6014 } 6015 } 6016 6017 ret = rte_eth_dev_create(&pci_dev->device, name, 6018 sizeof(struct bnxt_representor), 6019 NULL, NULL, 6020 bnxt_representor_init, 6021 &representor); 6022 if (ret) { 6023 PMD_DRV_LOG(ERR, "failed to create bnxt vf " 6024 "representor %s.", name); 6025 goto err; 6026 } 6027 6028 vf_rep_eth_dev = rte_eth_dev_allocated(name); 6029 if (!vf_rep_eth_dev) { 6030 PMD_DRV_LOG(ERR, "Failed to find the eth_dev" 6031 " for VF-Rep: %s.", name); 6032 ret = -ENODEV; 6033 goto err; 6034 } 6035 6036 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n", 6037 backing_eth_dev->data->port_id); 6038 backing_bp->rep_info[representor.vf_id].vfr_eth_dev = 6039 vf_rep_eth_dev; 6040 backing_bp->num_reps++; 6041 6042 } 6043 6044 rte_kvargs_free(kvlist); 6045 return 0; 6046 6047 err: 6048 /* If num_rep > 1, then rollback already created 6049 * ports, since we'll be failing the probe anyway 6050 */ 6051 if (num_rep > 1) 6052 bnxt_pci_remove_dev_with_reps(backing_eth_dev); 6053 rte_errno = -ret; 6054 rte_kvargs_free(kvlist); 6055 6056 return ret; 6057 } 6058 6059 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 6060 struct rte_pci_device *pci_dev) 6061 { 6062 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 6063 struct rte_eth_dev *backing_eth_dev; 6064 uint16_t num_rep; 6065 int ret = 0; 6066 6067 if (pci_dev->device.devargs) { 6068 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, 6069 ð_da); 6070 if (ret) 6071 return ret; 6072 } 6073 6074 num_rep = eth_da.nb_representor_ports; 6075 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n", 6076 num_rep); 6077 6078 /* We could come here after first level of probe is already invoked 6079 * as part of an application bringup(OVS-DPDK vswitchd), so first check 6080 * for already allocated eth_dev for the backing device (PF/Trusted VF) 6081 */ 6082 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6083 if (backing_eth_dev == NULL) { 6084 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 6085 sizeof(struct bnxt), 6086 eth_dev_pci_specific_init, pci_dev, 6087 bnxt_dev_init, NULL); 6088 6089 if (ret || !num_rep) 6090 return ret; 6091 6092 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6093 } 6094 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n", 6095 backing_eth_dev->data->port_id); 6096 6097 if (!num_rep) 6098 return ret; 6099 6100 /* probe representor ports now */ 6101 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev, 6102 pci_dev->device.devargs->args); 6103 6104 return ret; 6105 } 6106 6107 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 6108 { 6109 struct rte_eth_dev *eth_dev; 6110 6111 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6112 if (!eth_dev) 6113 return 0; /* Invoked typically only by OVS-DPDK, by the 6114 * time it comes here the eth_dev is already 6115 * deleted by rte_eth_dev_close(), so returning 6116 * +ve value will at least help in proper cleanup 6117 */ 6118 6119 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id); 6120 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 6121 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 6122 return rte_eth_dev_destroy(eth_dev, 6123 bnxt_representor_uninit); 6124 else 6125 return rte_eth_dev_destroy(eth_dev, 6126 bnxt_dev_uninit); 6127 } else { 6128 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 6129 } 6130 } 6131 6132 static struct rte_pci_driver bnxt_rte_pmd = { 6133 .id_table = bnxt_pci_id_map, 6134 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 6135 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs 6136 * and OVS-DPDK 6137 */ 6138 .probe = bnxt_pci_probe, 6139 .remove = bnxt_pci_remove, 6140 }; 6141 6142 static bool 6143 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 6144 { 6145 if (strcmp(dev->device->driver->name, drv->driver.name)) 6146 return false; 6147 6148 return true; 6149 } 6150 6151 bool is_bnxt_supported(struct rte_eth_dev *dev) 6152 { 6153 return is_device_supported(dev, &bnxt_rte_pmd); 6154 } 6155 6156 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE); 6157 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 6158 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 6159 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 6160