1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <rte_ethdev_driver.h> 11 #include <rte_ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 16 #include "bnxt.h" 17 #include "bnxt_filter.h" 18 #include "bnxt_hwrm.h" 19 #include "bnxt_irq.h" 20 #include "bnxt_ring.h" 21 #include "bnxt_rxq.h" 22 #include "bnxt_rxr.h" 23 #include "bnxt_stats.h" 24 #include "bnxt_txq.h" 25 #include "bnxt_txr.h" 26 #include "bnxt_vnic.h" 27 #include "hsi_struct_def_dpdk.h" 28 #include "bnxt_nvm_defs.h" 29 30 #define DRV_MODULE_NAME "bnxt" 31 static const char bnxt_version[] = 32 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 33 int bnxt_logtype_driver; 34 35 /* 36 * The set of PCI devices this driver supports 37 */ 38 static const struct rte_pci_id bnxt_pci_id_map[] = { 39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 92 { .vendor_id = 0, /* sentinel */ }, 93 }; 94 95 #define BNXT_ETH_RSS_SUPPORT ( \ 96 ETH_RSS_IPV4 | \ 97 ETH_RSS_NONFRAG_IPV4_TCP | \ 98 ETH_RSS_NONFRAG_IPV4_UDP | \ 99 ETH_RSS_IPV6 | \ 100 ETH_RSS_NONFRAG_IPV6_TCP | \ 101 ETH_RSS_NONFRAG_IPV6_UDP) 102 103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 104 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 105 DEV_TX_OFFLOAD_TCP_CKSUM | \ 106 DEV_TX_OFFLOAD_UDP_CKSUM | \ 107 DEV_TX_OFFLOAD_TCP_TSO | \ 108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 113 DEV_TX_OFFLOAD_QINQ_INSERT | \ 114 DEV_TX_OFFLOAD_MULTI_SEGS) 115 116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 117 DEV_RX_OFFLOAD_VLAN_STRIP | \ 118 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 119 DEV_RX_OFFLOAD_UDP_CKSUM | \ 120 DEV_RX_OFFLOAD_TCP_CKSUM | \ 121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 122 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 123 DEV_RX_OFFLOAD_KEEP_CRC | \ 124 DEV_RX_OFFLOAD_VLAN_EXTEND | \ 125 DEV_RX_OFFLOAD_TCP_LRO | \ 126 DEV_RX_OFFLOAD_SCATTER | \ 127 DEV_RX_OFFLOAD_RSS_HASH) 128 129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 134 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 135 static int bnxt_restore_vlan_filters(struct bnxt *bp); 136 137 int is_bnxt_in_error(struct bnxt *bp) 138 { 139 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 140 return -EIO; 141 if (bp->flags & BNXT_FLAG_FW_RESET) 142 return -EBUSY; 143 144 return 0; 145 } 146 147 /***********************/ 148 149 /* 150 * High level utility functions 151 */ 152 153 uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 154 { 155 if (!BNXT_CHIP_THOR(bp)) 156 return 1; 157 158 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings, 159 BNXT_RSS_ENTRIES_PER_CTX_THOR) / 160 BNXT_RSS_ENTRIES_PER_CTX_THOR; 161 } 162 163 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 164 { 165 if (!BNXT_CHIP_THOR(bp)) 166 return HW_HASH_INDEX_SIZE; 167 168 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR; 169 } 170 171 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 172 { 173 bnxt_free_filter_mem(bp); 174 bnxt_free_vnic_attributes(bp); 175 bnxt_free_vnic_mem(bp); 176 177 /* tx/rx rings are configured as part of *_queue_setup callbacks. 178 * If the number of rings change across fw update, 179 * we don't have much choice except to warn the user. 180 */ 181 if (!reconfig) { 182 bnxt_free_stats(bp); 183 bnxt_free_tx_rings(bp); 184 bnxt_free_rx_rings(bp); 185 } 186 bnxt_free_async_cp_ring(bp); 187 bnxt_free_rxtx_nq_ring(bp); 188 189 rte_free(bp->grp_info); 190 bp->grp_info = NULL; 191 } 192 193 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 194 { 195 int rc; 196 197 rc = bnxt_alloc_ring_grps(bp); 198 if (rc) 199 goto alloc_mem_err; 200 201 rc = bnxt_alloc_async_ring_struct(bp); 202 if (rc) 203 goto alloc_mem_err; 204 205 rc = bnxt_alloc_vnic_mem(bp); 206 if (rc) 207 goto alloc_mem_err; 208 209 rc = bnxt_alloc_vnic_attributes(bp); 210 if (rc) 211 goto alloc_mem_err; 212 213 rc = bnxt_alloc_filter_mem(bp); 214 if (rc) 215 goto alloc_mem_err; 216 217 rc = bnxt_alloc_async_cp_ring(bp); 218 if (rc) 219 goto alloc_mem_err; 220 221 rc = bnxt_alloc_rxtx_nq_ring(bp); 222 if (rc) 223 goto alloc_mem_err; 224 225 return 0; 226 227 alloc_mem_err: 228 bnxt_free_mem(bp, reconfig); 229 return rc; 230 } 231 232 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 233 { 234 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 235 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 236 uint64_t rx_offloads = dev_conf->rxmode.offloads; 237 struct bnxt_rx_queue *rxq; 238 unsigned int j; 239 int rc; 240 241 rc = bnxt_vnic_grp_alloc(bp, vnic); 242 if (rc) 243 goto err_out; 244 245 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 246 vnic_id, vnic, vnic->fw_grp_ids); 247 248 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 249 if (rc) 250 goto err_out; 251 252 /* Alloc RSS context only if RSS mode is enabled */ 253 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 254 int j, nr_ctxs = bnxt_rss_ctxts(bp); 255 256 rc = 0; 257 for (j = 0; j < nr_ctxs; j++) { 258 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 259 if (rc) 260 break; 261 } 262 if (rc) { 263 PMD_DRV_LOG(ERR, 264 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 265 vnic_id, j, rc); 266 goto err_out; 267 } 268 vnic->num_lb_ctxts = nr_ctxs; 269 } 270 271 /* 272 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 273 * setting is not available at this time, it will not be 274 * configured correctly in the CFA. 275 */ 276 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 277 vnic->vlan_strip = true; 278 else 279 vnic->vlan_strip = false; 280 281 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 282 if (rc) 283 goto err_out; 284 285 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 286 if (rc) 287 goto err_out; 288 289 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 290 rxq = bp->eth_dev->data->rx_queues[j]; 291 292 PMD_DRV_LOG(DEBUG, 293 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 294 j, rxq->vnic, rxq->vnic->fw_grp_ids); 295 296 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 297 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 298 else 299 vnic->rx_queue_cnt++; 300 } 301 302 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 303 304 rc = bnxt_vnic_rss_configure(bp, vnic); 305 if (rc) 306 goto err_out; 307 308 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 309 310 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) 311 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 312 else 313 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 314 315 return 0; 316 err_out: 317 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 318 vnic_id, rc); 319 return rc; 320 } 321 322 static int bnxt_init_chip(struct bnxt *bp) 323 { 324 struct rte_eth_link new; 325 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 326 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 327 uint32_t intr_vector = 0; 328 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 329 uint32_t vec = BNXT_MISC_VEC_ID; 330 unsigned int i, j; 331 int rc; 332 333 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 334 bp->eth_dev->data->dev_conf.rxmode.offloads |= 335 DEV_RX_OFFLOAD_JUMBO_FRAME; 336 bp->flags |= BNXT_FLAG_JUMBO; 337 } else { 338 bp->eth_dev->data->dev_conf.rxmode.offloads &= 339 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 340 bp->flags &= ~BNXT_FLAG_JUMBO; 341 } 342 343 /* THOR does not support ring groups. 344 * But we will use the array to save RSS context IDs. 345 */ 346 if (BNXT_CHIP_THOR(bp)) 347 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR; 348 349 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 350 if (rc) { 351 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 352 goto err_out; 353 } 354 355 rc = bnxt_alloc_hwrm_rings(bp); 356 if (rc) { 357 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 358 goto err_out; 359 } 360 361 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 362 if (rc) { 363 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 364 goto err_out; 365 } 366 367 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 368 goto skip_cosq_cfg; 369 370 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 371 if (bp->rx_cos_queue[i].id != 0xff) { 372 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 373 374 if (!vnic) { 375 PMD_DRV_LOG(ERR, 376 "Num pools more than FW profile\n"); 377 rc = -EINVAL; 378 goto err_out; 379 } 380 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 381 bp->rx_cosq_cnt++; 382 } 383 } 384 385 skip_cosq_cfg: 386 rc = bnxt_mq_rx_configure(bp); 387 if (rc) { 388 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 389 goto err_out; 390 } 391 392 /* VNIC configuration */ 393 for (i = 0; i < bp->nr_vnics; i++) { 394 rc = bnxt_setup_one_vnic(bp, i); 395 if (rc) 396 goto err_out; 397 } 398 399 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 400 if (rc) { 401 PMD_DRV_LOG(ERR, 402 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 403 goto err_out; 404 } 405 406 /* check and configure queue intr-vector mapping */ 407 if ((rte_intr_cap_multiple(intr_handle) || 408 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 409 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 410 intr_vector = bp->eth_dev->data->nb_rx_queues; 411 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 412 if (intr_vector > bp->rx_cp_nr_rings) { 413 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 414 bp->rx_cp_nr_rings); 415 return -ENOTSUP; 416 } 417 rc = rte_intr_efd_enable(intr_handle, intr_vector); 418 if (rc) 419 return rc; 420 } 421 422 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 423 intr_handle->intr_vec = 424 rte_zmalloc("intr_vec", 425 bp->eth_dev->data->nb_rx_queues * 426 sizeof(int), 0); 427 if (intr_handle->intr_vec == NULL) { 428 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 429 " intr_vec", bp->eth_dev->data->nb_rx_queues); 430 rc = -ENOMEM; 431 goto err_disable; 432 } 433 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 434 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 435 intr_handle->intr_vec, intr_handle->nb_efd, 436 intr_handle->max_intr); 437 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 438 queue_id++) { 439 intr_handle->intr_vec[queue_id] = 440 vec + BNXT_RX_VEC_START; 441 if (vec < base + intr_handle->nb_efd - 1) 442 vec++; 443 } 444 } 445 446 /* enable uio/vfio intr/eventfd mapping */ 447 rc = rte_intr_enable(intr_handle); 448 #ifndef RTE_EXEC_ENV_FREEBSD 449 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 450 if (rc) 451 goto err_free; 452 #endif 453 454 rc = bnxt_get_hwrm_link_config(bp, &new); 455 if (rc) { 456 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc); 457 goto err_free; 458 } 459 460 if (!bp->link_info.link_up) { 461 rc = bnxt_set_hwrm_link_config(bp, true); 462 if (rc) { 463 PMD_DRV_LOG(ERR, 464 "HWRM link config failure rc: %x\n", rc); 465 goto err_free; 466 } 467 } 468 bnxt_print_link_info(bp->eth_dev); 469 470 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 471 if (!bp->mark_table) 472 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 473 474 return 0; 475 476 err_free: 477 rte_free(intr_handle->intr_vec); 478 err_disable: 479 rte_intr_efd_disable(intr_handle); 480 err_out: 481 /* Some of the error status returned by FW may not be from errno.h */ 482 if (rc > 0) 483 rc = -EIO; 484 485 return rc; 486 } 487 488 static int bnxt_shutdown_nic(struct bnxt *bp) 489 { 490 bnxt_free_all_hwrm_resources(bp); 491 bnxt_free_all_filters(bp); 492 bnxt_free_all_vnics(bp); 493 return 0; 494 } 495 496 /* 497 * Device configuration and status function 498 */ 499 500 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 501 struct rte_eth_dev_info *dev_info) 502 { 503 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 504 struct bnxt *bp = eth_dev->data->dev_private; 505 uint16_t max_vnics, i, j, vpool, vrxq; 506 unsigned int max_rx_rings; 507 int rc; 508 509 rc = is_bnxt_in_error(bp); 510 if (rc) 511 return rc; 512 513 /* MAC Specifics */ 514 dev_info->max_mac_addrs = bp->max_l2_ctx; 515 dev_info->max_hash_mac_addrs = 0; 516 517 /* PF/VF specifics */ 518 if (BNXT_PF(bp)) 519 dev_info->max_vfs = pdev->max_vfs; 520 521 max_rx_rings = BNXT_MAX_RINGS(bp); 522 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 523 dev_info->max_rx_queues = max_rx_rings; 524 dev_info->max_tx_queues = max_rx_rings; 525 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 526 dev_info->hash_key_size = 40; 527 max_vnics = bp->max_vnics; 528 529 /* MTU specifics */ 530 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 531 dev_info->max_mtu = BNXT_MAX_MTU; 532 533 /* Fast path specifics */ 534 dev_info->min_rx_bufsize = 1; 535 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 536 537 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 538 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 539 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 540 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT; 541 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 542 543 /* *INDENT-OFF* */ 544 dev_info->default_rxconf = (struct rte_eth_rxconf) { 545 .rx_thresh = { 546 .pthresh = 8, 547 .hthresh = 8, 548 .wthresh = 0, 549 }, 550 .rx_free_thresh = 32, 551 /* If no descriptors available, pkts are dropped by default */ 552 .rx_drop_en = 1, 553 }; 554 555 dev_info->default_txconf = (struct rte_eth_txconf) { 556 .tx_thresh = { 557 .pthresh = 32, 558 .hthresh = 0, 559 .wthresh = 0, 560 }, 561 .tx_free_thresh = 32, 562 .tx_rs_thresh = 32, 563 }; 564 eth_dev->data->dev_conf.intr_conf.lsc = 1; 565 566 eth_dev->data->dev_conf.intr_conf.rxq = 1; 567 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 568 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 569 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 570 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 571 572 /* *INDENT-ON* */ 573 574 /* 575 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 576 * need further investigation. 577 */ 578 579 /* VMDq resources */ 580 vpool = 64; /* ETH_64_POOLS */ 581 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 582 for (i = 0; i < 4; vpool >>= 1, i++) { 583 if (max_vnics > vpool) { 584 for (j = 0; j < 5; vrxq >>= 1, j++) { 585 if (dev_info->max_rx_queues > vrxq) { 586 if (vpool > vrxq) 587 vpool = vrxq; 588 goto found; 589 } 590 } 591 /* Not enough resources to support VMDq */ 592 break; 593 } 594 } 595 /* Not enough resources to support VMDq */ 596 vpool = 0; 597 vrxq = 0; 598 found: 599 dev_info->max_vmdq_pools = vpool; 600 dev_info->vmdq_queue_num = vrxq; 601 602 dev_info->vmdq_pool_base = 0; 603 dev_info->vmdq_queue_base = 0; 604 605 return 0; 606 } 607 608 /* Configure the device based on the configuration provided */ 609 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 610 { 611 struct bnxt *bp = eth_dev->data->dev_private; 612 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 613 int rc; 614 615 bp->rx_queues = (void *)eth_dev->data->rx_queues; 616 bp->tx_queues = (void *)eth_dev->data->tx_queues; 617 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 618 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 619 620 rc = is_bnxt_in_error(bp); 621 if (rc) 622 return rc; 623 624 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 625 rc = bnxt_hwrm_check_vf_rings(bp); 626 if (rc) { 627 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 628 return -ENOSPC; 629 } 630 631 /* If a resource has already been allocated - in this case 632 * it is the async completion ring, free it. Reallocate it after 633 * resource reservation. This will ensure the resource counts 634 * are calculated correctly. 635 */ 636 637 pthread_mutex_lock(&bp->def_cp_lock); 638 639 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 640 bnxt_disable_int(bp); 641 bnxt_free_cp_ring(bp, bp->async_cp_ring); 642 } 643 644 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 645 if (rc) { 646 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 647 pthread_mutex_unlock(&bp->def_cp_lock); 648 return -ENOSPC; 649 } 650 651 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 652 rc = bnxt_alloc_async_cp_ring(bp); 653 if (rc) { 654 pthread_mutex_unlock(&bp->def_cp_lock); 655 return rc; 656 } 657 bnxt_enable_int(bp); 658 } 659 660 pthread_mutex_unlock(&bp->def_cp_lock); 661 } else { 662 /* legacy driver needs to get updated values */ 663 rc = bnxt_hwrm_func_qcaps(bp); 664 if (rc) { 665 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc); 666 return rc; 667 } 668 } 669 670 /* Inherit new configurations */ 671 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 672 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 673 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 674 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 675 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 676 bp->max_stat_ctx) 677 goto resource_error; 678 679 if (BNXT_HAS_RING_GRPS(bp) && 680 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 681 goto resource_error; 682 683 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 684 bp->max_vnics < eth_dev->data->nb_rx_queues) 685 goto resource_error; 686 687 bp->rx_cp_nr_rings = bp->rx_nr_rings; 688 bp->tx_cp_nr_rings = bp->tx_nr_rings; 689 690 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 691 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; 692 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 693 694 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 695 eth_dev->data->mtu = 696 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 697 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 698 BNXT_NUM_VLANS; 699 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 700 } 701 return 0; 702 703 resource_error: 704 PMD_DRV_LOG(ERR, 705 "Insufficient resources to support requested config\n"); 706 PMD_DRV_LOG(ERR, 707 "Num Queues Requested: Tx %d, Rx %d\n", 708 eth_dev->data->nb_tx_queues, 709 eth_dev->data->nb_rx_queues); 710 PMD_DRV_LOG(ERR, 711 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 712 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 713 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 714 return -ENOSPC; 715 } 716 717 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 718 { 719 struct rte_eth_link *link = ð_dev->data->dev_link; 720 721 if (link->link_status) 722 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 723 eth_dev->data->port_id, 724 (uint32_t)link->link_speed, 725 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 726 ("full-duplex") : ("half-duplex\n")); 727 else 728 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 729 eth_dev->data->port_id); 730 } 731 732 /* 733 * Determine whether the current configuration requires support for scattered 734 * receive; return 1 if scattered receive is required and 0 if not. 735 */ 736 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 737 { 738 uint16_t buf_size; 739 int i; 740 741 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 742 return 1; 743 744 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 745 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 746 747 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 748 RTE_PKTMBUF_HEADROOM); 749 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 750 return 1; 751 } 752 return 0; 753 } 754 755 static eth_rx_burst_t 756 bnxt_receive_function(struct rte_eth_dev *eth_dev) 757 { 758 struct bnxt *bp = eth_dev->data->dev_private; 759 760 #ifdef RTE_ARCH_X86 761 #ifndef RTE_LIBRTE_IEEE1588 762 /* 763 * Vector mode receive can be enabled only if scatter rx is not 764 * in use and rx offloads are limited to VLAN stripping and 765 * CRC stripping. 766 */ 767 if (!eth_dev->data->scattered_rx && 768 !(eth_dev->data->dev_conf.rxmode.offloads & 769 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 770 DEV_RX_OFFLOAD_KEEP_CRC | 771 DEV_RX_OFFLOAD_JUMBO_FRAME | 772 DEV_RX_OFFLOAD_IPV4_CKSUM | 773 DEV_RX_OFFLOAD_UDP_CKSUM | 774 DEV_RX_OFFLOAD_TCP_CKSUM | 775 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 776 DEV_RX_OFFLOAD_RSS_HASH | 777 DEV_RX_OFFLOAD_VLAN_FILTER))) { 778 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 779 eth_dev->data->port_id); 780 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 781 return bnxt_recv_pkts_vec; 782 } 783 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 784 eth_dev->data->port_id); 785 PMD_DRV_LOG(INFO, 786 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 787 eth_dev->data->port_id, 788 eth_dev->data->scattered_rx, 789 eth_dev->data->dev_conf.rxmode.offloads); 790 #endif 791 #endif 792 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 793 return bnxt_recv_pkts; 794 } 795 796 static eth_tx_burst_t 797 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) 798 { 799 #ifdef RTE_ARCH_X86 800 #ifndef RTE_LIBRTE_IEEE1588 801 /* 802 * Vector mode transmit can be enabled only if not using scatter rx 803 * or tx offloads. 804 */ 805 if (!eth_dev->data->scattered_rx && 806 !eth_dev->data->dev_conf.txmode.offloads) { 807 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 808 eth_dev->data->port_id); 809 return bnxt_xmit_pkts_vec; 810 } 811 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 812 eth_dev->data->port_id); 813 PMD_DRV_LOG(INFO, 814 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 815 eth_dev->data->port_id, 816 eth_dev->data->scattered_rx, 817 eth_dev->data->dev_conf.txmode.offloads); 818 #endif 819 #endif 820 return bnxt_xmit_pkts; 821 } 822 823 static int bnxt_handle_if_change_status(struct bnxt *bp) 824 { 825 int rc; 826 827 /* Since fw has undergone a reset and lost all contexts, 828 * set fatal flag to not issue hwrm during cleanup 829 */ 830 bp->flags |= BNXT_FLAG_FATAL_ERROR; 831 bnxt_uninit_resources(bp, true); 832 833 /* clear fatal flag so that re-init happens */ 834 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 835 rc = bnxt_init_resources(bp, true); 836 837 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 838 839 return rc; 840 } 841 842 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 843 { 844 struct bnxt *bp = eth_dev->data->dev_private; 845 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 846 int vlan_mask = 0; 847 int rc; 848 849 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 850 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 851 return -EINVAL; 852 } 853 854 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) { 855 PMD_DRV_LOG(ERR, 856 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 857 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 858 } 859 860 rc = bnxt_hwrm_if_change(bp, 1); 861 if (!rc) { 862 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 863 rc = bnxt_handle_if_change_status(bp); 864 if (rc) 865 return rc; 866 } 867 } 868 bnxt_enable_int(bp); 869 870 rc = bnxt_init_chip(bp); 871 if (rc) 872 goto error; 873 874 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 875 eth_dev->data->dev_started = 1; 876 877 bnxt_link_update(eth_dev, 1, ETH_LINK_UP); 878 879 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 880 vlan_mask |= ETH_VLAN_FILTER_MASK; 881 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 882 vlan_mask |= ETH_VLAN_STRIP_MASK; 883 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 884 if (rc) 885 goto error; 886 887 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 888 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 889 890 pthread_mutex_lock(&bp->def_cp_lock); 891 bnxt_schedule_fw_health_check(bp); 892 pthread_mutex_unlock(&bp->def_cp_lock); 893 return 0; 894 895 error: 896 bnxt_hwrm_if_change(bp, 0); 897 bnxt_shutdown_nic(bp); 898 bnxt_free_tx_mbufs(bp); 899 bnxt_free_rx_mbufs(bp); 900 eth_dev->data->dev_started = 0; 901 return rc; 902 } 903 904 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 905 { 906 struct bnxt *bp = eth_dev->data->dev_private; 907 int rc = 0; 908 909 if (!bp->link_info.link_up) 910 rc = bnxt_set_hwrm_link_config(bp, true); 911 if (!rc) 912 eth_dev->data->dev_link.link_status = 1; 913 914 bnxt_print_link_info(eth_dev); 915 return rc; 916 } 917 918 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 919 { 920 struct bnxt *bp = eth_dev->data->dev_private; 921 922 eth_dev->data->dev_link.link_status = 0; 923 bnxt_set_hwrm_link_config(bp, false); 924 bp->link_info.link_up = 0; 925 926 return 0; 927 } 928 929 /* Unload the driver, release resources */ 930 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 931 { 932 struct bnxt *bp = eth_dev->data->dev_private; 933 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 934 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 935 936 eth_dev->data->dev_started = 0; 937 /* Prevent crashes when queues are still in use */ 938 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 939 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 940 941 bnxt_disable_int(bp); 942 943 /* disable uio/vfio intr/eventfd mapping */ 944 rte_intr_disable(intr_handle); 945 946 bnxt_cancel_fw_health_check(bp); 947 948 bnxt_dev_set_link_down_op(eth_dev); 949 950 /* Wait for link to be reset and the async notification to process. 951 * During reset recovery, there is no need to wait 952 */ 953 if (!is_bnxt_in_error(bp)) 954 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN); 955 956 /* Clean queue intr-vector mapping */ 957 rte_intr_efd_disable(intr_handle); 958 if (intr_handle->intr_vec != NULL) { 959 rte_free(intr_handle->intr_vec); 960 intr_handle->intr_vec = NULL; 961 } 962 963 bnxt_hwrm_port_clr_stats(bp); 964 bnxt_free_tx_mbufs(bp); 965 bnxt_free_rx_mbufs(bp); 966 /* Process any remaining notifications in default completion queue */ 967 bnxt_int_handler(eth_dev); 968 bnxt_shutdown_nic(bp); 969 bnxt_hwrm_if_change(bp, 0); 970 971 rte_free(bp->mark_table); 972 bp->mark_table = NULL; 973 974 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 975 bp->rx_cosq_cnt = 0; 976 } 977 978 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 979 { 980 struct bnxt *bp = eth_dev->data->dev_private; 981 982 if (eth_dev->data->dev_started) 983 bnxt_dev_stop_op(eth_dev); 984 985 bnxt_uninit_resources(bp, false); 986 987 eth_dev->dev_ops = NULL; 988 eth_dev->rx_pkt_burst = NULL; 989 eth_dev->tx_pkt_burst = NULL; 990 991 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 992 bp->tx_mem_zone = NULL; 993 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 994 bp->rx_mem_zone = NULL; 995 996 rte_free(bp->pf.vf_info); 997 bp->pf.vf_info = NULL; 998 999 rte_free(bp->grp_info); 1000 bp->grp_info = NULL; 1001 } 1002 1003 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1004 uint32_t index) 1005 { 1006 struct bnxt *bp = eth_dev->data->dev_private; 1007 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1008 struct bnxt_vnic_info *vnic; 1009 struct bnxt_filter_info *filter, *temp_filter; 1010 uint32_t i; 1011 1012 if (is_bnxt_in_error(bp)) 1013 return; 1014 1015 /* 1016 * Loop through all VNICs from the specified filter flow pools to 1017 * remove the corresponding MAC addr filter 1018 */ 1019 for (i = 0; i < bp->nr_vnics; i++) { 1020 if (!(pool_mask & (1ULL << i))) 1021 continue; 1022 1023 vnic = &bp->vnic_info[i]; 1024 filter = STAILQ_FIRST(&vnic->filter); 1025 while (filter) { 1026 temp_filter = STAILQ_NEXT(filter, next); 1027 if (filter->mac_index == index) { 1028 STAILQ_REMOVE(&vnic->filter, filter, 1029 bnxt_filter_info, next); 1030 bnxt_hwrm_clear_l2_filter(bp, filter); 1031 bnxt_free_filter(bp, filter); 1032 } 1033 filter = temp_filter; 1034 } 1035 } 1036 } 1037 1038 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1039 struct rte_ether_addr *mac_addr, uint32_t index, 1040 uint32_t pool) 1041 { 1042 struct bnxt_filter_info *filter; 1043 int rc = 0; 1044 1045 /* Attach requested MAC address to the new l2_filter */ 1046 STAILQ_FOREACH(filter, &vnic->filter, next) { 1047 if (filter->mac_index == index) { 1048 PMD_DRV_LOG(DEBUG, 1049 "MAC addr already existed for pool %d\n", 1050 pool); 1051 return 0; 1052 } 1053 } 1054 1055 filter = bnxt_alloc_filter(bp); 1056 if (!filter) { 1057 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1058 return -ENODEV; 1059 } 1060 1061 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1062 * if the MAC that's been programmed now is a different one, then, 1063 * copy that addr to filter->l2_addr 1064 */ 1065 if (mac_addr) 1066 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1067 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1068 1069 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1070 if (!rc) { 1071 filter->mac_index = index; 1072 if (filter->mac_index == 0) 1073 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1074 else 1075 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1076 } else { 1077 bnxt_free_filter(bp, filter); 1078 } 1079 1080 return rc; 1081 } 1082 1083 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1084 struct rte_ether_addr *mac_addr, 1085 uint32_t index, uint32_t pool) 1086 { 1087 struct bnxt *bp = eth_dev->data->dev_private; 1088 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1089 int rc = 0; 1090 1091 rc = is_bnxt_in_error(bp); 1092 if (rc) 1093 return rc; 1094 1095 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) { 1096 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1097 return -ENOTSUP; 1098 } 1099 1100 if (!vnic) { 1101 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1102 return -EINVAL; 1103 } 1104 1105 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1106 1107 return rc; 1108 } 1109 1110 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete, 1111 bool exp_link_status) 1112 { 1113 int rc = 0; 1114 struct bnxt *bp = eth_dev->data->dev_private; 1115 struct rte_eth_link new; 1116 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT : 1117 BNXT_LINK_DOWN_WAIT_CNT; 1118 1119 rc = is_bnxt_in_error(bp); 1120 if (rc) 1121 return rc; 1122 1123 memset(&new, 0, sizeof(new)); 1124 do { 1125 /* Retrieve link info from hardware */ 1126 rc = bnxt_get_hwrm_link_config(bp, &new); 1127 if (rc) { 1128 new.link_speed = ETH_LINK_SPEED_100M; 1129 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1130 PMD_DRV_LOG(ERR, 1131 "Failed to retrieve link rc = 0x%x!\n", rc); 1132 goto out; 1133 } 1134 1135 if (!wait_to_complete || new.link_status == exp_link_status) 1136 break; 1137 1138 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1139 } while (cnt--); 1140 1141 out: 1142 /* Timed out or success */ 1143 if (new.link_status != eth_dev->data->dev_link.link_status || 1144 new.link_speed != eth_dev->data->dev_link.link_speed) { 1145 rte_eth_linkstatus_set(eth_dev, &new); 1146 1147 _rte_eth_dev_callback_process(eth_dev, 1148 RTE_ETH_EVENT_INTR_LSC, 1149 NULL); 1150 1151 bnxt_print_link_info(eth_dev); 1152 } 1153 1154 return rc; 1155 } 1156 1157 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev, 1158 int wait_to_complete) 1159 { 1160 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP); 1161 } 1162 1163 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1164 { 1165 struct bnxt *bp = eth_dev->data->dev_private; 1166 struct bnxt_vnic_info *vnic; 1167 uint32_t old_flags; 1168 int rc; 1169 1170 rc = is_bnxt_in_error(bp); 1171 if (rc) 1172 return rc; 1173 1174 /* Filter settings will get applied when port is started */ 1175 if (!eth_dev->data->dev_started) 1176 return 0; 1177 1178 if (bp->vnic_info == NULL) 1179 return 0; 1180 1181 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1182 1183 old_flags = vnic->flags; 1184 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1185 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1186 if (rc != 0) 1187 vnic->flags = old_flags; 1188 1189 return rc; 1190 } 1191 1192 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1193 { 1194 struct bnxt *bp = eth_dev->data->dev_private; 1195 struct bnxt_vnic_info *vnic; 1196 uint32_t old_flags; 1197 int rc; 1198 1199 rc = is_bnxt_in_error(bp); 1200 if (rc) 1201 return rc; 1202 1203 /* Filter settings will get applied when port is started */ 1204 if (!eth_dev->data->dev_started) 1205 return 0; 1206 1207 if (bp->vnic_info == NULL) 1208 return 0; 1209 1210 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1211 1212 old_flags = vnic->flags; 1213 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1214 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1215 if (rc != 0) 1216 vnic->flags = old_flags; 1217 1218 return rc; 1219 } 1220 1221 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1222 { 1223 struct bnxt *bp = eth_dev->data->dev_private; 1224 struct bnxt_vnic_info *vnic; 1225 uint32_t old_flags; 1226 int rc; 1227 1228 rc = is_bnxt_in_error(bp); 1229 if (rc) 1230 return rc; 1231 1232 /* Filter settings will get applied when port is started */ 1233 if (!eth_dev->data->dev_started) 1234 return 0; 1235 1236 if (bp->vnic_info == NULL) 1237 return 0; 1238 1239 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1240 1241 old_flags = vnic->flags; 1242 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1243 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1244 if (rc != 0) 1245 vnic->flags = old_flags; 1246 1247 return rc; 1248 } 1249 1250 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1251 { 1252 struct bnxt *bp = eth_dev->data->dev_private; 1253 struct bnxt_vnic_info *vnic; 1254 uint32_t old_flags; 1255 int rc; 1256 1257 rc = is_bnxt_in_error(bp); 1258 if (rc) 1259 return rc; 1260 1261 /* Filter settings will get applied when port is started */ 1262 if (!eth_dev->data->dev_started) 1263 return 0; 1264 1265 if (bp->vnic_info == NULL) 1266 return 0; 1267 1268 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1269 1270 old_flags = vnic->flags; 1271 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1272 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1273 if (rc != 0) 1274 vnic->flags = old_flags; 1275 1276 return rc; 1277 } 1278 1279 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1280 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1281 { 1282 if (qid >= bp->rx_nr_rings) 1283 return NULL; 1284 1285 return bp->eth_dev->data->rx_queues[qid]; 1286 } 1287 1288 /* Return rxq corresponding to a given rss table ring/group ID. */ 1289 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1290 { 1291 struct bnxt_rx_queue *rxq; 1292 unsigned int i; 1293 1294 if (!BNXT_HAS_RING_GRPS(bp)) { 1295 for (i = 0; i < bp->rx_nr_rings; i++) { 1296 rxq = bp->eth_dev->data->rx_queues[i]; 1297 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1298 return rxq->index; 1299 } 1300 } else { 1301 for (i = 0; i < bp->rx_nr_rings; i++) { 1302 if (bp->grp_info[i].fw_grp_id == fwr) 1303 return i; 1304 } 1305 } 1306 1307 return INVALID_HW_RING_ID; 1308 } 1309 1310 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1311 struct rte_eth_rss_reta_entry64 *reta_conf, 1312 uint16_t reta_size) 1313 { 1314 struct bnxt *bp = eth_dev->data->dev_private; 1315 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1316 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1317 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1318 uint16_t idx, sft; 1319 int i, rc; 1320 1321 rc = is_bnxt_in_error(bp); 1322 if (rc) 1323 return rc; 1324 1325 if (!vnic->rss_table) 1326 return -EINVAL; 1327 1328 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1329 return -EINVAL; 1330 1331 if (reta_size != tbl_size) { 1332 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1333 "(%d) must equal the size supported by the hardware " 1334 "(%d)\n", reta_size, tbl_size); 1335 return -EINVAL; 1336 } 1337 1338 for (i = 0; i < reta_size; i++) { 1339 struct bnxt_rx_queue *rxq; 1340 1341 idx = i / RTE_RETA_GROUP_SIZE; 1342 sft = i % RTE_RETA_GROUP_SIZE; 1343 1344 if (!(reta_conf[idx].mask & (1ULL << sft))) 1345 continue; 1346 1347 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1348 if (!rxq) { 1349 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1350 return -EINVAL; 1351 } 1352 1353 if (BNXT_CHIP_THOR(bp)) { 1354 vnic->rss_table[i * 2] = 1355 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1356 vnic->rss_table[i * 2 + 1] = 1357 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1358 } else { 1359 vnic->rss_table[i] = 1360 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1361 } 1362 } 1363 1364 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1365 return 0; 1366 } 1367 1368 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1369 struct rte_eth_rss_reta_entry64 *reta_conf, 1370 uint16_t reta_size) 1371 { 1372 struct bnxt *bp = eth_dev->data->dev_private; 1373 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1374 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1375 uint16_t idx, sft, i; 1376 int rc; 1377 1378 rc = is_bnxt_in_error(bp); 1379 if (rc) 1380 return rc; 1381 1382 /* Retrieve from the default VNIC */ 1383 if (!vnic) 1384 return -EINVAL; 1385 if (!vnic->rss_table) 1386 return -EINVAL; 1387 1388 if (reta_size != tbl_size) { 1389 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1390 "(%d) must equal the size supported by the hardware " 1391 "(%d)\n", reta_size, tbl_size); 1392 return -EINVAL; 1393 } 1394 1395 for (idx = 0, i = 0; i < reta_size; i++) { 1396 idx = i / RTE_RETA_GROUP_SIZE; 1397 sft = i % RTE_RETA_GROUP_SIZE; 1398 1399 if (reta_conf[idx].mask & (1ULL << sft)) { 1400 uint16_t qid; 1401 1402 if (BNXT_CHIP_THOR(bp)) 1403 qid = bnxt_rss_to_qid(bp, 1404 vnic->rss_table[i * 2]); 1405 else 1406 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 1407 1408 if (qid == INVALID_HW_RING_ID) { 1409 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 1410 return -EINVAL; 1411 } 1412 reta_conf[idx].reta[sft] = qid; 1413 } 1414 } 1415 1416 return 0; 1417 } 1418 1419 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 1420 struct rte_eth_rss_conf *rss_conf) 1421 { 1422 struct bnxt *bp = eth_dev->data->dev_private; 1423 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1424 struct bnxt_vnic_info *vnic; 1425 int rc; 1426 1427 rc = is_bnxt_in_error(bp); 1428 if (rc) 1429 return rc; 1430 1431 /* 1432 * If RSS enablement were different than dev_configure, 1433 * then return -EINVAL 1434 */ 1435 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 1436 if (!rss_conf->rss_hf) 1437 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 1438 } else { 1439 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 1440 return -EINVAL; 1441 } 1442 1443 bp->flags |= BNXT_FLAG_UPDATE_HASH; 1444 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf)); 1445 1446 /* Update the default RSS VNIC(s) */ 1447 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1448 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 1449 1450 /* 1451 * If hashkey is not specified, use the previously configured 1452 * hashkey 1453 */ 1454 if (!rss_conf->rss_key) 1455 goto rss_config; 1456 1457 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 1458 PMD_DRV_LOG(ERR, 1459 "Invalid hashkey length, should be 16 bytes\n"); 1460 return -EINVAL; 1461 } 1462 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 1463 1464 rss_config: 1465 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1466 return 0; 1467 } 1468 1469 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 1470 struct rte_eth_rss_conf *rss_conf) 1471 { 1472 struct bnxt *bp = eth_dev->data->dev_private; 1473 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1474 int len, rc; 1475 uint32_t hash_types; 1476 1477 rc = is_bnxt_in_error(bp); 1478 if (rc) 1479 return rc; 1480 1481 /* RSS configuration is the same for all VNICs */ 1482 if (vnic && vnic->rss_hash_key) { 1483 if (rss_conf->rss_key) { 1484 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 1485 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 1486 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 1487 } 1488 1489 hash_types = vnic->hash_type; 1490 rss_conf->rss_hf = 0; 1491 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 1492 rss_conf->rss_hf |= ETH_RSS_IPV4; 1493 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 1494 } 1495 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 1496 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 1497 hash_types &= 1498 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1499 } 1500 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 1501 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 1502 hash_types &= 1503 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1504 } 1505 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 1506 rss_conf->rss_hf |= ETH_RSS_IPV6; 1507 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1508 } 1509 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 1510 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 1511 hash_types &= 1512 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1513 } 1514 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 1515 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 1516 hash_types &= 1517 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1518 } 1519 if (hash_types) { 1520 PMD_DRV_LOG(ERR, 1521 "Unknwon RSS config from firmware (%08x), RSS disabled", 1522 vnic->hash_type); 1523 return -ENOTSUP; 1524 } 1525 } else { 1526 rss_conf->rss_hf = 0; 1527 } 1528 return 0; 1529 } 1530 1531 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 1532 struct rte_eth_fc_conf *fc_conf) 1533 { 1534 struct bnxt *bp = dev->data->dev_private; 1535 struct rte_eth_link link_info; 1536 int rc; 1537 1538 rc = is_bnxt_in_error(bp); 1539 if (rc) 1540 return rc; 1541 1542 rc = bnxt_get_hwrm_link_config(bp, &link_info); 1543 if (rc) 1544 return rc; 1545 1546 memset(fc_conf, 0, sizeof(*fc_conf)); 1547 if (bp->link_info.auto_pause) 1548 fc_conf->autoneg = 1; 1549 switch (bp->link_info.pause) { 1550 case 0: 1551 fc_conf->mode = RTE_FC_NONE; 1552 break; 1553 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 1554 fc_conf->mode = RTE_FC_TX_PAUSE; 1555 break; 1556 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 1557 fc_conf->mode = RTE_FC_RX_PAUSE; 1558 break; 1559 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 1560 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 1561 fc_conf->mode = RTE_FC_FULL; 1562 break; 1563 } 1564 return 0; 1565 } 1566 1567 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 1568 struct rte_eth_fc_conf *fc_conf) 1569 { 1570 struct bnxt *bp = dev->data->dev_private; 1571 int rc; 1572 1573 rc = is_bnxt_in_error(bp); 1574 if (rc) 1575 return rc; 1576 1577 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1578 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 1579 return -ENOTSUP; 1580 } 1581 1582 switch (fc_conf->mode) { 1583 case RTE_FC_NONE: 1584 bp->link_info.auto_pause = 0; 1585 bp->link_info.force_pause = 0; 1586 break; 1587 case RTE_FC_RX_PAUSE: 1588 if (fc_conf->autoneg) { 1589 bp->link_info.auto_pause = 1590 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1591 bp->link_info.force_pause = 0; 1592 } else { 1593 bp->link_info.auto_pause = 0; 1594 bp->link_info.force_pause = 1595 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1596 } 1597 break; 1598 case RTE_FC_TX_PAUSE: 1599 if (fc_conf->autoneg) { 1600 bp->link_info.auto_pause = 1601 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 1602 bp->link_info.force_pause = 0; 1603 } else { 1604 bp->link_info.auto_pause = 0; 1605 bp->link_info.force_pause = 1606 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 1607 } 1608 break; 1609 case RTE_FC_FULL: 1610 if (fc_conf->autoneg) { 1611 bp->link_info.auto_pause = 1612 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 1613 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1614 bp->link_info.force_pause = 0; 1615 } else { 1616 bp->link_info.auto_pause = 0; 1617 bp->link_info.force_pause = 1618 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 1619 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1620 } 1621 break; 1622 } 1623 return bnxt_set_hwrm_link_config(bp, true); 1624 } 1625 1626 /* Add UDP tunneling port */ 1627 static int 1628 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 1629 struct rte_eth_udp_tunnel *udp_tunnel) 1630 { 1631 struct bnxt *bp = eth_dev->data->dev_private; 1632 uint16_t tunnel_type = 0; 1633 int rc = 0; 1634 1635 rc = is_bnxt_in_error(bp); 1636 if (rc) 1637 return rc; 1638 1639 switch (udp_tunnel->prot_type) { 1640 case RTE_TUNNEL_TYPE_VXLAN: 1641 if (bp->vxlan_port_cnt) { 1642 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1643 udp_tunnel->udp_port); 1644 if (bp->vxlan_port != udp_tunnel->udp_port) { 1645 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1646 return -ENOSPC; 1647 } 1648 bp->vxlan_port_cnt++; 1649 return 0; 1650 } 1651 tunnel_type = 1652 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 1653 bp->vxlan_port_cnt++; 1654 break; 1655 case RTE_TUNNEL_TYPE_GENEVE: 1656 if (bp->geneve_port_cnt) { 1657 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1658 udp_tunnel->udp_port); 1659 if (bp->geneve_port != udp_tunnel->udp_port) { 1660 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1661 return -ENOSPC; 1662 } 1663 bp->geneve_port_cnt++; 1664 return 0; 1665 } 1666 tunnel_type = 1667 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 1668 bp->geneve_port_cnt++; 1669 break; 1670 default: 1671 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1672 return -ENOTSUP; 1673 } 1674 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 1675 tunnel_type); 1676 return rc; 1677 } 1678 1679 static int 1680 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 1681 struct rte_eth_udp_tunnel *udp_tunnel) 1682 { 1683 struct bnxt *bp = eth_dev->data->dev_private; 1684 uint16_t tunnel_type = 0; 1685 uint16_t port = 0; 1686 int rc = 0; 1687 1688 rc = is_bnxt_in_error(bp); 1689 if (rc) 1690 return rc; 1691 1692 switch (udp_tunnel->prot_type) { 1693 case RTE_TUNNEL_TYPE_VXLAN: 1694 if (!bp->vxlan_port_cnt) { 1695 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1696 return -EINVAL; 1697 } 1698 if (bp->vxlan_port != udp_tunnel->udp_port) { 1699 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1700 udp_tunnel->udp_port, bp->vxlan_port); 1701 return -EINVAL; 1702 } 1703 if (--bp->vxlan_port_cnt) 1704 return 0; 1705 1706 tunnel_type = 1707 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 1708 port = bp->vxlan_fw_dst_port_id; 1709 break; 1710 case RTE_TUNNEL_TYPE_GENEVE: 1711 if (!bp->geneve_port_cnt) { 1712 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1713 return -EINVAL; 1714 } 1715 if (bp->geneve_port != udp_tunnel->udp_port) { 1716 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1717 udp_tunnel->udp_port, bp->geneve_port); 1718 return -EINVAL; 1719 } 1720 if (--bp->geneve_port_cnt) 1721 return 0; 1722 1723 tunnel_type = 1724 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 1725 port = bp->geneve_fw_dst_port_id; 1726 break; 1727 default: 1728 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1729 return -ENOTSUP; 1730 } 1731 1732 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 1733 if (!rc) { 1734 if (tunnel_type == 1735 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) 1736 bp->vxlan_port = 0; 1737 if (tunnel_type == 1738 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) 1739 bp->geneve_port = 0; 1740 } 1741 return rc; 1742 } 1743 1744 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1745 { 1746 struct bnxt_filter_info *filter; 1747 struct bnxt_vnic_info *vnic; 1748 int rc = 0; 1749 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 1750 1751 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1752 filter = STAILQ_FIRST(&vnic->filter); 1753 while (filter) { 1754 /* Search for this matching MAC+VLAN filter */ 1755 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 1756 /* Delete the filter */ 1757 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 1758 if (rc) 1759 return rc; 1760 STAILQ_REMOVE(&vnic->filter, filter, 1761 bnxt_filter_info, next); 1762 bnxt_free_filter(bp, filter); 1763 PMD_DRV_LOG(INFO, 1764 "Deleted vlan filter for %d\n", 1765 vlan_id); 1766 return 0; 1767 } 1768 filter = STAILQ_NEXT(filter, next); 1769 } 1770 return -ENOENT; 1771 } 1772 1773 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1774 { 1775 struct bnxt_filter_info *filter; 1776 struct bnxt_vnic_info *vnic; 1777 int rc = 0; 1778 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 1779 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 1780 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 1781 1782 /* Implementation notes on the use of VNIC in this command: 1783 * 1784 * By default, these filters belong to default vnic for the function. 1785 * Once these filters are set up, only destination VNIC can be modified. 1786 * If the destination VNIC is not specified in this command, 1787 * then the HWRM shall only create an l2 context id. 1788 */ 1789 1790 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1791 filter = STAILQ_FIRST(&vnic->filter); 1792 /* Check if the VLAN has already been added */ 1793 while (filter) { 1794 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 1795 return -EEXIST; 1796 1797 filter = STAILQ_NEXT(filter, next); 1798 } 1799 1800 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 1801 * command to create MAC+VLAN filter with the right flags, enables set. 1802 */ 1803 filter = bnxt_alloc_filter(bp); 1804 if (!filter) { 1805 PMD_DRV_LOG(ERR, 1806 "MAC/VLAN filter alloc failed\n"); 1807 return -ENOMEM; 1808 } 1809 /* MAC + VLAN ID filter */ 1810 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 1811 * untagged packets are received 1812 * 1813 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 1814 * packets and only the programmed vlan's packets are received 1815 */ 1816 filter->l2_ivlan = vlan_id; 1817 filter->l2_ivlan_mask = 0x0FFF; 1818 filter->enables |= en; 1819 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1820 1821 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1822 if (rc) { 1823 /* Free the newly allocated filter as we were 1824 * not able to create the filter in hardware. 1825 */ 1826 bnxt_free_filter(bp, filter); 1827 return rc; 1828 } 1829 1830 filter->mac_index = 0; 1831 /* Add this new filter to the list */ 1832 if (vlan_id == 0) 1833 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1834 else 1835 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1836 1837 PMD_DRV_LOG(INFO, 1838 "Added Vlan filter for %d\n", vlan_id); 1839 return rc; 1840 } 1841 1842 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 1843 uint16_t vlan_id, int on) 1844 { 1845 struct bnxt *bp = eth_dev->data->dev_private; 1846 int rc; 1847 1848 rc = is_bnxt_in_error(bp); 1849 if (rc) 1850 return rc; 1851 1852 /* These operations apply to ALL existing MAC/VLAN filters */ 1853 if (on) 1854 return bnxt_add_vlan_filter(bp, vlan_id); 1855 else 1856 return bnxt_del_vlan_filter(bp, vlan_id); 1857 } 1858 1859 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 1860 struct bnxt_vnic_info *vnic) 1861 { 1862 struct bnxt_filter_info *filter; 1863 int rc; 1864 1865 filter = STAILQ_FIRST(&vnic->filter); 1866 while (filter) { 1867 if (filter->mac_index == 0 && 1868 !memcmp(filter->l2_addr, bp->mac_addr, 1869 RTE_ETHER_ADDR_LEN)) { 1870 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 1871 if (!rc) { 1872 STAILQ_REMOVE(&vnic->filter, filter, 1873 bnxt_filter_info, next); 1874 bnxt_free_filter(bp, filter); 1875 } 1876 return rc; 1877 } 1878 filter = STAILQ_NEXT(filter, next); 1879 } 1880 return 0; 1881 } 1882 1883 static int 1884 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 1885 { 1886 struct bnxt_vnic_info *vnic; 1887 unsigned int i; 1888 int rc; 1889 1890 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1891 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 1892 /* Remove any VLAN filters programmed */ 1893 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 1894 bnxt_del_vlan_filter(bp, i); 1895 1896 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 1897 if (rc) 1898 return rc; 1899 } else { 1900 /* Default filter will allow packets that match the 1901 * dest mac. So, it has to be deleted, otherwise, we 1902 * will endup receiving vlan packets for which the 1903 * filter is not programmed, when hw-vlan-filter 1904 * configuration is ON 1905 */ 1906 bnxt_del_dflt_mac_filter(bp, vnic); 1907 /* This filter will allow only untagged packets */ 1908 bnxt_add_vlan_filter(bp, 0); 1909 } 1910 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 1911 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 1912 1913 return 0; 1914 } 1915 1916 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 1917 { 1918 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 1919 unsigned int i; 1920 int rc; 1921 1922 /* Destroy vnic filters and vnic */ 1923 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 1924 DEV_RX_OFFLOAD_VLAN_FILTER) { 1925 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 1926 bnxt_del_vlan_filter(bp, i); 1927 } 1928 bnxt_del_dflt_mac_filter(bp, vnic); 1929 1930 rc = bnxt_hwrm_vnic_free(bp, vnic); 1931 if (rc) 1932 return rc; 1933 1934 rte_free(vnic->fw_grp_ids); 1935 vnic->fw_grp_ids = NULL; 1936 1937 return 0; 1938 } 1939 1940 static int 1941 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 1942 { 1943 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1944 int rc; 1945 1946 /* Destroy, recreate and reconfigure the default vnic */ 1947 rc = bnxt_free_one_vnic(bp, 0); 1948 if (rc) 1949 return rc; 1950 1951 /* default vnic 0 */ 1952 rc = bnxt_setup_one_vnic(bp, 0); 1953 if (rc) 1954 return rc; 1955 1956 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 1957 DEV_RX_OFFLOAD_VLAN_FILTER) { 1958 rc = bnxt_add_vlan_filter(bp, 0); 1959 if (rc) 1960 return rc; 1961 rc = bnxt_restore_vlan_filters(bp); 1962 if (rc) 1963 return rc; 1964 } else { 1965 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 1966 if (rc) 1967 return rc; 1968 } 1969 1970 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1971 if (rc) 1972 return rc; 1973 1974 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 1975 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 1976 1977 return rc; 1978 } 1979 1980 static int 1981 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 1982 { 1983 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1984 struct bnxt *bp = dev->data->dev_private; 1985 int rc; 1986 1987 rc = is_bnxt_in_error(bp); 1988 if (rc) 1989 return rc; 1990 1991 /* Filter settings will get applied when port is started */ 1992 if (!dev->data->dev_started) 1993 return 0; 1994 1995 if (mask & ETH_VLAN_FILTER_MASK) { 1996 /* Enable or disable VLAN filtering */ 1997 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 1998 if (rc) 1999 return rc; 2000 } 2001 2002 if (mask & ETH_VLAN_STRIP_MASK) { 2003 /* Enable or disable VLAN stripping */ 2004 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2005 if (rc) 2006 return rc; 2007 } 2008 2009 if (mask & ETH_VLAN_EXTEND_MASK) { 2010 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2011 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2012 else 2013 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2014 } 2015 2016 return 0; 2017 } 2018 2019 static int 2020 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2021 uint16_t tpid) 2022 { 2023 struct bnxt *bp = dev->data->dev_private; 2024 int qinq = dev->data->dev_conf.rxmode.offloads & 2025 DEV_RX_OFFLOAD_VLAN_EXTEND; 2026 2027 if (vlan_type != ETH_VLAN_TYPE_INNER && 2028 vlan_type != ETH_VLAN_TYPE_OUTER) { 2029 PMD_DRV_LOG(ERR, 2030 "Unsupported vlan type."); 2031 return -EINVAL; 2032 } 2033 if (!qinq) { 2034 PMD_DRV_LOG(ERR, 2035 "QinQ not enabled. Needs to be ON as we can " 2036 "accelerate only outer vlan\n"); 2037 return -EINVAL; 2038 } 2039 2040 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 2041 switch (tpid) { 2042 case RTE_ETHER_TYPE_QINQ: 2043 bp->outer_tpid_bd = 2044 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2045 break; 2046 case RTE_ETHER_TYPE_VLAN: 2047 bp->outer_tpid_bd = 2048 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2049 break; 2050 case 0x9100: 2051 bp->outer_tpid_bd = 2052 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2053 break; 2054 case 0x9200: 2055 bp->outer_tpid_bd = 2056 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2057 break; 2058 case 0x9300: 2059 bp->outer_tpid_bd = 2060 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2061 break; 2062 default: 2063 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2064 return -EINVAL; 2065 } 2066 bp->outer_tpid_bd |= tpid; 2067 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2068 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 2069 PMD_DRV_LOG(ERR, 2070 "Can accelerate only outer vlan in QinQ\n"); 2071 return -EINVAL; 2072 } 2073 2074 return 0; 2075 } 2076 2077 static int 2078 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2079 struct rte_ether_addr *addr) 2080 { 2081 struct bnxt *bp = dev->data->dev_private; 2082 /* Default Filter is tied to VNIC 0 */ 2083 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2084 int rc; 2085 2086 rc = is_bnxt_in_error(bp); 2087 if (rc) 2088 return rc; 2089 2090 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2091 return -EPERM; 2092 2093 if (rte_is_zero_ether_addr(addr)) 2094 return -EINVAL; 2095 2096 /* Check if the requested MAC is already added */ 2097 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2098 return 0; 2099 2100 /* Destroy filter and re-create it */ 2101 bnxt_del_dflt_mac_filter(bp, vnic); 2102 2103 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2104 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 2105 /* This filter will allow only untagged packets */ 2106 rc = bnxt_add_vlan_filter(bp, 0); 2107 } else { 2108 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2109 } 2110 2111 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2112 return rc; 2113 } 2114 2115 static int 2116 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2117 struct rte_ether_addr *mc_addr_set, 2118 uint32_t nb_mc_addr) 2119 { 2120 struct bnxt *bp = eth_dev->data->dev_private; 2121 char *mc_addr_list = (char *)mc_addr_set; 2122 struct bnxt_vnic_info *vnic; 2123 uint32_t off = 0, i = 0; 2124 int rc; 2125 2126 rc = is_bnxt_in_error(bp); 2127 if (rc) 2128 return rc; 2129 2130 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2131 2132 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2133 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2134 goto allmulti; 2135 } 2136 2137 /* TODO Check for Duplicate mcast addresses */ 2138 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2139 for (i = 0; i < nb_mc_addr; i++) { 2140 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2141 RTE_ETHER_ADDR_LEN); 2142 off += RTE_ETHER_ADDR_LEN; 2143 } 2144 2145 vnic->mc_addr_cnt = i; 2146 if (vnic->mc_addr_cnt) 2147 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2148 else 2149 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2150 2151 allmulti: 2152 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2153 } 2154 2155 static int 2156 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2157 { 2158 struct bnxt *bp = dev->data->dev_private; 2159 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2160 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2161 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2162 int ret; 2163 2164 ret = snprintf(fw_version, fw_size, "%d.%d.%d", 2165 fw_major, fw_minor, fw_updt); 2166 2167 ret += 1; /* add the size of '\0' */ 2168 if (fw_size < (uint32_t)ret) 2169 return ret; 2170 else 2171 return 0; 2172 } 2173 2174 static void 2175 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2176 struct rte_eth_rxq_info *qinfo) 2177 { 2178 struct bnxt *bp = dev->data->dev_private; 2179 struct bnxt_rx_queue *rxq; 2180 2181 if (is_bnxt_in_error(bp)) 2182 return; 2183 2184 rxq = dev->data->rx_queues[queue_id]; 2185 2186 qinfo->mp = rxq->mb_pool; 2187 qinfo->scattered_rx = dev->data->scattered_rx; 2188 qinfo->nb_desc = rxq->nb_rx_desc; 2189 2190 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2191 qinfo->conf.rx_drop_en = 0; 2192 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2193 } 2194 2195 static void 2196 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2197 struct rte_eth_txq_info *qinfo) 2198 { 2199 struct bnxt *bp = dev->data->dev_private; 2200 struct bnxt_tx_queue *txq; 2201 2202 if (is_bnxt_in_error(bp)) 2203 return; 2204 2205 txq = dev->data->tx_queues[queue_id]; 2206 2207 qinfo->nb_desc = txq->nb_tx_desc; 2208 2209 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2210 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2211 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2212 2213 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2214 qinfo->conf.tx_rs_thresh = 0; 2215 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2216 } 2217 2218 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 2219 { 2220 struct bnxt *bp = eth_dev->data->dev_private; 2221 uint32_t new_pkt_size; 2222 uint32_t rc = 0; 2223 uint32_t i; 2224 2225 rc = is_bnxt_in_error(bp); 2226 if (rc) 2227 return rc; 2228 2229 /* Exit if receive queues are not configured yet */ 2230 if (!eth_dev->data->nb_rx_queues) 2231 return rc; 2232 2233 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 2234 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 2235 2236 #ifdef RTE_ARCH_X86 2237 /* 2238 * If vector-mode tx/rx is active, disallow any MTU change that would 2239 * require scattered receive support. 2240 */ 2241 if (eth_dev->data->dev_started && 2242 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec || 2243 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) && 2244 (new_pkt_size > 2245 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 2246 PMD_DRV_LOG(ERR, 2247 "MTU change would require scattered rx support. "); 2248 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 2249 return -EINVAL; 2250 } 2251 #endif 2252 2253 if (new_mtu > RTE_ETHER_MTU) { 2254 bp->flags |= BNXT_FLAG_JUMBO; 2255 bp->eth_dev->data->dev_conf.rxmode.offloads |= 2256 DEV_RX_OFFLOAD_JUMBO_FRAME; 2257 } else { 2258 bp->eth_dev->data->dev_conf.rxmode.offloads &= 2259 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2260 bp->flags &= ~BNXT_FLAG_JUMBO; 2261 } 2262 2263 /* Is there a change in mtu setting? */ 2264 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) 2265 return rc; 2266 2267 for (i = 0; i < bp->nr_vnics; i++) { 2268 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2269 uint16_t size = 0; 2270 2271 vnic->mru = BNXT_VNIC_MRU(new_mtu); 2272 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 2273 if (rc) 2274 break; 2275 2276 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 2277 size -= RTE_PKTMBUF_HEADROOM; 2278 2279 if (size < new_mtu) { 2280 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 2281 if (rc) 2282 return rc; 2283 } 2284 } 2285 2286 if (!rc) 2287 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 2288 2289 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 2290 2291 return rc; 2292 } 2293 2294 static int 2295 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 2296 { 2297 struct bnxt *bp = dev->data->dev_private; 2298 uint16_t vlan = bp->vlan; 2299 int rc; 2300 2301 rc = is_bnxt_in_error(bp); 2302 if (rc) 2303 return rc; 2304 2305 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2306 PMD_DRV_LOG(ERR, 2307 "PVID cannot be modified for this function\n"); 2308 return -ENOTSUP; 2309 } 2310 bp->vlan = on ? pvid : 0; 2311 2312 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 2313 if (rc) 2314 bp->vlan = vlan; 2315 return rc; 2316 } 2317 2318 static int 2319 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 2320 { 2321 struct bnxt *bp = dev->data->dev_private; 2322 int rc; 2323 2324 rc = is_bnxt_in_error(bp); 2325 if (rc) 2326 return rc; 2327 2328 return bnxt_hwrm_port_led_cfg(bp, true); 2329 } 2330 2331 static int 2332 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 2333 { 2334 struct bnxt *bp = dev->data->dev_private; 2335 int rc; 2336 2337 rc = is_bnxt_in_error(bp); 2338 if (rc) 2339 return rc; 2340 2341 return bnxt_hwrm_port_led_cfg(bp, false); 2342 } 2343 2344 static uint32_t 2345 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 2346 { 2347 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2348 uint32_t desc = 0, raw_cons = 0, cons; 2349 struct bnxt_cp_ring_info *cpr; 2350 struct bnxt_rx_queue *rxq; 2351 struct rx_pkt_cmpl *rxcmp; 2352 int rc; 2353 2354 rc = is_bnxt_in_error(bp); 2355 if (rc) 2356 return rc; 2357 2358 rxq = dev->data->rx_queues[rx_queue_id]; 2359 cpr = rxq->cp_ring; 2360 raw_cons = cpr->cp_raw_cons; 2361 2362 while (1) { 2363 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 2364 rte_prefetch0(&cpr->cp_desc_ring[cons]); 2365 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2366 2367 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) { 2368 break; 2369 } else { 2370 raw_cons++; 2371 desc++; 2372 } 2373 } 2374 2375 return desc; 2376 } 2377 2378 static int 2379 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 2380 { 2381 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 2382 struct bnxt_rx_ring_info *rxr; 2383 struct bnxt_cp_ring_info *cpr; 2384 struct bnxt_sw_rx_bd *rx_buf; 2385 struct rx_pkt_cmpl *rxcmp; 2386 uint32_t cons, cp_cons; 2387 int rc; 2388 2389 if (!rxq) 2390 return -EINVAL; 2391 2392 rc = is_bnxt_in_error(rxq->bp); 2393 if (rc) 2394 return rc; 2395 2396 cpr = rxq->cp_ring; 2397 rxr = rxq->rx_ring; 2398 2399 if (offset >= rxq->nb_rx_desc) 2400 return -EINVAL; 2401 2402 cons = RING_CMP(cpr->cp_ring_struct, offset); 2403 cp_cons = cpr->cp_raw_cons; 2404 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2405 2406 if (cons > cp_cons) { 2407 if (CMPL_VALID(rxcmp, cpr->valid)) 2408 return RTE_ETH_RX_DESC_DONE; 2409 } else { 2410 if (CMPL_VALID(rxcmp, !cpr->valid)) 2411 return RTE_ETH_RX_DESC_DONE; 2412 } 2413 rx_buf = &rxr->rx_buf_ring[cons]; 2414 if (rx_buf->mbuf == NULL) 2415 return RTE_ETH_RX_DESC_UNAVAIL; 2416 2417 2418 return RTE_ETH_RX_DESC_AVAIL; 2419 } 2420 2421 static int 2422 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 2423 { 2424 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 2425 struct bnxt_tx_ring_info *txr; 2426 struct bnxt_cp_ring_info *cpr; 2427 struct bnxt_sw_tx_bd *tx_buf; 2428 struct tx_pkt_cmpl *txcmp; 2429 uint32_t cons, cp_cons; 2430 int rc; 2431 2432 if (!txq) 2433 return -EINVAL; 2434 2435 rc = is_bnxt_in_error(txq->bp); 2436 if (rc) 2437 return rc; 2438 2439 cpr = txq->cp_ring; 2440 txr = txq->tx_ring; 2441 2442 if (offset >= txq->nb_tx_desc) 2443 return -EINVAL; 2444 2445 cons = RING_CMP(cpr->cp_ring_struct, offset); 2446 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2447 cp_cons = cpr->cp_raw_cons; 2448 2449 if (cons > cp_cons) { 2450 if (CMPL_VALID(txcmp, cpr->valid)) 2451 return RTE_ETH_TX_DESC_UNAVAIL; 2452 } else { 2453 if (CMPL_VALID(txcmp, !cpr->valid)) 2454 return RTE_ETH_TX_DESC_UNAVAIL; 2455 } 2456 tx_buf = &txr->tx_buf_ring[cons]; 2457 if (tx_buf->mbuf == NULL) 2458 return RTE_ETH_TX_DESC_DONE; 2459 2460 return RTE_ETH_TX_DESC_FULL; 2461 } 2462 2463 static struct bnxt_filter_info * 2464 bnxt_match_and_validate_ether_filter(struct bnxt *bp, 2465 struct rte_eth_ethertype_filter *efilter, 2466 struct bnxt_vnic_info *vnic0, 2467 struct bnxt_vnic_info *vnic, 2468 int *ret) 2469 { 2470 struct bnxt_filter_info *mfilter = NULL; 2471 int match = 0; 2472 *ret = 0; 2473 2474 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 || 2475 efilter->ether_type == RTE_ETHER_TYPE_IPV6) { 2476 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in" 2477 " ethertype filter.", efilter->ether_type); 2478 *ret = -EINVAL; 2479 goto exit; 2480 } 2481 if (efilter->queue >= bp->rx_nr_rings) { 2482 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2483 *ret = -EINVAL; 2484 goto exit; 2485 } 2486 2487 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 2488 vnic = &bp->vnic_info[efilter->queue]; 2489 if (vnic == NULL) { 2490 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2491 *ret = -EINVAL; 2492 goto exit; 2493 } 2494 2495 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2496 STAILQ_FOREACH(mfilter, &vnic0->filter, next) { 2497 if ((!memcmp(efilter->mac_addr.addr_bytes, 2498 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2499 mfilter->flags == 2500 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP && 2501 mfilter->ethertype == efilter->ether_type)) { 2502 match = 1; 2503 break; 2504 } 2505 } 2506 } else { 2507 STAILQ_FOREACH(mfilter, &vnic->filter, next) 2508 if ((!memcmp(efilter->mac_addr.addr_bytes, 2509 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2510 mfilter->ethertype == efilter->ether_type && 2511 mfilter->flags == 2512 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) { 2513 match = 1; 2514 break; 2515 } 2516 } 2517 2518 if (match) 2519 *ret = -EEXIST; 2520 2521 exit: 2522 return mfilter; 2523 } 2524 2525 static int 2526 bnxt_ethertype_filter(struct rte_eth_dev *dev, 2527 enum rte_filter_op filter_op, 2528 void *arg) 2529 { 2530 struct bnxt *bp = dev->data->dev_private; 2531 struct rte_eth_ethertype_filter *efilter = 2532 (struct rte_eth_ethertype_filter *)arg; 2533 struct bnxt_filter_info *bfilter, *filter1; 2534 struct bnxt_vnic_info *vnic, *vnic0; 2535 int ret; 2536 2537 if (filter_op == RTE_ETH_FILTER_NOP) 2538 return 0; 2539 2540 if (arg == NULL) { 2541 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2542 filter_op); 2543 return -EINVAL; 2544 } 2545 2546 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 2547 vnic = &bp->vnic_info[efilter->queue]; 2548 2549 switch (filter_op) { 2550 case RTE_ETH_FILTER_ADD: 2551 bnxt_match_and_validate_ether_filter(bp, efilter, 2552 vnic0, vnic, &ret); 2553 if (ret < 0) 2554 return ret; 2555 2556 bfilter = bnxt_get_unused_filter(bp); 2557 if (bfilter == NULL) { 2558 PMD_DRV_LOG(ERR, 2559 "Not enough resources for a new filter.\n"); 2560 return -ENOMEM; 2561 } 2562 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2563 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes, 2564 RTE_ETHER_ADDR_LEN); 2565 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes, 2566 RTE_ETHER_ADDR_LEN); 2567 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2568 bfilter->ethertype = efilter->ether_type; 2569 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2570 2571 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0); 2572 if (filter1 == NULL) { 2573 ret = -EINVAL; 2574 goto cleanup; 2575 } 2576 bfilter->enables |= 2577 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2578 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2579 2580 bfilter->dst_id = vnic->fw_vnic_id; 2581 2582 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2583 bfilter->flags = 2584 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2585 } 2586 2587 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2588 if (ret) 2589 goto cleanup; 2590 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2591 break; 2592 case RTE_ETH_FILTER_DELETE: 2593 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter, 2594 vnic0, vnic, &ret); 2595 if (ret == -EEXIST) { 2596 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1); 2597 2598 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info, 2599 next); 2600 bnxt_free_filter(bp, filter1); 2601 } else if (ret == 0) { 2602 PMD_DRV_LOG(ERR, "No matching filter found\n"); 2603 } 2604 break; 2605 default: 2606 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2607 ret = -EINVAL; 2608 goto error; 2609 } 2610 return ret; 2611 cleanup: 2612 bnxt_free_filter(bp, bfilter); 2613 error: 2614 return ret; 2615 } 2616 2617 static inline int 2618 parse_ntuple_filter(struct bnxt *bp, 2619 struct rte_eth_ntuple_filter *nfilter, 2620 struct bnxt_filter_info *bfilter) 2621 { 2622 uint32_t en = 0; 2623 2624 if (nfilter->queue >= bp->rx_nr_rings) { 2625 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue); 2626 return -EINVAL; 2627 } 2628 2629 switch (nfilter->dst_port_mask) { 2630 case UINT16_MAX: 2631 bfilter->dst_port_mask = -1; 2632 bfilter->dst_port = nfilter->dst_port; 2633 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT | 2634 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2635 break; 2636 default: 2637 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 2638 return -EINVAL; 2639 } 2640 2641 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2642 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2643 2644 switch (nfilter->proto_mask) { 2645 case UINT8_MAX: 2646 if (nfilter->proto == 17) /* IPPROTO_UDP */ 2647 bfilter->ip_protocol = 17; 2648 else if (nfilter->proto == 6) /* IPPROTO_TCP */ 2649 bfilter->ip_protocol = 6; 2650 else 2651 return -EINVAL; 2652 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2653 break; 2654 default: 2655 PMD_DRV_LOG(ERR, "invalid protocol mask."); 2656 return -EINVAL; 2657 } 2658 2659 switch (nfilter->dst_ip_mask) { 2660 case UINT32_MAX: 2661 bfilter->dst_ipaddr_mask[0] = -1; 2662 bfilter->dst_ipaddr[0] = nfilter->dst_ip; 2663 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR | 2664 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2665 break; 2666 default: 2667 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 2668 return -EINVAL; 2669 } 2670 2671 switch (nfilter->src_ip_mask) { 2672 case UINT32_MAX: 2673 bfilter->src_ipaddr_mask[0] = -1; 2674 bfilter->src_ipaddr[0] = nfilter->src_ip; 2675 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR | 2676 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2677 break; 2678 default: 2679 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 2680 return -EINVAL; 2681 } 2682 2683 switch (nfilter->src_port_mask) { 2684 case UINT16_MAX: 2685 bfilter->src_port_mask = -1; 2686 bfilter->src_port = nfilter->src_port; 2687 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT | 2688 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2689 break; 2690 default: 2691 PMD_DRV_LOG(ERR, "invalid src_port mask."); 2692 return -EINVAL; 2693 } 2694 2695 bfilter->enables = en; 2696 return 0; 2697 } 2698 2699 static struct bnxt_filter_info* 2700 bnxt_match_ntuple_filter(struct bnxt *bp, 2701 struct bnxt_filter_info *bfilter, 2702 struct bnxt_vnic_info **mvnic) 2703 { 2704 struct bnxt_filter_info *mfilter = NULL; 2705 int i; 2706 2707 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2708 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2709 STAILQ_FOREACH(mfilter, &vnic->filter, next) { 2710 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] && 2711 bfilter->src_ipaddr_mask[0] == 2712 mfilter->src_ipaddr_mask[0] && 2713 bfilter->src_port == mfilter->src_port && 2714 bfilter->src_port_mask == mfilter->src_port_mask && 2715 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] && 2716 bfilter->dst_ipaddr_mask[0] == 2717 mfilter->dst_ipaddr_mask[0] && 2718 bfilter->dst_port == mfilter->dst_port && 2719 bfilter->dst_port_mask == mfilter->dst_port_mask && 2720 bfilter->flags == mfilter->flags && 2721 bfilter->enables == mfilter->enables) { 2722 if (mvnic) 2723 *mvnic = vnic; 2724 return mfilter; 2725 } 2726 } 2727 } 2728 return NULL; 2729 } 2730 2731 static int 2732 bnxt_cfg_ntuple_filter(struct bnxt *bp, 2733 struct rte_eth_ntuple_filter *nfilter, 2734 enum rte_filter_op filter_op) 2735 { 2736 struct bnxt_filter_info *bfilter, *mfilter, *filter1; 2737 struct bnxt_vnic_info *vnic, *vnic0, *mvnic; 2738 int ret; 2739 2740 if (nfilter->flags != RTE_5TUPLE_FLAGS) { 2741 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 2742 return -EINVAL; 2743 } 2744 2745 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) { 2746 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n"); 2747 return -EINVAL; 2748 } 2749 2750 bfilter = bnxt_get_unused_filter(bp); 2751 if (bfilter == NULL) { 2752 PMD_DRV_LOG(ERR, 2753 "Not enough resources for a new filter.\n"); 2754 return -ENOMEM; 2755 } 2756 ret = parse_ntuple_filter(bp, nfilter, bfilter); 2757 if (ret < 0) 2758 goto free_filter; 2759 2760 vnic = &bp->vnic_info[nfilter->queue]; 2761 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 2762 filter1 = STAILQ_FIRST(&vnic0->filter); 2763 if (filter1 == NULL) { 2764 ret = -EINVAL; 2765 goto free_filter; 2766 } 2767 2768 bfilter->dst_id = vnic->fw_vnic_id; 2769 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2770 bfilter->enables |= 2771 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2772 bfilter->ethertype = 0x800; 2773 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2774 2775 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic); 2776 2777 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2778 bfilter->dst_id == mfilter->dst_id) { 2779 PMD_DRV_LOG(ERR, "filter exists.\n"); 2780 ret = -EEXIST; 2781 goto free_filter; 2782 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2783 bfilter->dst_id != mfilter->dst_id) { 2784 mfilter->dst_id = vnic->fw_vnic_id; 2785 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter); 2786 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next); 2787 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next); 2788 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n"); 2789 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n"); 2790 goto free_filter; 2791 } 2792 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2793 PMD_DRV_LOG(ERR, "filter doesn't exist."); 2794 ret = -ENOENT; 2795 goto free_filter; 2796 } 2797 2798 if (filter_op == RTE_ETH_FILTER_ADD) { 2799 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2800 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2801 if (ret) 2802 goto free_filter; 2803 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2804 } else { 2805 if (mfilter == NULL) { 2806 /* This should not happen. But for Coverity! */ 2807 ret = -ENOENT; 2808 goto free_filter; 2809 } 2810 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter); 2811 2812 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next); 2813 bnxt_free_filter(bp, mfilter); 2814 bnxt_free_filter(bp, bfilter); 2815 } 2816 2817 return 0; 2818 free_filter: 2819 bnxt_free_filter(bp, bfilter); 2820 return ret; 2821 } 2822 2823 static int 2824 bnxt_ntuple_filter(struct rte_eth_dev *dev, 2825 enum rte_filter_op filter_op, 2826 void *arg) 2827 { 2828 struct bnxt *bp = dev->data->dev_private; 2829 int ret; 2830 2831 if (filter_op == RTE_ETH_FILTER_NOP) 2832 return 0; 2833 2834 if (arg == NULL) { 2835 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2836 filter_op); 2837 return -EINVAL; 2838 } 2839 2840 switch (filter_op) { 2841 case RTE_ETH_FILTER_ADD: 2842 ret = bnxt_cfg_ntuple_filter(bp, 2843 (struct rte_eth_ntuple_filter *)arg, 2844 filter_op); 2845 break; 2846 case RTE_ETH_FILTER_DELETE: 2847 ret = bnxt_cfg_ntuple_filter(bp, 2848 (struct rte_eth_ntuple_filter *)arg, 2849 filter_op); 2850 break; 2851 default: 2852 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2853 ret = -EINVAL; 2854 break; 2855 } 2856 return ret; 2857 } 2858 2859 static int 2860 bnxt_parse_fdir_filter(struct bnxt *bp, 2861 struct rte_eth_fdir_filter *fdir, 2862 struct bnxt_filter_info *filter) 2863 { 2864 enum rte_fdir_mode fdir_mode = 2865 bp->eth_dev->data->dev_conf.fdir_conf.mode; 2866 struct bnxt_vnic_info *vnic0, *vnic; 2867 struct bnxt_filter_info *filter1; 2868 uint32_t en = 0; 2869 int i; 2870 2871 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 2872 return -EINVAL; 2873 2874 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci; 2875 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID; 2876 2877 switch (fdir->input.flow_type) { 2878 case RTE_ETH_FLOW_IPV4: 2879 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 2880 /* FALLTHROUGH */ 2881 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip; 2882 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2883 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip; 2884 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2885 filter->ip_protocol = fdir->input.flow.ip4_flow.proto; 2886 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2887 filter->ip_addr_type = 2888 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2889 filter->src_ipaddr_mask[0] = 0xffffffff; 2890 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2891 filter->dst_ipaddr_mask[0] = 0xffffffff; 2892 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2893 filter->ethertype = 0x800; 2894 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2895 break; 2896 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 2897 filter->src_port = fdir->input.flow.tcp4_flow.src_port; 2898 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2899 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port; 2900 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2901 filter->dst_port_mask = 0xffff; 2902 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2903 filter->src_port_mask = 0xffff; 2904 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2905 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip; 2906 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2907 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip; 2908 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2909 filter->ip_protocol = 6; 2910 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2911 filter->ip_addr_type = 2912 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2913 filter->src_ipaddr_mask[0] = 0xffffffff; 2914 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2915 filter->dst_ipaddr_mask[0] = 0xffffffff; 2916 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2917 filter->ethertype = 0x800; 2918 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2919 break; 2920 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 2921 filter->src_port = fdir->input.flow.udp4_flow.src_port; 2922 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2923 filter->dst_port = fdir->input.flow.udp4_flow.dst_port; 2924 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2925 filter->dst_port_mask = 0xffff; 2926 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2927 filter->src_port_mask = 0xffff; 2928 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2929 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip; 2930 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2931 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip; 2932 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2933 filter->ip_protocol = 17; 2934 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2935 filter->ip_addr_type = 2936 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2937 filter->src_ipaddr_mask[0] = 0xffffffff; 2938 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2939 filter->dst_ipaddr_mask[0] = 0xffffffff; 2940 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2941 filter->ethertype = 0x800; 2942 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2943 break; 2944 case RTE_ETH_FLOW_IPV6: 2945 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 2946 /* FALLTHROUGH */ 2947 filter->ip_addr_type = 2948 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2949 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto; 2950 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2951 rte_memcpy(filter->src_ipaddr, 2952 fdir->input.flow.ipv6_flow.src_ip, 16); 2953 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2954 rte_memcpy(filter->dst_ipaddr, 2955 fdir->input.flow.ipv6_flow.dst_ip, 16); 2956 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2957 memset(filter->dst_ipaddr_mask, 0xff, 16); 2958 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2959 memset(filter->src_ipaddr_mask, 0xff, 16); 2960 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2961 filter->ethertype = 0x86dd; 2962 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2963 break; 2964 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 2965 filter->src_port = fdir->input.flow.tcp6_flow.src_port; 2966 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2967 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port; 2968 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2969 filter->dst_port_mask = 0xffff; 2970 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2971 filter->src_port_mask = 0xffff; 2972 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2973 filter->ip_addr_type = 2974 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2975 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto; 2976 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2977 rte_memcpy(filter->src_ipaddr, 2978 fdir->input.flow.tcp6_flow.ip.src_ip, 16); 2979 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2980 rte_memcpy(filter->dst_ipaddr, 2981 fdir->input.flow.tcp6_flow.ip.dst_ip, 16); 2982 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2983 memset(filter->dst_ipaddr_mask, 0xff, 16); 2984 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2985 memset(filter->src_ipaddr_mask, 0xff, 16); 2986 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2987 filter->ethertype = 0x86dd; 2988 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2989 break; 2990 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 2991 filter->src_port = fdir->input.flow.udp6_flow.src_port; 2992 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2993 filter->dst_port = fdir->input.flow.udp6_flow.dst_port; 2994 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2995 filter->dst_port_mask = 0xffff; 2996 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2997 filter->src_port_mask = 0xffff; 2998 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2999 filter->ip_addr_type = 3000 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 3001 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto; 3002 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 3003 rte_memcpy(filter->src_ipaddr, 3004 fdir->input.flow.udp6_flow.ip.src_ip, 16); 3005 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 3006 rte_memcpy(filter->dst_ipaddr, 3007 fdir->input.flow.udp6_flow.ip.dst_ip, 16); 3008 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 3009 memset(filter->dst_ipaddr_mask, 0xff, 16); 3010 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 3011 memset(filter->src_ipaddr_mask, 0xff, 16); 3012 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 3013 filter->ethertype = 0x86dd; 3014 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3015 break; 3016 case RTE_ETH_FLOW_L2_PAYLOAD: 3017 filter->ethertype = fdir->input.flow.l2_flow.ether_type; 3018 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 3019 break; 3020 case RTE_ETH_FLOW_VXLAN: 3021 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3022 return -EINVAL; 3023 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 3024 filter->tunnel_type = 3025 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN; 3026 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 3027 break; 3028 case RTE_ETH_FLOW_NVGRE: 3029 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3030 return -EINVAL; 3031 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 3032 filter->tunnel_type = 3033 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE; 3034 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 3035 break; 3036 case RTE_ETH_FLOW_UNKNOWN: 3037 case RTE_ETH_FLOW_RAW: 3038 case RTE_ETH_FLOW_FRAG_IPV4: 3039 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 3040 case RTE_ETH_FLOW_FRAG_IPV6: 3041 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 3042 case RTE_ETH_FLOW_IPV6_EX: 3043 case RTE_ETH_FLOW_IPV6_TCP_EX: 3044 case RTE_ETH_FLOW_IPV6_UDP_EX: 3045 case RTE_ETH_FLOW_GENEVE: 3046 /* FALLTHROUGH */ 3047 default: 3048 return -EINVAL; 3049 } 3050 3051 vnic0 = BNXT_GET_DEFAULT_VNIC(bp); 3052 vnic = &bp->vnic_info[fdir->action.rx_queue]; 3053 if (vnic == NULL) { 3054 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue); 3055 return -EINVAL; 3056 } 3057 3058 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 3059 rte_memcpy(filter->dst_macaddr, 3060 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6); 3061 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 3062 } 3063 3064 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) { 3065 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 3066 filter1 = STAILQ_FIRST(&vnic0->filter); 3067 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0); 3068 } else { 3069 filter->dst_id = vnic->fw_vnic_id; 3070 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 3071 if (filter->dst_macaddr[i] == 0x00) 3072 filter1 = STAILQ_FIRST(&vnic0->filter); 3073 else 3074 filter1 = bnxt_get_l2_filter(bp, filter, vnic); 3075 } 3076 3077 if (filter1 == NULL) 3078 return -EINVAL; 3079 3080 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 3081 filter->fw_l2_filter_id = filter1->fw_l2_filter_id; 3082 3083 filter->enables = en; 3084 3085 return 0; 3086 } 3087 3088 static struct bnxt_filter_info * 3089 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf, 3090 struct bnxt_vnic_info **mvnic) 3091 { 3092 struct bnxt_filter_info *mf = NULL; 3093 int i; 3094 3095 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3096 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3097 3098 STAILQ_FOREACH(mf, &vnic->filter, next) { 3099 if (mf->filter_type == nf->filter_type && 3100 mf->flags == nf->flags && 3101 mf->src_port == nf->src_port && 3102 mf->src_port_mask == nf->src_port_mask && 3103 mf->dst_port == nf->dst_port && 3104 mf->dst_port_mask == nf->dst_port_mask && 3105 mf->ip_protocol == nf->ip_protocol && 3106 mf->ip_addr_type == nf->ip_addr_type && 3107 mf->ethertype == nf->ethertype && 3108 mf->vni == nf->vni && 3109 mf->tunnel_type == nf->tunnel_type && 3110 mf->l2_ovlan == nf->l2_ovlan && 3111 mf->l2_ovlan_mask == nf->l2_ovlan_mask && 3112 mf->l2_ivlan == nf->l2_ivlan && 3113 mf->l2_ivlan_mask == nf->l2_ivlan_mask && 3114 !memcmp(mf->l2_addr, nf->l2_addr, 3115 RTE_ETHER_ADDR_LEN) && 3116 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask, 3117 RTE_ETHER_ADDR_LEN) && 3118 !memcmp(mf->src_macaddr, nf->src_macaddr, 3119 RTE_ETHER_ADDR_LEN) && 3120 !memcmp(mf->dst_macaddr, nf->dst_macaddr, 3121 RTE_ETHER_ADDR_LEN) && 3122 !memcmp(mf->src_ipaddr, nf->src_ipaddr, 3123 sizeof(nf->src_ipaddr)) && 3124 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask, 3125 sizeof(nf->src_ipaddr_mask)) && 3126 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr, 3127 sizeof(nf->dst_ipaddr)) && 3128 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask, 3129 sizeof(nf->dst_ipaddr_mask))) { 3130 if (mvnic) 3131 *mvnic = vnic; 3132 return mf; 3133 } 3134 } 3135 } 3136 return NULL; 3137 } 3138 3139 static int 3140 bnxt_fdir_filter(struct rte_eth_dev *dev, 3141 enum rte_filter_op filter_op, 3142 void *arg) 3143 { 3144 struct bnxt *bp = dev->data->dev_private; 3145 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg; 3146 struct bnxt_filter_info *filter, *match; 3147 struct bnxt_vnic_info *vnic, *mvnic; 3148 int ret = 0, i; 3149 3150 if (filter_op == RTE_ETH_FILTER_NOP) 3151 return 0; 3152 3153 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 3154 return -EINVAL; 3155 3156 switch (filter_op) { 3157 case RTE_ETH_FILTER_ADD: 3158 case RTE_ETH_FILTER_DELETE: 3159 /* FALLTHROUGH */ 3160 filter = bnxt_get_unused_filter(bp); 3161 if (filter == NULL) { 3162 PMD_DRV_LOG(ERR, 3163 "Not enough resources for a new flow.\n"); 3164 return -ENOMEM; 3165 } 3166 3167 ret = bnxt_parse_fdir_filter(bp, fdir, filter); 3168 if (ret != 0) 3169 goto free_filter; 3170 filter->filter_type = HWRM_CFA_NTUPLE_FILTER; 3171 3172 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 3173 vnic = &bp->vnic_info[0]; 3174 else 3175 vnic = &bp->vnic_info[fdir->action.rx_queue]; 3176 3177 match = bnxt_match_fdir(bp, filter, &mvnic); 3178 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { 3179 if (match->dst_id == vnic->fw_vnic_id) { 3180 PMD_DRV_LOG(ERR, "Flow already exists.\n"); 3181 ret = -EEXIST; 3182 goto free_filter; 3183 } else { 3184 match->dst_id = vnic->fw_vnic_id; 3185 ret = bnxt_hwrm_set_ntuple_filter(bp, 3186 match->dst_id, 3187 match); 3188 STAILQ_REMOVE(&mvnic->filter, match, 3189 bnxt_filter_info, next); 3190 STAILQ_INSERT_TAIL(&vnic->filter, match, next); 3191 PMD_DRV_LOG(ERR, 3192 "Filter with matching pattern exist\n"); 3193 PMD_DRV_LOG(ERR, 3194 "Updated it to new destination q\n"); 3195 goto free_filter; 3196 } 3197 } 3198 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 3199 PMD_DRV_LOG(ERR, "Flow does not exist.\n"); 3200 ret = -ENOENT; 3201 goto free_filter; 3202 } 3203 3204 if (filter_op == RTE_ETH_FILTER_ADD) { 3205 ret = bnxt_hwrm_set_ntuple_filter(bp, 3206 filter->dst_id, 3207 filter); 3208 if (ret) 3209 goto free_filter; 3210 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 3211 } else { 3212 ret = bnxt_hwrm_clear_ntuple_filter(bp, match); 3213 STAILQ_REMOVE(&vnic->filter, match, 3214 bnxt_filter_info, next); 3215 bnxt_free_filter(bp, match); 3216 bnxt_free_filter(bp, filter); 3217 } 3218 break; 3219 case RTE_ETH_FILTER_FLUSH: 3220 for (i = bp->nr_vnics - 1; i >= 0; i--) { 3221 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3222 3223 STAILQ_FOREACH(filter, &vnic->filter, next) { 3224 if (filter->filter_type == 3225 HWRM_CFA_NTUPLE_FILTER) { 3226 ret = 3227 bnxt_hwrm_clear_ntuple_filter(bp, 3228 filter); 3229 STAILQ_REMOVE(&vnic->filter, filter, 3230 bnxt_filter_info, next); 3231 } 3232 } 3233 } 3234 return ret; 3235 case RTE_ETH_FILTER_UPDATE: 3236 case RTE_ETH_FILTER_STATS: 3237 case RTE_ETH_FILTER_INFO: 3238 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op); 3239 break; 3240 default: 3241 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 3242 ret = -EINVAL; 3243 break; 3244 } 3245 return ret; 3246 3247 free_filter: 3248 bnxt_free_filter(bp, filter); 3249 return ret; 3250 } 3251 3252 static int 3253 bnxt_filter_ctrl_op(struct rte_eth_dev *dev, 3254 enum rte_filter_type filter_type, 3255 enum rte_filter_op filter_op, void *arg) 3256 { 3257 int ret = 0; 3258 3259 ret = is_bnxt_in_error(dev->data->dev_private); 3260 if (ret) 3261 return ret; 3262 3263 switch (filter_type) { 3264 case RTE_ETH_FILTER_TUNNEL: 3265 PMD_DRV_LOG(ERR, 3266 "filter type: %d: To be implemented\n", filter_type); 3267 break; 3268 case RTE_ETH_FILTER_FDIR: 3269 ret = bnxt_fdir_filter(dev, filter_op, arg); 3270 break; 3271 case RTE_ETH_FILTER_NTUPLE: 3272 ret = bnxt_ntuple_filter(dev, filter_op, arg); 3273 break; 3274 case RTE_ETH_FILTER_ETHERTYPE: 3275 ret = bnxt_ethertype_filter(dev, filter_op, arg); 3276 break; 3277 case RTE_ETH_FILTER_GENERIC: 3278 if (filter_op != RTE_ETH_FILTER_GET) 3279 return -EINVAL; 3280 *(const void **)arg = &bnxt_flow_ops; 3281 break; 3282 default: 3283 PMD_DRV_LOG(ERR, 3284 "Filter type (%d) not supported", filter_type); 3285 ret = -EINVAL; 3286 break; 3287 } 3288 return ret; 3289 } 3290 3291 static const uint32_t * 3292 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3293 { 3294 static const uint32_t ptypes[] = { 3295 RTE_PTYPE_L2_ETHER_VLAN, 3296 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3297 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3298 RTE_PTYPE_L4_ICMP, 3299 RTE_PTYPE_L4_TCP, 3300 RTE_PTYPE_L4_UDP, 3301 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3302 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3303 RTE_PTYPE_INNER_L4_ICMP, 3304 RTE_PTYPE_INNER_L4_TCP, 3305 RTE_PTYPE_INNER_L4_UDP, 3306 RTE_PTYPE_UNKNOWN 3307 }; 3308 3309 if (!dev->rx_pkt_burst) 3310 return NULL; 3311 3312 return ptypes; 3313 } 3314 3315 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3316 int reg_win) 3317 { 3318 uint32_t reg_base = *reg_arr & 0xfffff000; 3319 uint32_t win_off; 3320 int i; 3321 3322 for (i = 0; i < count; i++) { 3323 if ((reg_arr[i] & 0xfffff000) != reg_base) 3324 return -ERANGE; 3325 } 3326 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3327 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3328 return 0; 3329 } 3330 3331 static int bnxt_map_ptp_regs(struct bnxt *bp) 3332 { 3333 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3334 uint32_t *reg_arr; 3335 int rc, i; 3336 3337 reg_arr = ptp->rx_regs; 3338 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3339 if (rc) 3340 return rc; 3341 3342 reg_arr = ptp->tx_regs; 3343 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3344 if (rc) 3345 return rc; 3346 3347 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3348 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3349 3350 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3351 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3352 3353 return 0; 3354 } 3355 3356 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3357 { 3358 rte_write32(0, (uint8_t *)bp->bar0 + 3359 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3360 rte_write32(0, (uint8_t *)bp->bar0 + 3361 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3362 } 3363 3364 static uint64_t bnxt_cc_read(struct bnxt *bp) 3365 { 3366 uint64_t ns; 3367 3368 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3369 BNXT_GRCPF_REG_SYNC_TIME)); 3370 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3371 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3372 return ns; 3373 } 3374 3375 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3376 { 3377 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3378 uint32_t fifo; 3379 3380 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3381 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3382 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3383 return -EAGAIN; 3384 3385 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3386 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3387 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3388 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3389 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3390 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3391 3392 return 0; 3393 } 3394 3395 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3396 { 3397 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3398 struct bnxt_pf_info *pf = &bp->pf; 3399 uint16_t port_id; 3400 uint32_t fifo; 3401 3402 if (!ptp) 3403 return -ENODEV; 3404 3405 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3406 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3407 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3408 return -EAGAIN; 3409 3410 port_id = pf->port_id; 3411 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3412 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3413 3414 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3415 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3416 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 3417 /* bnxt_clr_rx_ts(bp); TBD */ 3418 return -EBUSY; 3419 } 3420 3421 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3422 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3423 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3424 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3425 3426 return 0; 3427 } 3428 3429 static int 3430 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3431 { 3432 uint64_t ns; 3433 struct bnxt *bp = dev->data->dev_private; 3434 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3435 3436 if (!ptp) 3437 return 0; 3438 3439 ns = rte_timespec_to_ns(ts); 3440 /* Set the timecounters to a new value. */ 3441 ptp->tc.nsec = ns; 3442 3443 return 0; 3444 } 3445 3446 static int 3447 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3448 { 3449 struct bnxt *bp = dev->data->dev_private; 3450 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3451 uint64_t ns, systime_cycles = 0; 3452 int rc = 0; 3453 3454 if (!ptp) 3455 return 0; 3456 3457 if (BNXT_CHIP_THOR(bp)) 3458 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3459 &systime_cycles); 3460 else 3461 systime_cycles = bnxt_cc_read(bp); 3462 3463 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3464 *ts = rte_ns_to_timespec(ns); 3465 3466 return rc; 3467 } 3468 static int 3469 bnxt_timesync_enable(struct rte_eth_dev *dev) 3470 { 3471 struct bnxt *bp = dev->data->dev_private; 3472 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3473 uint32_t shift = 0; 3474 int rc; 3475 3476 if (!ptp) 3477 return 0; 3478 3479 ptp->rx_filter = 1; 3480 ptp->tx_tstamp_en = 1; 3481 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3482 3483 rc = bnxt_hwrm_ptp_cfg(bp); 3484 if (rc) 3485 return rc; 3486 3487 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3488 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3489 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3490 3491 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3492 ptp->tc.cc_shift = shift; 3493 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3494 3495 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3496 ptp->rx_tstamp_tc.cc_shift = shift; 3497 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3498 3499 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3500 ptp->tx_tstamp_tc.cc_shift = shift; 3501 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3502 3503 if (!BNXT_CHIP_THOR(bp)) 3504 bnxt_map_ptp_regs(bp); 3505 3506 return 0; 3507 } 3508 3509 static int 3510 bnxt_timesync_disable(struct rte_eth_dev *dev) 3511 { 3512 struct bnxt *bp = dev->data->dev_private; 3513 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3514 3515 if (!ptp) 3516 return 0; 3517 3518 ptp->rx_filter = 0; 3519 ptp->tx_tstamp_en = 0; 3520 ptp->rxctl = 0; 3521 3522 bnxt_hwrm_ptp_cfg(bp); 3523 3524 if (!BNXT_CHIP_THOR(bp)) 3525 bnxt_unmap_ptp_regs(bp); 3526 3527 return 0; 3528 } 3529 3530 static int 3531 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3532 struct timespec *timestamp, 3533 uint32_t flags __rte_unused) 3534 { 3535 struct bnxt *bp = dev->data->dev_private; 3536 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3537 uint64_t rx_tstamp_cycles = 0; 3538 uint64_t ns; 3539 3540 if (!ptp) 3541 return 0; 3542 3543 if (BNXT_CHIP_THOR(bp)) 3544 rx_tstamp_cycles = ptp->rx_timestamp; 3545 else 3546 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3547 3548 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3549 *timestamp = rte_ns_to_timespec(ns); 3550 return 0; 3551 } 3552 3553 static int 3554 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3555 struct timespec *timestamp) 3556 { 3557 struct bnxt *bp = dev->data->dev_private; 3558 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3559 uint64_t tx_tstamp_cycles = 0; 3560 uint64_t ns; 3561 int rc = 0; 3562 3563 if (!ptp) 3564 return 0; 3565 3566 if (BNXT_CHIP_THOR(bp)) 3567 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3568 &tx_tstamp_cycles); 3569 else 3570 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3571 3572 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3573 *timestamp = rte_ns_to_timespec(ns); 3574 3575 return rc; 3576 } 3577 3578 static int 3579 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3580 { 3581 struct bnxt *bp = dev->data->dev_private; 3582 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3583 3584 if (!ptp) 3585 return 0; 3586 3587 ptp->tc.nsec += delta; 3588 3589 return 0; 3590 } 3591 3592 static int 3593 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3594 { 3595 struct bnxt *bp = dev->data->dev_private; 3596 int rc; 3597 uint32_t dir_entries; 3598 uint32_t entry_length; 3599 3600 rc = is_bnxt_in_error(bp); 3601 if (rc) 3602 return rc; 3603 3604 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 3605 bp->pdev->addr.domain, bp->pdev->addr.bus, 3606 bp->pdev->addr.devid, bp->pdev->addr.function); 3607 3608 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3609 if (rc != 0) 3610 return rc; 3611 3612 return dir_entries * entry_length; 3613 } 3614 3615 static int 3616 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3617 struct rte_dev_eeprom_info *in_eeprom) 3618 { 3619 struct bnxt *bp = dev->data->dev_private; 3620 uint32_t index; 3621 uint32_t offset; 3622 int rc; 3623 3624 rc = is_bnxt_in_error(bp); 3625 if (rc) 3626 return rc; 3627 3628 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3629 bp->pdev->addr.domain, bp->pdev->addr.bus, 3630 bp->pdev->addr.devid, bp->pdev->addr.function, 3631 in_eeprom->offset, in_eeprom->length); 3632 3633 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3634 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3635 in_eeprom->data); 3636 3637 index = in_eeprom->offset >> 24; 3638 offset = in_eeprom->offset & 0xffffff; 3639 3640 if (index != 0) 3641 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3642 in_eeprom->length, in_eeprom->data); 3643 3644 return 0; 3645 } 3646 3647 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3648 { 3649 switch (dir_type) { 3650 case BNX_DIR_TYPE_CHIMP_PATCH: 3651 case BNX_DIR_TYPE_BOOTCODE: 3652 case BNX_DIR_TYPE_BOOTCODE_2: 3653 case BNX_DIR_TYPE_APE_FW: 3654 case BNX_DIR_TYPE_APE_PATCH: 3655 case BNX_DIR_TYPE_KONG_FW: 3656 case BNX_DIR_TYPE_KONG_PATCH: 3657 case BNX_DIR_TYPE_BONO_FW: 3658 case BNX_DIR_TYPE_BONO_PATCH: 3659 /* FALLTHROUGH */ 3660 return true; 3661 } 3662 3663 return false; 3664 } 3665 3666 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3667 { 3668 switch (dir_type) { 3669 case BNX_DIR_TYPE_AVS: 3670 case BNX_DIR_TYPE_EXP_ROM_MBA: 3671 case BNX_DIR_TYPE_PCIE: 3672 case BNX_DIR_TYPE_TSCF_UCODE: 3673 case BNX_DIR_TYPE_EXT_PHY: 3674 case BNX_DIR_TYPE_CCM: 3675 case BNX_DIR_TYPE_ISCSI_BOOT: 3676 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3677 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3678 /* FALLTHROUGH */ 3679 return true; 3680 } 3681 3682 return false; 3683 } 3684 3685 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3686 { 3687 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3688 bnxt_dir_type_is_other_exec_format(dir_type); 3689 } 3690 3691 static int 3692 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3693 struct rte_dev_eeprom_info *in_eeprom) 3694 { 3695 struct bnxt *bp = dev->data->dev_private; 3696 uint8_t index, dir_op; 3697 uint16_t type, ext, ordinal, attr; 3698 int rc; 3699 3700 rc = is_bnxt_in_error(bp); 3701 if (rc) 3702 return rc; 3703 3704 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3705 bp->pdev->addr.domain, bp->pdev->addr.bus, 3706 bp->pdev->addr.devid, bp->pdev->addr.function, 3707 in_eeprom->offset, in_eeprom->length); 3708 3709 if (!BNXT_PF(bp)) { 3710 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3711 return -EINVAL; 3712 } 3713 3714 type = in_eeprom->magic >> 16; 3715 3716 if (type == 0xffff) { /* special value for directory operations */ 3717 index = in_eeprom->magic & 0xff; 3718 dir_op = in_eeprom->magic >> 8; 3719 if (index == 0) 3720 return -EINVAL; 3721 switch (dir_op) { 3722 case 0x0e: /* erase */ 3723 if (in_eeprom->offset != ~in_eeprom->magic) 3724 return -EINVAL; 3725 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3726 default: 3727 return -EINVAL; 3728 } 3729 } 3730 3731 /* Create or re-write an NVM item: */ 3732 if (bnxt_dir_type_is_executable(type) == true) 3733 return -EOPNOTSUPP; 3734 ext = in_eeprom->magic & 0xffff; 3735 ordinal = in_eeprom->offset >> 16; 3736 attr = in_eeprom->offset & 0xffff; 3737 3738 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3739 in_eeprom->data, in_eeprom->length); 3740 } 3741 3742 /* 3743 * Initialization 3744 */ 3745 3746 static const struct eth_dev_ops bnxt_dev_ops = { 3747 .dev_infos_get = bnxt_dev_info_get_op, 3748 .dev_close = bnxt_dev_close_op, 3749 .dev_configure = bnxt_dev_configure_op, 3750 .dev_start = bnxt_dev_start_op, 3751 .dev_stop = bnxt_dev_stop_op, 3752 .dev_set_link_up = bnxt_dev_set_link_up_op, 3753 .dev_set_link_down = bnxt_dev_set_link_down_op, 3754 .stats_get = bnxt_stats_get_op, 3755 .stats_reset = bnxt_stats_reset_op, 3756 .rx_queue_setup = bnxt_rx_queue_setup_op, 3757 .rx_queue_release = bnxt_rx_queue_release_op, 3758 .tx_queue_setup = bnxt_tx_queue_setup_op, 3759 .tx_queue_release = bnxt_tx_queue_release_op, 3760 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3761 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3762 .reta_update = bnxt_reta_update_op, 3763 .reta_query = bnxt_reta_query_op, 3764 .rss_hash_update = bnxt_rss_hash_update_op, 3765 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3766 .link_update = bnxt_link_update_op, 3767 .promiscuous_enable = bnxt_promiscuous_enable_op, 3768 .promiscuous_disable = bnxt_promiscuous_disable_op, 3769 .allmulticast_enable = bnxt_allmulticast_enable_op, 3770 .allmulticast_disable = bnxt_allmulticast_disable_op, 3771 .mac_addr_add = bnxt_mac_addr_add_op, 3772 .mac_addr_remove = bnxt_mac_addr_remove_op, 3773 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3774 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3775 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3776 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3777 .vlan_filter_set = bnxt_vlan_filter_set_op, 3778 .vlan_offload_set = bnxt_vlan_offload_set_op, 3779 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 3780 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3781 .mtu_set = bnxt_mtu_set_op, 3782 .mac_addr_set = bnxt_set_default_mac_addr_op, 3783 .xstats_get = bnxt_dev_xstats_get_op, 3784 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3785 .xstats_reset = bnxt_dev_xstats_reset_op, 3786 .fw_version_get = bnxt_fw_version_get, 3787 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3788 .rxq_info_get = bnxt_rxq_info_get_op, 3789 .txq_info_get = bnxt_txq_info_get_op, 3790 .dev_led_on = bnxt_dev_led_on_op, 3791 .dev_led_off = bnxt_dev_led_off_op, 3792 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op, 3793 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op, 3794 .rx_queue_count = bnxt_rx_queue_count_op, 3795 .rx_descriptor_status = bnxt_rx_descriptor_status_op, 3796 .tx_descriptor_status = bnxt_tx_descriptor_status_op, 3797 .rx_queue_start = bnxt_rx_queue_start, 3798 .rx_queue_stop = bnxt_rx_queue_stop, 3799 .tx_queue_start = bnxt_tx_queue_start, 3800 .tx_queue_stop = bnxt_tx_queue_stop, 3801 .filter_ctrl = bnxt_filter_ctrl_op, 3802 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3803 .get_eeprom_length = bnxt_get_eeprom_length_op, 3804 .get_eeprom = bnxt_get_eeprom_op, 3805 .set_eeprom = bnxt_set_eeprom_op, 3806 .timesync_enable = bnxt_timesync_enable, 3807 .timesync_disable = bnxt_timesync_disable, 3808 .timesync_read_time = bnxt_timesync_read_time, 3809 .timesync_write_time = bnxt_timesync_write_time, 3810 .timesync_adjust_time = bnxt_timesync_adjust_time, 3811 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3812 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3813 }; 3814 3815 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 3816 { 3817 uint32_t offset; 3818 3819 /* Only pre-map the reset GRC registers using window 3 */ 3820 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 3821 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 3822 3823 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 3824 3825 return offset; 3826 } 3827 3828 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 3829 { 3830 struct bnxt_error_recovery_info *info = bp->recovery_info; 3831 uint32_t reg_base = 0xffffffff; 3832 int i; 3833 3834 /* Only pre-map the monitoring GRC registers using window 2 */ 3835 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 3836 uint32_t reg = info->status_regs[i]; 3837 3838 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 3839 continue; 3840 3841 if (reg_base == 0xffffffff) 3842 reg_base = reg & 0xfffff000; 3843 if ((reg & 0xfffff000) != reg_base) 3844 return -ERANGE; 3845 3846 /* Use mask 0xffc as the Lower 2 bits indicates 3847 * address space location 3848 */ 3849 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 3850 (reg & 0xffc); 3851 } 3852 3853 if (reg_base == 0xffffffff) 3854 return 0; 3855 3856 rte_write32(reg_base, (uint8_t *)bp->bar0 + 3857 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 3858 3859 return 0; 3860 } 3861 3862 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 3863 { 3864 struct bnxt_error_recovery_info *info = bp->recovery_info; 3865 uint32_t delay = info->delay_after_reset[index]; 3866 uint32_t val = info->reset_reg_val[index]; 3867 uint32_t reg = info->reset_reg[index]; 3868 uint32_t type, offset; 3869 3870 type = BNXT_FW_STATUS_REG_TYPE(reg); 3871 offset = BNXT_FW_STATUS_REG_OFF(reg); 3872 3873 switch (type) { 3874 case BNXT_FW_STATUS_REG_TYPE_CFG: 3875 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 3876 break; 3877 case BNXT_FW_STATUS_REG_TYPE_GRC: 3878 offset = bnxt_map_reset_regs(bp, offset); 3879 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3880 break; 3881 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3882 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3883 break; 3884 } 3885 /* wait on a specific interval of time until core reset is complete */ 3886 if (delay) 3887 rte_delay_ms(delay); 3888 } 3889 3890 static void bnxt_dev_cleanup(struct bnxt *bp) 3891 { 3892 bnxt_set_hwrm_link_config(bp, false); 3893 bp->link_info.link_up = 0; 3894 if (bp->eth_dev->data->dev_started) 3895 bnxt_dev_stop_op(bp->eth_dev); 3896 3897 bnxt_uninit_resources(bp, true); 3898 } 3899 3900 static int bnxt_restore_vlan_filters(struct bnxt *bp) 3901 { 3902 struct rte_eth_dev *dev = bp->eth_dev; 3903 struct rte_vlan_filter_conf *vfc; 3904 int vidx, vbit, rc; 3905 uint16_t vlan_id; 3906 3907 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 3908 vfc = &dev->data->vlan_filter_conf; 3909 vidx = vlan_id / 64; 3910 vbit = vlan_id % 64; 3911 3912 /* Each bit corresponds to a VLAN id */ 3913 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 3914 rc = bnxt_add_vlan_filter(bp, vlan_id); 3915 if (rc) 3916 return rc; 3917 } 3918 } 3919 3920 return 0; 3921 } 3922 3923 static int bnxt_restore_mac_filters(struct bnxt *bp) 3924 { 3925 struct rte_eth_dev *dev = bp->eth_dev; 3926 struct rte_eth_dev_info dev_info; 3927 struct rte_ether_addr *addr; 3928 uint64_t pool_mask; 3929 uint32_t pool = 0; 3930 uint16_t i; 3931 int rc; 3932 3933 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) 3934 return 0; 3935 3936 rc = bnxt_dev_info_get_op(dev, &dev_info); 3937 if (rc) 3938 return rc; 3939 3940 /* replay MAC address configuration */ 3941 for (i = 1; i < dev_info.max_mac_addrs; i++) { 3942 addr = &dev->data->mac_addrs[i]; 3943 3944 /* skip zero address */ 3945 if (rte_is_zero_ether_addr(addr)) 3946 continue; 3947 3948 pool = 0; 3949 pool_mask = dev->data->mac_pool_sel[i]; 3950 3951 do { 3952 if (pool_mask & 1ULL) { 3953 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 3954 if (rc) 3955 return rc; 3956 } 3957 pool_mask >>= 1; 3958 pool++; 3959 } while (pool_mask); 3960 } 3961 3962 return 0; 3963 } 3964 3965 static int bnxt_restore_filters(struct bnxt *bp) 3966 { 3967 struct rte_eth_dev *dev = bp->eth_dev; 3968 int ret = 0; 3969 3970 if (dev->data->all_multicast) { 3971 ret = bnxt_allmulticast_enable_op(dev); 3972 if (ret) 3973 return ret; 3974 } 3975 if (dev->data->promiscuous) { 3976 ret = bnxt_promiscuous_enable_op(dev); 3977 if (ret) 3978 return ret; 3979 } 3980 3981 ret = bnxt_restore_mac_filters(bp); 3982 if (ret) 3983 return ret; 3984 3985 ret = bnxt_restore_vlan_filters(bp); 3986 /* TODO restore other filters as well */ 3987 return ret; 3988 } 3989 3990 static void bnxt_dev_recover(void *arg) 3991 { 3992 struct bnxt *bp = arg; 3993 int timeout = bp->fw_reset_max_msecs; 3994 int rc = 0; 3995 3996 /* Clear Error flag so that device re-init should happen */ 3997 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 3998 3999 do { 4000 rc = bnxt_hwrm_ver_get(bp); 4001 if (rc == 0) 4002 break; 4003 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 4004 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 4005 } while (rc && timeout); 4006 4007 if (rc) { 4008 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 4009 goto err; 4010 } 4011 4012 rc = bnxt_init_resources(bp, true); 4013 if (rc) { 4014 PMD_DRV_LOG(ERR, 4015 "Failed to initialize resources after reset\n"); 4016 goto err; 4017 } 4018 /* clear reset flag as the device is initialized now */ 4019 bp->flags &= ~BNXT_FLAG_FW_RESET; 4020 4021 rc = bnxt_dev_start_op(bp->eth_dev); 4022 if (rc) { 4023 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 4024 goto err; 4025 } 4026 4027 rc = bnxt_restore_filters(bp); 4028 if (rc) 4029 goto err; 4030 4031 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 4032 return; 4033 err: 4034 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4035 bnxt_uninit_resources(bp, false); 4036 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 4037 } 4038 4039 void bnxt_dev_reset_and_resume(void *arg) 4040 { 4041 struct bnxt *bp = arg; 4042 int rc; 4043 4044 bnxt_dev_cleanup(bp); 4045 4046 bnxt_wait_for_device_shutdown(bp); 4047 4048 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, 4049 bnxt_dev_recover, (void *)bp); 4050 if (rc) 4051 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 4052 } 4053 4054 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 4055 { 4056 struct bnxt_error_recovery_info *info = bp->recovery_info; 4057 uint32_t reg = info->status_regs[index]; 4058 uint32_t type, offset, val = 0; 4059 4060 type = BNXT_FW_STATUS_REG_TYPE(reg); 4061 offset = BNXT_FW_STATUS_REG_OFF(reg); 4062 4063 switch (type) { 4064 case BNXT_FW_STATUS_REG_TYPE_CFG: 4065 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 4066 break; 4067 case BNXT_FW_STATUS_REG_TYPE_GRC: 4068 offset = info->mapped_status_regs[index]; 4069 /* FALLTHROUGH */ 4070 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4071 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4072 offset)); 4073 break; 4074 } 4075 4076 return val; 4077 } 4078 4079 static int bnxt_fw_reset_all(struct bnxt *bp) 4080 { 4081 struct bnxt_error_recovery_info *info = bp->recovery_info; 4082 uint32_t i; 4083 int rc = 0; 4084 4085 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4086 /* Reset through master function driver */ 4087 for (i = 0; i < info->reg_array_cnt; i++) 4088 bnxt_write_fw_reset_reg(bp, i); 4089 /* Wait for time specified by FW after triggering reset */ 4090 rte_delay_ms(info->master_func_wait_period_after_reset); 4091 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 4092 /* Reset with the help of Kong processor */ 4093 rc = bnxt_hwrm_fw_reset(bp); 4094 if (rc) 4095 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 4096 } 4097 4098 return rc; 4099 } 4100 4101 static void bnxt_fw_reset_cb(void *arg) 4102 { 4103 struct bnxt *bp = arg; 4104 struct bnxt_error_recovery_info *info = bp->recovery_info; 4105 int rc = 0; 4106 4107 /* Only Master function can do FW reset */ 4108 if (bnxt_is_master_func(bp) && 4109 bnxt_is_recovery_enabled(bp)) { 4110 rc = bnxt_fw_reset_all(bp); 4111 if (rc) { 4112 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 4113 return; 4114 } 4115 } 4116 4117 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 4118 * EXCEPTION_FATAL_ASYNC event to all the functions 4119 * (including MASTER FUNC). After receiving this Async, all the active 4120 * drivers should treat this case as FW initiated recovery 4121 */ 4122 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4123 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 4124 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 4125 4126 /* To recover from error */ 4127 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 4128 (void *)bp); 4129 } 4130 } 4131 4132 /* Driver should poll FW heartbeat, reset_counter with the frequency 4133 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 4134 * When the driver detects heartbeat stop or change in reset_counter, 4135 * it has to trigger a reset to recover from the error condition. 4136 * A “master PF” is the function who will have the privilege to 4137 * initiate the chimp reset. The master PF will be elected by the 4138 * firmware and will be notified through async message. 4139 */ 4140 static void bnxt_check_fw_health(void *arg) 4141 { 4142 struct bnxt *bp = arg; 4143 struct bnxt_error_recovery_info *info = bp->recovery_info; 4144 uint32_t val = 0, wait_msec; 4145 4146 if (!info || !bnxt_is_recovery_enabled(bp) || 4147 is_bnxt_in_error(bp)) 4148 return; 4149 4150 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4151 if (val == info->last_heart_beat) 4152 goto reset; 4153 4154 info->last_heart_beat = val; 4155 4156 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4157 if (val != info->last_reset_counter) 4158 goto reset; 4159 4160 info->last_reset_counter = val; 4161 4162 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4163 bnxt_check_fw_health, (void *)bp); 4164 4165 return; 4166 reset: 4167 /* Stop DMA to/from device */ 4168 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4169 bp->flags |= BNXT_FLAG_FW_RESET; 4170 4171 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4172 4173 if (bnxt_is_master_func(bp)) 4174 wait_msec = info->master_func_wait_period; 4175 else 4176 wait_msec = info->normal_func_wait_period; 4177 4178 rte_eal_alarm_set(US_PER_MS * wait_msec, 4179 bnxt_fw_reset_cb, (void *)bp); 4180 } 4181 4182 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4183 { 4184 uint32_t polling_freq; 4185 4186 if (!bnxt_is_recovery_enabled(bp)) 4187 return; 4188 4189 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4190 return; 4191 4192 polling_freq = bp->recovery_info->driver_polling_freq; 4193 4194 rte_eal_alarm_set(US_PER_MS * polling_freq, 4195 bnxt_check_fw_health, (void *)bp); 4196 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4197 } 4198 4199 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4200 { 4201 if (!bnxt_is_recovery_enabled(bp)) 4202 return; 4203 4204 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4205 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4206 } 4207 4208 static bool bnxt_vf_pciid(uint16_t device_id) 4209 { 4210 switch (device_id) { 4211 case BROADCOM_DEV_ID_57304_VF: 4212 case BROADCOM_DEV_ID_57406_VF: 4213 case BROADCOM_DEV_ID_5731X_VF: 4214 case BROADCOM_DEV_ID_5741X_VF: 4215 case BROADCOM_DEV_ID_57414_VF: 4216 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4217 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4218 case BROADCOM_DEV_ID_58802_VF: 4219 case BROADCOM_DEV_ID_57500_VF1: 4220 case BROADCOM_DEV_ID_57500_VF2: 4221 /* FALLTHROUGH */ 4222 return true; 4223 default: 4224 return false; 4225 } 4226 } 4227 4228 static bool bnxt_thor_device(uint16_t device_id) 4229 { 4230 switch (device_id) { 4231 case BROADCOM_DEV_ID_57508: 4232 case BROADCOM_DEV_ID_57504: 4233 case BROADCOM_DEV_ID_57502: 4234 case BROADCOM_DEV_ID_57508_MF1: 4235 case BROADCOM_DEV_ID_57504_MF1: 4236 case BROADCOM_DEV_ID_57502_MF1: 4237 case BROADCOM_DEV_ID_57508_MF2: 4238 case BROADCOM_DEV_ID_57504_MF2: 4239 case BROADCOM_DEV_ID_57502_MF2: 4240 case BROADCOM_DEV_ID_57500_VF1: 4241 case BROADCOM_DEV_ID_57500_VF2: 4242 /* FALLTHROUGH */ 4243 return true; 4244 default: 4245 return false; 4246 } 4247 } 4248 4249 bool bnxt_stratus_device(struct bnxt *bp) 4250 { 4251 uint16_t device_id = bp->pdev->id.device_id; 4252 4253 switch (device_id) { 4254 case BROADCOM_DEV_ID_STRATUS_NIC: 4255 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4256 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4257 /* FALLTHROUGH */ 4258 return true; 4259 default: 4260 return false; 4261 } 4262 } 4263 4264 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 4265 { 4266 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4267 struct bnxt *bp = eth_dev->data->dev_private; 4268 4269 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4270 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4271 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4272 if (!bp->bar0 || !bp->doorbell_base) { 4273 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4274 return -ENODEV; 4275 } 4276 4277 bp->eth_dev = eth_dev; 4278 bp->pdev = pci_dev; 4279 4280 return 0; 4281 } 4282 4283 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4284 struct bnxt_ctx_pg_info *ctx_pg, 4285 uint32_t mem_size, 4286 const char *suffix, 4287 uint16_t idx) 4288 { 4289 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4290 const struct rte_memzone *mz = NULL; 4291 char mz_name[RTE_MEMZONE_NAMESIZE]; 4292 rte_iova_t mz_phys_addr; 4293 uint64_t valid_bits = 0; 4294 uint32_t sz; 4295 int i; 4296 4297 if (!mem_size) 4298 return 0; 4299 4300 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4301 BNXT_PAGE_SIZE; 4302 rmem->page_size = BNXT_PAGE_SIZE; 4303 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4304 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4305 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4306 4307 valid_bits = PTU_PTE_VALID; 4308 4309 if (rmem->nr_pages > 1) { 4310 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4311 "bnxt_ctx_pg_tbl%s_%x_%d", 4312 suffix, idx, bp->eth_dev->data->port_id); 4313 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4314 mz = rte_memzone_lookup(mz_name); 4315 if (!mz) { 4316 mz = rte_memzone_reserve_aligned(mz_name, 4317 rmem->nr_pages * 8, 4318 SOCKET_ID_ANY, 4319 RTE_MEMZONE_2MB | 4320 RTE_MEMZONE_SIZE_HINT_ONLY | 4321 RTE_MEMZONE_IOVA_CONTIG, 4322 BNXT_PAGE_SIZE); 4323 if (mz == NULL) 4324 return -ENOMEM; 4325 } 4326 4327 memset(mz->addr, 0, mz->len); 4328 mz_phys_addr = mz->iova; 4329 4330 rmem->pg_tbl = mz->addr; 4331 rmem->pg_tbl_map = mz_phys_addr; 4332 rmem->pg_tbl_mz = mz; 4333 } 4334 4335 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4336 suffix, idx, bp->eth_dev->data->port_id); 4337 mz = rte_memzone_lookup(mz_name); 4338 if (!mz) { 4339 mz = rte_memzone_reserve_aligned(mz_name, 4340 mem_size, 4341 SOCKET_ID_ANY, 4342 RTE_MEMZONE_1GB | 4343 RTE_MEMZONE_SIZE_HINT_ONLY | 4344 RTE_MEMZONE_IOVA_CONTIG, 4345 BNXT_PAGE_SIZE); 4346 if (mz == NULL) 4347 return -ENOMEM; 4348 } 4349 4350 memset(mz->addr, 0, mz->len); 4351 mz_phys_addr = mz->iova; 4352 4353 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4354 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4355 rmem->dma_arr[i] = mz_phys_addr + sz; 4356 4357 if (rmem->nr_pages > 1) { 4358 if (i == rmem->nr_pages - 2 && 4359 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4360 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4361 else if (i == rmem->nr_pages - 1 && 4362 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4363 valid_bits |= PTU_PTE_LAST; 4364 4365 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4366 valid_bits); 4367 } 4368 } 4369 4370 rmem->mz = mz; 4371 if (rmem->vmem_size) 4372 rmem->vmem = (void **)mz->addr; 4373 rmem->dma_arr[0] = mz_phys_addr; 4374 return 0; 4375 } 4376 4377 static void bnxt_free_ctx_mem(struct bnxt *bp) 4378 { 4379 int i; 4380 4381 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4382 return; 4383 4384 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4385 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4386 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4387 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4388 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4389 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4390 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4391 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4392 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4393 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4394 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4395 4396 for (i = 0; i < BNXT_MAX_Q; i++) { 4397 if (bp->ctx->tqm_mem[i]) 4398 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4399 } 4400 4401 rte_free(bp->ctx); 4402 bp->ctx = NULL; 4403 } 4404 4405 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4406 4407 #define min_t(type, x, y) ({ \ 4408 type __min1 = (x); \ 4409 type __min2 = (y); \ 4410 __min1 < __min2 ? __min1 : __min2; }) 4411 4412 #define max_t(type, x, y) ({ \ 4413 type __max1 = (x); \ 4414 type __max2 = (y); \ 4415 __max1 > __max2 ? __max1 : __max2; }) 4416 4417 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4418 4419 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4420 { 4421 struct bnxt_ctx_pg_info *ctx_pg; 4422 struct bnxt_ctx_mem_info *ctx; 4423 uint32_t mem_size, ena, entries; 4424 int i, rc; 4425 4426 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4427 if (rc) { 4428 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4429 return rc; 4430 } 4431 ctx = bp->ctx; 4432 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4433 return 0; 4434 4435 ctx_pg = &ctx->qp_mem; 4436 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4437 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4438 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4439 if (rc) 4440 return rc; 4441 4442 ctx_pg = &ctx->srq_mem; 4443 ctx_pg->entries = ctx->srq_max_l2_entries; 4444 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4445 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4446 if (rc) 4447 return rc; 4448 4449 ctx_pg = &ctx->cq_mem; 4450 ctx_pg->entries = ctx->cq_max_l2_entries; 4451 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4452 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4453 if (rc) 4454 return rc; 4455 4456 ctx_pg = &ctx->vnic_mem; 4457 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4458 ctx->vnic_max_ring_table_entries; 4459 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4460 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4461 if (rc) 4462 return rc; 4463 4464 ctx_pg = &ctx->stat_mem; 4465 ctx_pg->entries = ctx->stat_max_entries; 4466 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4467 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4468 if (rc) 4469 return rc; 4470 4471 entries = ctx->qp_max_l2_entries + 4472 ctx->vnic_max_vnic_entries + 4473 ctx->tqm_min_entries_per_ring; 4474 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4475 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring, 4476 ctx->tqm_max_entries_per_ring); 4477 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) { 4478 ctx_pg = ctx->tqm_mem[i]; 4479 /* use min tqm entries for now. */ 4480 ctx_pg->entries = entries; 4481 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4482 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i); 4483 if (rc) 4484 return rc; 4485 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4486 } 4487 4488 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4489 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4490 if (rc) 4491 PMD_DRV_LOG(ERR, 4492 "Failed to configure context mem: rc = %d\n", rc); 4493 else 4494 ctx->flags |= BNXT_CTX_FLAG_INITED; 4495 4496 return rc; 4497 } 4498 4499 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4500 { 4501 struct rte_pci_device *pci_dev = bp->pdev; 4502 char mz_name[RTE_MEMZONE_NAMESIZE]; 4503 const struct rte_memzone *mz = NULL; 4504 uint32_t total_alloc_len; 4505 rte_iova_t mz_phys_addr; 4506 4507 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4508 return 0; 4509 4510 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4511 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4512 pci_dev->addr.bus, pci_dev->addr.devid, 4513 pci_dev->addr.function, "rx_port_stats"); 4514 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4515 mz = rte_memzone_lookup(mz_name); 4516 total_alloc_len = 4517 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4518 sizeof(struct rx_port_stats_ext) + 512); 4519 if (!mz) { 4520 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4521 SOCKET_ID_ANY, 4522 RTE_MEMZONE_2MB | 4523 RTE_MEMZONE_SIZE_HINT_ONLY | 4524 RTE_MEMZONE_IOVA_CONTIG); 4525 if (mz == NULL) 4526 return -ENOMEM; 4527 } 4528 memset(mz->addr, 0, mz->len); 4529 mz_phys_addr = mz->iova; 4530 4531 bp->rx_mem_zone = (const void *)mz; 4532 bp->hw_rx_port_stats = mz->addr; 4533 bp->hw_rx_port_stats_map = mz_phys_addr; 4534 4535 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4536 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4537 pci_dev->addr.bus, pci_dev->addr.devid, 4538 pci_dev->addr.function, "tx_port_stats"); 4539 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4540 mz = rte_memzone_lookup(mz_name); 4541 total_alloc_len = 4542 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4543 sizeof(struct tx_port_stats_ext) + 512); 4544 if (!mz) { 4545 mz = rte_memzone_reserve(mz_name, 4546 total_alloc_len, 4547 SOCKET_ID_ANY, 4548 RTE_MEMZONE_2MB | 4549 RTE_MEMZONE_SIZE_HINT_ONLY | 4550 RTE_MEMZONE_IOVA_CONTIG); 4551 if (mz == NULL) 4552 return -ENOMEM; 4553 } 4554 memset(mz->addr, 0, mz->len); 4555 mz_phys_addr = mz->iova; 4556 4557 bp->tx_mem_zone = (const void *)mz; 4558 bp->hw_tx_port_stats = mz->addr; 4559 bp->hw_tx_port_stats_map = mz_phys_addr; 4560 bp->flags |= BNXT_FLAG_PORT_STATS; 4561 4562 /* Display extended statistics if FW supports it */ 4563 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4564 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4565 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4566 return 0; 4567 4568 bp->hw_rx_port_stats_ext = (void *) 4569 ((uint8_t *)bp->hw_rx_port_stats + 4570 sizeof(struct rx_port_stats)); 4571 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4572 sizeof(struct rx_port_stats); 4573 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4574 4575 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4576 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4577 bp->hw_tx_port_stats_ext = (void *) 4578 ((uint8_t *)bp->hw_tx_port_stats + 4579 sizeof(struct tx_port_stats)); 4580 bp->hw_tx_port_stats_ext_map = 4581 bp->hw_tx_port_stats_map + 4582 sizeof(struct tx_port_stats); 4583 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4584 } 4585 4586 return 0; 4587 } 4588 4589 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4590 { 4591 struct bnxt *bp = eth_dev->data->dev_private; 4592 int rc = 0; 4593 4594 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4595 RTE_ETHER_ADDR_LEN * 4596 bp->max_l2_ctx, 4597 0); 4598 if (eth_dev->data->mac_addrs == NULL) { 4599 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4600 return -ENOMEM; 4601 } 4602 4603 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) { 4604 if (BNXT_PF(bp)) 4605 return -EINVAL; 4606 4607 /* Generate a random MAC address, if none was assigned by PF */ 4608 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 4609 bnxt_eth_hw_addr_random(bp->mac_addr); 4610 PMD_DRV_LOG(INFO, 4611 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 4612 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 4613 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 4614 4615 rc = bnxt_hwrm_set_mac(bp); 4616 if (!rc) 4617 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr, 4618 RTE_ETHER_ADDR_LEN); 4619 return rc; 4620 } 4621 4622 /* Copy the permanent MAC from the FUNC_QCAPS response */ 4623 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN); 4624 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 4625 4626 return rc; 4627 } 4628 4629 static int bnxt_restore_dflt_mac(struct bnxt *bp) 4630 { 4631 int rc = 0; 4632 4633 /* MAC is already configured in FW */ 4634 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) 4635 return 0; 4636 4637 /* Restore the old MAC configured */ 4638 rc = bnxt_hwrm_set_mac(bp); 4639 if (rc) 4640 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 4641 4642 return rc; 4643 } 4644 4645 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 4646 { 4647 if (!BNXT_PF(bp)) 4648 return; 4649 4650 #define ALLOW_FUNC(x) \ 4651 { \ 4652 uint32_t arg = (x); \ 4653 bp->pf.vf_req_fwd[((arg) >> 5)] &= \ 4654 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \ 4655 } 4656 4657 /* Forward all requests if firmware is new enough */ 4658 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) && 4659 (bp->fw_ver < ((20 << 24) | (7 << 16)))) || 4660 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) { 4661 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd)); 4662 } else { 4663 PMD_DRV_LOG(WARNING, 4664 "Firmware too old for VF mailbox functionality\n"); 4665 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd)); 4666 } 4667 4668 /* 4669 * The following are used for driver cleanup. If we disallow these, 4670 * VF drivers can't clean up cleanly. 4671 */ 4672 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR); 4673 ALLOW_FUNC(HWRM_VNIC_FREE); 4674 ALLOW_FUNC(HWRM_RING_FREE); 4675 ALLOW_FUNC(HWRM_RING_GRP_FREE); 4676 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE); 4677 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE); 4678 ALLOW_FUNC(HWRM_STAT_CTX_FREE); 4679 ALLOW_FUNC(HWRM_PORT_PHY_QCFG); 4680 ALLOW_FUNC(HWRM_VNIC_TPA_CFG); 4681 } 4682 4683 static int bnxt_init_fw(struct bnxt *bp) 4684 { 4685 uint16_t mtu; 4686 int rc = 0; 4687 4688 bp->fw_cap = 0; 4689 4690 rc = bnxt_hwrm_ver_get(bp); 4691 if (rc) 4692 return rc; 4693 4694 rc = bnxt_hwrm_func_reset(bp); 4695 if (rc) 4696 return -EIO; 4697 4698 rc = bnxt_hwrm_vnic_qcaps(bp); 4699 if (rc) 4700 return rc; 4701 4702 rc = bnxt_hwrm_queue_qportcfg(bp); 4703 if (rc) 4704 return rc; 4705 4706 /* Get the MAX capabilities for this function. 4707 * This function also allocates context memory for TQM rings and 4708 * informs the firmware about this allocated backing store memory. 4709 */ 4710 rc = bnxt_hwrm_func_qcaps(bp); 4711 if (rc) 4712 return rc; 4713 4714 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 4715 if (rc) 4716 return rc; 4717 4718 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 4719 if (rc) 4720 return rc; 4721 4722 /* Get the adapter error recovery support info */ 4723 rc = bnxt_hwrm_error_recovery_qcfg(bp); 4724 if (rc) 4725 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 4726 4727 bnxt_hwrm_port_led_qcaps(bp); 4728 4729 return 0; 4730 } 4731 4732 static int 4733 bnxt_init_locks(struct bnxt *bp) 4734 { 4735 int err; 4736 4737 err = pthread_mutex_init(&bp->flow_lock, NULL); 4738 if (err) { 4739 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 4740 return err; 4741 } 4742 4743 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 4744 if (err) 4745 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 4746 return err; 4747 } 4748 4749 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 4750 { 4751 int rc; 4752 4753 rc = bnxt_init_fw(bp); 4754 if (rc) 4755 return rc; 4756 4757 if (!reconfig_dev) { 4758 rc = bnxt_setup_mac_addr(bp->eth_dev); 4759 if (rc) 4760 return rc; 4761 } else { 4762 rc = bnxt_restore_dflt_mac(bp); 4763 if (rc) 4764 return rc; 4765 } 4766 4767 bnxt_config_vf_req_fwd(bp); 4768 4769 rc = bnxt_hwrm_func_driver_register(bp); 4770 if (rc) { 4771 PMD_DRV_LOG(ERR, "Failed to register driver"); 4772 return -EBUSY; 4773 } 4774 4775 if (BNXT_PF(bp)) { 4776 if (bp->pdev->max_vfs) { 4777 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 4778 if (rc) { 4779 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 4780 return rc; 4781 } 4782 } else { 4783 rc = bnxt_hwrm_allocate_pf_only(bp); 4784 if (rc) { 4785 PMD_DRV_LOG(ERR, 4786 "Failed to allocate PF resources"); 4787 return rc; 4788 } 4789 } 4790 } 4791 4792 rc = bnxt_alloc_mem(bp, reconfig_dev); 4793 if (rc) 4794 return rc; 4795 4796 rc = bnxt_setup_int(bp); 4797 if (rc) 4798 return rc; 4799 4800 rc = bnxt_request_int(bp); 4801 if (rc) 4802 return rc; 4803 4804 rc = bnxt_init_locks(bp); 4805 if (rc) 4806 return rc; 4807 4808 return 0; 4809 } 4810 4811 static int 4812 bnxt_dev_init(struct rte_eth_dev *eth_dev) 4813 { 4814 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4815 static int version_printed; 4816 struct bnxt *bp; 4817 int rc; 4818 4819 if (version_printed++ == 0) 4820 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 4821 4822 eth_dev->dev_ops = &bnxt_dev_ops; 4823 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 4824 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 4825 4826 /* 4827 * For secondary processes, we don't initialise any further 4828 * as primary has already done this work. 4829 */ 4830 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 4831 return 0; 4832 4833 rte_eth_copy_pci_info(eth_dev, pci_dev); 4834 4835 bp = eth_dev->data->dev_private; 4836 4837 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 4838 4839 if (bnxt_vf_pciid(pci_dev->id.device_id)) 4840 bp->flags |= BNXT_FLAG_VF; 4841 4842 if (bnxt_thor_device(pci_dev->id.device_id)) 4843 bp->flags |= BNXT_FLAG_THOR_CHIP; 4844 4845 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 4846 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 4847 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 4848 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 4849 bp->flags |= BNXT_FLAG_STINGRAY; 4850 4851 rc = bnxt_init_board(eth_dev); 4852 if (rc) { 4853 PMD_DRV_LOG(ERR, 4854 "Failed to initialize board rc: %x\n", rc); 4855 return rc; 4856 } 4857 4858 rc = bnxt_alloc_hwrm_resources(bp); 4859 if (rc) { 4860 PMD_DRV_LOG(ERR, 4861 "Failed to allocate hwrm resource rc: %x\n", rc); 4862 goto error_free; 4863 } 4864 rc = bnxt_init_resources(bp, false); 4865 if (rc) 4866 goto error_free; 4867 4868 rc = bnxt_alloc_stats_mem(bp); 4869 if (rc) 4870 goto error_free; 4871 4872 /* Pass the information to the rte_eth_dev_close() that it should also 4873 * release the private port resources. 4874 */ 4875 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 4876 4877 PMD_DRV_LOG(INFO, 4878 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", 4879 pci_dev->mem_resource[0].phys_addr, 4880 pci_dev->mem_resource[0].addr); 4881 4882 return 0; 4883 4884 error_free: 4885 bnxt_dev_uninit(eth_dev); 4886 return rc; 4887 } 4888 4889 static void 4890 bnxt_uninit_locks(struct bnxt *bp) 4891 { 4892 pthread_mutex_destroy(&bp->flow_lock); 4893 pthread_mutex_destroy(&bp->def_cp_lock); 4894 } 4895 4896 static int 4897 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 4898 { 4899 int rc; 4900 4901 bnxt_free_int(bp); 4902 bnxt_free_mem(bp, reconfig_dev); 4903 bnxt_hwrm_func_buf_unrgtr(bp); 4904 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 4905 bp->flags &= ~BNXT_FLAG_REGISTERED; 4906 bnxt_free_ctx_mem(bp); 4907 if (!reconfig_dev) { 4908 bnxt_free_hwrm_resources(bp); 4909 4910 if (bp->recovery_info != NULL) { 4911 rte_free(bp->recovery_info); 4912 bp->recovery_info = NULL; 4913 } 4914 } 4915 4916 bnxt_uninit_locks(bp); 4917 rte_free(bp->ptp_cfg); 4918 bp->ptp_cfg = NULL; 4919 return rc; 4920 } 4921 4922 static int 4923 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 4924 { 4925 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 4926 return -EPERM; 4927 4928 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 4929 4930 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 4931 bnxt_dev_close_op(eth_dev); 4932 4933 return 0; 4934 } 4935 4936 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 4937 struct rte_pci_device *pci_dev) 4938 { 4939 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt), 4940 bnxt_dev_init); 4941 } 4942 4943 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 4944 { 4945 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 4946 return rte_eth_dev_pci_generic_remove(pci_dev, 4947 bnxt_dev_uninit); 4948 else 4949 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 4950 } 4951 4952 static struct rte_pci_driver bnxt_rte_pmd = { 4953 .id_table = bnxt_pci_id_map, 4954 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 4955 .probe = bnxt_pci_probe, 4956 .remove = bnxt_pci_remove, 4957 }; 4958 4959 static bool 4960 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 4961 { 4962 if (strcmp(dev->device->driver->name, drv->driver.name)) 4963 return false; 4964 4965 return true; 4966 } 4967 4968 bool is_bnxt_supported(struct rte_eth_dev *dev) 4969 { 4970 return is_device_supported(dev, &bnxt_rte_pmd); 4971 } 4972 4973 RTE_INIT(bnxt_init_log) 4974 { 4975 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver"); 4976 if (bnxt_logtype_driver >= 0) 4977 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE); 4978 } 4979 4980 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 4981 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 4982 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 4983